H.K.

E SOCIETY’S
POOJYA DODDAPPA APPA COLLEGE OF ENGINEERING
GULBARGA – 585102

(An Autonomous Institution, Affiliated to VTU Belgaum, and Approved by AICTE)

SEMINAR REPORT
ON

3D INTEGRATED CIRCUITS

Submitted to the
Poojya Doddappa Appa College of Engineering, Gulbarga
(Autonomous Institution)

BACHELOUR OF ENGINEERING
In
ELECTRONICS AND INSTRUMENTATION ENGINEERING

Submitted By:
RAHUL.P
(3PD16EI023)
Under the Guidance of
Dr. CHANNAPPA BHYRI

DEPARTMENT OF ELECTRONICS AND INSTRUMENTATION ENGINEERING

POOJYA DODDAPPA APPA COLLEGE OF ENGIERING
[Type text] KALABURAGI – 585102 Page 1
2019 – 2020
 CONTENTS

Sl. No. Particulars Page No

1 INTRODUCTION 1
2 MOTIVATION FOR 3-D ICs 2
3 3D ARCHITECTURE 3
4 AREA AND PERFORMANCE ESTIMATION 4
5 PRESENT SCENARIO OF THE 3-D INDUSTRY 6
6 ADVANTAGES 7
7 APPLICATIONS 8
8 FAILURE F THE 3D IC INDUSTRY 9
9 REFERNCES 10
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1.INTRODUCTION

There is a saying in real estate; when land get expensive, multi-storied buildings
are the alternative solution. We have a similar situation in the chip industry. For
the past thirty years, chip designers have considered whether building integrated
circuits multiple layers might create cheaper, more powerful chips.

Performance of deep-sub micrometer very large scale integrated (VLSI) circuits is

being increasingly dominated by the interconnects due to increasing wire pitch and
increasing die size. Additionally, heterogeneous integration of different technologies
on one single chip is becoming increasingly desirable, for which planar (2-D) ICs
may not be suitable.

The three dimensional (3-D) chip design strategy exploits the vertical dimension to
alleviate the interconnect related problems and to facilitate heterogeneous integration
of technologies to realize system on a chip (SoC) design. By simply dividing a planar
chip into separate blocks, each occupying a separate physical level interconnected by
short and vertical interlayer interconnects (VILICs), significant improvement in
performance and reduction in wire-limited chip area can be achieved.

In the 3-Ddesign architecture, an entire chip is divided into a number of blocks, and
each block is placed on a separate layer of Si that are stacked on top of each other.

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2. MOTIVATION FOR 3-D ICs

The unprecedented growth of the computer and the information technology

industry is demanding Very Large Scale Integrated ( VLSI ) circuits with increasing
functionality and performance at minimum cost and power dissipation. Continuous
scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect
delays. A significant fraction of the total power consumption can be due to the wiring
network used for clock distribution, which is usually realized using long global
wires.

Furthermore, increasing drive for the integration of disparate signals

(digital,analog,RF) and technologies (SOI,SiGe,GaAs,and so on)is introducing
various SoC design concepts, for which existing planner (2-D) IC design may not be
suitable.

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3. 3D ARCHITECTURE

Three-dimensional integration to create multilayer Si ICs is a concept that can

significantly improve interconnect performance ,increase transistor packing density,
and reduce chip area and power dissipation. Additionally 3D ICs can be very effective
large scale on chip integration of different systems.

In 3D design architecture, and entire(2D) chips is divided into a number of blocks is

placed on separate layer of Si that are stacked on top of each other. Each Si layer in
the 3D structure can have multiple layer of interconnects(VILICs) and common
global interconnects.

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4. AREA AND PERFORMANCE ESTIMATION

1. Chip area minimization with fixed interconnect delay

Here, VILICs are assumed to consume negligible area, interconnect line width is
assumed to equal half the metal pitch at all times, and the total number of metal layers
for 2-D and 3-D case was conserved. A key assumption for the geometrical
construction of each tier of the multilevel interconnect network is that all cross
sectional dimensions are equal within that tier.

As Psemi increase from its value at the minimum Ac the semi global and global pitches
increase resulting in a larger wiring requirement and thus a larger A c. Furthermore,
as Psemi increases, even longer wires can now satisfy the maximum delay requirement
in the semi global tier. These results in global wires to be rerouted to the semi global
tie0, which in turn will require greater chip area. Under such circumstances, the semi
global tier begins to dominate and determine the chip area. Conversely, as P semi
decreases from its value at the minimum Ac, the longer wires in the semi global tier
no longer satisfy the maximum delay requirement of that tier and they need to be
rerouted to the global tier where they can enjoy a larger pitch. The populations of
wires in global tiers increases and since these wires have a large cross section they
have a greater area requirement. Under such circumstances the global tier begins to
dominate and determine the chip area.

2. Increasing Chip Area and Performance

3-D IC performance can be enhanced to exceed the performance of 2-D ICs by

improving interconnect delay. This is achieved by increasing the wire pitch, which
causes a reduction in the resistance. The effect of increasing psemi and pglobal on the
operating frequency and Ac.

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This illustrates how the optimum semi global pitch (i.e., the psemi associated with the
minimum Ac) increases to obtain higher operating frequencies. Also, as the semi
global tier pitch increases, chip area and, therefore, interconnect length also increases.
However, we can see that the increase in chip area still remains well below the area
required for the 2-D case.
Two scenarios are considered 1)global pitch is increased to match the global pitch
for the 2-d case and 2)global pitch is increased to match the chip area (footprint) for
the 2-d case. Note that the delay requirements sets a maximum values of interconnect
length are given tier. Therefore, as interconnect lengths are increased, lines which
exceed this maximum length criterion for that particular tier need to be rerouted on
upper ties.

3. Effect Of Increasing Number Of Silicon Layer

As the number of silicon layers increases beyond two, the assumption that all
interlayer interconnects (ILICs) are vertical and consume negligible area becomes
less tenable. The area used up by these horizontal ILICs can be estimated from their
total length and pitch.

The decrease in interconnect delay becomes progressively smaller as the numbers of

active layers increase. This is due to the fact that the area required by ILICs begins
to offset any area saving due to increasing the number of active layers.

4.Effect Of Increasing The Number Of Metal Layer

It is likely that there are local and semi global tiers associated with every active
layer, and a common global tier is used . This would result in an increase in the total
number of metal layers for the 3-D case. The effect of using 3-D case. The effect of
using 3-D ICs with constant metal layers and the effect of employing twice the
number of metal layers as in 2-D

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5. PRESENT SCENARIO OF THE 3-D IC INDUSTRY

Many companies are working on the 3-D chips ,including groups at Massachusetts
institute of technology (MIT),international business machines(IBM). Rensselar
Polytechnic and SUNY Albany are also doing research on techniques for bonding
conventional chips together to form multiple layers .whichever approach ultimately
wins ,the multilayer chip building technology opens up a whole new world of design
.

However ,the Santa Clara, California US based startup company matrix

semiconductor will bring the first multilayer chip to the market ,while matrix’s
techniques will not likely result in more computing power ,they will produce cheaper
chips for certain applications, like memory used in digital cameras , personal digital
assistants ,cellular phones ,hand held gaming devices ,etc .matrix has adapted the
technology developed for making flat –panel liquid crystal displays to build chips
with multilayer of circuitry.

The company’s first products will be memory chips called 3-Dmemory,for

consumer electronics like digital cameras and audio players. current flash memory
cards for such devices are rewritable but expensive .however the newly produced
chips will cost ten times less, about as much as an audio tape or a roll of film, but
will only record information once. The cost is so largely because the stacked chips
contain the same amount of circuitry as flash cards but use a much smaller area of
the extremely expensive silicon wafers that form the basis for all silicon chips. The
chips will also offer a permanent record of the images and sounds users record

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6. ADVANTAGES OF 3-D MEMORY

Disks are inexpensive, but they requires drives that are expensive bulky ,fragile and
consume a lot of battery power . Accidentally dropping a drive or scratching a disk
can cause significant damage and the potential loss of valuable pictures and data.
Flash and other non volatile memories are much more rugged, battery efficient
compact and require no bulky drive technologies . Dropping them is not a problem
they are however much more expensive. Both require the use of a pc.

The ideal solution is a 3-D memory that leverages all the benefits of non volatile
media, costs as little as a disk, and is as convenient as 35 mm film and audio tape.

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7. APPLICATIONS

Portable electronic digital cameras, digital audio players ,PDAs ,smart cellular
phone, and handheld gaming devices are among the fastest growing technology
market for both business and consumers. To date ,one of the largest constraints to
growth has been affordable storage, creating the marketing opportunity for ultra low
cost internal and external memory. These applications share characters beyond rapid
market growth.

Portable devices all require small form factors , battery efficiency, robustness, and
reliability. Both the devices and consumable media are extremely price sensitive with
high volumes coming only with the ability to hit low price points. Device designers
often trade application richness to meet tight cost targets. Existing mask ROM and
NAND flash non volatile technology force designers and product planners to make
the difficult choice between low cost or field programmability and flexibility.
Consumers value the convenience and ease of views of readily available low cost
storage. The potential to dramatically lower the cost of digital storage weapons many
more markets than those listed above. Manufacturers of memory driven devices can
now reach price points previously inaccessible and develop richer, easier to use
products.

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8. FUTURE OF THE 3-D IC INDUSTRY

3.4 DOUBLE Matrix is working with partners including Microsoft Corp, Thomas
Multimedia ,Eastman Kodak and Sony Corp. three product categories are planned:
bland memory cards :cards sold preloaded with content, such as software or music
; and standard memory packages, for using embedded applications such as PDAs and
set-top boxes .

Thomson electronics , the European electronic giant, will begin to incorporate 3-D
memory chips from matrix semiconductor in portable storage cards ,a strong
endorsement for the chip start –up.

Thomson multimedia will incorporate the 3-D memory in memory cards that cane
be used to store digital photos or music. Although the cards plug into cameras
Thomson is also working on card readers that will allow consumers to view digital
photos on a television. The Thomson /matrix cards price makes the difference from
completing flash cards from Sony and Toshiba .the 64 MB Thomson card will cost
about as much as camera film does today. to further strengthen the relationship with
film ,the cards will be sold under the name Technicolor Digital Memory Card.

Similar flash memory cards from other companies cost around Rs.1900 or more-
though consumers can erase and rerecord data on them, unlike the matrix cards.
As a result of their price, consumers buy very few of them .Thomson, by
contrast , expects to market its write-once cards in retail outlet such as Wal-Mart.

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The first Technicolor cards will offer 64 MB of memory; version with 128 MB and
192 MB will appear later. The first 3-D chips will contain 64 MB. Taiwan
Semiconductor Manufacturing Co. is producing the chips on behalf of matrix.

9. REFERNCES

1. Proceedings of the IEEE, vol 89,no 5,may 2019:

(a) Jose E Schutt-Aine , sung-Mo Kang,
“Interconnections –addressing the next challenge of IC technology” at page
583

(b)Robert h Have Mann, James A Hutch by,

“High performance interconnects: an integration overview” at page 586.

(c) Kaustav Banerjee, Shukri J Souri, Pawan Kapur and Krishna CSara swath
3-D ICs: a novel chip design for improving deep sub micrometer
interconnect performance and Soc integration at page 602.

2. Electronics today June 2018.

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