4961 soqweoag '90-61008 ON renueyy Jenuey aovuag pue BugeiedQSERIAL NO. LIFEPAK® and Physio-Control®, Quik-Look®, Quik-Charge®, Quik-Pace® are trade- marks of the Physto-Contro) Corporation, 11811 Willows Road, P.0. Box 97006, Rednond, Washington 98073-9706. WARRANTY POLICY (USA ONLY Refer to the product warranty statement included in the accessory kit shipped with the product. Duplicate copies may be obtained from the local Physio- Control Sales and Service Office. © ap. 1985 PHYSTO-CONTROLLIST OF EFFECTIVE PAGES secon ___—~( AGE ‘SECTION ace | _ pare are Title Page Dec ‘87 | section 5 5-1 bec '87 (Assemblies, Parts Thru Trademark and Dec 'a7 | ‘Lists, Schematics) |5-219] Warranty Page Section 6 6-1 |Nov '86 List of Effective i | pec *87 ] "(Component Reference | Thru Pages Diagrans) 6-29 Configuration it | Dec 187 Information Table of Contents iti | Dec 87 Thru vit List of Iustrations |viti | dec ‘87 and List of Tables x | Nov *86 How to Use This Manual] xi | Nov ‘86 Sefety Information | xii | Nov ‘a6 Thru xiv Section 1 aa | dec ‘87 (Description) Thru 1-80 Section 2 2-1 | dec ‘87 (Operation) Thry 2-40 Section 3 3-1 | dec *87 (Testing and They Troubleshooting) | 3-44 Section 4 4-1 | ec *87 (Service and Thru Maintenance) 4-18 ©npR. 1985 PHYSTO-CONTROLCONFIGURATION INFORMATION This manual is current with the listed revision level of the following part unbers. The following part numbers appear in the same order as in Table 5-1. DESCRIPTION MONITOR FINAL ASSEMBLY UPPER FRONT PANEL ASSEMBLY LOWER FRONT PANEL ASSEMBLY GENERIC MONITOR ASSEMBLY REAR PANEL ASSEMBLY RECORDER. ASSEMBLY (CHARGER PCB ASSEMBLY POWER SUPPLY ASSEMBLY ECE PCB ASSEMBLY ‘CONTROL PCB ASSENBLY GATEWAY PCB ASSENBLY CRT PCB ASSEMBLY ANODE. SUPPLY PCB ASSEMBLY RECORDER PFC ASSEMBLY UPPER SWITCH MODULE PCB ASSEMBLY [LOWER SWITCH MODULE PCB ASSEMBLY REAR PANEL PCB ASSEMBLY MAIN PEC. ASSEMBLY DEFIBRILLATOR FINAL ASSEMBLY UPPER FRONT PANEL ASSEMBLY LOWER FRONT PANEL ASSEMBLY GENERIC DEFIBRILLATOR ASSEMBLY GENERIC APEX AND STERNUN PADDLE ASSEMBLIES REAR PANEL ASSEMBLIES POWER SUPPLY PCB ASSEMBLY MAIN PCB ASSEMBLY LOGIC PCB ASSEMBLY OPTICAL INTERFACE PCB ASSEMBLY TEST LOAD PCB ASSEMBLY ‘UPPER SKITCH MODULE PCB ASSEMBLY LOWER SWITCH MODULE PCB ASSEMBLY (CASSETTE. INTERFACE PCB ASSEMBLY CONTROL PFC ASSENBLY PACING CASSETTE FINAL ASSEMBLY PACING CASSETTE SWITCH DISPLAY PCB ASSEMBLY PACING CASSETTE PFC. ASSEMBLY DEFIBRILLATOR CASSETTE FINAL ASSEMBLY i PART NUMBER 802800-14 802803-05 80280405 80280103 802808-05 1802854-02 802821-07 802815-03 802833-05 802827-04 802835-05 802831-03 1802813-01 802819-05 1802845-01 1802844-04 802829-01 180282301 802700-07 802707-05 802702-05 802701-03 '302901-08 802703-03 1302719-06 802715-03 802725-08 802717-01 802713-02 802711-02 802709-02 803869-01 '302721-03 802904-04 80291301 80291102 802903-03 ©poR. 1985 PHYS1O-CONTROL THRU -26 THRU -07 THRU -09 THRU -16 THRU -08 THRU -08, AND -05 ca 8 onica onic 8 a 0s oRrce‘TABLE OF CONTENTS ‘SECTION PAGE LIST OF ILLUSTRATIONS. . . . err LUST OF TABLES «=. eer HOWTOUSETHISMANUAL | 2... * SAFETYINFORMATION .. 5... eee aes 1 DESCRIPTION... 2... . Peery PHYSICAL DESCRIPTION « ° FUNCTIONAL DESCRIPTION. | | Nonitor and Defibrillator Nonitor Performance... . Defibrillator Performance ‘THEORY OF OPERATION... | | LPBMONITOR. 2... Charger PCB Assenbiy’(éo2eé1) ¢ ¢ ‘AC Line Conditfoning . Bootstrap Power Supply Pulse Width Nodulator Gate Drive/Poxer Switch Rectifier/Filters .. . High Line Shutdown 2 <<< ¢ Battery Charger. ° 1. 2 AC/Battery Relay Controi * °° Battery Operation Indicator (LED Drive), Power Supply PCB Assenbly (802615)... . Battery Protection/Reference Voltage » | ON/OFF Control. see eee ee ee ee Low Battery Detection’ ttt ltt Transforner Output Rectifiers and Filters. eee ee Transformer’ Drive’ <2 2 Flyback Detection and Osci Control Feedback. ee ee Long-Term Current Limit. © 2022204 Defibrillator Serial Data Receiver... 1 Wake Up Message Decoder... . . 1 Wake Up Suppression. . : 1 Syne Signal Encoder <>? an Interface Drive...) eee ae Audio Amplifier: 2 L Watchdog... : og 1 Voltage Monitor” <2 TTT TII ID 4 1 1 1 1 1 I L BEBE BRESBREESE SRLS RESRESS cg cB Assenbly (sodai3) 222222222 £06 Microprocessors. 122222122 Isolated Power Suppiy’ 22 <2: Isolated Preamplifier Nonfsolated Preamplifier » . 2. Paddles ECG Demodulator: : >> Anti-Aliasing Filter. 2222225 ¢ be & at ©npR, 1985 PHYSTO-CONTROL‘TABLE OF CONTENTS (Continued) SECTION PAGE 1 DESCRIPTION (Continued) 1-43, MD Converter... 2.5 -28 1a4 Gain Control and D/A st -28 1-85 Control PCB Assenbly (02827) | | -29 146 Executive Microprocessor . -29 Keyboard Interface... 20222 s 730 Audio Interface. 21111 t Dl 130 Display/Recorder interface << 231 Analog Circuitry... 2 31 Trace Controer sss. 3 32 Raster Controtler 2 oo. -35 Gateway PCB Assenbly (802835) °° 37 Gateway Microprocessor. . < : 37 Fitton rant eteet 37 Address Cycles. ss -38 Frequency Divider <2. 2: 38 Real Tine Clock Interface: -38 Printer Nessage Format... . 40 External Communication > <>. 40 CRT PcB Assenbly (802831) : 22 42 Horizontal eflection Dl wae Horizontal Sweep Generator 22 122 1-43 Horizontal Deflection Amplifier... . 1-48 Horizontal Retracer Amplifier. Dl iae Vertical Deflection... . . . Dl baa Vertical Sweep Generator 2112 1-45 Raster Amplifier... 1. PED D 14s Vertical Retrace Amplifier ree] ECG Active Filter... 5 Til a6 Analog Deflection Aapiifier. Dil 146 172 Power Savers. swe eee see 146 173 Rate Intensity Compensation. 2... 1-47 174 Dot Amplifier... 2... ccc 1-48, 15 Voltage References |... 221.2 ida 1-76 Anode Supply PCB Assenbly (902813). 1... 1-49 Ln Voltage Controlled Oscillator. +: : 1-49 1-78 Power Switching ss... sess e180 1-79 Grid Voltage Reguiation ¢ 222222. 1-8t 1-80 Anode Voltage Regulation «122. 3 151 1°81 Recorder PFC Assembly (802819) (Bodsi1) ¢ 2 1-51 1-82 OO eee ee ee eee ESL 183 Real Time Clocks 222221 L 1 ase 188 Printhead Drive. sss. s cesses 153° 185 PenHeat. se 22 Pillit asa 1-86 paper Wotor Brive" ire Only} <2 << 13 1-87 Paper Motor Drive (GSI Only) 2222 1-86 188 Ben Deflectfon (HEE Qnty}. « Dl isa 183 Pen Deflection (GSI Only). = 1-54 1-90 Serial Data Communication. - 1-55, 191 LPO DEFIBRILLATOR. 2185 1-92 "Power Supply PCB Assembly ( Dill rss iv ©npR. 1985 PHYSIO-CONTROLSECTION ‘TABLE OF CONTENTS (Continued) DESCRIPTION (Continued) 1-130 1-131 1132 1-133 1134 1-135 1-136 1-137 1138 1-139 1-140 1a AG Line Power Conditioning... . « Bootstrap Power Supply... . s+ Pulse Width Modulator. << Power Switching, . . Output Rectification and Ftitering : : : Battery Charger... « « errr AC/Battery Operation Switching ©. ¢ Speaker Driver «ee Wain PCB Assembly (802715)... ON/OFF Control... ... Isolated Power Supply. < . Paddles Preamplifier «oo. Optical Interface and Accessory cabie, Optical Channel One... 2. ss Optical Channel Two. 2222 L tt Optical Channel Three, 2.211 Energy Storage Capacitor Charger: << Oscillator/Control. . . - Current Switch. . 01222 Overcharge Protection. ESC High Voltage. Tlf Transfer/Duep Relay Drive, > 2.1. Logic PCB Assenbly (802725). 2222212 Reset Circuits... . 1. ttle Watchdog and Power Monitoring. <> >: Voltage Reference Regulators. |. . Unregulated ~10Vdc Power Supply. < << Clock Divider... s,s or Switch and Interlock Sensing 2112 2 Key Click and Alarm Logic. . 22111 Energy Select and Charge Limit |< 22 Dump and Charge Control... . . Status Indicators and Eneray bispiay - ¢ Analog to Digital Conversion Multiplexer... eee ee Controller inhibit ©) 2 2 Transfer Relay Control © 22.22 2 Serfal Data Transmission» 2227 PACINGCASSETTE..... oie Pacing Cassette PFC Assembly (éoasin} Wicroprocessor ss. ses ee Control and Display circuit: | Pulse Width Modulator... . : Isolated Power Supply. «2.2.2 Pulse Generator. 2... . peer Pacing Pulse Output. Leads Off Detector Failsafe Circuits.» Test Load Circuit. Switch Display PCB Assembly (8025: v npr. 1985 PAGE PHYSTO-CONTROL,‘SECTION OPERATION «2.2... ‘TABLEOF CONTENTS (Continued) 24° OVERVIEW. 2-2 ACCESSORIES AND REPLACEMENT ITEMS . <> | 23 CONTROLS AND INDICATORS... . 1 2-4 GONNECTING THE INSTRUMENTS | 22222 25 PERIODIC SERVICE PROCEDURES. ||) | 2-6 —_LIFEPAK 6 SYSTEM PERFORMANCE VERIFICATION PROCEDURE... 2-7 LIFEPAK 8 MONITOR PERFORMANCE VERIFICATION PROCEDURE oe 2-8 — LIFEPAK 8 DEFIBRILLATOR PERFORMANCE VERIFICATION PROCEDURE... . 2-9 PACING CASSETTE PenroRMANicé VEjuFicATi PROCEDURE... ere 240 OPERATOR MAINTENANCE 02.2 : 2-11 Recorder Paper Replacement. << 2. eer 2:12 Recorder Stylus Replacement. and Adjustment... ss eee 213 Recorder Printhead Replacement and Adjustment... ss Peer) 2-14 Battery Maintenance se 2-15 External Cleaning. 5. <1 eer 2:16 Preparation for Storage or’Shipment . + + TESTING AND TROUBLESHOOTING... . . . reer 34 OVERVIEW ee Go 32 SERVICING TECHNIQUES | 22D S 3-3 TESTEQUIPMENT «wo. : 3-4 MONITOR FUNCTIONAL TEST AND Citisrarion : 35 Initial Setup. ee ee ee ee : 36 Current Tests 222000 er 37 Front Panel Tests so. ot ere 38 CRT Display and Recorder Annotation Tests: 39 Power Supply Tests. . prreiee 310 Real Time Clock Sets sss sss s tse S11 LEAD SELECT Logic. It 3-12 Recorder Speed/CRT Tim Base. 2222S B13 ECS Display... . eee ce oe B14 Heart Rete, Slit 3-15 Systole Beepers . 00. ae 3-16 Alarm Function/Meart Rate Step’Response/ Auto Record Function... . + + 3-17 ~ EVENT Function... 222 318° FREEZE Function © 222211 3-19 DELAY Functfon. ooo tL 3-20 Delay and Diagnostic’ Recorder/¢aT Frequency Response. sve ee eee ee 3-21 Diagnostic Recorder Frequency Response. + ° vi ©npR. 1985 be eeeeegeeesegers PHYSTO-CONTROL,SECTION 3 TABLE OF CONTENTS (Continued) PAGE ‘TESTING AND TROUBLESHOOTING (Continued) 3-22 CAL Pulse Function... 22.222 3-12 3230 Gain Adjust. DDT 3.12 3:24 ‘Recorder Status Hessage Annotation... >. 3:13 3:25 MLECG Output... ee Tilil 3 3-26 ‘Preamp Common Mode Rejection. . |. 313 3-27 Preamp Offset Recovery... ..55.5: 3:13 3-28 CRT Trace Quality... sss 0 ts 3b 3-29 Anode Supply Adjustment 2211 22S 3-15 3-30 CRT Calibration... 2. 222 Dill 316 hoe eee eee Eee rer fill gas Recorder calibration. «2.1L 220 ‘AC Power Transient Rejection. < . . >? 3:23 3:34 MONITOR SERVICE MODE FUNCTIONS: 2223-28 3-35 MONITOR FAULTISOLATION .. 0.0.2.) 3:24 3-36 MONITOR TROUBLESHOOTING GUIDE |...) 3-29 3:37 DEFIBRILLATOR FUNCTIONAL TEST AND CALIBRATION. ©... . peer anS| Initial Setup DS 13 Power-On... lilt 13 Charge Time and Ready Tone 3 Charge Calibration... . ees Multiple Charge and Bischarge 2222222 3. Output Waveforms... . cee: Charge Current. 22 2222 DITIIII! 3 Ready Time and Refresh Action... | 3 Internal Dump and Open Air Discharge... 3-80 Interlock Test... es ee ee eee 3-40 Cassette Interface Test 222222212 3-41 Battery Mode... ss Dil sar 3-50 DEFIBRILLATOR TROUBLESHOOTING GuibE | 1) 3-41 3-51 PACING CASSETTE FUNCTIONAL TEST AND CALIBRATION... . ere 3-42 3-52 Initial Test’ setup,» |< 3-43 3-63 Poner-On. ss Dl ug 3-84 Pacing Maveform 2222222222110 33 SERVICE AND MAINTENANCE... 2.2... ea 4-1 OVERVIEW . a1 42 TOOLS AND MATERIALS | a1 43 List of Tools and Materials for Cleaning Activities. ee eee ees ee Gd a4 List of Toots and Materials for Repair Activities. oe eer marl 4-5 MONITOR DISASSEMBLY PROCEDURE: : ! | | 1 42 46 Rear Case Removal... . Peete 47 Rear Panel Assembly Renova 1222221 4.2 48 Charger PCB Removal... . 22222112 43 49 Control PCB Removal» 2222222222 43 410 ECG PCB Removal. TIT TTI t 433 4-11 Power Supply PCB'Renovat. 2222222 thas vit ©apR. 1985 PHYSTO-CONTROLSREEERE ‘TABLE OF CONTENTS (Continued) ‘SERVICE AND MAINTENANCE (Continued) 4-12 Gateway PCB Removal... 6. 4-13 CRT Assembly Renova 2222 CRT Removal. Anode Supply’ PC8’Renoval. <> Loner Front’ Panel Assembly’ Renoval Upper Front Panel Assembly Renova Recorder Assembly Removal... . > : Recorder PFC Removal... 0.0.00 Batteries Renoval. v2 22st sce Main PFC Removal DEFIBRILLATOR DISASSEMBLY PROCEDURE : | ° Rear Case Removal... ee ce a : Chassis Removal. 22222 Battery Pak Removal... Rear Panel Asserbly Renovai Wain PCB Assenbly Removal . «<<. Power Supply PCB Assenbly Renoval : Logic PCB Assembly Removal... . - Paddle Removal ves PACING CASSETTE DISASSEMBLY PROCEDURE Pacing Cassette Case Separation... . =: Pacing Cassette PFC Assenbly Removal... INSPECTIONTECHNIQUES .... 2.) sss CLEANING TECHNIQUES. 22222222201 REPAIR TECHNIQUES. . 2.2.2! a ASSEMBLIES, PARTS LISTS, SCHEMATICS... 5. S41 OVERVIEW 0... ee eee ee _ $2 PARTSLISTS | DLDit art 5-3 PARTS ORDERING | >> | eee Ett COMPONENT REFERENCE DIAGRAMS.......... 6-1 61 OVERVIEW... eee eee eee eee ee Gol LIST OF ILLUSTRATIONS PAGE LIFEPAK 8 MONITOR/DEFIBRILLATOR/PACING CASSETTE... . 1-2 OPTICAL INTERFACE BLOCK DIAGRAH. ..... . eee) LP 8 MONITOR BLOCK OIAGRIM. TIL tt) lao DEFIBRILLATOR BLOCK DIAGRAM. FIle riz TYPICAL ECG AVE FORM. 2 Lit 113 MONITOR CHARGER pcB BLOCK DIAGRAM. «ot 16 MONITOR POWER SUPPLY PC8 BLOCK DIAGRAN S22... 119 viti © apr. 1985 PHYSIO-CONTROLLIST OF ILLUSTRATIONS (Continued) PAGE ECG PCB BLOCK DIAGRAM. . pe etree?) CONTROL PCB: EXECUTIVE” SECTION’ BLOCK’ DIAGRAM... > 29 CONTROL PCB: CONTROL SECTION BLOCK DIAGRAM. © > > 1-30 CONTROL PCB: DISPLAY CONTROLLER BLOCK DIAGRAN . LL 1-32 GATEWAY PCB BLOCK DIAGRAM... . Dl ge RTC INTERFACE TIMING «wo. 1 t 1139 ACIA WRITE CYCLE TIMING. ©... ral CCRT PCB BLOCK DIAGRAM. «SL si tae ANODE SUPPLY PCB BLOCK BuAGRaN <<. . 149 RECORDER PFC BLOCK DIAGRAM. < o. 1-82 POWER SUPPLY PCB ASSEMBLY BLOCK’ DIAGRAM. 186 WAIN PCB ASSEMBLY INTERFACE SECTION BLOCK’ DiAGRIN. . . 1-60 MAIN PCB ASSEMBLY ISOLATED PREAMP SECTION BLOCK Sic Ct eee MAIN PcB AsSeNBLY HiGi ENERGY’ CONTROL sécTION’BLOGK Di eT Cre ec ee LOGIC PCB ASSEMBLY BLOCK O1AGRAK SS St PACING CASSETTE BLOCK OIAGRAM, << 2 °° 7 2 MONITOR FRONT PANEL CONTROLS AND INDICATORS: + MONITOR REAR PANEL CONTROLS. . ee ecw SL DEFIBRILLATOR FRONT PANEL CONTROLS AND INDICATORS. DEFIBRILLATOR REAR PANEL CONTROLS. ss PACING CASSETTE FRONT PANEL CONTROLS AND INDICATORS. CONNECTING THE INSTRUMENTS LIFEPAK 8 ‘SYSTEM PERFORMANCE VERIFICATION CHECKLIST. LIFEPAK 8 MONITOR PERFORMANCE VERIFICATION CHECKLIST < LIFEPAK 8 DEFIBRILLATOR PERFORMANCE VERIFICATION CHECKLIST. LIFEPAK 8 PACING CASSETTE’ PERFORMANCE’ VERIFICATION Gets nnn ee ett RECORDER ADJUSTHENTS << STYLUS DEFLECTION WAVEFORH PREPARATION FOR STORAGE OR SHipwENT: F.2D SSS LIFEPAK 8 PACING CASSETTE LOD... 221d STANDARD TEST SIGNAL INPUT... 222222222 OFFSET CHECK SETUP. 2. 222 eee DRAIN PULSE WIT. it CRT Pca ADJUSTMENT LocaTIONS 2222S ar RASTER AND TRACE POSITION, °° <2 err RECORDER PFC ADJUSTMENT LOCATIONS: <2 ¢ STYLUS DEFLECTION WAVEFORM... ss ss ss OUTPUT WAVEFORM PARAMETERS <<< > een CASSETTE LOAD connections. 2222 TTIIIII It PACING WAVEFORM... ww ss eee Er RECORDER AND UPPER FRONT PANEL ASSEMBLY’ REMOVAL: LOWER FRONT PANEL REMOVAL. oss eee vee TYPICAL PRINTED WIRING DAMAGE, 2 lt REPAIRING DAMAGED CONDUCTOR, «> stl ttl ttle TYPICAL LIFTED CONDUCTOR 2 st ix ©neR, 1985 pHYSIO-cONTROLUST OF TABLES SCHEMATICS oss ee ec eee Lp 8 ACCESSORY CASsErieS AsSeieités, PARTS L1STS, SCHEMATICS ss ee ete ee ee eae 3 3 LP 8 MONITOR ASSEMBLIES, PARTS LISTS, SCHEMATICS << 5. 5 5 Up 8 MONITOR AsSEiBLY"LcATION Codes. LDL t 5a LP & DEFIBRILLATOR ASSEMBLY LOCATION CoDeS ¢ 22 << 2 5 5 EP 8 PACING CASSETTE ASSEMBLY LOCATION CODES © <<. : EP 8 DEFIBRILLATOR CASSETTE ASSEMBLY LOCATION CODES. : 5. GONPONENT REFERENCE DIAGRAMS»... 1... 0 6 TABLE PAGE 1-1 LIFEPAK 8 GENERAL SPECIFICATIONS «2... 18 2-1 MONITOR FRONT PANEL CONTROLS AND INDICATORS: 2222 223 2-2 MONITOR REAR PANEL CONTROLS... ss. float 2-3 DEFIBRILLATOR FRONT PANEL CONTROLS AnD inbICATORS: © 2-9 2-4 DEFIBRILLATOR REAR PANEL CONTROLS. . 22a 2-5 PACING CASSETTE FRONT PANEL CONTROLS AND inDICATORS: 2-15 BL TEST EQUIPMENT so eee ee es RZ 3-2 ECG PCA PROGRAMMING suITCH SeTTiNgs. SLD DD 365 3-3 CONTROL PCB PROGRAMMING SWITCH SETTiNés: 122222 3-6 3-4 PRINTHEAD DOT ON-TIME AT TPS... ee ts Di Be 3-5 MONITOR FAULT ISOLATION. 1 22D IDIE 3-26 3-6 MONITOR TROUBLESHOOTING aUIbE. °° STITT III 329 Ee] EFTORILAToR, Tout esHoorinG oiiGes «2 eg ks eae 5-2 LP 8 DEFIBRILLATOR ASSEMBLIES, PARTS LISTS, 3 3 4 4 5 5 1 x © apr. 1985 PHYSTO-CONTROLHOW TO USE THIS MANUAL This manual is divided into 6 major sections in addition to the front matter. ‘The front matter contains information about the current revision configura tions, a Safety Sumary and general operating cautions as well as the Table of Contents, List of Illustrations and List of Tables. Section 1 of the LIFEPAK 8 manual provides the user with introductory information including General Specifications, PHYSICAL and FUNCTIONAL DESCRIPTIONS. This section also. includes the THEORY OF OPERATION with detailed circuit descriptions. Section 2 familiarizes the user with the operation of the equipment. It lists [ACCESSORIES AND REPLACEMENT ITENS, identifies CONTROLS AND INDICATORS, provides PERIODIC SERVICE PROCEDURES and gives OPERATOR MAINTENANCE instructions. This section is not intended to instruct the operator in the clinical use of the instruments a separate OPERATING INSTRUCTIONS booklet is available for that purpose. Section 3 contains a list of recommended TEST EQUIPMENT, explains the TEST SETUP, and provides procedures to perform FUNCTIONAL TEST AND CALIBRATION. Troubieshooting information fs also included. Section 4 provides general maintenance procedures for the LIFEPAK 8. Included ‘are a list of TOOLS AND MATERIALS for cleaning and repair procedures. DISASSENBLY PROCEDURES are also included. Section 5 contains ILLUSTRATED PARTS LISTS for mechanical assemblies; PARTS LISTS, COMPONENT LAYGUTS and SCHENATIC DIAGRANS are provided for Printed Gireult assemblies. Section 6 consists of COMPONENT REFERENCE DIAGRAMS, which provide data for Selected electronic components used in this instrument. xi ©apR. 1985 PHYSTO-CONTROL‘SAFETY INFORMATION SAFETY SUMMARY The general safety information in this sumary is for both operating and servicing personnel. Specific warnings and cautions will be found throughout ‘the manual where they apply, but may not appear in this sumary. TERMS IN THIS MANUAL CAUTION statenents identify conditions or practices that could result in damage to the equipment or other property. WARNING statements identify conditions or practices that could result in personal injury. ‘TERNS AS MARKED ON EQUIPHENT CAUTION indicates a personal injury hazard not immediately accessible as one reads the marking, or a hazard to property including the equipment itself. DANGER indicates a personal injury hazard immediately accessible as one reads the marking. SYMBOLS IN THIS MANUAL in HA, Identifies a Static Sensitive Device ye Indicates that additional information about a device my be found in Section 6, Component Reference Diagrans. SYMBOLS AS MARKED ON EQUIPMENT The symbols below may be found on various configurations of the LIFEPAK & Nonitor and Defibrillator. QD vwisee-Hign vortage. © Protective ground (earth) terminal. A, meio z [Alf versvritiation protected, type BF patent connection ‘efer to manual. Aileen eee eet ee eee Oh ee Lon (Power: connection to the mains) > fusible link YY cavipotentsansty comector xi ©ppR. 1985 PHYSTO-CONTROLMAKE PERIODIC SAFETY INSPECTIONS ect the power cord periodically for fraying or other danage, and replace UE Rected” Bonet operate the apperatus from mains pover with a damaged power Cord or piug. requent electrical and visual checks should be made on cables and electrode irese”” Groten or frayed electrode wires, or loose Srap-fiteings may cause Tnterverence or joss of signel. Particular attention should be paid to the point at which the wire enters the terminals, since flexure will eventually Bluse breakage of strands at this point. POWER SOURCE This product is intended to operate from a power source that does not apply more than 264V RMS (129V RMS in U.S.A. and Canada) between the supply con~ ductors or between either supply conductor and ground. A protective ground connection by way of the grounding conductor in the power cord is essential for safe operation. If the integrity of the protective earth conductor of the ac. mains power outlet is in doubt, the equipment shall be operated from the ‘internal. power source. The product is compatible with isolated power systems as used in operating USE THE PROPER POWER CORD Use only the power cord and connector provided with your product. Use only a ower cord that is in good condition, This product requires a three-wire (18 gauge, SJT-grade) power cord which is supplied (in U.S.A. and Canada) with a three-terminal, polarized plug (Hospital Grade) for connection to the power source and protective ground. The ground (earth) terminal of the plug is directly connected to the frane of the product. For maximum electric shock protection, insert this plug only in a sating (Hospital Grade) poner outlet with a protective ground contact. Oo nat bypass the grounding connection. Any interruption of the grounding connection could create an electric shock hazard. USE THE PROPER FUSE To reduce Fire hazard, use only the fuse specified for your product, identical fn type, voltage rating, and current rating. Fuse replacenent instruct fens are ‘in the Haintenance Sect fon. USE PROPER ELECTROSURGERY RETURN CIRCUIT Reduce the likelihood of electrosurgery burns at monitoring sites by ensuring prope comgcton oF the electronrgery refure circu ary funy ‘aelted Eiectrosurgery units (ESUs) alton other return paths 1? improperly comectess Refer to the ESU operating instructions. " mproperiy ected 0 NOT OPERATE IN EXPLOSIVE ATMOSPHERES Do not operate this product in the presence of Flammable gasses or anesthetics. Explosion can result. Refer to safety documents NFPA S6A, Standards for. the ait ©ppR. 1985 PHYSIO-CONTROLUse of Inhalation Anesthetics, and NFPA 70, National Electrical Code (Health ities section}, betore operating ents product in Me-eessint ee flanmable gases or anesthetics. , mene USE ONLY SAFE METHODS OF INTERCONNECTION To protect against electrical shock from the product cabinet whenever auxiViary equipment is electrically connected to this product, proper. grounding “fz essential. When this product is connected to other line-operated equipment, battery operation should be avoided. If it cannot be avoided, the product ‘ust be grounded using the terminal provided on the rear panel. it is extrenes ly important that equipnent interconnections be made in accordance with NFPA No. 70-1981, National Electrical Code, Article 517, Health Care Facilities, Compliance with paragraph 517-80 and 617-120 1s especially important NOTE: Within certain governmental jurisdictions, all__ interconnected accessory equipment must be labeled by an approved testing laboratory. After interconnection with accessory equipments Teakage current and grounding requirenents must be maintained. SERVICE Conponent replacement and internal adjustments mist be made by personnel qualified by appropriate training and/or experience. D0 NOT MOUNT PRODUCT DIRECTLY ABOVE PATIENT Place the product in 2 location where it cannot harm the patient or others should it fall from its shelf or other mount. USE ONLY RECONMENDED ACCESSORIES To promote patient safety, use only accessories recomended and/or provided by Physio-Control.. USE ONLY RECOMMENDED STERILIZATION METHODS Do not autoclave this product. D0 not autoclave any Physio-Control defibrillator paddles. Many accessories can be severely damaged by autoclaving. Pediatric paddles and sterflizable paddles may be gas sterilized. A product that has been dropped or severely abused should be checked by ersomely qualified "by" appropriate tretning and/or’ experience, to. verity roper operation and acceptable Teakage current values. xiv ppp. 1985 PHYSTO-CONTROL12. SECTION 1 DESCRIPTION ‘OVERVIEW tion describes the general features and specifications and provides circuit. descriptions. for the LIFEPAK @ Cardiac. Monitor, Beribrittator, and Pacing Cassette. The section is divided into three parts: "Physical Description. provides. a general description of the PiFEPAx 9 vand ists spectficationsi Functional Description. briefly describes the LIFEPAK 8 etreuttry at a functional block Tevel;. Theory of Operation provides detatted ctrcute descriptions atthe component. Tevel PHYSICAL DESCRIPTION The LIFEPAK 8 is a modular systen designed to be flexible and expand- able. The Monitor may be used as part of the LIFEPAK 8 System or as a compiete stand alone ECG monitor/recorder. The Honitor can interface with a central station or computer and can accept other Physio-Control monitoring nodules and display their information. An internal battery assures that operation will be continuous, even in the event of an ac Power failure. Recordings my be delayed, real time diagnostic, or automatic upon alarm, Because of a built-in 10 second delay, alarm recordings capture pre-alarn events. The LIFEPAK & Defibrillator incorporates a synchronizer for cardio Version, special low energy selections for open heart or neonatal application, and the capability to accept and power an external trans~ chest pacemaker "cassette." Another cassette allows the rapid use of disposable defibrillator paddles, anterior-posterior, and. internal paddles while leaving the standard adult external paddles connected and ready for use. Pediatric paddles slip over the standard adult paddles. The Defibrillator module also has its ovn internal battery. at Cher. 1985 PHYSTO-conTROLSection 1 Description FIGURE 1-1. LIFEPAK 8 MONITOR/DEFIBRILLATOR/PACING CASSETTE 12 © ppp. 1985 PHYSTO-CONTROLSection 1 Description TABLE 1-1 LIFEPAK 8 GENERAL SPECIFICATIONS (CHARACTERISTIC “QUANTITY OR SPECIFICATIONS ONTTOR fe 1wuT (© PATIENT CABLE LENGTH (© COMMON ODE REJECTION © CARDIOSCOPE DISPLAY size ‘Sweep Speed Frequency Response (~348) ‘© RECORDER DISPLAY Paper Size Paper Speed Recorder Hodes Frequency Response Annotation (© HEART RATE METER (© HEART RATE ALARHS © &c6 OUTPUT (© FREEZE CONTROL Isolated ECE via QuikcLook Defib- rillator paddles when ECG Monitor is connected to Defibrillator. Isolated Ecg via 3, 4, or 5 lead patient cable, 6 pin patient cable connector. 4,0n (13. ft); cable 3.1m (10 ft), leads 1am (3 Ft). 100d8 minimum with respect to chassis ground with 51 k% imbalance at 60Hz. 65dB. minimum with respect to isolated ground. 76mm (3 in) x 102m (4 én). 25 stmn/s, 50 =2nm/s Liz to 30lz, 50mm x 30m (100 ft). 25 Inm/s or 50 +2nm/s Real time, or delayed by approxinately 5 seconds. ,05Hz to 100H2 (DIAG); .1Hz to 30H2 (oetay). Includes time, date, recording mode, Jead, gain, heart rate, defibritiation, and pacing’ paraneters, and markers for alam and event. 3 digit readout displays rates from 20 to 300BPM. +3 BPM or 4% whichever is greater. User selectable alarm limits. 80-2408PM; Low 20-100BPM, 1v/mv, .05Hz to 100H2. High Momentary push button switch, 13Section 1 Description TABLE 1-1 (Continued) LIFEPAK 8 GENERAL SPECIFICATIONS CHARACTERISTIC QUANTITY OR SPECIFICATIONS © EVENT CONTROL @ CALIBRATION (© POWER souRCE AC Input Options Battery Type Battery Capacity © LOW BATTERY INDICATOR (© BATTERY CHARGING INDICATOR ‘© BATTERY INDICATOR (© BATTERY CHARGE TINE © SERVICE INDICATOR (© NAKTHUM POWER CONSUMPTION size ‘© NeIGHT Momentary push button switch which causes Recorder to run 20 seconds With full annotation. "If Recorder ts running, will” mark strip. with annotation, Momentary push button switch simulates 1 mitlivolt signal to. preamplifier. Nominally 120Vac (90Vac minimum, 129Vac ‘maxirum) or 240Vac (198Vac minimum, 264Vac maximum), 50 or GOH. Nicket-cadnium, Typically 2.8 hours continuous cardioscope monitoring or 1 hour of continuous recording (or any linear combination) at 25°C with a heart rate of 60 and 2 1.5cm cardioscope display. Indicates low Monitor battery. voltage level of Iluminates when battery is charging from line power. TMuminates when instrument is powered from battery. 20 hours for depleted battery. Indicates continuous _se1f-dtagnostic routines have detected improper operation requiring service attention. 26 watts during cardioscope nonitor- ing. &5 watts while recording 26.7om L x 24.1em W x 28,60m H (10.5 in'x 9.5 in x 11,25 in). 7.5kg (16.6 Tbs). DEFIBRILLATOR “OVAVEFORN 5 miTlisecond monophasic pulse (Edmark) per AAMT Standard. 41998 PHYSTO-CONTROLsection 1 Description TABLE 1-1 (Continued) LIFEPAK 8 GENERAL SPECIFICATIONS (CHARACTERISTIC ‘QUANTITY OR SPECIFICATIONS ‘© OUTPUT ENERGY (Delivered) External paddles: 1,2,3)4,5,6,7,8,9, 10,20,30,50,100,150,200,300,360 joules. Internal” peddles: " 1,2,3,4,5,6,7,89, 10,20,30,50 joules. Defibrillator’ out put electrically isolated TEST LOAD Verifies energy delivery accuracy (215%) and timing (within 30ns) at 100 and 360 joule settings. (© CHARGE CONTROL Independent momentary push _ button controls on front panel and Apex paddle. (© CHARGE INDICATORS Flashing lamps on paddle and front panel along with increnenting digital display indicate charge in progress. Upon full charge, AVAILABLE ENERGY message illuminates and a tone sounds. Three digit display shows eneray available for discharge. (© CHARGE TINE Charge to 360 joules in Tess than 10 seconds at 25°C when ac operated, or dc operated from a fully charged battery. Charge to 360 joules in less than 12 seconds when dc operated after 15 maximum energy discharges. (© OUTPUT PADDLE Electrode Area 82 ont, Cord Length 3m (10 ft). Discharge Controt Discharge controls on both paddles in © DEFIBRILLATOR srncHRONIzER | Synchronizes Defibrillator pulse to patient-generated R wave. Sync Indicator Marker on cardioscope display indi~ cates sync detection. Syncronized Discharge Defibritlator will discharge within 30 ms after application of the sync pulse to the Defibrillator. — (ANSI/ AAMT DF2 1982 section 3.2.1.23). Sensitivity control Monitor ECG SIZE control acts as 1 npr. 1985 pyysto-contprySection 1 Description TABLE 1-1 (Continued) LIFEPAK 8 GENERAL SPECIFICATIONS ChaRacTERISTIC| QUANTITY OR SPECIFICATIONS © BATTERY TYPE Nickel-cadmium battery. fe BATTERY CAPACITY Typically twenty-five (25) 360 joule discharges at 25°C, (Also applicable at 20°C.) © LOW BATTERY INDICATOR Indicates low voltage level of Defib- rillator battery, (© BATTERY CHARGING INDICATOR | I1Tuminates when battery is charging. (© BATTERY CHARGE TIME 20 hours for depleted battery. © SERVICE INDICATOR Indicates continuous se1f-diagnostic outines fave detected improper operation requiring service attention. © AC INPUT OPTIONS Woninally 120Vac (90Vac minimum, 129 Vac maximum) or 240Vac (19@Vec mintsun, 264Vac maximum), 50 or 60H2. (© CASSETTE RECEPTACLE Accepts cassettes which allow use of other paddles (internal or disposable) or pacing capability. (© HAXTHUH POWER CONSUMPTION 160 watts during Defibrillator charge. 25 watts on standby. eo size 24.8 cm L x 26 cm W x 27.9 om H (8.75 fn x 10.25 in X il in) © WEIGHT 8,91 kg (19.6 Ibs) ENVIRONMENTAL (Nonitor/DefibriTiator) (© ATMOSPHERIC PRESSURE Seoety to 7a7mMy (11,000 to. -670 eet). © RELATIVE HUMIDITY 0 to 95% (noncondensing) at 0-34°C. 0 to 80% (noncondensing) at 34-85°C, (© TEMPERATURE 0% to 45°C operating, -30°C to 65°C storage PACING CASSETTE (© RATE RANGE, 40 BPM to 90 GPM (+12) in six discrete steps ©ppa. 1995 PHYSTO-CONTROL 1-6Section 1 Description ‘TABLE 1-1 (Continued) LIFEPAK 8 GENERAL SPECIFICATIONS CHARACTERISTIC QUANTITY OR SPECIFICATIONS ‘RATE ACCURACY “TIE over entire range. Monophasicy truncated, _ exponential ourur current pulse with 15-25% decay. PERK OUTPUT CURRENT 0-200nh =15% (cont nuously_ adjustable) oremcon for Toads. between "0 and “S00 chns- © ouTPuT PuLse ouRATiON 20 sins. fe sensitivity Demand mode R wave detection supplied by Monitor. Denand and nondemand modes require use of Monitor. (© REFRACTORY PERIOD 340 ms 108, (© PACING ELECTRODES QUIK-PACE self adhesive electrodes, e wersHT 0.5 kg (1.1 Ibs) © LEAKAGE CURRENT 1OuA source maximum, 20yA sink maximum, (© DEFIBRILLATION TOLERANCE Wil] withstand a 400 joule discharge across pads shunted by 50 ohn load without ‘damage to pacing electronics. (© POWER REQUIREMENTS Supplied by Defibrillator. (© POWER CONSUMPTION 0.3 watts standby. 1.5 watts average acing at 60 stimuli ‘per minute, 500 ohm Toad. ‘Specifications subject to change without notice. AIT specifications at 25°C unless otherwise stated. 1-3. FUNCTIONAL DESCRIPTION ‘The following paragraphs contain system data and brief descriptions of both Monitor and Defibrit ator. 1-4. Monitor and Defibrillator System, The LIFEPAK 8 Monitor and Defibritlator connect by a latching fin assenbly or an accessory cable. Either method provides three optically isolated communication’ channels which carry ‘Analog Data, Tri-State Control, and Defibrillator Serial Data. Each channel is multiplexed to conserve hardware. (See Figure 1-2.) 17 npr. 1985 PHYSIO-CONTROLSection 1 Description FIGURE 1-2. OPTICAL INTERFACE BLOCK DIAGRAM 18 ©ppr. 1985 PHYSIO-CONTROLSection 1 Description fe Monitor uses a Seria]. Data Bus for Internal and. external Tremutcation. ‘Serial dove is transmitted Sn’ packets contotning from 7 forge Kytese” packets are separated by 0 nuit period during wich the Sita bus remains High eof these date packets c{rvlate around an internal loop_comecting the Honitor's three microprocessors. Refer to Figure 1-3. The Control Pea's. Executive microprocessor generates packets at reguiar intervals. The ECG slcropracessor receives. this data, makes changes, and. passes the packets on to. the Gateway microprocessor, Again changes are made as" data Is updated.” These moaified packets return to the Executive iicroprocessor and the cycle begins agains The Defibrillator also generates a data packet containing Pacing Cassette and Defibrillator status information and requests. This data is received by both Gateway and Executive microprocessors. With the Monitor and Defibrillator connected, turning on the Defibril- lator will automatically turn on the Monitor in PADDLES mode. (Note that a switch in the Nonitor may be set so that LEAD II 1s almays selected at power-on. Refer to paragraph 3-5 and Table 3-3). Monitor power is activated by a burst of serial data, containing the wake-up byte, transmitted across nomally powered optical channel ‘three. "If the Wonitor is already on, the wake-up byte 1s ignored. When Defibrillator power is on, a serial data string is sent to the Monitor at .41 second intervals. The string contains discharge status, Pacing Cassette data, and failure codes. These packets of data are coded for annotation on the Recorder or CRT alphanumeric display. Optical chenne! two is used to communicate cardioversion sync signals ‘oF QUIK-LOOK request to the Defibrillator. The Monitor then "watches" optical channel one for receipt of PADDLES/EVECLOSE carrier frequencies. Detection of these carriers establishes Defibrillator presence. and allows entry to the desired node of operation. QUIK-LOOK ECG is obtain- ed from a switched off Defibrillator when the Monitor electronically turns the paddles preamplifier power on. QUIK-PACE utilizes Monitor and Defibrillator resources to provide external transchest pacing impulses. All three optical channels support this function. Power and audible tones for QUIK-PACE are provided. by the Defibrillator. “Message printout and display, and R wave synchron ization are Monitor functions. LIFEPAK 8 system integrity is constantly tested by each of its six microprocessors. Tests include RAM, ROM, and software module check sums. Failure detection results in selective inhibition of system Performance based on the nature of the problem. Any fault detection causes a SERVICE alert to be given. Versatility of LIFEPAK 8 is significantly increased through use of two external interfaces. Both Monitor and Defibrillator function as. hosts to two optional modules: © QUIK-PACE - Noninvasive transchest Pacing Cassette 19 ©rpR. 1985 PHYSTO-CONTROLTOYINUD-UISAHE S8OL “Ag, cr VEOVTG Y007H YOLINON @ 7 “E-b BBNOLSCc 15. 1-6, Section 1 Description ‘© Internal/disposable paddles Defibrillator Cassette onitor consists of a. single trace eardloscope, dual Tread harm Gcelvates annotating recorder and digital heart vate meter LESS Tans, “le featuree.a youd display for aiphoruseric-tnformation Tn analog sionals Te ts {nnd tbe dsed for ongrtemy routine, dnd energeney monitoring.” hantear: power ay. be. obtained fromthe ac ine or an Ynternaty rechargeabie. nickel-cadaium battery pack. This battery pack 1s ers/iy resoved through the front ponels when the Monitor 1s turned on, LEAD II 4s automatically selected except when the Monitor 1s connected to a. powered-on befioriTvator. ss noted in Paragraph I-4.." Patient CG signals ve cisplayed on a nonfade cardio~ Scope which provides "5. seconds” of Information in. 25mn/sec. ode. (2.8 Seconds when S0mn/sec is selected); moving from right. to Teft across. the GRT with ‘new data added atthe right edge. An alphanumeric field presents heart rate, slarm settings, lead selected, gain, and. various messages pertaining to. system performance. - Alphanunerics’ are. arranged in either display fields, each six characters wide. AVI functions of the CRT are managed by the display controller {located on the Control PCB) which receives user comands fron front panel touch Keys. through 8n Executive wieroprocessor. Monitor operation is controlled by two push button panels that provide Togic signals to the Control PCB's Executive microprocessor. Upper Panel push buttons control ECG acquisition, alarms, and display functions; lower panel push buttons operate the annotating Recorder. Actuation of any ‘button is accompanied by tactile feedback and an electronic audible click. IVluninated legends indicate battery status and need for service. Push button functions are defined in Table 2-1. Defibritlator Performance, ‘The LIFEPAK 8 Defibrillator consists of a de defibrillator with varfous Paddle options, capability of synchronized cardioversion, and single Joule resolution in the one to ten joule range. Control of Oefibriliac ‘tor operation is implemented in to microprocessors to enhance product reliability and failure mode definition. Digital displays provide visual indications of available energy and energy delivered to an integral test load. Alerts are given to bring the user's attention to faults requiring service or to battery deple- tion. The Defibrillator may be operated in the stand alone mode;, power gd from ac Tine or an internal rechargeable nickel-cadmium battery pack. The battery pack is accessable through the Defibrillator front panel. Several possible modes of Defibrillator operation are summarized bel © DEFIB Mode - Ventricular defibriTlation mode. © FAILSAFE State ~ Charge oscillator, transfer relay, charge status indicator, and “SYNC mode indicator are. disabled;” dump relay. is 1 ©apr. 1985 PHYSIO-coNTROLSection 1 Description ad aH FIGURE 1-4. DEFIBRILLATOR BLOCK DIAGRAM 1-12 @pR. 1985 PHYSIO-CONTROLSection 1 Description © NOT READY State - Defibrillator has been charged for more than 60 seconds. Discharge is disabled and energy indicators are extin- quished but eneray on the Energy Storage Capacitor is not dumped. Depressing the CHARGE switch rapidly restores the READY state. © READY State - Energy of the selected level is stored and ready for discharge. (© STANDBY/REDUCE CHARGE - Defibrillator is awaiting user commands, is not ready to transfer, and the dump relay is bleeding charge from the Energy Storage Capacitor. Defibrillator operation is controlled by two push button panels; one of wnich has a rotary switch. These panels also carry circuitry used for display of energy information and status annunciators. Energy discharge is controlled solely by paddle discharge switches; charge may also be initiated by a paddle switch. The lower panel. push buttons control low energy settings and sync mode selection. The upper panel push buttons are used for ON/OFF control, energy selection, and charge initiation. Actuation of any push button is accompanied by tactile feedback and an electronic audible click. Push button and indicator functions are outlined in Table 2-3. Synchronized cardioversion can be selected. This feature uses the patient's monitored ECG signal (R wave) to trigger the Defibrillator discharge. The LIFEPAK B Monitor must be connected to the LIFEPAK & Defibrillator to use this feature. The synchronized discharge is used to correct atrial fibrillation, atrial flutter, or other arrhythmias. Figure 1-5 shows how, by using the R wave as the triggering signal, the defibrillating energy pulse is delivered at the proper tine. ‘This avoids the undesireable T wave portion of the ECG signal where electrical shock may cause ventricular fibrillation. DertoRnLLaring pus ‘TaloseeeD oY OeFlanuuatoR SINEHRONTZER CIRCUIT PADDLE. pusnauTTONS IEPRESSED ‘TALS Reston me FIGURE 1-8, TYPICAL ECG WAVE FORM La ©apR. 1985 PHYSIO-cONTROL14, 1-9, 110. AC Line Conditionin Firters Tine voTtage Section 1 Description ‘THEORY OF OPERATION Block diagrams in Figures 1-3, 1-4 and 1-23 provide an overall view of ‘the systen operation of the’ LP8 Monitor, Defibrillator, and Pacing Cassette as well as the operation of individual printed circuit boards Schematic diagrans of these PCBS appear in Section 5. Refer to the schematics while reading the following circuit descriptions. Section 6 contains additional information about selected ICs (indicated by a * on the schematic) to aid in circuit analysis and troubleshoot ing. NOTE: There may be more than one configuration of a printed circuit board described in this section. ANI PCB descriptive headings are followed by an identifying part nunber which also appears. on’ the PCB assembly as well as on the schematics, layout diagrans, and parts lists. LP 8 MONITOR Paragraphs 1-9 through 1-88 provide circuit descriptions for the Charger, Power Supply, ECS Preamp, Contro?, Gateway, CRT, and Anode Supply PCB Assemblies and the Recorder PFC Assembly. The Monitor Interconnect Diagram (Figure 5-8) provides interconnection data for all the subassenb] ies. CHARGER PCB ASSEMBLY (802821). The Monitor Charger PCB (see Figures 1-6 and 5-9) functions as a switch- ing power supply to maintain Tine isolation. After rectification and filtering, dc voltages are supplied for Monitor operation and battery ‘charge current. The Monitor will function even with variations in the Tine voltage from SOV to 127V RAS (domestic units) or fron 180V to 264V RMS (international units). Regulation of the Monitor's power supply voltages is achieved by pulse width modulation; the longer the pulse width from the power supply to the transformer, the higher the current output for a given voltage. The Charger PCB also controls relay switch ing. (required for battery operation), and provides charge and battery operation annunciator drive signals. AC line conditioning circuitry rectifies and Voltage is split between Cl and C2, allowing the circuit to operate as a voltage doubler. When a switch from pin 5 to pin 7 of Jl is open, peak-to-peak Vine voltage is effectively applied across bath Cl and C2 for operation on 220V line. When this switch is Closed, peak-to-peak line voltage 1s applied across Cl alone during the positive phase, and across (2 alone during the negative phase; doubling ‘the voltage for operation on 110V Tine. 20. and VR1 prevent damage from high voltage spikes. A very high voltage surge will also cause VRI to conduct so that Fl opens before the voltage on Cl and C2 increases greatly. L6 reduces susceptibility to common mode voltage spikes by presenting a high inductance to common mode currents. RTI protects CRl by limiting inrush current. Following inrush, a steady current drops the resistance of RTI from about 5 ohms La ©ppa, 1985 PHYSIO-CONTROL12, Section 1 Description FIGURE 1-6. MONITOR CHARGER PCB BLOCK DIAGRAM Bootstrap Power Supply. uring normal operation, T1 provides power to ‘UE through CS——Hovever, during start-upy. before UL begins regutating the power supply, another source of power is required. For this briet Period, C5 is charged through R6 and R7 to a voltage of about +13V, At this point CR6 conducts enough to turn on Q3. AS Q3 turns an Q4, QS Tatches on.” CR? conducts in the reverse direction to charge C6 "and power U1 (CR7's zener voltage ensures that Qé 1s turned on even when C6 is fully discharged). The bootstrap is successful when Ul remains on, due to the charge across C5, long enaugh for power to begin to flow through L3 back to transformer Tl. The high voltage at C5 maintains a forward bias across CR7 and keeps Q4 and Q3 turned on. This prevents any bootstrap pulses after successful start-up has occurred. If the bootstrap is unsuccessful (for example during very low line voltage) then C5 discharges to 3.5-8V. Q4 then turns off, turning off Q3, allow ‘ing C5 to recharge and repeat the cycle. Pulse Width Modulator. Ul is @ pulse width modulator used to regulate ‘The supply voTEage. The operating frequency is set by RIS and CB, while the minimum dead time is set by R16. Ui generates an error signal, compares it with the ramp voltage across C8, and determines the duty 115 ©ppR. 1985 PHYSTO-CONTROL113, 14, 15. Section 1 Description cycle for pulse wish sodvltion. One Input of the error amp, pin ts" comected tothe sacV reterene Voltage. "the cone ipa, ott 1," te connected 2 a veguioted B.A deleratass mea en PUB Ecasisting ‘of RID and” Mies €5, IO, and BLT Ons Hecae fsee Fequired" tor systen“stabitity. ’ the auepetecof Oh, Sacre arent romally present a Tow inpesance to grounds Noworer duit albu 22 output {ateerating with’ te other utp) weree eet meh.” Seite Serles with the Ul outpt' stage ts: revise crners Mies rae Uf protection,” Cll provides soft fart cperation cumeeh eat" Om Widths to"stomy fncresse fvom zero to'the neqiataa niee sicete Pass Prevents potentially amuging Nigh corents "hist (Bs ana” ourees fectitiers during startups "the mutator utp ase with foro bythe voltage stored oh CLI" wich To, stony. Cursed oy" acaneeeed Client souree within Vir’ Note thot a sor Gott start teams Seek ane Sootstrap ireute mst power Ul for loner period of" ciar Gate Drive/Power Switching. Two switching FETs, Ql and Q2, are used in HE HATT-ortage Supply Since a BOO al ference in source’ voleages can exist, T2 fs required to couple the gates to UL, maintaining isolation. Between pulses, 12 reflects a low impedance fron gate to source for both QL and 2 keeping them off. For any given pulse, @ positive voltage is applied gate to source for one FET, and a negative voltage is applied to tthe other due to the winding polarities of T2. Gate drive signals are prevented from exceeding the 20V gate to source maximum rating of the FETs by CRZ or through CRS. RB and RS control the speed of turn off and ‘turn on, which reduces ringing, preventing unwanted very high frequency oscillation of Ql and Q2, C3 provides a high frequency current return path to the storage capacitors Cl and C2, which ensures that the dc Current through the transformer is always zero. C4 and R5 reduce the amplitude and duration of leakage inductance caused ringing which might otherwise damage Ql or Q2. F2 is used to protect Tl. Rectifiers/Fiiters, This circuitry provides rectification, f¥lterings voTtage Timiting. Resistors R24 and R25 are also used’ for current Timiting in the event of a fault affecting the nomally very low current sense output, The inductors L3, L, and LS are used not only for Filtering but for regulation as ‘well. These inductors average the ‘output pulses to derive a pulse width dependent voltage. When there is ‘no appreciable Toad however (such as when the Monitor is turned off) the Inductors lose their regulating effect, and the filtered voltage can rise to nearly equal the transformer output. However, CR23 and CR24 prevent the +21V and +30V lines from rising above 425V and #39V, respec- tively, C12 and R20 provide additional protection of CRIS’ and the switching transistors. High Line Shutdown. During Tine voltage surges, the rectified Tine Yottage may rise to levels dangerous to Q1 and Q2, But not high enough to cause either varistor to conduct and open Fl. To increase their resistance to these line voltage surges, Ol and (2 are kept off by the high Tine shutdown circuit. CR@ and CRS are 200V zener diodes. If the rectified line voltage rises to approximately 7 volts above the conbined CRB and CRO voltages, enough current flows into U1, pin 10, to cause UL to automatically shut down. CRIO protects the input voltage at U1, pin 10, preventing it from exceeding a safe level. 116 ©npR. 1985 PHYSIO-CONTROL1-16. 1. Section 1 Description attery Charger, US 1s an adjustable output voltage regulator con- Here Bee current source to charge the Honiton battery pack. Tt Tpaurtes by maintatning’s ic? to Lav drop Between the sense pin and the soerat pias the curvent. through RIE which charges, the buttery must Seite idan tor dk” QS uses, the sane 12 to 1.2 supply fron US, WSeener with ao to produce 18.904 to" 720k current source only wheh ete" rent ts Flowings” This provides erive current for the front panel otGe LED. ery Relay Control, The relay control circuitry has a number of Sapettaee"St-artves:the relay colt with a constant current even though THe Eiopty volcageeay ronge from to to v251. Tt turns on the relay wien initial full voltage eo the relay coil, it emediately turns off whe" cuprent. to the colt when ‘the Se supply voltage drops Delon +16 {to Glow bavtery’ operation to begin before the. paver supply” shuts Som) Pinatiys Ye prevents the relay drive fron turning on again anti] the’ Sippy voltage rises back up fo approximately #21¥. The relay control circuit drives the relay coil with @ constant current source comprised of USA, USD, R21, and R39. Current is set at 11.3mA by the base-emitter drop’ across U6D through R39. U68, with C16 and R26, disables the current limiting, allowing full voltage across the relay coil for the first 10 to 20ns.’ Q5 will not turn on and cause the relay ‘to open, until CRI7 and CRI9 conduct (so +21V mist exceed 420.1V plus the base-enitter drop across 05). However, when Q5 turns on, which turns UGC on and shorts out CRI7, so that the +21V supply must fall to below #15V plus a base-emitter junction drop before Q5 will shut off allowing the relay to close and operate the instrument on battery power. CRIB is included for protection. Battery Operation Indicator (LED Drive). This circuit, supplies a con- Stunt LarPent tothe Fant poner BRTERY LeDe menever ene rior 16°R ‘and operating on battery power. 9 turns on when +15V CRT is present (Monitor on) and Z1V is not present (Tine power not connected) So that Q9 gets its base drive from Rél. When 9 turns on, it draws about 20mA and the voltage drop across Ra2 ‘turns on Q10. QO then starts to deplete the base of 09, thus limiting the current through Q9. When operating from line power, *21V is present and reverse biases CR27. The base drive to Q9 is shut off, and no LED current flows. The same LEDs are used to indicate battery operation and are Iit when the Monitor batteries are charging. CRZ2 prevents reverse current flow between the LEDs which iVluminate BATTERY and the two LEDs which {l]uminate CHARGE. POWER SUPPLY PCB ASSEMBLY (802815), The Monitor Power Supply PCB (see Figures 1-7 and 5-10) consists of ‘three functional sections each of which appear on a separate sheet of Figure 5-10. Sheet two, the main power supply, provides nine different regulated supplies (six'different voltages) all derived fron #21V UNREG (From the Charger PCB, Figure 5-9) by means of a flyback converters sheet three consists of Defibrillator Interface circuitry used for the serial data and sync channels; and sheet four consists of voltage ‘monitoring, a microprocessor watchdog, and an audio amplifier. 17 ©apR. 1985 PHYSTO-CONTROL1-20. 121. 122. 1-23. Section 1 Description Latter Protacton/iferege Voltage. | Power to. this assembly te Stop fe-oy SON UAREES“THE-YTABE range’ on Tinepone Stas (5 4261. “hen the instrument. operating_on batteries tts range is fron Ov to about s24v."” Gland CRI shut off battery current ‘wen battery voltage drops below approxinately +13¥" to. protect the micad. batserieg from excessive draining. When the battery output voltege ts above s131> Ok provides Pover fo reuters wich ton outs Be 48 INSk HS 1 used’ to power the Tow power OW/OFF and WARP etrcuttry. an ‘supply @ reference voltage. po ee STOBY FOWER 1s used to drive the real tine clock on the Recorder PFC. ihe #211 INES Ts ico Tow and‘Gh offs Gf Tanks Tite Olan Teatone Siode,_al¥oring a 1ithium battery on the’ Recorder PFC“ ta' supply Sts) POWER’ without having current. flow Into the <5 GN supsty. iNer the SEL UME. Tine 1 shove "IO, GE al fons 4.0 t0 be supplied for STD8Y POvER, caving’ the Iithiun batiery.” han the pore supply trted ene Geis tured. on abvoving the fail voV UNEL"tD: be Supplied Yor ST08Y Hove, and pernsting prover Sntertacing ot the veel lee clock with ther powered up circuits, On/Off Control, Flip-Flop U2B determines the on/off state of the power Sptys the ‘input fs from the ON front panel key which when pressed, switches this line to ground, UIA through UIC debounce this Signal so only one toggling of U2B can occur every 10Gns. When U2, pin 13, goes high, Q5 is turned on. This supplies power, VSW, to enable operation of the ‘transformer drive circuitry, turning on the supply as well as other circuits. UD, and timing circuit R5 and C2, insures that the power supply will initially be off when +21V UNREG is rapidly brought up. Low Battery Detection. The battery voltage monitoring circuitry is used forwarn- of impending battery depletion, or to protect the battery by shutting off the Monitor. G4 insures that this circuitry uses battery power only When the power supply is on. CR21 insures that a low battery Noltage is "disregarded as long as the #21V UNREG is a higher voltage than the VBATT Vine, indicating the Monitor fs running on ac Tine power. Resistors RNG, R23 and R24 divide VBATT for comparison with +5V UNSW. LOW BATT 1s generated at U3C, pin 14, when VBATT is less than 17.7¥. U4A uses this divider reference to detect when VBATT is Tess than 15.1V, at which tine it resets U2B, turning off the Monitor. R26, C9, UIE, and UIF prevent’ the Honitor fron being turned off until UA has sensed & low battery condition for at least .5 seconds. Transformer Output Rectifiers and Filters, Transformer Tl drives 2 Yarlapte Frequency flyback converter. Wien current flows in the primary Winding, the secondary rectifiers are reverse biased and no secondary current flows. This primary current is then shut off and the flux that has built up in the core induces a corresponding current in the second- ary windings and in the now forward biased rectifiers. A triangular Current pulse 1s delivered through diode rectifiers CRI3, CRIS through R20, tol the output Filter capacitors C18 through C25. The longer that voltage is applied to the primary, the higher the peak primary current will be, and the greater the eneray transferred during each cycle. Using various taps of the secondary winding produces the different voltages needed. 1-18 ©qpR. 1985 PHYSTO-CONTROLSection 1 Description Siete aoeepo! FIGURE 1-7. MONITOR POWER SUPPLY PCB BLOCK DIAGRAM 1-19 ©npr. 1985 PHYSIO-CONTROL1-24, 1-25. 1-26. 127, Section 1 Description Transformer Drive. Q10 and O11 are used to switch current inthe ‘primary on and off. When the transistors are turned on, primary current amps up from zero to a current (up to 20 amps) determined by the on time, When Q1O and O11 are shut off, @ small leakage inductance in the transformer tries to keep current flowing through 10 to O11, instead of transferring this current entirely to the secondary side. This results ina voltage spike from the drain to source which could damage the FETS. R12 absorbs that current and protects the FETS. Flyback Detection and Oscillator/Tiser. The osciTlator/tiner circuitry ‘Getermines the primary covl on tise, The length of the ott tine 1s determined by the flyback detection circuit, Peak efficiency is assured by causing the osciliator/tiner to wait until the end of flyback before turning on. 9 holds the FET drive off as long as there is @ positive voltage at Ti, pin 12. C7 is used to speed up the turn on of (9. CRI? insures that there is always enough voltage at Tl, pin 12 during flyback to turn on Q9, even at start-up, when all the caps are discharged. Control Feedback, The contro) section generates an error voltage at aE, pin 7, which is used by the oscilletor/tiner section to determine ‘the'Tl prinary on time. The higher the error voltage, the longer the primary on tine, and the greater the power output. The +5V supply is applied to UAB," pin 6, and compared with the +5V UNSW reference. | The resulting error voltage varies inversely to the +5V supply. The feed- back circuit, RNG, C13, and Cl2, provides stability and response time. CRIO and CRIL prevent ‘the output of U4B from rising mich above *9V. Long-Term Current Limit. The long-term current limit circuit normally Fasqo efector the control section. If the error voltage ‘at UAB, pin 7, remains above #5V long enough to charge Cll to above +5 UNSH, then comparator U30 turns on and pin 13 drops to ground. This quickly discharges C15. Error amplifier U4B now tries to make the #5V supply match this discharge voltage. The error voltage at UB, pin 7, drops to almost ground and. shuts down the power supply. It” also eventually discharges C11 to below *5¥ UNSW and the voltage on C15 is allowed to rise back up to +5 UNSW again. This cycle will repeat itself until the abnormal load is removed. Note that an error voltage greater than +5V ‘corresponds to @ power output greater than S5W. Defibrillator Serial Data Receiver. This circuitry receives Defibril- ator signaTs etther through the optical interface, when Monitor and Defibrillator are mechanically connected, or through @ SYSTEMS connector cable. For optically received data, DEFIB CABLE goes high allowing data to pass Inverted through U320. "The +5 UISN is connected to the collector Of a photo-transistor in the optical interface, DEFIB DATA 1 to the emitter and DEFIB DATA 2 to the base. The 200k2 resistor, RNG, increases. the speed of the photo-transistor while decreasing its 'sensi= tivity. With about 0.6nk of emitter current through the 4.98k resistor, Used, pin 5 goes high. Therefore, when light is detected, both inputs of U32D are high. The resulting’ low output is passed through CR1O2. 1-20 ner. 1985 PHYSIO-CONTROL »1-29, 1-20, 1-31. 1-32, Section Description The anode of CR21 can also be pulled Tow by U2i during cable operation ‘since 1t 1s ORed with U32D. Having the SYSTENS cable connected grounds DEFIB CABLE which disables U320. Opto-isolator U21 provides electrical Ysolation between the Nonitor and the Defibrillator during cable opera: tion. From either the anode of CRIO2 or U2l, pin 5, the data signal passes through two inverters, U32A and U22A, which are powered by +5V. The signal can then interface safely with other +5V digital circuitry. R126 prevents misoperation of W22A {f +5 UNSW and +5Y are not close in value. Wake Up Message Decoder, The purpose of the wake up feature is to ‘How turning of of both the Honitor and the DeftbrilTator by pressing only the DefibrilTator ON button when the two are connected. The wake Up message decoder looks for a string of four alternating ones and zeroes, delivered at exactly 244 Baud, equivalent to four cycles of a 122H2 ‘square wave. when this happens, counter U30 is clocked four consecutive times without a reset, and the third bit (03) goes high. Fhis causes the monostable multivibrator U29B to fire a positive pulse which turns on the Monitor by setting U2B. The monostable multivibrators U28A and U28B are set so that when their outputs are NANDed together, a logic low pulse is generated concurrently with the clock pulse from U29A which only occurs for a 122 Hz square wave. If the reset input is only enabled during the clock pulse, and the WANDed signal is used for the reset, then reset does not occur and the counter counts up. If anything other than a 122Hz square wave is, detected, a reset will get through and the counter will not set the ‘third bit. Wake Up Suppression. The wake up suppression circuit allows the user to Tinr-off the Wonttor and keep it off without disconnecting ¥t: from the Defibritiator. When the power supply turns on, U32C detects the pre- sence of the *5V supply and sets flip-flop U27. This prevents U29B from delivering any more wake-up pulses. U27 cannot be cleared until the Q output of UZ6 goes low. 26, a retriggerable monostable mlti- Vibrator, will remain set 234ms after the last Defibrillator serial data pulse is received, which happens when the Defibrillator is turned Off. " Therefore to have the Defibrillator turn on the Nonitor, the Defibritlator must be cycled fron off to on. Syne Signal Encoder. The sync signal is frequency encoded. SYNC ‘GHRANELEMBLED Ts"an eh signal, wit le the SIN PULSE stonal Ts 324n@. Counter U23 provides @kiz and 32kiz signals by dividing the IMiz & clock. | U24 and U22B gate these signals according to the SYNC ENABLE and S¥NC PULSE inputs. Interface Drive. The interface drive circuit provides sync data, of ‘appropriate signal amplitude, to the Monitor optical coupler. When’ the sync channel is enabled, an Bkiz SYNC ENABLED signal is fed to the interface. A 32kHz signal that represents SYNC PULSE 1s gated to the ‘optical coupler whenever an R wave is detected. The Defibrillator receiver circuits are designed to detect narror, high intensity infrared pulses. 121 ©ppR. 1985 PHYSIO-CONTROL1-33, 1-34, 1-38, Section 1 Description The output from syne signal encoder U24B, pin 6, 1s applied to trensie= tor eter G21. "en Eee "in fs. hghy Geb te oets ae Gs urned on, the “infrared drivers receive’ Osh peak current spike has a decay time constant by 1.5us. me alee R105 and CHOS insure that the 1.518 tine constant. 1s matntained even with the OPTO SMMC and SINC CABLES disconnected. #08 and C112 desoupta the'ariver etreutt fron the S8V paver Supply for nolse Peauction” Audio Amplifier. The audio amplifier circuitry is based on U201, an ‘integrated 1-28 ousio amplifier, Input signe from attage Somes. of ALARM VOL are first. bandpass filtered before being’ summed at pin} (signals will appear at only one input at a tine). Gain is set by R307 to about 348 (gain of approximately 50). Capacitor C304 Tinits. the hhigh end response to 20kitz, The cutput goes through connector a2 to an 8 ohm spesker. Watchdog. The watchdog circuit monitors the Executive microprocessor {UE, Control PCB, see Figure 5-12) or ‘errors in the program operation: If an abnormality is detected, the SERVICE legend is i1Tuminated and the Executive microprocessor is reset. During normal operation, a 100 to 125Hz signal, with a 60us pulse width, is present at WD RESET.” A retriggerable monostable multivibrator, Ul02, with a pulse width of 16.9ms, is held in the set condition only as long as the WD RESET is of the proper frequency. A decrease in the retrigger frequency would allow the WATCHOOE to reset thus stonal ing. a progran fault. Should the MO RESET increase in frequency, or become stuck high, C203 will begin to charge through RNS. These’ components are connected to U102 (reset), pin 9. If the voltage at Ul02, pin 9, is high enough, the WATCHDOG wiTl be reset and again signal a program fault. The Q output of U102 is high in normal operation and transitions low When faulty operation is detected. When Q is Tow, Q31 is turned on to provide a high current +5V source for other Monitor circuitry. Note that ND and WDG Q are of the sane polarity. Noltage Monitor. The voltage monitor circuitry is intended to prever inpredictabTe Behavior which may occur when power supply voltages. drop. Tt also assures predictable start-up behavior. During start-up, both ESET and STANDBY start out low. A few niTli- Seconds into startup, the supply voltages have risen ‘and comparators UIOIA, VIOIC, ‘and UIGI0 ‘shut ‘off and C202 starts’ charging through RZ S90}, Soan after, VIOIB shuts off and’ C201 charges. through RIG 1004 ggg ta sealler Re ioe constant, C201 chargee Fiat a0 that ‘the STARDE? line goes high first. The RESET line goes high about 100ms Tater. During operation, small drops in the +5V supply (to just below 4.7V) will ‘cause the STANDBY Tine to go low, and freeze the microprocessor. Greater drops in voltage will cause a full reset. 12 ©npR. 1985 PHYSIO-CONTROL 51:36. 1.37, Section 1 Description ECG POB ASSEMBLY (802833). The ECG PCB (see Figures 1-8, ECG PCB Block Diagram and 5-11) is the primary processor of patient generated electrical signals. Circuitry is, provided for gzin control and filtering of these signals so they may be used in the rest of the LIFEPAK 8. A microprocessor controls all ‘operations performed by the ECG PCB. The microprocessor exchanges information with the Gateway and Control PCBs through the serial data Toop. In addition the ECG PCS performs the following functions: R Kave detection, sync pulse generation, heart rate calculation, demodulation fof QUIK-LO0K ECG, electronic lead selection, leads off detection, and heart rate alarms. ECG Microprocessor. The microprocessor, UI9, is a 6301, 8 bit single ‘thip-aicroprocessor with 4K bytes. of internal ROM. This memory space contains the special purpose program that is required for control of €CS Preamp PCB signal processing. The microprocessor clock 1s derived from an external 4iliz crystal, Yi. The RESET line, fed from the Honitor power supply to U9, pin 6, is held low for the First 100ns of power application. When RESET goes high, the microprocessor latches 1/0 Port 2, bits 0, 1, 2 into the program contro? register, selecting mode 5 (nonnultiplexed/partial decode) which prograns ‘the T/0 ports as follows: Port 1 Port 2 Port 3 Port 4 Paraliel 1/0 only, U19, pins 13-20 Parallel and seriat 1/6, U19, pins 8-12 Data bus, U19, pins 30-37 A(0-3) and input only, U19, pins 22-29 The starting address of the program is also loaded into the program counter when RESET goes high. Also at power-on the state of DIP switch SI is read by UI9, pins 14 through 17, to configure software, Sl-1 (the rocker switch closest to the rear of the Monitor) selects 50/60Hz notch filter for PADDLES (open = 60liz). S1-2 through S1-4 should also be open during normal operation. Circuitry connected to the data bus is selected and enabled through decode Togic. The dual multiplying OAC, UI7, is selected when E and Al are high and 10S is low. U16C, pin 8, goes Tow, enabling date to be written to DAC A or 8 depending’ upon the state of A(O). Data is read from analog to digital converter, U29, when E and AZ are high and 10S is low. This data is manipulated by the program for R wave detection or digital filtering as required. Serial data packets from the Control PCB, pass through U19 carrying information about the Honitor system, Alarm limit, CAL, SYNC ON, GAIN, and PACE ON information is loaded into the microprocessor. HEART RATE, ALARM HIGH, LOW TRIP and LEADS OFF are sent out to the Gateway PCE (See Figure’ §-13). 1-23 ©apr. 1985 PHYS1O-CONTROL(TocoNTROL PCaSAA OREAR PANEL) FIGURE 1-8, ECG PCB BLOCK DIAGRAM 1-28 Section 1 Description © npr, 1985 PHYSTO-CONTROLc 1-38. 1-39, Section 1 Description Inputs and outputs of the ECG microprocessor are listed below: QRS = software detects and sends out at UI9, pin 20. SYNC Pulses are ‘generated within U19 and delivered through pin 19. CAL - active when the user wishes to inject a known signal into the preamp. LEAD SELECT - outputs enable the user to look at the patient's ECG through different lead combinations. Port 1, bits 1, 2, 3 provide a LEAD SELECT word that is decoded by the isolated preamp’ enabiing certain Yeads to be processed by the Monitor. LEADS/PRODLES - enables switching circuits for routing lead or paddles ECG through the system. EYECLOSE ENABLE - active whenever the Pacing Cassette is on; allows ECS to be disabled during pacing pulse and is also used during fast restore. = is fed to the ECG baseline restore circuit whenever 2 new lead is selected. EVECLOSE - received from the DefibriTlator when a pacing pulse is inminent. OVERLOAD - is received when the baseline restore circuit is triggered. Isolated Poner Supply. Isolated dc voltages are necessary to protect he patTert- fron hazérdous leakage currents. Circuitry in the isolated preamp requires +15V and -15V. Nonisolated +15V is modulated into a B4.5kHz square wave and transformer coupled to a full wave bridge rectifier in the isolated secondary. This rectified signal is then filtered for use by the isolated preamp. The 34.5kHz transformer drive, applied to the primary of 12, is generated by a triggered pulse’ width modulator, U6. A 69kHz square wave, applied to the gate of Q2, is obtained from counters U22 and U23 Which are configured to divide the Miz clock by a factor of 58. The Grain of Q2 is tied to a network that triggers US to operate at 34.5kiiz. Diodes ¢R6 and CR7 clamp the UG outputs to +15V for protection from voltage transients. The isolated 24.5kHz, present on the center-tapped secondary of T2, is applied to a full wave bridge rectifier, CR3. Positive signal excur- Sions at the ac inputs to CR3 are stored on C16 and become isolated 415¥dc. Negative swings are stored on C17 and becone isolated -15 Véc. Isolated Preamplifier, The isolated preamplifier provides input buffer- ‘ing, lead sefection, common mode rejection and. patient protection fron Teakage currents. The output ECG is modulated and transformer coupled across the isolation barrier for additional amplification and signal processing. ECG signals are coupled into the preamp through J3, from a three, four or five lead cable attached to patient electrodes. Surge protectors, 1-25 ©npR. 1985 PHYSIO-CONTROL1-40, Section 1 Description VSP2 through 6, prevent introduction of large voltages to the preamp during delivery’ of a defibrillation pulse. U12, 2 monolithic quad op amp, is a unity gain buffer. The outputs of Ul2 are applied to the Wilson network, RNS, a sunming array. The sum fractions, available at ‘the various outputs’ of RNS, correspond to different lead’ combinations; AVR, AVL, AVF, and V. Leads I, II, and IIT are not sumed through the Wilson network. Lead selection is accomplished electronically by the efght channel ana~ og demultiplexers 38 through U40. A three bit control word, supplied by the ECG microprocessor, is applied to the opto-isolators U25 through U27. A high on pin 1 of CNY65 (U25 through U28) turns on the internal transistor, grounding one of the control lines of U38 through U40. If any opto-fsolators are off, pull-up resistors in RWIO, force these Control lines to +15, enabling a selected input to the analog demulti~ plexer output pin 8. ‘A truth table for U38 through U40 fol lows: Control Pins output Pin Selected 616 1 8 Lead o 00 sl Paddles/ST0 oo sz 1 er) 33 " oa sh ur 1 00 8 avR 1 01 $6 AVL 110 7 AVE aod $8 v ‘The outputs of U38 and U39 are fed to the noninverting inputs of UL, a differential amplifier with a nominal gain of 10. Outputs at U1, pins 1 and 7, are sumed together at the junction of R17 and R18 for appli- cation to the right leg drive circuit. These outputs are also applied to Us, a dual SPOT analog switch, where they are modulated by the 34,5kH2 preamp drive tapped from 12, pin 3. The modulated ECG is transformer coupled, in Tl, to the nonisolated preamp. In the right leg drive circuit the summed ECG, from R17/R18, is invert- ed, and fed to U40, pin 8. Depending upon the lead select code, the Fight leg drive is ‘routed to the appropriate patient lead. This drive cancels noise that may be induced into the Monitor/patient systen. Non{solated Preamplifier. The modulated ECG signal is fed from the Secondary oF TT to U5. dual SPOT analog switch, which switches ata Frequency of 36.5kHz and denodulates the ECG from the isolated preamp. UIA'functions as a unity gain subtractor which takes all signals common to both inputs and removes then fron the output at U7A, pin 7. Modula~ tion noise is suppressed by C19 and C20, 1-26 ©apR. 1985 PHYSTO-CONTROL1a. Section 1 Description A calibration signal may be switched into U7A, pin 5, through UlO pins 2 ‘and 3, The 10nV CAL signal is derived from a *5.1V' reference in UB and divided by RNI7. Pressing the Front Panel CAL key causes U10 to output the calibration ‘signal. ‘The ECG from U7A, pin 7, passes through Eyeclose switch, US. This switch isolates the ECG signal circuitry from pacing pulses. When the Pacing Cassette is ony switch U36 is closed between pins 10 and Il. This allows the EYECLOSE signal appearing as a high at U36A, pin 14, to bass shrough UB6 and tum U9 oft (te, UK and UBC ave opened and UBB fs closed). The ECG signal output from U9, pin 10, is applied to the non-inverting input of U7D. This op anp stage serves as a low-pass filter, elimi- nating any switch-bounce fron U9. The output. signal of U70 ‘is then passed to a bandpass amplifier that has a nominal gain of 50. Oc offsets of + 4V or greater at U78 will trigger an output from the baseline restore window detector at U30, pin 1. The resulting negative output prevents UTA, pin 7 from latching at a voltage rail condition. [At the time U30A, pin 1 goes low, Schmitt trigger USE, pin 8, will go high. The result fs an OVERLOAD'signal to the ECG microprocessor that inhibits R wave detection routines. The baseline is restored through U7C when U30A activates 04, which turns Q3 off. The ECS microprocessor closes U9D, pins 6 and 7, by activating the SHITCH SROOTH Tine for approximately 20ns in response to the OVERLOAD signal. The charge stored on C82 holds 3 on for approximately 4 seconds. USA is configured as a X2 amplifier providing a total gain of 1000, Paddles ECG Denodulator. The paddles ECS is frequency modulated and ‘passed through the optical interface or directly through an interconnect cable. Several functions are performed in the denodulator circuit: signal source selection, frequency demodulation, Defibrillator valida- tion, and eyeclose detection. Frequency modulated ECS is input through PJ, pin 2A, or Pl, pin 5B. U37 optically ‘isolates the Defibrillator cable input.” Connection of the cable grounds Pl, pin 28, which in turn pulls 36, pin 6, low. The out- put at U37, pin 3, is now switched to U36, pins 2’and 5." Paddles signal From Pi, pin 2h, is present at 36, pin 5, with no DeffbriNlator cable connected. The selected paddles signal is 2c coupled through C69 and amplified by USA and U338. Capacitor C60 decouples the output of 33 for applica: tion to the phase locked loop (PLL), U34. The PLL converts ac to dc with an increased frequency resulting in a greater dc output. The paddles ECG center frequency is 1SkKz and deviates + SkHz when actively transmitting information. A 32kHz signal is present on the paddles ECG Tine whenever the Pacing Cassette requests Eyeclose otherwise an 8kiz signal is present. The denodulated analog signal from U34, pin 11, 1s applied to amplifier UaéA,U34, pin Il, output is also. sensed by the EYECLOSE and YACTB comparators USSD and U35C. U3SC, pin 9, 1s compared to a voltage 1-27 ©npR, 1985 PHYSTO-CONTROL142, 1-43, 144, Section 1 Description reference that represents a 4kHz minimum carrier input from the paddles interface. U36D, pin 6, 15 compared to a reference representing 2 32kKz Eyeclose carrier present at the paddles interface. If either of these comparators is toggled, appropriate circuits will be enabled. LEADS/PRODLES is applied to Ul0, pin 9, and is used to select which ECG source will be present at the XY000 ECS’ output. Anti-Aliasing Filter, An A/D converter must sample at a frequency at ‘east trice that oF the highest’ frequency present” in the analog signal. It 4 possible, however, that an unwanted high frequency component of ‘the analog signal nay be sampled. Anti-aliasing filters have been incorporated to prevent this. ‘The amplified ECG signal is applied to a 600Hz twin T-notch filter made up of C27 through C30, R73 through R77, and U13A. U13B forms a 250Hz Yow pass filter. From U13B, pin 8, the ECG is sent through buffer amp U13¢ to A/D converter U29.” WD Converter. The analog ECG signal is converted to an eight bit word BP aE iyo converter. Tas chip. performs a complete. succes approximation cycle in 1Sus, as determined by the RC tine of RBB and C37. Conversion starts when the & line, U29, pin 15, goes high. The ECG’ microprocessor then goes on to other program functions and” loops back to fetch the conversion word. When RD goes low, the date is placed fon the bus, loaded into the ECG microprocessor where it is evaluated for R wave detection. Then when the instrument is in the paddles mode, the data is digitally passed through a notch filter. Gain Control and /A. The ECS PCB must provide ECG signals of appropri- See Siar tor the CH atgplay. Ore half of 8 duel multiplying OAC is used for D/A conversion so that paddles ECG may be reconstructed for CRT dis- plays the other half is an electronic attenuator used for gain control. CRT and Recorder ECG size is determined by UI7B in conjunction with Serial data decoded by the U19, 1000 ECS Is amplified by a factor of four in USB, and applied to U17, pin 18. ‘An eight bit word, representing the ECG size, is latched from the data bus Into the OAC B register when UI7, pin 16, is low and Ul7, pin 6, is high. This eight bit word is applied to a R2R network within U17 which sets the ratio for the op anp USC. In this manner, the ECG will be multiplied by a factor of one or less. This ECG signal is routed to the anti-aliasing filter and the output select switch, U14. ECG digital data 4s converted to an analog signal by UI7A. The data is Joaded, from the bus, into the DAC A register where it controls the anount’of the -10V reference that is to be amplified by UBD. This -10V reference is generated by U13D using as reference the +5.1V from U6. ‘The output of U8 is then routed to the output select switch. The LEADS/FRODLES control from U19, pin 18, selects which source is to be present on the CRT and at the ECG output jack. When UI4, pins 9 and 6, are high, XG-ECG will be fed from UBC, pin 1, and ECG OUT will be equal to X1000 ECG. In PADDLES, U14, pins’9 and 6, are low, XG ECG and 1-28 ©ppR, 1985 PHYSIO-CONTROLSection 1 Description ECG QUT are fed by USD, pin 7. This is 2 gain adjusted signal and not a X1000 ECE output. Buffering’ of these outputs 1s provided by U33D and 308, Op amp U35B forms a reconstruction filter for UL7. 1-45, CONTROL PCB ASSEMBLY (802827). The Control PCB (see Figures 1-9 thru 1-11 and Figure 5-12) consists of ‘two functional parts, the executive microprocessor and the display con- troller. The Executive microprocessor circuitry serves as the interface between’ the user and the LP 8 system. The display controller provides the timing signals and menory functions for both the alphanumeric raster and analog trace displays. 1-46. Executive Microprocessor. The Executive microprocessor, U6, provides he mode Tagie for the-entire LP 8 Monitor. This iss. HD603. micro processor with 128 bytes of internal RAM and no internal ROM. It executes software resident in the executive EPROM UI5. The micro- Processor accesses the EPROM through the eight bit address/data bus, buffered by U7 and multiplexed by U16. The upper addresses are directly applied to the EPROM and the chip select input is provided by decoder UB. This decoder is also used to address control latches and text RAM. ‘The microprocessor controls the system through three Tatches: Audio Con- tro} Latch UI7, Display Control Latch U35, and Analog Control Latch U3. The microprocessor clock consists of crystal Y1 and capacitors C9 and C10." The microprocessor divides this 4illz down and provides a 1Nz, E Clock output. This signal is conbined with the 4#Hz signal through flip-flop U9, an OR gate, and 2 inverters to provide a signal used to clock data into the mode control latches. if sft i i al FIGURE 1-9, CONTROL PCB: EXECUTIVE SECTION BLOCK DIAGRAM 1-29 ‘APR. 1985 PHYSIO-CONTROL107. 148. Section 1 Description Keyboard Interface. The Executive microprocessor and _ peripheral ‘GHevltry provide" the interface for the Nonttor Keyboord and. various signals generated by the LF8 Defibrillator. ‘The Monitor front panel keyboard is organized electrically as 3 colums Gf done switches and 1 colum of LEDS. There are & rocker switches (Service switches, $1) on the Control PO that. are also read. In order fo read the switches, U6 enables each colunn (in sequence) by applying the appropriate code’ to’ decoder U2 through port.2.. This tums on the appropriate PIP transistor (Qi through Q4) which then applies +SV to. the Switch colum, If a switch is closed, the *5V is applied to @ row which #5 relayed to the microprocessor through port 1. Port 1 acts as an input port for both keyboard end Defibrillator inputs, and as an output port for driving LEDs. The input path ¥s through RKS, the output peth is. through Uf. ‘Most of the. tine however is. spent driving the LEDS. The keys are Scanned every 8.2usec. for approximately 10s.” The service switches. and colunn 1 switches are scanned sequen~ tally, then Ins later the colum 2 and column 3 (FREEZE) switches are sinned.” The Defibrilietor inputs are scanned every 1.024ns through port 1 and tri-state buffers US and U6O (their outputs are enabled by Gecoder U2 and microprocessor port 2). Audio Interface. The microprocessor, through the tone latch U17, provides the user with audio alaras, RS beep volume control, and an audible key click each time a push button is pressed. The audio alas fare provided by gating the outputs of frequency divider U27 and pins 15 fand 16 of the tone latch Ul7 through U20C and U200. The gated outputs fare applied through resistors to amplifier U22C and then sent to an audio anplifier on the Power Supply PCB which drives the speaker. FIGURE 1-10. CONTROL PCB: CONTROL SECTION BLOCK DIAGRAM 1-30 © pe, 1985 PHYSTO-CONTROL1-50, Section 1 Description ‘The QRS volune (systole beep) is adjustable through eight tone levels by digitally varying the gain of U228. A 40ms QRS pulse AND-ed with 4kiz at U20A is applied to an R2R ladder consisting of RN7 and RNB. A three bit code from outputs 2 through Q4 of tone Tatch UI7 causes U36 to switch different resistor combinations into the input of UZ2B. This Provides the adjustable gain. The audible key click is controlled by UL7, pin 12. This output is applied to amplifier U228 through CRI4. The microprocessor applies a GOus pulse to this stage whenever it detects a push button being pressed. Display/Recorder Interface. The Executive microprocessor controls the ‘Operating mode of the Recorder and the CRT through display control latch U35. Two of the latch outputs are used as hardware interrupt enables/ disables (pins 2 and 6). Pin 2 gates the text interrupt (IR01 ENABLE) to the microprocessor; pin 6 gates the trace interrupt (| ). When UG receives a text interrupt, it updates the CRT essage fields. When 2 trace interrupt is received, the microprocessor takes 2 new ECG trace A/D sample and writes the new sample to the trace latch, U61. U35, pins 5 and 9 provide the trace FREEZE and SWEEP SPEED features and’are direct inputs to U58, the no fade gate array. U35, pins 12, 15, and 19, are Recorder control lines. A low output on pin'19 turns’ the Recorder on. Pins 12 and 15 provide the following logic when the Recorder is on: Pin 12 Pin 15 Result ° ° Megat 0 1 Delay Record 1 ° Diagnostic Record 1 1 Recorder pen railed (This only happens when Recorder is in Delay mode.) 35, pin 16, provides the sync interface enable signal which allows the LP 4 to perform synchronous cardioversion. This signal is also used in pacing. When a text interrupt is received by U6, the Executive microprocessor updates the CRT Text RAM UN7. US has access to the text RAM for a minimum of 1.0ns following the falling edge of the text update signal ‘at analog switch U13D, pin 14. The microprocessor accesses the Text RAN through data buffer U19 and address latch Ul8. The decoder UB is used to provide enable and read/write signals to the buffer, latch and RAM. The analog control latch U31 controls the low end cutoff of the ECG trace input to the cardioscope. It is used to trigger and read the trace A/D converter and to select either a peripheral device trace or the ECG preamp trace. ‘Analog Circuitry. The only analog input to the executive portion of The conerat boava 1s the Ece rece input circuit at al, pins 20k" and 1-31 ©npR. 1985 PHYSIO-CONTROL1-51. Section 1 Description 288. This circuitry consists of two gain stages and low and high pass filters. The input is selected by the analog control latch, U31. The trace signal is switched by analog switch U23A, U23B, applied ‘to an active low pass filter with a gain of 2, and then applied to a high pass filter with a cutoff frequency of ‘elther .25 or .8Hz. This is Selectable by one of the service switches on SI (Refer to paragraph 1-47). USL selects .25Hz based on input from UZ3C except when PADDLES are chosen, then USL always selects .8H2. The trace signal is then buffered with voltage follower U220 and appli- ed to A/D converter U30 which is connected to the microprocessor data bus. Trace Controller. The no fade analog display, sync marker generation, waveform reconstruction, and Recorder memory’ circuitry functions are AIT implemented by the’ trace controller circuitry and no fade gate array, USB. The E clock of microprocessor US, is prescaled by raster controller gate array, U#9, to provide U5B with a 400kHz clock signal. FIGURE 1-11, CONTROL PCB: DISPLAY CONTROLLER BLOCK DIAGRAM 132 ‘APR. 1985 PHYSIO-CONTROLSection 1 Description The duration of the no fade cycle is variable depending on the state of the FREEZE and 250ms/S0ms control lines. If FREEZE is high, then the gycle is 1024 address tines long, or about 5.12ns. Although’ there are 2048 bytes of trace menory, only 1024 of these are addressed in any trace cycle, allowing the Recorder delay to be longer than the amount of data displayed on the CRT. In order to freeze the display, the starting address of each cycle must be identical. When the FREEZE signal is low and the 25ms/SURE signal is high, the display enters a mode in which the analog data sweeps from right to’ left across the CRT at Z5m/s. In this mode, the no fade cycle is 1025 ‘addresses long with the extra address time being devoted to Recorder update. Since the address is that of the oldest data in menory at the end of a cycle, the Recorder update occurs 10 seconds after the data was acquired. In addition to allowing Recorder update, the added address ‘time causes the starting address to increase by one each cycle. Thus, the displayed franes add one byte of new data each trace cycle. As a result, the trace appears to move across the CRT. In the 50m/s mode, both the FREEZE Tine and the 25ms/50RRS line are Tow. The cycle 4s 1026 addresses long, made possible by adding another Recorder update tine at the end of the cycle. This results in the starting address of the cycle advancing by two addresses per cycle, or twice that of the 25m/s mode. The visual result is a moverent of data at double speed, or S0mm/s. Another effect of the double Recorder Update 1s that unlike the previous mode, the newest data is written into two bytes and preserved since the next cycle does not cause overwriting of the older data. This results in the delay tine of the buffer being reduced to 5 seconds. The recorder display is not affected by the double update since the data is the some in both bytes. In effect, the extra Recorder update has no effect on the Recorder, but allows a longer cycle tine with a minimum of internal circuitry. The addresses that have been discussed are internally generated in USE, ‘the no fade gate array, and are used to address memories U63 and U64. Actual analog data is stored in U64 and is controlled by US8 through the R/, NSE, and AQl Tines. U63 is essentially in parallel with U64 and 1s controled by the same signals. This byte wide memory 1s used for sync storage and eyeclose storage. The other six bits are unused, In addition, the bytes of U63 are mapped to USS on a 1:2 basis, as is evident by the fact that AO does not drive U63. Digitized data 1s presented to the memory from US, by U61, an octal tri-state latch. This Tatch is enabled only during memory write times by the no fade gate array signal LATCH OE. Data fs latched into U61 by the microprocessor's, TRACE LATCH ENABLE. The executive software quarantees that a new byte of data is entered into the latch after receiving a TRICE UPDATE signal from USS and before 5.10ns pass. TRACE LATCH’ ENABLE is generated at the end of each no fade cycle by the terminal count detection circuitry. The following are other memory control functions generated by the no fade gate array: SIGNAL FUNCTION Jl Provides memory chip select function 1B ©npe. 1985 PHYSTOACONTROLSection 1 Description RDU Defines address periods during which the Recorder is updated NSE Defines address periods during which menory is updated The data from the analog monory is bused to dual DAC, U65, which has internal Tatching. USB, pin 10 4s a power-on input signal to the US8. At power-on, this signal is low for 1.5 seconds. “When this input is held low, the functions of LATCH GE, NSE, R/R and the address line A10 change slightly. Instead of indicating the read and write intervals as defined above, LATCH OE is always inactive, inhibiting data from U6. In addition, USS, pin 4 (WSE), is always high, disebling the memory outputs,” and R/ is pulsed on every address.’ Since RNI4 pulls the enory data lines to hexadecimal 80, this value is read into all memory ‘addresses. To allow this to occur in 1.5 seconds instead of 10 seconds, ‘the conplenenting of Al0 at the end of a no fade cycle is inhibited when PUR UP is Tow. The 80 hex represents an output of zero in the offset binary representation used by USS. The result is thet the no fade RAM is cleared to prevent randon data fron being displayed at turn on. UGEA and US6C form current to voltage buffers for the CRT and Recorder DACs respectively. Output voltages range fron 0 to -5V. Components Us68, RNIS, CSB and C59 form the first stage of four pole, low pass, Butterworth filter with a -3 d8 point at approximately 37kHz.” U66B also Deavides offset and scaling of the stonel to within a range of #8V to “8. USED, RNIS, C64 and C65 form a low pass reconstruction filter for the Recorder system with a -3 8 point at 592. However, the scaling and offset of this anplifier is such that the output range is +2.5V to -2.5V. An additional function is performed by this buffer. The synthesized. syne marker for the Recorder is presented to the non- Snverting reference terminal of US60. Normally, this signal is at zero vaTts and the ECG is reproduced normally. However, when RECORDER SYNC WARK is high, the output of the Recorder buffer is driven toward the positive supply rail, generating the syne mark which is printed on the Recorder paper. Easy selection of a lon/n scale factor for European Monitors or a L.Tocm/a scale factor for domestic Monitors is provided by Sl, pins & and 9. When open, the ratio is :1 and the attenuation into ‘the CRT deflection systen {s increased, since R40 forms a divider with the input ‘impedance of the ECG buffer amp Tocated on the CRT PCB. When this switch is closed, the ratio is 1:1.7, R60 1s shorted, and there fs no attenuation. UGTA provides a means of making one gain adjustment to calibrate both CRT and Recorder buffer gains. Matching of the monolithic DACS in U65 is excellent, as is the ratio tracking of the resistors in RNIS. Thus, by varying the reference voltage to the DACs and the buffer amps, 2 Single adjustment can be used. US7 forns a noninverting amplifier with a gain of lel in series with an attenuator whose range 1s .7B to 1. The net result is an adjustable reference of approximately 8V. 4 ©ppR. 1985 PHYSIO-COWTROLSection 1 Description The remaining function of US8 is that of sync marker generation. The delayed data’ is removed from U63 and internally processed by USB to yield a single pulse at the rising edge of each sync period. CRT SYNC WARK has a duration of 5 microseconds whereas RECORDER SYNC MARK has 2 duration of 5.12 milliseconds. UGOA provides isolation between the ECG microprocessor SYNC signal and the bidirectional DELAYED SYNC line. Raster Controller. The raster controller gate array, U49, generates the ‘timing and addressing necessary for the character display. The Execu- tive microprocessor clock US, pin 40, provides the INHz signal required for timing. Internal prescalers divide this frequency to 400kHz for the no, fade gate array, "UBB, and 00KKe for the baste: character tine interval. The state of the display at any time is determined by timing signals derived from U49 and the TRACE UPDATE and MSE signals from USB. The state transition sequence and timing are outlined below. STATE, DURATION. EXTERNAL SIGNAL CONDITION TRACE 5.12ms TRACE = 0 HORIZONTAL RETRACE 1 1.26ns HRT = 15 SLOW SNP RASTER 7.560s RASTER = 0 WAIT 5.04ns TRACE = 15 HRT = 0 RASTER = 1 HORIZONTAL RETRACE 2 1.02ns HRT = 15 SLOW SHP = 0 The internal timing signals are generated by a string of counters which also generate the addressing for the text RAM during the raster state. These counters essentially count the 18 characters per column of the display (15 visible characters during vertical sweep, 3 invisible characters during vertical retrace), seven vertical scan lines per character column, and six colums. Because a character requires seven scan lines to be formed, the address sequence for a character colum must be repeated seven tines. At the end of the last character column, the display controller enters a wait state. This wait state serves two purposes: it reduces the power dissipation in the display drivers by lowering the active duty cycle and it provides a dead time to take up minor timing discrepancies between the no fade gate array and raster controler gate array. 1-35 © ppm. 1985 PHYSIO-CONTROLSection 1 Description The text RAM, U7, 1s configured as a two port memory, accessible by both the rester controler gate array, 49,” and the Executive mere: processor, U6. U18 is an address Tatch which, demiltiplexes, the. U6 fddress/data bus for accessing the dual port memory, and sso serves to fsolate the dual port nemory address bus ‘ron that of the microprocessor. Similarly, UI9 provides ‘solation between the dual port. merory dats bus and the Eiecutive mlroprocessor adtress/dats bus. "Eotral of the dual port mesory 1s granted tothe microprocessor only during the hor'zontal Fetrace periods to prevent Glsplay disruption. "A low TEXT UPDATE signal Fron UtS, pin.%, provides an. interrupt, U6 signaling. the Text ei Wire te avelTable. "ne ail other tines Uso has exclusive use of UA?” Operdtton of UA7 depends on the software in the Executive microprocessor we prover pronbied acess since the catgut enables of Ulead U8 fare under direct. control of U6. The chip select signal at U87, pin Ie, is under the direct. control. of U&S. The TEXT-UBOMTE. signal: ron U49” Pin Ii, controls UIOF and VIIA which act as a 2:1 multiplexer. ‘when the Eteroprocessor Us, has access to the text RAM, the multiplexer switches fhe master £ clock to the chip select Tine of UA7. When USS has eccess to. Us7,. the DISPLAY CONTROL ‘RAN ACCESS {OCE) ‘signal’ U49, pin Ss is switched to U7, pin 18. Addressing of U47 by U&9 is not sequential since operation requires scanning by colunn. Addressing by U6 is sequential, since messages are formed horizontally. As a test feature, jumper JB1, pins 1 and 7, and resistor, R67, are provided to continually deselect Ul7. This allows the outputs of the text RAM to be pulled high by RNI3. Since the microprocessor bus is isolated from the U47 bus during the raster display period, this selects the character code 7F hex, which corresponds to x. Removing jumper JB1, pins 1 and 7, will display all x's on the CRT providing @ regular test pattern to allow easy verification of display operation. The display requires approximately 108 bytes, only 2 small portion of ‘the memory’ available in U&7. The remaining menory is usable by US as auxiliary storage but it is accessible only during horizontal retrace. R12 provides series impedance between UI8 and U49 in the event that both I.C.'s inadvertently try to drive the text address bus simuitane- ously.” Normally the timing is such that this does not occur, however, ‘this impedence limits the power dissipation in each component should bus contention occur due to hardware or software malfunction. Gate array U49, pins 31 and 32, are signals which control vertical retrace and rastering. RASTER " eVRT controls the vertical retrace amplifier by turning it on during the 30 microseconds corresponding to the invisible characters of each column. A high signal on this line indicates vertical retrace. RASTER + VAT controls the vertical sweep amplifier by turning it on during the 150 microseconds corresponding to tthe visible characters of a colusn. A low signal on this Tine indicates vertical sweep. The blanking control of the video signal is controlled entirely by the internal circuitry of US9. In addition, it multiplexes the sync mark 1.36 spr. 1985 PHYSIO-CONTROL1-53. 1-54. Section 1 Description signal onto the OTS video signal during the trace state. The net effect 1s to superimpose a high intensity dot on the ECG signal to represent a sync mark. 49, pin 33, provides demultiplexing of the memory line in the trace controller to represent LIFEPAK 8 pacing activation. This multiplexed data Tine, PIO, 1s isolated from U6 signal Tine, EYECLOSE, by U60B. The timing signal for proper demultiplexing of the pacing signal originates {in USB and is introduced to the U49, pin 36, PACER DEMUX. The recovered data is DELAYED PACER MARK, which is sent fo the Recorder controller to be annotated. The final function of U49 is to provide a timing signal for signature analysis (SA). This signal is not used in normal operation of the LP 8 {and 4s provided solely as a service feature. GATEWAY PCB ASSEMBLY (902635). The Gateway PCB (see Figures 1-12 and 5-13) controls the exchange of data between a LP 8 Monitor and the Defibrillator, a Central Monitor System (CHS) or other external device. The Gateway PCB is able to transmit and receive both serial and parallel data. Parallel data is used only on the Gateway address/data bus. A serial data format is used for all communications external to the Monitor. Refer to paragraph 1-4 for additional serial data information. The LP 8 Recorder PCB receives control signals, real time clock set- ‘tings, and data for the annotating printer from’ the Gateway PCB. Real time data may then be read fron the real time clock and encoded for serial transmission elsewhere. Gateway Microprocessor. AI1 functions performed by the Gateway PCB are ‘GrtratTed-by- the Gateway microprocessor, Ul. Instructions. fron its program are decoded and executed to provide data or control signals to be used on the Gateway PCB and elsewhere. The microprocessor is a 6303, 8 bit processor. It does not have internal ROM so Us, an 8K by 8 bit EPROM, is used for memory. During power-on Ul must be initialized. A 100ms RESET, from the power supply, is applied to Ul, pin 6. When RESET goes high, U1, pins 8, 9 ‘and 10, are latched into ‘the program control register, selecting Mode 2 (rultiplexed mode) which programs the 1/0 ports as follows: Port 1 - Parallel 1/0 only, Ul, pins 13 through 20 (contro! Ines). fare 2 = Serial 1/0 only.‘ ‘pis 11 and Te (serial communication Low Address/Data (AD) - Address information when the address strobe (AS) ts high and data when AS ts low, UL, pins 30 through 37. High Address = High byte of address, Ul, pins 22 through 23, E Clock, UL supplies a IMiz clock signal that is derived from an exter~ ‘nat Giz crystal, Yi. The E clock is the main timing clock for ACIAS U2 and U3 and for EPROM Ut. The E clock signal is also used as a clock ine fut for both the 14 stage frequency divider UI3 and for the real tise clock interface. 1.37 ©ppR, 1985 PHYSIO-CONTROL1-56. Section 1 Description Address Cycle. The address strobe (AS) goes high when the low address Byte Te present ‘and stable on the address/data bus. This address. is Yatched into UG and applied to the EPROM, U4, when AS goes high. The address (AO-A7) will remain latched in U6 until AS goes high gain. High order address lines, AB-AIS of Ul, are present during an entire machine cycle. The three highest address bits, A13-A1S, are applied to the high address decoder, US. This three bit input is used to select one of eight Outputs’ and drive it Tow. Six of these lines are used as enables for other Gateway circuitry. READ/MRITE (R/M) 1s high when UL is reading data from the bus or when Ft does not care what is on the bus. R/W goes low when data is to be sent to an enabled peripheral device. = eV 2 Je |e =o BAW hee ot | Le 188. FIGURE 1-12. GATEWAY PCB BLOCK DIAGRAM Access to the data stored in EPROM U4 is obtained when: U6 has latched the low address byte, AB-Al2 have stable address information, AL3-AIS are all high and E is high. The data, previously addressed, is read nto Ul on the falling edge of E. Frequency Divider. A 15.625kHz clock signal is required to set the ‘Gestred-sertel deta baud rate for the ACIAS. The IMHz E clock signal fs divided by 2 factor of 64 in a 14 stage counter, UI3, and fed to the receive/transmit clock inputs of U2 and U3. Real Time Clock Interface. The real tine clock (RTC) interface provides ‘Timing signals and chip enables for the RIC circuitry located on the Recorder PFC. These signals enable information to be exchanged between various circuits connected to the Gateway address/data bus. 1.38) ©npR. 1985 PHYSTO-CONTROLSection 1 Description Comnication with the RTC is accomplished by using two successive instruction cycles. uring the first cycle, the RTC is provided with an address where it will store or read data during the second instruction cycle. The data to be loaded represents time settings and other control data required for operation of the RTC. The address cycle begins when UB, pin 13, goes low. This low fs. invert: ed by UL6B and directed to AND gate UIB, pin S. When goes high, RIC Address Strobe (AS) is sent fron U17B, pin 6, to the Recorder. RTC AS also resets UI6A through U19B, providing RTC CE. (Note that ULEA was Set during power-on by RESET.) Ul sends out a WRITE command that enables the ‘RTC to latch the low address information on the trailing ‘edge of RTC AS. ‘The data cycle begins when UB, pin 12, goes low, A high from the inverter, UI6A, cause the output of UITA to go high. This high is applied to the Recorder as RTC E. During this time, RTC CE is high, so depending upon RTC R/H, data will either be read fron or written to’ the RTC. The RTC € signal is inverted by UID which sets U18B, pin 11, hhigh. When the next Ul address strobe (AS) occurs, UI9C, pin 8, goes Tow; U17C goes Tow which in turn sets UIGA and pulls RTC'CE Tow. The ow output. from UGA, pin 14, is fed back to UI8B, pin 8, forcing the flip-flop to be reset’ awaiting the next RTC access cycle. The RTC is updated by microprocessor U1 when the TIME MODE SW pulls JI, pin 16A, low. At this time, a prompt appears on the CRT indicating Which clock information is to be changed (hours, minutes, day, month and year). Depressing the TIME SET switch causes’ the displayed pronpt to tei ted dt | JAS el UU J -“——____|— EE pce {=> Aerl rd ti FIGURE 1-13. RTC INTERFACE TIMING 139 © npr. 1985 PHYSTO-CONTROL1-59. Section 1 Description crol] through all combinations appropriate for that clock function (e.g. the months will advance). Upon release of the TIME SET switch, the RTC is loaded with the updated information and allowed to operate normally. Successive depressions of the TIME MODE switch will allow the operator to update other RIC registers. Once a complete update has been per- fored, the CRT pronpt is removed, Printer Message Format. The Recorder printer uses codes prepared on the ‘Gateway POS to reconstruct alphanumeric characters. These characters are printed in a five by seven dot matrix. Since the print head can only make one vertical colum of seven dots at a tine, the Gateway must provide the proper dot patterns, in sequence, for the message to be written, The EPROM, Ut, contains all of the dot patterns for the LP 8 messages, This mepory {5 arranged ‘so that all five columns for a character are stored in successive locations. Complete words and messages are stored jn a sintlar manner. The microprocessor U1 needs only to look up the it pattern and send it, along with PRINT, to. the printer latch (on the Recorder PFC). Printer message formatting 1s accomplished ‘through a software routine. Once U1 has retrieved a bit pattern and placed it in internal buffer, it will address the printer latch, forcing U8, pin 14, low. This low is inverted by UI6C and NANDed with E; PRINT goes Tow. ‘When E is high, the bit pattern is available on the data bus. PRINT goes high at the end of the E period and causes the bit pattern to be latched by the printer. The speed at which the Recorder operates will determine how often the Printer {s updated with a new pattern, the printer 1s updated every 6ns for S0my/sec and every 12ns for 25m/sec speeds. External Comunication. Serial communication between the LP 8 and ‘external devices Ts controlled by the Gateway PCB. General” purpose asynchronous communication interface adapter circuits (ACIA), U2 and U3, act as translators between the Gatevay parallel data bus and external equipment. These devices operate under control of the U1 software. The ACIAS are addressed by U8, pins 9 and 10, when either of these pins go lon. Other UI control Tines, R/M, £, and RS are also necessary to direct operation of U2 and U3. The DIP switches SI-1 through S1-8 are used for signature analysis and should be fn the open position for normal Gateway operation. The operational cycle begins with initialization of the ACIA. The control register is loaded with data from Ul on the trailing edge of E when UB, pin 9, (low any tine U2 is enabled), RS and R/W are low. The device is now ready for operation. Transmission of a character begins when data is written into the transmit data register on the falling edge of E when RS is high and R/W is Tow. AIT other transmit operations are hhandied by the ACIA automatically. Characters are received and stripped of start/stop bits automatically. The microprocessor checks the status register to see if anything new has arrived. If so, a read cycle is, initiated and the contents of the receive data register may be sent to 1-40 npr. 1985 PHYSTO-CONTROL ‘S 9D i)Section 1 Description ‘the microprocessor. Note that receive data register contents are not destroyed by a read. In the LP 8, a baud rate of 976 has been selected (976 bits/sec). The ten bit serial word length is divided into one start bit, eight date bits and a stop bit. No parity is used. If any errors are detected, during serfal data transmission, incorrect characters wil! be ignored land corrected during successive serial packets. Each of the ACIAs is_responsible for communication with a different peripheral device. The Central Monitor System (CNS) is interfaced Through U2; ACIA U3 is provided for future expansion of the system. The CHS serial interface operates on + 15V logic. For this reason, UIIA ts Set up as Tevel shifter to convert 0 to +5V logic from U3 toa usable amplitude. When serial data is received, ULI6 and U14C reverse this Tevel shife for use by U2, Gf and CRF Grovide static protection for these serial Vines. poe | | UL PIN 30. RcAO/ARTTE DATA LATOHED i oe et en ve rim 20, IP SeLEET un rin 25 aesisren seuect’ YX X UL PINS 20-37 DATA BUS — TaD CHCLE es | | ———onTa uaTeHED UL Pin 33 READ/RTTE TRAILING cE vw pin 20 hI SET ui pt 2s nesrsten seuect X UL PINS 30-37 OATA BUS ware crete FIGURE 1-14, ACIA WRITE CYCLE TIMING 1a ©app, 1985 PHYSIO-CONTROL,Section 1 Description 1-61. CRT PCB ASSEMBLY (802831). The CRT PCB (see Figures 1-15 and 5-14) incorporates al1 the analog driver circuitry necessary to support the hybrid analog trace and the alphanumeric display. The PCB's four major functions are horizontal deflection, vertical deflection, intensity control, and voltage refer- ence, Timing signals and the analog display signal’ are provided by the Control PCB. FIGURE 1-18, CRT PCB SLOCK DIAGRAM 1462. Horizontal Deflection. The horizontal deflection circuitry provides ‘pean deflection at tivo rates, one for analog trace display and the other, a reduced rate, for raster formation. 142 © pea, 1985 PHYSIO-CONTROL1-63. Section 1 Description The sequence of events during one 20ns display cycle is as follows: for Sms the bean moves from left to right across the CRT providing an ECG trace. Next is a 1.25ms horizontal retrace and beam positioning period. Following that, 7.6us are used for raster construction during which the beam fs deflected’ about one quarter of the way across the CRT, from left to right at about 1/9 of its ECG trace speed. Ouring this time the intensity is modulated by the DOTS signal to display the alphanumeric information. After completion of raster construction the beam is blanked and swept to the right at normal ECG trace speed across the remainder of the CRT. There 1s a 1.54ms second horizontal retrace and beam positioning perfod and then the cycle begins again. The timing of this cycle fs controlled by two digital signals, HRT and SLOW SNP. These signals drive U2, which contains three two-to-one multiplexers. Multiplexers x (U2, pin 14) and Z (U2, pin 4) perform current steering functions for the sweep generator, Ul, while multi- plexer Y (U2, pin 15) acts as an inverter driving the sweep generator reset transistor, Ql. Horizontal Sweep Generator. The sweep generator, Ul and associated ‘components, "provides the” drive. signal, for the horizontal detlection circuit. UIA is configured as an inverting integrator. When SLOW SWP is low, input X0 of U2 1s switched to output X, allowing current. to flow from the positive reference through RNS and R3. This current enters the summing node of the integrator. Alternatively, when SLOW SMP is high, input X1 of U2 4s switched to output X, allowing current to flow from the positive reference through RNG and RS into the sunming node of the integrator. These currents cause the output voltage of UIA to ramp negatively’ at rates dependent on the settings of R3 and RS. AS a result, R3, which allows a larger current to flow, determines the sweep rate during trace. Similarly, R5, which controls a smaller current flow, determines character width during raster scan. During the interval when HRT is high, the Y output of U2 floats, allox- ‘ng RNB to pull the gate of Ql to ground. Ql turns on, discharging C3, which effectively resets the integrator. When HRT is low, the gate of QL is pulled to +5V, causing the FET to turn off and allowing the integrator to function. Diodes CR22 to CR25 act as clanps to Timit the differential input voltages to UIA and UIB. U1B performs tho functions related to sweep generation. It provides an Offset which determines the horizontal position of the trace or charac~ ters, and it also provides a linearity correction. When SLOW SHP is ow, current flows from the positive reference UID through RNB and R14 to the Z output of U2 and into the summing node of UIB. "A high SLOW SMP signal causes current to flow from the positive reference through RNG and R13 to to the Z output. Consequently RIS determines raster character horizontal position and R14 determines ECG trace horizontal position, A yoke current change of Imi at the edge of the CRT face causes greater deflection than a ImA change at the center of the CRT face. To compen- sate for this effect, the gain of UlB 1s made to decrease by approxi- mately 128 for large’ outputs from UIA. The point at which the gain 1-43 © nea, 1985 PHYSIO-CONTROL1-64, 1-65. 1-66. Section 1 Description decrease occurs is determined by the reference voltage (from UIC), CRI, CR2, and the ratio of the 249k and 69.8k resistors of RNB. The magnitude of the gain reduction is controlled by the ratio of the 69.8K resistor of RNB and the 10K feedback resistor of RMI. Horizontal Deflection Amplifier. The sweep signal at the output of ule Serapptied-te the horizontal deflection amplifier. This amplifier. con sists of U3, and the current boosting transistors, Q2 and 3. The amp- Vifier is an inverting transconductance amplifier producing ‘a negative output current proportional to the input voltage. The output current is Sensed by R22, Feedback through R19 causes the deflection amplifier to adjust its output so that the sensed voltage at R22 is proportional to tthe input voltage. Transistors Q2 and Q3 are driven by signals derived from the supply current of U3. If the output of U3 is zero, no current Flows through Ri7 and the only current. drawn from the power supplies is the quiescent current of U3. Under these conditions resistors R16 and RI7 fave approximately 400ai across then. If, for example, the output of U3 goes positive, additional current flows from the’ +5V supply through R16, U3, and R17 to ground. This current increases the voltage drop across’ RIG, increasing the base to emitter voltage of Q2. For sufficiently large currents, Q2 turns on, delivering current to the load. Conversely when the output of U3 swings ‘sufficiently negative, Q3 turns fon. Note that any current in excess of the quiescent current, los from fone supply to ground and not between supplies. This prevents both current boosting transistors from turning on simultaneously. Horizontal Retracer Amplifier. During horizontal retrace, it is necessary to reposTtion the beam quickly to the left side of’ the CRT. The horizontal deflection amplifier, powered by the *V supply, is Unable to drive the large horizontal’ yoke inductance fast enough.” In order to accelerate horizontal retrace, a retrace amplifier 1s employed. This switchable current source consists of R20 and Q4, and is controlled by HRT through Q5.. When HRT goes high, Q5 turns on, driving the base of 4 Tow and producing a voltage across R20. This ‘determines magnitude of the retrace current source. CRE in deflection amplifier prevents ‘current fron entering the +5V supply instead of the yoke. When yoke current is less than that required at the end of horizontal retrace, the deflection anplifier is saturated trying to drive more Current’ through. the yoke. At sone point the yoke voltage drops low enough so that the deflection amplifier can supply current to the yoke fn addition to that supplied by the retrace amplifier. The deflect ion amplifier adjusts this additional current through its feedback until the proper current is achieved. [At the end of horizontal retrace, HRT goes low turning Q5 and Q4 off. At this point, the deflection amplifier begins to supply the entire yoke current, which is proportional to its input voltage. Vertical Deflection. The vertical deflection system produces a series ‘OF raster Tines as well as a reconstruction of an analog signal. A typical display cycle proceeds as follows. During the horizontal retrace tine, all amplifier: outputs of the vertical deflection system 1a ©npr. 1985 PHYSTO-CONTROL1-67, 1-68, Section 1 Description are inactive, At the beginning of trace, the output driver of the analog deflection amp is enabled, renaining active for the Sns trace time. As the horizontal sweep is’from left to right, the reconstructed analog signal is presented to the analog deflection anp in chronological order. During the next horizontal retrace period, the vertical deflection systen outputs are again inactive. At the start of the 7.6ns raster period, the vertical retrace amplifier is active for 30s, pulling ‘the beam to the top of the CRT. A scan line ts then generated by enabling the output of the raster amplifier for 150ns. This cycle of retrace and scan line generation is repeated 42 times during the raster time, allowing 6 colums of 7 scan lines each. Again during the Sus inactive period of the display, the vertical deflection system is inactive as a power conservation measure. Vertical sweep Generator. Unlike the horizontal deflection system, in Whten the swoop Ts"controlled by "a. transconductence. emplifiers” the Vertical deflection systen uses a current source to determine the initial point of a raster sweep in an open loop configuration, USA is configured as @ proportional~integral controller, with @ constant current derived from the negative reference through Ri? and potentio- meter, R52. This current, flowing through C12, is integrated to form a ramp.’ The current also’ flows through the 576 ohn resistor of RN7 resulting ina ramp with a constant offset present at the output of USA. Controller USA is reset every vertical retrace time by the VRT+RISTER Signal turning on Q1O, which discharges C12. Raster Hier. After C12 has been discharged, the offset ramp from irives the inverting poner amplifier composed of USB, 026 through 28, and QIS and 16. When VATAAGTER. ts. low,” switching trensistors Ol] and Q12 are off, allowing the gates of MOSFETs Q13 and Ql4 to be pulled hhigh. In this State, MOSFETs Q13 and Ql4 conduct, allowing Q26 and Q27 to drive the power ‘amplifier output transistors Q15 and Q16. This results in the amplified offset ramp being applied to the yoke winding at 2 pins 3 and 4. Due to the switching of the amplifier, the offset appears to the yoke to be a step in voltage, providing the requisite waveform at the yoke for a nearly linear current ramp. During the ‘interval when VRI#RASTER is high, the MOSFETs are off, isolating the bases of 015 and Q16, and preventing any conduction through then. The diodes (R12 and CRI3 prevent yoke voltages greater than the supply voltages of Q15 and Q16 from causing operation in the reverse active region. Note that the positive supply for the power output stage of the raster amplifier is ground. This is possible since the drive voltage to the yoke is guaranteed to be negative. In effect the yoke inductance is being discharged through 015. 26 through Q28 are simply a current booster for USB, to assist in driving the relatively low beta power transistors, 'Q28 provide a constant bias of approximately 1,6 diode drops between the bases of G26 and G27. With the 20 ohm enitter resistors of RNA, this bias method reduces crossover distortion without danger of thermal runaway. 1-45, ©npR. 1985 PHYSIO-CONTROL1-69. 1-70. Ln. Lr. Section 1 Description Vertical Retrace Amplifier. Vertical retrace is controlled by the RASTERSVRT Signa?” WHICH” enables. the retrace current amplifier only during the retrace portion of the raster period. When RASTEREVRT is, high, Q17 conducts; this allows CR11 to maintain a constant voltage across Q18, RAS, and R45. This produces 2 constant current flow from the collector of Q19 into the vertical winding of the yoke, stabilizing the ‘vertical retrace. The amount of current is set by R46, the character height adjustment. Since the current is derived directly from the *20V supply, a large voltage can be applied to the yoke inductance producing a rapid retrace. At the end of the vertical retrace period, RASTERCVRT. goes low, turning Ql7 off and disabling the current source prior to the next scan Tine sweep. ECG Active Filter. The reconstructed analog signal to be displayed is ‘applied to an inverting buffer/active filter consisting of U9A, RN7, ChO4 and C105, Configured as the second stage of a 37kHz, 4 pole Butterworth fiiter, this circuit removes any high frequency noise. |The filtered signal is then applied to USB where final gain is set by adjusting R68. Analog Deflection Amplifier. The power anplifier formed by UB, 40 SR HE Ga and WE is statin to the raster amplifier.” Here the voltages supplying the power output stage are +15V and -15V rather than Ov and -6V. The larger supply voltages provide the slew rate required to reproduce ECG waveforms accurately. The reconstructed analog signal then drives the noninverting trans conductance amplifier composed of UB, and Q40 through Q82, and Q24 and 5. hen is low, switching transistors 20 and Q21 are off, allowing the gates of MOSFETs Q22 and Q23 to be pulled high. The power amplifier output stage is then driven by Qé0 through Q42 through the on HOSFETs.. ‘This results in the yoke winding being driven by the raster ‘amplifier, Since the anplifier feedback is taken from the yoke current Sensing resistor, R76, the current through the yoke 1s proportional to ‘the reconstructed analog signal. During the ‘interval when TRACE is high, the MOSFETs are off, isolating the bases of G24 and Q25, and preventing any conduction "through then. Diodes CRI7 prevents” yoke Noltages greater than the supply voltages of 25 fron causing operation in the reverse active region. (40 through Q42 provide current booster for UB, to aid in driving the relatively low beta power transistors Q24 and Q25, O41 provides 2 constant bias of approximately 1.6 diode drops between the bases of 40 and Qé2. With the 20 ohm emitter resistors of RNS, this bias method reduces crossover distortion without danger of thermal runaway. Power Saver. When the Monitor is turned on, the vertical deflection ‘GircuTEry could present a heavy load to the poner supply before the Supply voltages have stabilized. This load would increase the tine Fequited by the supply to achieve a stable output, and cause the switch~ ing. frequency to drop into the audible range as the supply attempted to supply the heavy load. Consequently, @ soft start circuit disables the vertical deflection systen until the supplies are stable. 186 ©ppR, 1985 PHYSTO-CONTROLSection 1 Description This circuit consists of 932 through G34, C103, CR26 and CR7, RITE and” three resistors in RNB. Fron a. cold start, C103 ‘is discharged. AS a result any increase in the supply voltages as the power supply is energized appears across R114 as C103 begins to charge. Since. the NOSFETS used for Q32 through Q34 have 2 low threshold, they are quickly turned'on by the voltage across RIl4. . Q33 actively pulls the gates of Q13 and Q14 to the -15V rail. This is the Tovest voltage in the circuit at all tines. The result is’ that 013 and Q1¢ are held off disebling the power output stage ‘of the raster amplifier. —Sinilorly, Q34 pulls. the fates of G22 and 023 to -15V to disable the’ analog deflection anplifier output. Q32 holds 017 off by pulling its base toward -ISV, but in order to Prevent reverse breakdown of (7's base-enitter junction, the two resistors of RNG are scaled to limit the base voltage to greater then ov. R27. and the 4.7K resistor of RNS function as @ simple voltage regula tor. This prevents smell drops in the supply lines from causing. the soft start to cut in. CR26 rapidly discharges C103 when the supplies actually disappear, ailowing the soft start to function in the case of rapidly cycled power. Rate Intensity Compensation, The LP 8 intensity control system provides ‘Fadependent cortrol--of the ECG trace tnd siohenumeric’ intensities; blanking, a user accessible intensity control and rate intensity compensation. This last feature causes the intensity to modulate during {an analog trace to compensate for increased bean speed during transients Tike R waves. Intensity modulation in this manner allows operation at ow average beam currents, resulting in longer phosphor life. Providing a1] of these features requires modulation of the voltages on both the CRT control grid and cathode. The actual beam current and intensity depend on the difference in potential applied to these electrodes. "As the grid is made more negative with respect to the cathode, the beam current decreases. The dc level on the grid is set by a resistive divider consisting of R33 and a rear panel potentiometer, CRT BRIGHT. This potentioneter allows the user to control the grid bias, directly affecting overall intensity. The impedance the divider presents to the grid is stable regardless of potentiometer setting due to the series impedance of R32. This altows ac coupling of other signals to the grid without attens- ation. Rate intensity compensation is controlled by U4. The process consists of, differentiating the analog display signal to extract rate informa- tion, full wave rectification to obtain the absolute value of the rate, and tinal amplification of the compensation signal. UGA is configured by RN2 and ClO as a differentiator whose output is Proportional to the rate of change of the input. Since the differenti- ator's gain increases with frequency, it is prone to oscillation. R27 and C11 provides limits to USA's gain at high frequency to prevent. oscillation and limit the noise bandwidth, 147 © ape. 1985 PHYSIO-CONTROL174, Section 1 Description Half wave rectification is provided by U48, whose output is taken from the anode of CRB. At this point the gain is -1V if the input is positive; the output is zero if the input 1s negative, since no current Flows from the inverting terminal of U&B through CRB and RN2. Two functions are performed by UAC. First it provides summation of the output of the differentiator and the scaled output of the half wave rec- tiffers second it provides overall gain of the compensation signal. Configured as an inverting amplifier, U&C's inverting intput acts as current summing node. Since the resistance connecting the half wave rectifier to the suming node is one half that connecting the differen tiator to the summing node, UAC effectively adds twice the half wave rectifier output to the differentiator output. The input to U&C is therefore @ full wave rectified rate compensation signal. UAC subjects this Input to its inverting gain, which is adjustable through R36, and ac couples the final compensation signal to the arid through CB. ‘The analog trace signal is applied to the rate compensation circuitry at all tines, AS a result, it would be possible to have rate compensation occur when there is notrace displayed. To prevent this, Q31 is con- Grolied'by tne HACE ‘signal. Mien TRACE is high the Gisplay” is notin trace mode, and Q31 turns of, forcing the gain of the rate compensation circuit to zero. Dot Amplifier. The dot amplifier perforns blanking and dot driver Function thrsugh the cathode electrode of the CRI.” Control of this amplifier is accomplished through the TRACE and DOTS signals. When THLE is Tow, 09 15 held off, forcing QB off as its gate 1s pulled high by R37, During trace tine, when the DOTS signal is Tow, R29 holds Q7 off. Therefore the cathode is héld to 2 dc potential by a relatively high resistance divider consisting of R39 and potentiometer R40. By adjusting RéO, the trace baseline intensity can be varied. CR41 guards against variations in intensity due to power supply loading, G43 blanks ‘the CRT beam immediately as power is turned off. It is possible for the OTS signal to go high during the ECG trace period. This occurs during a sync marker. When DOTS goes high, Q7 turns on, pulling the cathode toward ground potential. The resuTt is a very intense, defocused spot which serves as a sync mark. At the end of the trace period, TRACE goes high, turning on Q9 and 8. With G8 on, a low impedance pith exists fron the *60V supply to the cathode in’ parallel to the high resistance divider. This pulls the Cathode to approximately +60V, Blanking the trace. During the raster period, the OOTS input goes high and is capacitively coupled to the gate of Q7. The capacitive coupling prevents continuous turn on of Q7; which would lead to excessive power consumption. When Q7 turns on in response to the DOTS signal, it pulls one end of a low mpedance divider formed by R30 and R31 to ground. The resulting volt- age applied to the cathode is determined solely by this divider, as its ‘impedance is mich lower than that of the trace intensity control divider. This allows control of alphanumeric intensity through potentioneter R31. An additional benefit of the low impedance of the divider is that. the response tine ts Test enough to prevent blurring of the dots due to slow rise and fall times. 1-48 ©ppR. 1985 PHYSIO-CONTROL a) 5 4Section 1 Description (175. ottage References. The voltage reference outputs are bipolar and are seh te provide a stable signal source for the generation of the hori Zontal and vertical sweeps. The positive reference also goes to the ‘Anode Supply PCB. CRB 4s an LUSZ9B reference diode which provides 2 highly stable voltage. The reference voltage is buffered by 2 pair of op amps, UIC and UID. UIC 4s configured as an inverting amplifier with a gain of .5 to provide a reference of -3.45V. Since the inverting terminal of UlC is a virtual round, the pair of input resistors form a divider from which the input Of UID'ts taken. Configured as a voltage follower, the output of UID is the divided reference voltage, 3.45V. 1-76, ANODE SUPPLY PCB ASSEMBLY (802813). ‘The Anode Supply PCB (see Figures 1-16 and 5-15) provides the 9kV anode voltage and the 400V accelerator grid voltage required by the CRT. These voltages are produced by a voltage controlled oscillator (VCO) driving 2 flyback switching regulator. The VCC uses #5V and -6V suppl i- es. Note therefore that the reference for the VCO, switching transistor, Flyback transformer, and grid voltage regulator 1s -6V not ground, 1-77. Voltage Controtes Oscillator. The voltage controtle oscillator (VCO), Ue, te 2 BE timer configured as an estable miltivibrator. U2 oscil] ates at a frequency determined by the values of R12, potentioneter R13, Rid and 5. The charging tine constant is deternined by R12 and C5. Cc During this tine, the voltage at UZ pins 2 and 6 1s below approxinately two-thirds of the supply voltage. [ss | [a FIGURE 1-16. ANODE SUPPLY PCB BLOCK DIAGRAM 149 ©ppR. 1985 PHYSTO-CONTROL1-78. Section 1 Description Internal comparators detect, this below-threshold condition, causing the ‘output of U2 to go high. When the capacitor voltage reaches the upper threshold voltage, these comparators then change state, forcing the output, pin 3, low, as well as the discharge output, pin 7. During @ typical cycle, Ql is turned on by the voltage applied to its base from Rll, A discharge path then exists through Q1, R13 and R14. By adjusting R13, the off time of the oscillator can be controlled. The ‘output. of U2 renains Tow until the voltage at U2, pins 2 and 6, drops to approximately one-third of the supply voltage.” The discharge pin is then allowed to float and current can again flow through R12 and CR5 to charge C5 starting a new cycle. The VCO regulates output voltage through Rl; the voltage at RI is proportional to the sense voltage of MI as the voltage on RI increases Bbove the level on timing capacitor C5, current flows through CRI and RL as well as the normal charging path through R12. Charge tine therefore decreases proportionally to the voltage at Rl.” U2, pin 3, stays high for a shorter period resulting in less energy being transferred to the output. The discharge path is unaffected directly by the voltage on RI so the off time of the oscillator renains the sane. The frequency of oscilla tion, therefore, changes as the on time changes. Power Switching. The output of the VCO drives the power MOSFET 02. When the VCO output is high, Q2 is turned on hard, allowing current to flow in the prinary of Ti, the flyback transformer. The supply voltage of 11V. is applied across this prinary inductance, resulting in an Gncreasing current. ramp through Tl and Q2. Since the VCO modulates the on tine of Q2, the energy stored in 11, during a cycle, fs also modulated. When the VCO output switches to its low state, G2 is suddenly turned off, The energy stored in the prinary of Tl is’ then transferred to the Secondary where a high voltage, low current pulse is produced. This ‘output pulse 1s the voltage source for the output regulator and voltage multiplier. During this flyback period when current flows through the secondary, CR9 is forvard biased, clamping Tl, pin 6 to approximately -6.6V. "RIL keeps the anode of CR6 pulled high and CR6 begins to conduct, clamping the base of Ql to -6V. QL is then turned off while current is flowing in the transformer secondary. C5 has no discharge path as Tong as Ql is off, This dead tine in the VCO cycle guarantees maximum energy transfer to the secondary thus increasing efficiency. The off tine adjustment provided by potentiometer R13 is used to trim the waveform at the drain of Q2, If the dead tine 1s msadjusted, the resonant circuit formed by Cll and the prinary inductance of Tl causes the voltage at the drain of Q2 to rise during the on period. R13, should be adjusted (with the output at its noninal level) to eliminate this voltage rise. 1-50 ©npR. 1985 PHYSIO-CONTROLCc 1.79, 1-80, 1-81. 1-82, Section 1 Description The soft start network consisting of CR7, C7, RIS, and R16 prevents overstressing Q2 at turn on. The RC time constant prevents the gate of 2 from reaching *5V during the first few VCO cycles. Q2 does not turn on fully thus limiting the initial current flow. This is necessary since the zero output voltage at start up causes the VCO to run at maximum duty cycle. Grid Voltage Regulation. RIO is _@ high voltage rectifier which ‘Converts the output pulses of Tl, pin 5, into a regulated de voltage on the filter cap (9. This de level is then more tightly regulated by the passive network R18, R19, CRI1 and CRIZ. Filtering is provided by C10. R20 and R21 provide’ relatively low power dissipation bleed resistance for the output filter. Anode Voltage Regulation. Tl, pin 4, is tied directly to 2 voltage suteiptier, NI, which Boosts the output voltage by 2 factor of eight, RO divides’ the’ sense output of M1 by 1000. C& reduces high frequency components of the signal which is then buffered and inverted by UIB. R6 adjusts amplifier gain. UIA then integrates the difference between UIB output and a reference voltage and provides the control voltage to the VCO through 1. When the error between the scaled output voltage and reference voltage is reduced to zero, the integrating nature of the controller maintains the proper control’ voltage at Rl. The series resistance, R2, in the feedback path of UIA provides a signal that is directly proportional to the error voltage. This decreases the time required to respond to transients on the output voltage. Cl provides control Toop frequency compensation in conbination with R2 and the integrator capacitor (2. RECORDER PFC ASSEMBLY (802819). The LIFEPAK 8 has been designated to be used with a record from one of two manufacturers, WFE and GSI. For this reason, two different recorder PFCs have been designed (see Figures 1-13, 5-168, and 5-168). These flex assemblies have several identical circuits but sone circuits are completely different. To avoid redundancy, the paragraphs will be labeled to show whether the description applies to the NFE, the FSI or BOTH recorder assemblies. NOTE: when circuitry is common for both recorders, component designations, if different, will be given for the NPE recorder first with the corresponding GSI comonents listed in parentheses. The annotating Recorder 1s used to provide a diagnostic hard copy of a patient's ECG waveform. A string of five by seven dot matrix characters may also be printed in the upper margin of the recorder paper. This annotating feature provides data relevant to alarms, time, heart rate, QUIK PACE and Defibrillator performance. Refer to Figure 1-17, Recorder PFC Block Diagram and Figure 5-16, Recorder PFC Assenbly. Recorder On/Off (Both). Recorder power is activated by the Control PCB when the RECORDER ON/OFF line, J1-87, is pulled low. This low passes through RI (R14) to the base'of Q3 ‘(Q7) ‘turns the transistor on and forces its collector to +5V._ The #5V turns on Q6 (Q5), passing -15V to the collector for use as -15V SW SOURCE. The +5V is also supplied to 151 Sper. 1985 PHYSIO-CONTROLSection 1 Description the base of Q5 (Q8), pulling the collector to ground. This turns on Q6 (05) and passes +15V power to its collector for use as +15V SW SOURCE. A-s5V SH SOURCE 15 developed replaces 1-82 regulated by the zener diode U13 (CRE and R13). 1-83, Real Time Clock , The Real Time Clock (RTC) provides time of day and Calendar Tnformation to the Gateway PCB for use in the LIFEPAK 8 systen. A single chip RTC carries out all time keeping functions, powered at all tines by standby power or by a back-up lithium battery (not on Recorder PEC Assenbly).. CRS (CRS) protects the battery during normal operation when the RTC is powered by STOBY HR. ‘The RIC, UB, 1s addressable like any other menory location connected to the Gateway’ address/data bus. Additional information about RTC opera~ Hon may be found in paragraph 1-58, Real Time Clock Interface, of the Gateway PCB circuit description. A low power crystal oscillator, U9, provides a 32.768kiz time base for the clock, When power 1s renoved’ from the Monitor, Q9 turns off and Forces CE high to isolate the clock from the address/data bus. ~f+— FIGURE 1-17. RECORDER PFC BLOCK DIAGRAM 1-82 ©ppr. 1985 PHYSIO-CONTROL 2)Cc 1-84, 1-85, 1-86. Section 1 Description Printhead Drive (Both). Characters are thermally printed on the Fear eee even macrite Dot tode ata. Hron’ the eateuny BCE is latched into U6 when PRINTHEAD ENABLE ts pulsed low. The positive transition toggles the one-shot UIIA, The pulse width of UIIA is determined by SPEED SELECT and switch USB. The Q output of ULIA, pin 4, goes low enabling the outputs of U6 which drive the NPN transistor array, U7. The connon side of the dot heat elenent is connected to +15V. Individual dots are heated when U7 provides a current path from ground. The pulse width of UIIA, pin 4, determines dot darkness and is control- Jed by an RC network consisting of Cll (C5), R12 (R6), and RIO (R3) or RIL (Ré). Dot darkness is adjustable by varying R12 (R6). The analog switch, USB, selects either RIO (R3) for @ longer dot heat tine for the 25nm/s” paper speed, or R11 (R4) for a shorter dot heat tine for the S0mn/s paper speed, Pen Heat (Both). The stylus heat circuit consists of a triangle wave Generator, a comparator and a current source. A quick heat circuit is also provided for Recorder turn on. A 1OkHz triangle waveform is generated by UZA (U2C) as it charges and discharges capacitor C9 (C13). The output of UZA (U2C) is +5V (+7.56V) when C9 is discharged, The capacitor charges until its voltage equals that on U2's noninverting input, about +4V (+6V) causing the output to go low. The noninverting input ‘to U2A (2c) is now +1.1V (41.5V).. The capacitor discharges to the new reference whereupon the U2 output is forced high. The cycle is now repeated. The triangle wave is applied to comparator U2B (U2A). Since the other input to the comparator is a de voltage, whose level is adjusted by R6 (R21), the output is a series of +151 square waves whose width fs controlled by the dc input level. These outputs pulses turn Q7 (Q1) on (and off) which supplies current pulses to heat the stylus. When the recorder is turned on, C10 (C14) is discharged which allows 08 (Q2) to conduct temporarily pulling one end of the stylus to -15V. This quick-heat feature brings the stylus up to operating temperature in about 1 second. When C10 (C14) charges sufficiently, QB (G2) turns off, clamping one end of the stylus to +.7V. Paper Motor Drive (NFE Only). Paper motor speed is electronically EatratTedosiag tea ron a achooter “Connected Ws" the ‘satot itself. Actual motor speed is converted to pulse information for application to the driver, Q1O. The tachometer produces a sine wave which is full wave rectified, by CR6 through CR9, and converted to narrow trigger pulses when outputed from comparator J2C, pin 1. When the speed control loop is stabilized (at the correct paper motor speed) ULIB outputs a square wave with a 40% duty cycle. “The pulse width is controled by USA and RC network RNI/ C18. These pulses are integrated by C20. The voltage at TP1 (C20) therefore has a dc component of 40% of the +5V reference with a ripple that triggers comparator UZD. The motor speed is adjusted by RI8 which sets the trigger point for U20. The output 1.83 ©apR. 1985 PHYS1O-CONTROLSection 1 Description ‘from U20 is a pulse width modulated square wave at twice the tachoneter Frequency. The pulse width increases if tachoneter frequency decreases. Current to the wotor is controlled through drive transistor Q10. 1-87. Paper Motor Drive (GSI Only). The GSI_paper drive motor speed is Eontrolred In much the same way as the NFE recorder. Tachoneter pulses fare converted to pulse width modulated drive for the motor. A triangle wave, from C13, is applied to the noninverting input of U28 While a variable voltage reference is fed to the inverting input. The output, from U2B, pin 14, is a pulse width modulated signal used to drive the motor through Q4. The variable voltage reference is derived from a frequency to voltage Converter, U3. The tachoneter provides a square wave whose frequency {proportional to paper speed. At a speed of 25en/s the frequency 1s approximately 4kHz; at 50nm/s approximately 168kHz. These pulses drive a charge pump, in U3, which uses 2 constant, current to charge Ch. The current to C4 1 mirrored at C17 and R32 where it is averaged fand applied to an internal operational amplifier. A voltage, adjusted by Ret (for 25mn/see speed) or R23 (for S0un/sec speed), is used as @ Speed control. The variable voltage reference appears at U3-5. An Ghcrease in this voltage will result in an increase of motor speed. 1-88. Pen Deflection (NFE Onl The pen deflection circuitry translates Ft FE ore nechanfcal notions Provisions are. made for gain adjustment, damping and minimizing distortion. The bandwidth of the incoming ECS is boosted from 70 to 400Kz in UIA to Conpensate for the normally poor high frequency response of a galvano- meter drive. Recorder ECG size is adjusted by R5. A class B amplifier, Consisting of UIB, Ql and Q2 with two feedback paths actually drives the pen deflection coil, Deflection current is sensed across R9, through Ros, and applied as negative feedback to UlB, pin 9, Mechanical reso- anges of the pen motor and stylus are damped through UIC. [A bridge circuit. is formed by the pen deflection coil, pen balance coil, RNS-7/8, RB and RN4-7/10, - From this, ULC extracts the velocity- dependent back EMF generated by the deflection coil from the super- fmposed drive signal. This signal fs summed at U18, pin 9. Distortion He minimized by adjusting RB. Square wave overshoot is damped by adjustment of R7. 1-09, fen Deflection {GS-Only)> The incaning Ec, ts, buffered, by, UWA and Givens high Frequency boost by C7. Gain ts adjusted through Rl. The output from U4A is clamped between #5.7V at the junction of CRI and GR2. UAB is configured asa unity gain inverting amplifier. Stylus Gefiection is limited to 2Zen. Centering of the stylus 1s accomplished by adjustnent of precision voltage divider R2. Power anplification for the galvanoneter is provided by Ul. A feedback Signal from 25 1s sent to Ul. This signal is a composite of voltage applied to and current sensed through the pen deflection coil. R25 is adjusted for critical damping of the stylus resulting in a flat frequency response to 40HZ. 154 © ppp. 1985 PHYSIO-CONTROL1-90. 191. 1-92. 1-93. Section 1 Description A velocity feedback coil, within the galvanoneter, produces 2 feedback Signal which 1s sumed with the incoming ECG. Adjustment of R16 sets ‘the high end frequency response to 100H2. Serial Data Conmunication. For an explanation of how the Monitor comunicates with the Defibrilta- tor, see paragraph 1-4. LP 8 DEFIBRILLATOR Paragraphs 1-92 through 1-129 provide circuit descriptions for the Power Supply, Main, and Logic PCB Assenblies. The Defibrillator Interconnect Diagram in Section 5 provides interconnection data for all subassenbl ies. POWER SUPPLY PCB ASSENBLY (802719), ‘The Defibrillator Power Supply PCB Assenbly provides a11 power for the LIFEPAK 8 Uefibri}lator and Pacing Cassette as well as continuous battery charging when connected to ac mains. The speaker driver is also Vacated on the Power Supply PCB. (See Figures 1-18 and 5-28.) AC _Line Power Conditioning. The Power Supply PCB will withstand line Voltage transtents up fo 6kV. F2 and RVI provide most of this protec- tion by limiting the voltage presented to the input rectifier. RV1 is @ petal oxide varistor which has a nonlinear resistance. This device normally presents a high inpedance to the ac Tine. However, should the peak voltage exceed approximately 430V, the resistance drops rapidly, Clamping the voltage to this level. FuSe F2 opens when it encounters a Yine voltage transient fron a source with a low effective impedance. When the Defibrillator is first plugged in, the rectifier and filter capacitors, Ch and C5, appear as short circuits to the line due to their Tow effective source resistance. If line voltage happens to be applied at’ the peak of its cycle, currents exceeding 100A can flow possibly Gamaging the bridge rectifier CR3. Power-on surge currents are limited primarily by the negative temperature coefficient thermistor RTI and inductor Ll. At room temperature, RTL has a resistance of about 5 ohns. This and the effective series inductance of Li limit the inrush current to safe levels. As the power supply operates, current flows through RTL, which results in. a temperature rise. ‘As the temperature rises, the’ resistance of RTI drops until equilibrium is established. Having Tower operating resistance results in less wasted power during normal operation. CRS, C4, and C5 rectify and filter Vine voltage. When configured for 2300 operation, pins 5 and 7 of P15 are open. For 115V operation, pins 5 and 7 of P1S are shorted together with a rear panel switch, recon- Figuring CR3, C4, and C5 as a voltage doubler. This results in a nominal 230Vde supply for the power switching circuitry regardless of the operating mode. In either case, R2 and R3 serve to equalize the voltage on each capacitor, as well ‘as providing a path for bleeding charge off the capacitors without a large decrease in efficiency. 1-55 ©ape. 1985 PHYSIO-CONTROLSection 1 Description FIGURE 1-18. POWER SUPPLY PCB ASSEMBLY BLOCK DIAGRAM Both the Tine rectifiers and the power switching circuitry can generate large amounts of high frequency noise. Conduction of this noise from ac mains connection must be limited, This filtering is provided by LI to reduce the high frequency noise components without significant losses due to currents at the ac mains frequency. 1-94, Bootstrap Power Su The power switching control circuitry must be provided with supply power to start-up, otherwise switching cannot occur fand no power will be delivered to the Defibrillator. In the power supply, an auxiliary low power linear supply operates in parallel to the switching power supply to provide all power for the control circuitry, not just that required at start-up. TL is an impedance Timited transfomer that provides power for the pulse width modulator, U1, across the 4kVac isolation barrier. Transient protection of the boctstrap supply 1s provided by parallel connection of the primary of TL and RV1. The primary of Tl consists of unswitched winding. The result is that regulation of the output over a wide range 4s required to allow operation from both 115Vac and 230Vac mains. RL and C3 rectify and filter the output of T1, resulting in an output that varies between approximately +12V and +60V, depending upon actual ac mains voltage. Since the nominal bootstrap power supply voltage is ‘Hv, the Input to output drop at high Tine +230V exceeds the rating of 1-56 © pp, 1985 PHYSIO-CONTROL1-95, 1-96. Section 1 Description monolithic regulators. Instead, CR27, R57, R61, Q10, and QU are Configured asa regulator. The resistor and zener diode provide a reference voltage of 112V, which is buffered by the complementary Darlington formed by 010 and G11. The conplenentary Darlington con- figuration is used to minimize drop across the regulator when operating from low line +115V. C19 then provides output filtering of the boot- strap supply voltage Pulse Width Modulator. Control of the power switching circuitry is ‘provided by an Integrated circuit pulse width modulator (PMN), Ul. UL Contains an oscillator, error amplifier, reference, PkM comparator, and drivers. The basic oscillation frequency of the power switcher is set at 60kiz by CIS and RNL, pins 8 and 9, tied to Ul, pin 6. A dead time of approxi~ rately 1% i$ set by R24.’ This resistor, in series with the discharge circuit, controls the reset time which must pass before a new oscillator cycle can begin. The 45.1V reference is divided, by two, by RNI and applied to the non inverting terminal of the error amplifier at Ul, pin 2. The error amplifier calculates the difference between this’ voltage and the attenuated power supply output voltage applied to pin 1 through RNL. The amplified difference is applied internally to the PHM comparator, which controls the duty cycle of the driver transistors. The output of the error amplifier modulates the duty cycle so the voltages applied to the inverting and noninverting terminals of the error anplifier are the same. AS a result, the +12V output is derived from the reference volt- age and the-ratio’of the attenuation of the two dividers within RNL. The RC network formed by C12, C13 and RNi, pins 5 and 12, connected between U1, pins 1 and 9, provides frequency conpensation of the power switcher a a whole. Finally, C16, in conjunction with an on-chip current source, sets the soft start tine constant. Soft starting the power switcher entails Viniting the maximum duty cycle at start-up, to prevent overstressing the transistor switches as they drive the output filter capacitors in their discharged state. These capacitors appear as short circuits to the switcher at start-up due to their low effective source resistance. The driver transistors in the PkM cannot directly drive the FETS, QL ‘and Q2, which do the actual power handling, since the PIM lies on’ the isolated ‘side of the 4kVac isolation barrier. Instead, the drivers alternately pull opposite ends of the primary of the gate drive trans~ former, T3, to ground. The result is a bipolar drive waveform applied to the’ gate drive circuitry on the non-isolated side of the barrier. Power Switching. C4, C5, Ql, and Q2 form a half bridge converter, with ‘he primary of the main power” transformer (Tz) connected across the bridge. Consequently, one end of the primary is always held at. about GOV vite the other end ts alternately pulled to 320V by Qi and OY by 1-87 ©npr. 1985 PHYSIO-CONTROLSection 1 Description Driving the transistors in this manner requires a drive signal for qh iten"s"dertved: from the’ source of 1, nich is constantly switehing whiten 320" ond OV.” the transformer caupling of che gate drive signet seem provides a wathod’ ‘oF accomplishing, this ‘level. shifting. by [EForencidg one gate arive_ secondary’ to this point, Sinilariy, the TGrreetreverence'for dl is achieved dy referencing the other gate drive Secondary to G's source. The drive circuitry for Ql and Q2 are identical so the following discussion will concern itself only with the drive for 2. As pin 5 of 13 becomes more positive, CRIO is forward biased and the gate capacitance of G2 is charged through the series connection of CRIO ind R7, rapidly turning the FET on. During the time the FET is on, it $5 driven by about +9V on its gate to achieve the lowest possible on Tesistance to minimize power losses, At the end of the on period, there Ts a short dead tine when neither transistor is driven on, This is to Querantee that. the land Q2 are never on simultaneously, which would Short the input filter caps, draw large currents and damage the FETS. During this time, R5 discharges the gate capacitance of Q2, turning the FET off. short. switehing tines ore accomplished by 08 and cRI6 during turn off stare rite ndeiStanee of R7 during turn’ on, When the voltage at the seats y OF the gove drive transformer coliapses at the start of the Secandary, OF A See cspacttance of GE is, stil charged. to about SV.) Gene NUS the eaitter of C4 Up, so the enftter-bese junction of O8 13 Tees wenee Ae" he gate drive isoppears. As QW turns ony. the gate Eafutteance’of Q2 if'dtscharged wore rapidly than if by BS alone. During the period of reverse drive, that 1s, when Ql fs on, the voltage appearing at pin 5 of the gate drive transformer is negative, holding 04 ‘on and a low impedance across the gate and source terminals of Q2. CRI6 prevents the negative drive from forward biasing the collector base Bunction of G8, which would steal gate drive from the other FET. CRB ‘and CRO prevent’ overstressing the gate of Q2. The primary of T2 is ac coupled through C6. This prevents net de Currents from flowing in the transformer which could cause core satura tion. R13 and C18 absorb the energy stored each cycle in the primary Teakage inductance. 1.97. Qutput Rectification and Filtering. Fuses F7 through F10 (or R63 and RE Tar She cOG} are provided to Finit the amount of current drawn under shorted secondary conditions. The main supply output is #12V at currents up to 10A during the Eneray Storage Capacitor charge cycle. Nominal operating current exclusive of Energy Storage Capacitor charging is 500 milliamps. CRIS provides full wave rectification from a center tap secondary of 12 with these current Capabilities. Riz and C17 reduce secondary Teakage inductance. 2 and C11 form a nondissipative low-pass filter for ripple elimination on the Fegulated 12 supply. R27 and R2B provide a minimum load of 100mA. 1-58 © ape. 1985 PHYSTO-CONTROL1-98, 1-99, 1-100. Section 1 Description CRIZ and CRI provide rectification for a low current auxiliary supply Used for battery charging. C9 is connected to the +12V supply as a filter. Battery Charger. Voltage regulator U3 is used as a constant current Source to provide slow charge at a C/15 rate. U3 operates by maintain- jing 1.25V between pins 1 and 2. This voltage is applied across current setting resistor RIO to produce a 100nA charge current. CB provides noise bypassing of the regulator adjustment terminal. The charging current also flows through R11, where it produces a bias across the base-enitter junction of 5. ‘Whenever battery charging current flows, Q5 1s on.” This applies the +20V battery charge supply voltage to RD, allowing current to flow through the front panel BATTERY CHARGE LED. Ac/Battery Operation Switching. When the Defibrillator is not plugged nto ac mains, relay KITS in the normally closed. position, and” the battery is connected to the rest of the Defibrillator. In this state, CRII prevents the battery from reverse biasing the charging current source. Khen the Defibrillator first has power applied to it, the Power switching circuitry starts-up and the +12V supply rises. Q6 turns fon. through C10 and pins 11 and 6 of RWI. This keeps Q12 off, allowing the voltage on soft start capacitor C16 to rise. Eventually the gate threshold of Q13 is reached, turning Q13 on. Capacitor (22, which is initially discharged, acts as a shart circuit allowing maximim current to energize Kl. The energized coil of KI switches the relay to the normally open position. When C22. is completely charged, the current through coil drops toa level sufficient to hold Ki in its energized state. This connects ac power to the rest of the Defibrillator. Upon renoval of ac power, Q6 turns off and O12 turns on momentarily. This allows quick discharge of C16 and turns off Q13. with Q13 off, Ki returns to its normally closed position, reconnecting battery power. Speaker Driver. A secondary function of the Power Supply PCB is to ‘rive the Spesker which produces, key click and. informative tones, 7 ‘and G8 form a push-pull driver stage which 1s ac coupled through C27 to an eight ohm speaker. P18, pins 1 and 3, are connected to a rear panel potentfoneter which ‘sets the tone volume. Normally, when no tone is Present, the speaker drive line presents 2 high impedance. In this case, the base of Q7 is pulled to +12V and C27 is charged to this voltage, less a diode drop. When a tone is to be applied, the speaker drive Tine is alternately pulled to ground and floated.” The volume adjust potentioneter then acts as a divider, applying an ac signal to tthe bases of Q7 and Q8 whose amplitude is proportional to the potentio- meter setting. This signal, through C27, drives the speaker. In order to provide key clicks of a constant volume independent of the Potentioneter setting, a separate driver and input is provided. The key Click signal is applied to the base of Q9, causing St to tum on and reverse bias zener diode CR26.. The bases of Q7 and QB are pulled down 2 fixed amount, resulting in an’ independent key click amplitude. 1-59 © npr. 1985 PHYSTO-CONTROL1-101. 1-102. Section 1 Description WAIN PCB ASSENBLY (802715). The Main PCB Assembly provides the Defibrillator with the following functfons: pulse width modulated isolated power supply; Energy Storage Capacitor (ESC) charging; instrumentation amplifier; transfer and dump relay drive. Additional circuitry has been provided for ON/OFF control, power distribution and optical interface with the LIFEPAK 8 Monitor. QUIK-LOOK ECG is amplified and frequency modulated for transmission acrass this optical interface. (See Figures 1-19 and 5-29.) ON/OFF Control. Power for the Defibrillator is electronically switched Gidercontrot-of either the front. panel ON control or the Monitor when PADDLES are selected. The Charger and battery voltage is monitored to ensure the ON/OFF CONTROL is reset when power is applied or voltage is 00 Tow. FIGURE 1-19. MAIN PCB ASSEMBLY INTERFACE SECTION BLOCK DIAGRAM The Power Supply PCB Assembly provides +12V¢, fused at 2.5K, to JIL pins ISA and 158, which is filtered by a network consisting of: C55, Boe, C48, C62 and LI. Zener diode CR30 provides over-voltage limiting: Power for the ON/OFF CONTROL, designated +12V, 1s derived by CR29, 12, Be and C45, +12V 1s controlled by conparator‘tircuitry centered around ti26.°"This circuft compares +12Vy to a reference voltage set by U25. When +12Vy fal1s below 7-3V, U26 turns Q23 off. When Q23 is turned off, +1aV_ 1s Fenoved fron’ the power on/off circutt. 1-60 ©ppR. 1985 PHYSIO-CONTROL1-103, 1-104, Section 1 Description The OFF state of UI9 fs assured by U26 and associated components when ac mains is not connected and when the batteries are too low. The RESET input of UI9 is forced high whenever U26, pin 2, is less positive than 26, pin 3. Actuation of the front panel power switch pulls J10, pins 29A and 298, to ground, which causes UI7C, pin 6, to go high clocking U19, pin 3. However, before reaching U19, sone signal conditioning is performed. | A low pass filter is formed by R85 and C52. This filter stops excessively short duration pulses from reaching U19, Two inverting Schnidt. triggers UITE and UI7D, are also included to provide positive input signal transitions. linen U19, pin 3, is clocked, the output 0, pin 2, is sent. to the D input, pins.” Tf Dts high, will go low with @ positive going clock, In this state, @ pulls the gates of 24 ‘and. G25 Tow. G24 end C25 conducts supplying S12, and +124,” to the Defibrillator. The +12Vp supply may be switched on regardless of the state of Ul9. Steering diodes CR31 through CR34 route the signals from UI9 and SYNC INTERFACE VALID for control of ‘the PADDLES output. With Defibrillator Power off, PADDLES are selected by a low on SYNC INTERFACE VALID. when ‘the Defibrillator power is on, SYNC INTERFACE VALID selects the EVECLOSE channel when Tow and PADDLES when high. Isolated Poner Supply. | Patient leakage current is limited to less than TOuk by the Use oF ah isolated power supply. Whenever *i2\, ison, the pulse width modulator, U11, chops this voltage at 30kiz as dBtermined by R20 and C18. The output is coupled to the isolated secondary of Tl. Isolated de voltages are derived from the circuit consisting of CRé, C14, C15, U9 and UI0. (See Figure 1-20.) Paddles Preamplifier. The QUIK-LOOK feature electrically isolates the ‘paddTes—‘Trom env’ ground.” Patient. leakage protection ts. ensured through the use of an isolated preamplifier. The incoming QUIK-LOOK signal is amplified and frequency modulated for transmission to the Monitor via an optical interface. The ECG signal from the paddles is applied to a differential anplifier made up of UIA through UIC. The output of this stage is a single-ended signal, at UIC, pin 8, with a gain of 500. Small de offsets are extrac- ted by’ UID which acts as a variable impedance source for the voltage divider formed by R12, R11 and RNI3, pins 4 and 8, This circuit effec- tively controls the size of the signal applied to the noninverting input of UIC, RIZ is adjusted to compensate for circuit tolerances and enhance common mode rejection. This circuit constitutes the slow de restore Toop. Large de offsets are sensed by a window detector made up of U2C and associated components. Whenever the output of UIC, pin 8, exceeds 23.0V, U2C, pin 8, goes low and turns off Ql. When Qi 1s off, the gain of UID is ‘increased as is the low frequency response of the differential amp. The result is that large de offsets are rapidly rejected. 1-61 © ape, 1985 PHYSIO-CONTROLSection 1 Description The circuit consisting of U2A and its associated components reduce the effect of ac signals comon to both paddle electrode inputs. This is accomplished by summing the conplement of such signals into the front end of the differential amplifier. FIGURE 1-20. MAIN PCB ASSEMBLY ISOLATED PREANP SECTION BLOCK DIAGRAM The single-ended ECG signal is frequency modulated by U3, a phase locked Toop (PLL). With a shorted paddle input, the PLL output, U3, pin 4, has a Lbkkz ‘square wave, which is set by C13 and R17.’ The frequency deviates = SkHz as the ECS signal input voltage changes at U3, pin 9. FET Q2 provides rapid switching of the PLL output to the opto-coupler, Us. The modulated ECG signal is fed fron U4, pin 3, to U1ZB, pin 6, for further processing by the optical interface. 1-105, Optical Interface and Accessory Cable. The Defibrillator carries on ‘osnaycommunveatTon withthe Monitor "via the Optical Interface Assenbly or an accessory cable. The accessory cable may also be used to communicate with a LIFEPAK 6s Monitor for synchronized cardioversion. Three separate optical channels are utilized to process Analog Data, Tri-State Control and Serial Data. Refer to Figure 1-2. 1-62 ©npe, 1985 PHYSTO-CONTROLCc 1-106. 1-107, Section 1 Description Optical Channel One. ECG/EVECLOSE data is multiplexed onto the inter- ‘Face by UISK, When PADDLES. is. selected by the Monitor, UISA, pin Il, is highs enabling the output of U12B, which functions as a comparator through 'UI3A, pin 14. During Pacing Cassette operation, UI3A, pin Il, is low and the two-state EYECLOSE is available at UIA, pin 14, acing Cassette operation overrides the paddles output via STAC THTERPRCE VALID. Re this tine, an-Shie EVES OPEN signal is present ot UL3K, pin 14. Upon receipt of ‘an EYECLOSE pulse, VISE switenes a 40ns, Slkkz burst to pin 18. Optical channel one is driven by Q4, Q5 and associated components. when UIBR, pin 14, goes Tow, Qé turns on’and Q5 turns off. The +12V step at the collector of Q¢ is differentiated by C19 and C20; creating a narrow spike which is fed to the LEDs. When UI3A, pin 14, goes high, Q¢ turns Off while Q5 is turned on by R90. The emitter of QS is switched to ground providing a rapid discharge’ of C19 and C20 through CRE and CRT. ‘These diodes also clamp the waveform to ground. 9 Selection of ECG or EYECLOSE/SYNC is handled ‘hrough the second optical chanel A trivstoves frequency moduloted, Signal is processed through UI3C which is defined as follows: ‘STATE DEFIBRILLATOR POWER CONDITION ACTIVE (Low) OFF NOTHING INACTIVE (LOW) on PADDLES kHz oFF PADDLES ki on SYNC/EYECLOSE alkHz on SYNC PULSE NOTE: The Bkiz and 31kHz signals are made up of 1.5us positive pulses. Selection of the SYNC DATA source 1s made by LIFEPAK 8 CABLE DETECT. A low at J11, pin 148, enables the CABLE input; a high enables the OPTICAL input.’ Selected SYNC DATA is ac coupled through C63 to a pulse squaring circuit made up of UZIA and U2IB. Inverting amplifier UZIA insures there is a signal of adequate strength to be processed by comparator U21B. The output of U2IB, pin 7, is a series of 1.5us, +12V pulses at the input frequency, The phase locked loop (PLL), Ul8, provides a de output at pin 10 which varies directly with the frequency at its input, pin 14. The leading edges of pulses fed to pin 14 are detected by a phase comparator whose output, pin 13, is used to control a voltage controlled oscillator (vco).” “If ‘the input is running faster than the VCO, the phase comparator output will be high a greater proportion of’ tine which increases VCO frequency. The phase comparator output, pin 13, 1s fed to a low pass filter consisting of R67, R76, and C57, which provides a triangle ‘input to the VCO, at pin 9.” As the VCO input increases, its Frequency output increases’ until the VCO is locked to the signal input. 1-63 ©ppR. 1985 PHYSIO-CONTROL1-108. 1-109, 1-110, Section 1 Description An 8 kHz signal from UI3C wil) trigger U24B and force its output low. {Inis. low 1s, SYRCTRTERFACE-VACID. The signal is inverted by UIE which turns Q21 off; allowing U23R, pin 13, to Float to +5V. Denodulation of a 31kHz signal (SYNC) will force comparator U24A, pin i, low. This SYNC ‘ig. inverted by U17B and fed to switch 238. The condition of LIFEPAK 6s CABLE DETECT determines which sync circuit has control of the syne interface. A Tow at U23, pins 10 and 11, enables the LIFEPAK 6s; a high enables the LIFEPAK 8. ‘The LIFEPAK 6s Honitor may be used to synchronize the LIFEPAK 8 Defib- rillator to a patient generated R wave. LIFEPAK 6s SYNC (J11, pin 138) is a tri-state signal that is used to indicate that the Nonitor is connected, the sync is enabled, and the sync pulse is present. When sync is requested, SYNC MODE goes high and toggles U20D, pin 13, high. Since the output of U20 is open collector,” LIFEPAK 6s SYNC is allowed to float as high as +12V. Normally, with ‘a LIFEPAK 6s Monitor Connected, this line will be held to less than +2.5V; sync is enabled but no R wave has been detected, Any circuit fauit that allows U208, pin 4, to rise above 8.5V will force U20B, pin 2, low which signifies LIFEPAK 6s sync interface is NOT valid. Detection of an R wave by the LIFEPAK 63 Monitor results in a 6.2ns, +5V pulse at U20C, pin 9. This pulse exceeds the 42.50 reference on’ pin and forces UZ0C, pin 14, high. This high level is routed through U23B as 2 SYNC PULSE to the Logie PCB Assembly. Optical Channel Three. The third LIFEPAK 8 optical channel is used Solely Yor DeFTUriTator serial data which is generated on the’ Logie PCB Assembly (Refer to paragraph 1-127). Energy Storage Capacitor Charger. The Energy Storage Capacitor (ESC) ‘Efardtr operates asa de-tande Step-up converter. The circuit is com prised of an oscillator, current switch and a flyback transformer. The Converter operates in the high power made when charging to 20-360J. Low power (slow) charging is used for refresh or when an eneray level of 1-10) is required. — Overcharge protection circuits disable the ESC charger if the high voltage output reaches S00QV. (Refer to Figure 1-21.) OsciTator/Control. The oscillator and control is comprised of 15, 06 ‘Through US and assoctated components. Timer U15 provides an unbalanced square wave, between 10 and 20kHz, to the current switching network made up of Ql1 through Qs. Eneray Storage Capacitor (ESC) charging is initiated when CHARGE goes high and Q6 conducts, however, the OUNB Tine must oo high, opening the dump relay through Qi0, before Q7 may conduct. Timer osciliation begins when UI5, pin 4, goes high. ‘The primary timing elements, C22, CR9, R24 and R25, contro} the total tine U5, pin 3, 18 high during each’ oscillator cycle. Internal U1S Comparators, fixed at one-third and two-thirds of #5.1V (set by zener Grid), sense the voltage on C22; forcing UI5, pin 3, high, when C22 is charging and Tow when its discharging. U15, pin '7, is’ switched to ground when the voltage at UI5, pins 6 and 2, equals two-thirds of S5c1V, providing a path for the discharge of C22 to the one-third reference. 1-64 ©apR. 1985 PHYSIO-CONTROLran. Section 1 Description FIGURE 1-21. HAIN PCB ASSEMBLY HIGH ENERGY CONTROL SECTION BLOCK DIAGRAM Discharge of C22 is controlled by RNIO, pins 3 and 4, Q8 and R26. AS long as_current is flowing in the secondary of T2, the base of 08 is, held off by -0.6V. When secondary current ceases, the CRO zener voltage ig reestablished, allowing Q8 to conduct and discharge C22. This hold- off period is necessary for efficient transfer of eneray and may be adjusted by R26. ‘The low power charge mode is enabled when HI/LO CHARGE is Tow. In this state, Q9 conducts and places C2l in the flyback circuit. The hold-oft period is increased because C21 slows the re-establishnent of the +3.3V zener potential of CRI. Rapid discharge of C21 is permitted by CRil. Low battery compensation is provided by UL4A. Should battery voltage drop to +8V, UL4A, pin 1, will go high and’ supply additional charge current to C22.” Rapid charging of C22 reduces the pulse width output from U15, pin 3, which in turn, shortens the current switch on time. Current Switch. Large currents must be switched through the primary of luring DeffbriTlator charge. Q1é conducts when Q13 is turned on by a high from UIS, pin 3; QlI and QI2 are off and C24 is charging through CRI. Primary current flows during this period and energy is stored in the core of T2. After 60us, U5, pin 3, goes low. Q14 and Q13 are now off; Q11 and Giz turn on. ‘Conduction of 12 grounds the positive side 1-65 ©npR. 1985 PHYSTO-CONTROLie. 1-113. 114, Section 1 Description of C24 and couples a negative turn-off spike to the base of G14. The rapid turn-off of Q14 increases charger efficiency. As the prinary field collapses, a high voltage current pulse is induced into the secondary of T2. This positive pulse is applied to the Eneray Storage Capacitor through the forward biased CRIB. Diode CRI7 clamps the base of QI4 to -0.6V. C23 speeds up turn on of U2. _CRZO protects Ql4 by shunting inductive voltage spikes that would exceed its maximum collector to enitter voltage. Overcharge Protection. The Defibrillator Eneray Storage Capacitor (ECS) ‘$Eprevented tron charging above *5000V in the event of a failure of the Logie PCB Assembly. HI VOLTAGE DIVIDER 42 is monftored and conpared against a 42.5V reference by UB. If the inverting input of U148 exceeds the noninverting input, U148, pin 7, will go low, turning on Q11 fand inhibiting ESC charger operation. Energy Storage Capacitor voltage must be reduced to less than 1000Vdc before the overcharge protection circuit releases its hold on the charger. RESET INHIBIT prevents U143 from latching, at power-on, through the conduction of (26 and Q15. ESC High Voltage. Voltage dividers provide a low voltage analog repre- entation of the Eneray ‘storage Capscitor (ECS) voltage. CR2B. clamps the divider Vines to Vg in case the diviger grounds open. R40 and C26 ensure the charger will not charge into an open circuit should the output, at P2l, open. High frequency noise from charger operation is shunted by C28 and C3i. Transfer/Dump Relay Drive. The transfer and dump relays are activated By controT ergnals—tron the Logic PUB Assembly.” ‘The dump relay must ‘open prior to activation of the ESC charger. Once charging is complete, a two step transfer conmand must be received before energy is delivered to the paddles. NOTE: The dup condition is a norma] state for the Defibritiator. Energizing the dump relay or its drive circuitry implies that relay contacts are being opened. The term dump refers to the transfer of stored energy in the Storage Capacitor. The dump relay is energized when OURP goes high and turns on Ql0, providing a current path from ground through the relay to *12V;. The fransfer relay. 1s. armed when the discharge switches are closdd by a ‘ow on TRANSFER ARM. The Logic PCB Assembly delivers a 200ns, positive pulse to the base of Q18 when all conditions for transfer have been met. Two transistors, Q17 and Q20, mist be conducting simultaneously for the transfer relay to energize. Safety is insured, in that no single shorted transistor will cause the Defibrillator to transfer. TRANSFER SENSE goes high when the discharge switches are closed and low when TRANSFER goes high. TRANSFER SENSE is routed to the Logic PCB for use in SYNC TEST. 1-66 ©rpr, 1985 PuYSTO-CONTROLc Cc ns. 1-116, Section 1 Description LOsTC PCB ASSEMBLY (802725). The Logic PCB Assesbly controls and monitors many of the LIFEPAK 8 Deftbritiator functions. These functions can be separated into. to Categories: user input, processing and mode control, end system status Sonttoring. and generation of user status indfeations. (see Figures :22'end'8-30.) These tasks are accomplished through the use of two interconnected inicroprocessors. The Controller microprocessor, U18, accepts all user ‘inputs and controls Defibrillator charge, discharge’ and energy dump. The Controller microprocessor also drives’ the low energy digit, charge and sync indicators. The Monitor microprocessor, Ul, controls the available energy display, test Toad energy display and their associated Vegends. In addition, U1 controls the alarm, service and low battery legends, and formulates Defibrillator status information for serial output to the LIFEPAK @ Monitor. The microprocessors execute self-test routines continuously so any fault that presents a hazard will result in the disabling of Defibrillator controls. Other faults, of a less critical nature, my result in par- tially disabled functions. For example, a transfer timing malfunction will “inhibit. sync discharge. Efther a “fault or hazard condition will result in a service alert tothe user. “Most malfunctions resuTt only in a service alert. Reset Circuits. During power-on of the Defibrillator, the micropro- Gessors are reset to starting program address 00004. This reset state is held for 100ms to allow the Logic PCB Assenbly power supplies and clocks to stabilize, System integrity is then monitored continuously ‘and, a system fault reset is generated if a malfunction is detected. Hatchdog ctreutts are disabled until the reset cycle 1s complete and microprocessor operation begins. The +5¥ power supply 1s compared to +2.SUREF4 by UISA through UISC. An RC network formed by RD, Ri0, C26, and C27 conditions the POWER Ok Stgnal 'so that a decrease ‘nthe %5V supply will rapidiy erigger a RESET Gyele. "As C26 and (27 charge, POWER Ok reaches 42-8V; forcing the open collector outputs of UISA through UISC high. C19 will begin to charge, through 828, toward #5V. The output of UI2F, pin 12, is driven high, providing 2'2,25s RESET THHTGIT, untit C19 charges sufficiently to be Considered a iogic 1. this inhibit is applied to. NOR gates. ULIB. and ULID ‘eausing thetr outputs to be Tew which are Inverted by UI4A and UI4G respectively. The RC tine of RNG, pins 6 and 11, and RA7, pins 4 and Lis determines the 10065 duration of power up RESET signals applied to 1 microprocessors. For the -08 assembly, UISB is configured with R63, R64, C53, and Vref 4 to form the reset circuit for both microprocessors in the’ event of a surge in the *5V supply. This circuit, together with UI5A and UI5C, function as a window comparator for the +5 power supply microprocessor reset circuit. If the microprocessor does not trigger its watchdog by the time RESET INFTBIT goes Tow, the microprocessor will be reset. In this case, the 1-67 ©npr. 1985 PHYSIO-CONTROL1-17, ins, 1-119, 1-120, ila. Section 1 Description User must bring the microprocessor out of reset by pressing the CHARGE Switch. This action grounds UISA, pin 1, discharges C19 and generates another RES 2 Watchdog and Power Monitoring. The watchdog circuits are used to ‘Giteratae i7" the microprocessors are operating within Defibrillator design Tin If for some reason either microprocessor fails to function, their respective watchdog will issue @ ‘command. NOTE: The watchdog for UI8 is discussed in paragraph 1-125, Controller Inhibit. The UI watchdog operates in the sane fashion as the UIB watchdog. UTA, pin 4, is retriggered, Keeping Gy pin 6 highs by the chip "select Grlginaing et Ute pin 27 Intarrntion ofthis Goma! it! cau 82 Go dow and’ pin’ 7 to-go high. The Q output of UTA 1s fed to « NOR 3 eta whose output will bes high it the RESET TRITBTT is low. This High ts auto verted hy UT, Gatmreg Cll, and ecoes RSET fr uns. Voltage Reference Regulators. The Logic PCB Assembly requires voltages ‘Seber than the: s12V" suppTiee by the battery or the Power Supply PCO Assenbly.. To develop these voltages, +12VA 1s applied to three-terminal regulators, U16, Ul?, and U26, and’ zener diode CR3 producing +5V. for Joie, S5VREFL » +2,SVREF2, and 42.SYREFS. A fourth reference, VREF3, fe-used to clamp analog signals to *5Vdc. "This reference is taken from the emitter of G3 and 15 set at 4.30 by the voltage drop across CR4 and crs. Unregulated -10Vde Power Supply. Unregulated -10Vde is used to Pinte S enrough OTs oF the energy select circuit, are turned off when they are supposed to’ be. Since ~10Vde 1s not generated elsewhere, 2 charge punp 1s used. The 977Hz output from the clock divider, U22, is fed to UI3F, pin 6, here +5Y logic is converted to +12V signal level. A high at U13, pin 13, charges. C15 to +12V through CR20. When pin 13 goes Tow, C15 will have -12V stored with respect to ground. This -12V forward biases the helf wave rectifier, CR19, and C15 distributes its charge to C16. The voltage at C16 is the unregulated -10Vde. Clock Divider. Division of the IMHz E clock is used to derive 500ki2, iy Gkliz,, 1953Hz, 9772 and 488Hz square waves for use in other Defibrillator circuits. This frequency division takes place in U22, a twelve stage binary ripple counter. Switch and Interlock Sensing. The Controller microprocessor, U18, Seiten ate TaTUS OF the Switch and interTock inputs at. 8 1200H2 rate: ‘Any switch closures result. in a mode change and the output of KEY CLICK. Switen and interlock inputs to the Controller microprocessor, U18, are converted from parallel to serial foreat by U20 and U2l. These parallel fn and serial out shift registers load switch status when pin 1 of U20 and U21 goes Tow, Latch 1s again set high by Ul8, pin 15, and the Controller microprocessor outputs 2 serial shift clock that moves data, starting with the post significant bit, through U21, pin 9, Yneo UAB, pin 9. 1-68 ©npR. 1985 PHYSIO-CONTROL 9Section 1 Description coe FIGURE 1-22. LOSIC PCB ASSEMBLY BLOCK DIAGRAM 1-69 ©ApR. 1985 PHYSIO-CONTROL,Section 1 Description NOTE: The data in U20 must shift into U21 before entering u1B. 1-122. Key Click and Alam Logic, Alarms are used to draw attention to the ‘Seitis ofthe DorTEriTTator. A low frequency tone. indicates Deribr’ ioe tor charge is complete and’ ready to discharge. A high frequency tone indicates failures or low battery. Key clicks provide the user with audible feedback to show that @ key comand has been recognized. A KEY CLICK command may originate in the Pacing Cassette or the controller nicroprocessor. 4e8Kz_and_1953Hz, from the clock divider, are routed to U25A and U25B. A COWFREQUENCY coomand fron UL, pin 23, enables 488Hz through U25A. This signal is inverted in U25C and U2SD where it is applied to UL4C for output to the speaker. A 1953H2 signal is gated to the speaker whenever UBB, pin 11, goes low. UB is 2 dual one of four decoder; a two bit input code drives one of four outputs high. With tone disabled, UL, pin 20, is high which forces USB, pin 11, high. A high input at UBB, pin 13, fron TONE ON or @ low at UBB, pin 14, will enable 1953Hz through 258, Signal flow is now the same as that for 488Hr. KEY CLICK is a short +5V pulse that is fed to the speaker whenever @ switch closure is detected on the Defibrillator or Pacing Cassette. CRI and CR22 form a logical OR gate to steer the KEY CLICK conmand, 1-123, Energy Select and Charge Lint. The Controller microprocessor, U8, yeade the eneray Selector through the partic! to serial shift register, Ul, The energy select switch provides. the following four bit code! Pi ping pipin10 © Plpin32 PL Pin Low 109 209 309 509 1003 1509 2003 3003 360) If LOW is selected, energies between one and nine joules may be selected by the use of the Tow eneray increase and decrease switches. The energy select word, described above, is used within UI8 as one input to a digital energy ‘conparator. The second input to this eneray conparator is developed by successive approximation register (SAR) U19 that converts divided capacitor high voltage to a digital word. The Controller microprocessor samples ‘the SAR at a 1200Hz rate, A 1-70 ©ppR. 1985 PHYSIO-CONTROL124, 1-125. Section 1 Description comparison of these two words are used to continue charging, dump energy, initiate refresh or terminate charge and illuminate the AVATLABLE legend. The signal input to U19 must be scaled to a range in proportion to the energy level selected. A voltage divider 1s formed between the Energy Storage Capacitor and ground. A tap on this divider is applied to pin'5 of Ul0B, an amplifier with gain adjustable by varying R19, to correct Circuit’ tolerances. The division factor is determined by grounding resistors in RNS. "A three bit word, from UI8, pins 27 through 29, is input to mltiplexer U24 which selects one of ‘seven outputs, connected t0°Q5 through Ql. The output is switched from -10V which turns the FET off to OV which causes the FET to conduct, resulting in a resistor in RNS being selected. The following table shows which resistors are grounded for a particular energy setting. 100-150 Joules 200-360 Joules Energy Selected AKS_Pins Grounded 1 Joules 9 2-3 Joules 9,3 4-6 Joules 34 7-10 Joules 35 20-30 Joules 3,6 50 Joules a7 a8 a2 Dump and Charge Control. Before Defibrillator eneray can be stored, the ‘Ginp-retay “mast be opened, the charge oscillator must be enabled and either the HI or LOW charge’ rate mist be selected. ‘The Controller microprocessor wiTl make 2 determination, based on soft~ ware, of the charge status. Upon receipt of a CHARGE command, U18, Pins’10 and 16 go low activating OUNP and CHARGE respectively. The HI charge rate is used for selected energies from 20 joules through 360 Joules. LOW charge is used for 1 joule through 10 Joules or refresh, Status Indicators and Energy Display. Front panel indicators are driven by several circavts nthe Logie fee Assembiy The available energy display segment code is provided by Monitor microprocessor Ul, pins 13 through 19. This display word is applied to high current Darling- ton transistor array US, that provides energy display segment drive. Low eneray digit, charge, and syne mode indicators are developed from ‘the output of U23, a serial to parallel shift register. Data is shifted into U23 when its strobe input is high. U18 then outputs serial shift clock pulses from pin 14 and provides the data at U23, pin 13." The parallel outputs of U23 are enabled as long as the CONTROLLER OK output at U8, pin 19, is active. The seven segment displays, status, and some legend LEDs are mltiplex- ed. UBA is a one of four decoder. The input from UL at UBR, pins 2 and 3, determines which outputs, QO through Q3, will be active, U13 isa hhigh current source driver for the LEDs. The decoder select Vines are An ©ppR. 1985 PHYSTO-CONTROL1-126. Section 1 Description updated once every 6.8us (approximately 166Hz) with each one active 25% of the time, BATTERY and CHARGE Tegends are active independent of the microprocessors. ‘The SERVICE legend is activated by Ul or the Monitor microprocessor watchdog, U7A. ‘Analog to Digital Conversion Multiplexer. To provide the greatest Flextovitey and ensure” maximum UeiTization of Monitor. wicroprocessor resources, nine analog inputs are sampled by a multiplexed analog to digital converter. This device, U2, has as its inputs: TRANSFER SENSE, PADDLES 1 CAL, BATTERY, H.V. DIVIDER #2, VREFL, VREFZ, PACE AMPLITUDE, SYNC LEGEND and PADDLES’ CURRENT. Actual A/D conversion is accomplished by sample and hold and successive approximation. The Monitor microprocessor program calls for a specific ‘analog signal’ conversion through the output of U2, pin 15, and a four bit serial address to U2, pin 17. At the sane tine, UL supplies eight. serial clock pulses to the 1/0 clock input of U2. "Eight clock pulses are used so that an address may be loaded at the sane tine as an eight bit serial data word is output to U1, pin 30. Upon completion of this data/address shift cycle, U2, pin 15, goes high and the conversion cycle begins. The conversion’ takes place during the forty E clock periods Following the eighth 1/0 clock pulse. A protocol for sampling is implemented in software. If 100 joules or 360 joules charge 1s commanded, the Monitor microprocessor will deter- imine if the paddies are stored and the Pacing Cassette is not installed. Having met the above conditions, the Monitor microprocessor will acti- vate U2, pin 6, for 100 joules’ or U2, pin 5, for 360 joules paddles current ‘sensing. U10A, pin 1, provides'a divide by one analog represen tation of paddies current for use by U2 during 100 joules test load reading. A resistor network, RNS, pins 10-12, divides the current by two for use in the 360 joules ‘test oad reading. PADDLES I CAL is used to provide compensation for circuit tolerances Rl provides a + 258 adjustment range to the test load calibration, PRODLES I CAL and PADDLES CURRENT samples are then factored into the calculation of test load energy delivered. HIGH VOLTAGE DIVIDER #2 fs used by the Monitor microprocessor to deter- imine how mich energy is stored in the Eneray Storage Capacitor. The voltage sample from USA, pin 1, is used to generate the energy available display on the front panel. 'R3 is for calibration of this display. TRANSFER SENSE 1s tested continuously and is used to look for open or shorted transfer drive transistors, Ql7 and 20, on the Main PCB Assenbly. SYNC LEGEND 1s sampled by U2 to determine that it 1s active when in sync and inactive when in the Defibrillator mode. A fault detected results na SERVICE alert. Voltage references are used extensively in the analog to digital converters. For this reason, VREFI and VREFZ are sampled by U2. These 172 Sper. 1985 PHYSIO-CONTROL 7c 1-27. 1-18. 1-129. Section 1 Description samples are used by the Monitor microprocessor to calculate the ratio between the voltage references. Any error in this ratio results in 2 SERVICE alert. BATTERY is sampled by U2 so that the Monitor microprocessor can give a LOM BATTERY alert. This alert occurs when the battery reaches 10V or when twenty-five 360) discharges have occurred while running on batteri— Gontroler Inhibit. Since the Controller micropracessor controls poten= ‘Tally hazardous voltages, circuitry that monitors and disables its ‘operation is provided, In normal operation, a 300H2 CONTROLLER OK signal is sent to the Monitor microprocessor and "U78, pin 12. U7B is a retriggerable monostable multivibrator with a pulse width of 4.02ns. As long as U78, pin 12, is, clocked at 300Hz, pin 10 will be high and pin 11 will be low. ‘Any interruption of CONTROLLER OK or a Tow on CONTROLLER RESET at U7B, pin 11, will cause U7B outputs to switch states. This condition results in 2 Controller microprocessor reset and disabling of the CHARGE, DUMP, and TRANSFER Tines by grounding them through C12. Transfer Relay Control. For safety reasons, the transfer relay is only energized after the following conditions have been met: the Defibrilla~ tor has energy stored within the correct tolerances refresh isnot active in SYNC mode; APEX and STERNUM paddle discharge switches have been activated for a minimum of 125ns; the Controller microprocessor has recognized 2 discharge comand; and SINC pulse is present if tn the SYiC rode, The APEX and STERNUM discharge switches are normally open. hen dis charge is required, the switches are closed, applying ground on P10, Pins 22A, 228, 21A and 218. NOR gate ULIC, pin 10, goes high, with doth switches’ closed, signaling the Controller microprocessor that transfer is required. 019 and Qi3 are biased on, with lows on their bases. 45 fs placed on the noninverting input of comparator U9A which forces its output high. This signal splits into two: TRANSFER ARM is sent to Monitor microprocessor U1, pin 25, and TRANSFER ARM OUT is inverted by UI4F and sent to the Main PCB Assembly. The RC time of R27 and C21 determines the mininum tine TRANSFER ARN will be active, For the -08 assenbly, the transfer signal at the collector of Q13 is also fed to U2, pin 11 through R61 and R62. This provides redundancy for the transfer signal, which is monitored by the monitor microprocessor U1. The TRANSFER output P10, pins 19A and 198, goes low for 200ns. Failsafe operation is ensured because the collector of Ql5 can only go high if Ql2 is off. The negative going 200ms pulse, is fed to Ul, pin 26, for use in the sync test software, display mode software, transfer drive test, low battery detection, and test load operation. Serial Data Transmission. The Defibritiator sends serial data to the Wonttor via the Optical interface Assembly. A serial data string 1s fed 173 ©ppR, 1985 PHYSIO-CONTROLSection 1 Description from Monitor microprocessor U1, pin 12, to inverter U128. This inverted 450 logic 1s converted to +12V logic’ by UI3A and fed’ to the Optical Interface Assenbly. 1-130, PACING CASSETTE The LIFEPAK 8 Pacing Cassette (see Figure 1-23) {s a microprocessor controlled transcutaneous pacemaker. It operates in conjunction with the LIFEPAK @ Monitor and Defibrillator to provide denand and nondenand pacing pulses for short-term support of patients with circulatory prob- Tens. All electronics, displays and controls required for pacing logic ‘and pacing pulse generation are contained within this cassette. How- fever, it is supported by power supplies and electrical interfaces pro- vided by the Defibrillator and indirectly by the Monitor. 1-131, PACING CASSETTE PFC ASSENBLY (802911). The Pacing Cassette PFC Assembly (see Figure 5-40) developes and produces the outputs required for cardiac pacing. 1-132. Microprocessor. The Pacer microprocessor, U9, controls all functions performed by the Pacing Cassette. Programing for. the microprocessor fs. stored in an integral 4k by 6 bit RON. The operating mode of U9, single chip mode, 1s selected by the state of P2(0-2) at reset. In the single chip mode, 211 ports my be configured as inputs and outputs. The Pacer microprocessor assigns the inputs and outputs as follows: Port 1(0-4) Port 2(0,2-4) Port 3(0-3) Fort 3(4,5) Port _4(0~7; Beet tay Gee ba Sects? | Gotpoe-otty | Taper Orig When +12Vde is present at J2, pin BL, U10 provides a regulated +5¥dc to the Pacing Cassette circuitry. The Pacer microprocessor is now powered. However, remains low for an additional 20ns because of the RC time of RN7B and Cél. This allows the power supply and oscillator to Stabilize, Khen’ RESET goes high, U9 starts its program and selects single chip operation. 1-133, Control and Display Circuit. The Pacing Cassette is active whenever DeFibriTlator power-Ts-on-~ Status of the DEMAND, NONDEMAND, START’ STOP and RATE switches is determined every 10ms ty U9, port 4. Upon detection of a switch closure, the microprocessor will ‘output KEY CLICK, {Muminate or extinguish the appropriate display, and enter the selected node of operation. Port 1 of U9 fs connected to a Darlington transistor array, U8, Each of the transistors in UB has {ts collector tied, through current Timit~ ing resistors, to. the cathode of an LED on ‘the Switch Display PCB Assembly. The anodes of the LEDs are tied to +12V. A high from any bit fon port 1 will turn on its respective transistor and provide a current path through the LED. 1-134, Pulse Width Modulator. Isolated power supplies and pacing pulses are ‘developed from outputs of the pulse width modulator, Ul1. The frequency ‘at which ULL operates is determined by R22, R66 and C18. Operation is Centered at 30kH2 with a =5kH2 adjustment range. Pacing pulse output is adjusted by R66. 174 ©npr. 1985 PHYSIO-CONTROL1-135, 1-136, 1137, 1-38. Section 1 Description [A redundant soft start scheme is used to protect (3 through Q6 from potentially damaging current surges. Output. switching from U1 is Sohibited until C16 is charged by an internal current source, When oscillation begins, the oscillator output, Ul1, pins 11 and 14, is fed to the gates of Q3 through Q6 and U13. slated Power Sui Pacing Cassette power cones from the Defibrilla~ Tar nidtde cireute-~ Patient: protection from hazardous. leakage current is established in ‘the isolated power supply circuitry on the Pacing Cassette PFC Assembly. A 30kHz square wave drives the chopper circuit made up of 03, Q4, and 12, The gate drive from U13, pins 4 and 12, is 180° out of phases while one FET 1s on, the other is off. When Q3 conducts, current flows in one half of 12's primary, storing energy in the transformer core. This energy is transferred ‘to the secondary when Q3 turns off and the stored energy field collapses. AC voltage from the secondary is rectified by Che" and filtered to provide isolated = 12Vdc. A =5V supply 1s developed from #12V by regulator U4. Pulse Generator. The pulse generator, U11, develops positive 20ns ‘trapezoidal pulses for application to the center tap of TI. The pulses are varied in amplitude by adjusting the PACE AMPLITUDE potentioneter, REE. The +5V supply connected to R6B is a precision reference output from UIL, pin 9. When the microprocessor determines that a pulse is necessary, U9, pin 10, will be set low for 2 period of 50ns. After 20ns, U9, pin 8,” goes ‘ow which renoves ground from R100 and C31. The voltage at’ R68 is’ gated to'@ pulse shaper made up of C30 and R63. The pulse shaper converts the gated voltage input to a trapezoidal pulse with 2 20% slope from the leading to trailing edge. R63 and C30 fare selected to provide a linear slope to the 20ns pulse. Diode ck24 Clamps the positive input of U1ZA to ground, preventing this pin from going negative. Shaped pacing pulses are then fed to an amplifier loop, made up of UIZA, 8 and Q7, which provides a voltage gain of 1.8 as set by R59 and REO. This results in a current gain between UI2A and the collector of Q7 which provides 0-9¥, 9A maximum trapezoidal pulse to the center tap Pacing Pulse Output. The gates of pulse chopper FETs Q5 and Q6 are ‘river continuously but switching occurs only when voltage ts present on the center tap of Tl. A trapezoidal pulse 1s gated to Tl when a pacing pulse Is necessary. "QS and G6 are protected fron overvoltage by zener iodes CRIB and CRi9. ‘When pulsed, a voltage is induced in the secon- dary of Tl which is rectified by CRI and filtered by Cl and CR3 for PACE output. Leads Off Detector. The Pacing Cassette leads off detector senses external impedance to determine continuity of the Pacing Cassette output circuit. In a sense, 175 ©npR. 1985 PHYSIO-CONTROLSection 1 Description LEFT BLANK INTENTIONALLY 1-76 ©npe. 1985 PHYSTO-CONTROL2a. ‘SECTION 2 ‘OPERATION ‘OVERVIEW This section of the manual contains information and procedures for the operation and perfodic testing of the LIFEPAK 8. A list of accessories ‘and replacenent itens is also provided. ACCESSORIES AND REPLACEMENT ITEMS The following list 1s provided for reference only. Customers should contact the factory Order Desk or a District Office when placing an order. Ac Power Strap (803395-00) Adult External Paddles, replacenent DefibritTator Cassette’ (802903-00) Defibrillation Electrode Cable (803461-01) DERNA JEL Electrode Jelly 4 oz. tube (9-10236-00) Case, twelve tubes (9-10236-012) Disposable FAST-PATCH Defibrillation Electrodes Carton: 5 sets of 2 pads (803630-105) Case: 5 cartons. (803630-125) Disposable QUIK-PACE Pacing Electrodes ‘Shelf pack: 5 set of 2 electrodes (803377-501) Case pack: 5 shelf packs (603377-251) 6 Paper. Box, 3_rols/box (801262-003) Case, 50 boxes/case (801262-150) Electrode Accessory Kit, 12 lead (800153-00) contains the following: ‘netal aduit lind electrodes (3-10179-00) 4 adult Tinb straps_(9-10181-00) 430'm suction cup electrode (8-10183-00) 15 am suction cup electrode (9-10178-00) 5 tead patient cable (5-10817-00) Internal Paddie Handles and Connector (800461-02) specify paddle size from the following: 2.5 cm dianeter Internal Paddles, pair (aut 3:8 om diameter Internal Paddles, pair (802154-11) 5:1 cm diameter Internal Paddles, pair (802154-12 6:4 cm dianeter Internal Paddles, pair (802154-13) 8.9 cm dianeter Internal Paddles, pair (802154-14| LIFEPAK 6s Sync Kit LIFE PATCH ECG Electrodes, adult, pre-gelled Box of 75 (800139-075} Case of 300, 4 boxes/case (800139-300) Nonitor/Defibritlator Interface Cable (803371-00) Operating Instructions LIFEPAK 8 Moni tor/Defibréliator (803334-02) QUIK-PACE External Transchest Pacing Cassette (803369-02) 2-1 apr. 1985 PHYSO-CONTROL,Section 2 Operation ae a FIGURE 2-1. MONITOR FRONT PANEL CONTROLS AND INDICATORS 22 ©npR. 1985 PHYSTO-CONTROLSection 2 Operation Operating and Service Manual (803195-05) Pacing Cable. (802905-02), Pacing Cassette (802904-04) Paddle Assembly, external, sterilizable (804507) Patient Cable, 5 lead, replacement (9-10417-00) Patient Cable, 5 lead, European (800948-00) Patient Cable, 4 lead (800289-00) Patient Cable, 3 lead (9~10418-02) Pediatric Paddle, external (800418-00) Pole Mount Bracket, for ECG Monitor (802807-00) Posterior Paddle, external, adult (802461-00) Printhead Assembly, replacement (802842-00) Recorder Writing Stylus, replacement (801553-00) Stylus Adjustment Too! (801470-00) Seylus Insertion Tool, replacenent (801513-00) Stylus Replacenent’ ity” includes stylus insertion toot (801590-00) Wall Hount Bracket, for Eos Monitor (202606-00) Walsh Suction Cup Electrode, 18mm, replacement (200521-000) 2-3, CONTROLS AND INDICATORS. The following provides a brief description of the Control and Indicators on the LIFEPAK 8 Monitor, Defibrillator, and Pacing Cassette. TaBLe2 owITOR FRONT PANEL CONTROLS AND tROTCATORS rigune | conrao. oe FueTion ero. | ShoterroR @ [a Push button ewitch turns Monitor on and off. Cia" Tluninates ‘whet Of @ | cewsesecr [push tutton switch selects _€06 inputs Paatiess std, Leeds 1. Tf fire nm. As RIF, Wonitor is Sutomat ically 46 esd TI when activated (in Paddles when activated by “Deribrilvator). "Push moneneartly ts auvance one posifton. Pushesans holes tive through Sciectlons raptaty. E06 Size Control adjusts vertical. size of £08 trace on ERT and Recorder. “A xt goln ts selected Sitomticatty at powrcone © Push Saxe nr tS indrcase' or docréase ize, raeeze Switch freezes the RT display and routes feat eine Eee Yo the kecorabe tt Wets ‘inning in DELAY ode © | Maw stuence | push to silence alarms, Alor will vemnin Siat°rdr oppositely one mittee 23 ©npe. 1985 PHYSTO-cONTROLSection 2 Beret ion TABLE 2-1 (Coninued) YONITOR FRONT PANEL CONTROLS AID_INOICATORS rroune | congo. on roncrion eee. | inoreeroe @® | cow aam Sitch sets Tow Timit for heart rate, Range" is 20 Sco! apn. aes A US reuse or crease, WG ALA witch sets igh limit for_peart rate. to increase or decrease. Range 1s 80 - 240 BPH. Push im or AL Depressing switch superinposes a Inv cali- Tead position. Inactive bration signal on CRT and Recorder in any in SYNC mode. RS VOLUME Contro} adjusts volume of systole beeper. Push aim or “WW to increase or decrease 50 m/s Push button to select 50 m/s speed for CRT 25 m/s. and Recorder. Push again to return to Low BATTERY TMuminated message indicates voltage is below normal operating level. battery BATTERY TMluminated message indicates battery, not ac Tine voltage, is the power source. internal BATTERY CRG TMuminated message indicates battery charging and ac power is applied. SERVICE IMuminated message indicates Monitor mal~ technician. function requiring service by qualified DELAY Depressing switch places Recorder in DELAY mode. Recording 1s delayed 10 seconds from real tine. An LED in the switch is 1l1umt~ nated when DELAY mode is activated. DIAG Depressing switch causes Recorder to be in real tine diagnostic mode. When DIAG is pushed an LED In the switch ts tlluminated. qq aggqgegaqg ee a eo EVENT If depressed while Recorder is running, an during tined run. event mark will appear followed by the tine ‘and day. If not running, the Recorder will ‘turn on for 20 seconds’ and annotate the recording. An LED in the switch iTuminates 28 © npr. 1985 PHYSIO-CONTROLTABLE 2-1 (Continued) Section 2 Operation MONITOR FRONT PANEL CONTROLS AND INDICATORS Ficune ]cowrra. on FunTION kev no. | inovestoe @® | ann Control for automatic activation of Recorder vihen alarm 11 Seconds of pi postealarm, 1 alarm, depres: and disarm aul ininated when its are violated. Records. ten re-alarm data and 10. seconds Recorder is running due to an ‘ing switch will stop Recorder ‘o mode. A switch LED is iTlu- uto mode is selected. Patient Connector Connector for! Cable, Physio-Control 6 pin Patient ® © Recorder Records ECG paper. Print: ‘ing mode, 1 events. ind annotation on standard ECG date, time, ECG size, record sad configuration, and marks Nessage Display Indicates syst SYNC: USE Li ren status: PACING LEADS OFF, ADS, and PADDLE SIGNAL LOSS. Trace sHonfade displ left. y trace moves from right to Calibrated Gain Display indie: 2 enn to 4 tes actual gain selected from 0 cma. ® Qe) @ © © © © Lead Select On screen indication of lead selected. Indicator Low Alam (On screen indication of low alarm setting. Indicator Heart Rate Digital display of QRS rate from 20-300 BPM. High Alarm (On screen indication of high alarm setting. Indicator QS Indicator LED Heart blinks on at each QRS detection. 25 Cape. 1985 PHYSIO-CONTROLSection 2 Operation TOIL POWER CORD RECEPTACLE FIGURE 2-2. MONITOR REAR PANEL CONTROLS 26 ape. 1985 Puvs10-conTROLSection 2 Operation TABLE 22 MONITOR REAR PANEL CONTROLS FIGURE ‘CONTROL OR FUNCTION Key NO. | INDICATOR NAINS. POWER. Rocker switch to select ac line power (ON) or battery power (OFF). 2 ANP FUSE Fuse for ac voltage/current overload protec- ton. Voltage 110/220 Slide switch to select Tine voltage. Factory preset. (Covered by label.) gq Ggoq gq G9 Ground Equipotential ground tie point. SPARE Storage for spare fuse tn 115Vae tnstrments ony. S1STOS Gomector to interface Instrument with other Fhystottontrol” coulpnent vor’ “LIFEPAE'E befibrilictor. for" syne intercomect "vie «| cebter "Contains tv cee outputs TINE/OATE Hecessed push buttons for setting the real tite lock woe Causes CHT to display clock fHeld to be tastes, ser Increnents selected field. @ | aw vo. Rotary control to. tnerease or decrease Volare of"alarm tones”"Eamot be Sajusted Tibtus. ® CRT BRIGHT Rotary control to adjust brightness of CRT display. 27 ©ppR. 1985 PHYSIO-CONTROLSection 2 Operation PHYSIOCONTROL FIGURE 2-3. DEFISRILLATOR FRONT PANEL CONTROLS AND INDICATORS 28 Sap, 1985 PHYSIO-CONTROLSection 2 Beetatlon TABLE 23 DEFIBRILLATOR FROKT PANEL CONTROLS AND tOTCHTORS rime] coro. on Function vio. | Tratetton © [rm Wain power contro’ (push) for DefibriNetor functions. Push button iTluminates when Power 1s on. Also activates Monitor when instrunents are connected. @ 2 ENERGY SELECT JOULES Rotary switch with 10 discrete delivered energy levels: Low, 10, 20, 30, 50, 100, 150, 200, 300, and 360 joules. ‘3 CHARGE Nomentary push button to initiate oefibri]- ator charge cycle. Push button LED flashes When instrument. is charging, glows steadily when selected charge is reached. Charged eneray 1s available for approxinately one minute. ENERGY Display Window Window for digital display of energy being charged (nunbers scroll) or fully charged (numbers ‘steady, AVAILABLE ENERGY message iMuminates). "Also displays amount of energy delivered into test Toad when either 100) or 360) is discharged (ENERGY TEST message iTluminates). Low Energy ay Controls to adjust energy for levels between 1 and 9 joules inclusive when LOW is select~ ed on ENERGY SELECT. 5 joules is preselect- ed. Push <2 to increase or ~> to decrease. LOW Energy SELECT Window Displays selected 1ow energy. I1Tuminated only when LOW is selected. ge aq oO sinc Nonentary push button switch to select synchronized mode (LEO will {lluminate). To Feturn to defibrillate (asynchronous) mode, depress button again. SYNC MODE Message illuminates when syne mode is sel- Nore: ected. Message flashes with each detected as. Defibritlate mode is automatically selected when Defibrillator is activated and ENERGY SELECT fs set to any energy level. Defibritiator automatically returns to ‘defibriMate mode after each SyRenronous discharge. 29 ©npR. 1985 PHYSTO-CONTROLSection 2 Operation ‘TABLE 2.3 (Continued) DEFIBRILLATOR FRONT PANEL CONTROLS AND INDICATORS FIGURE CConTROL OR FUNCTION Key NO. _| INDICATOR BATTERY HRS Illuminated wessage indicates battery 1s charging and that power source is ac Tine. BATTERY IMuminated message indicates that power source is the internal battery. Low BATTERY Hluminated message indicates battery power is Tow. @| O} © © SERVICE Iluminated message indicates system mal- function requiring service attention. PADDLES AND STORAGE AREA © STERNUM Paddte Defibrittating electrode with one discharge push button, usually placed to left of sternum (patient's right). Also serves as negative ECG electrode during QUIK-LOOK paddle monitoring. ® APEX Paddle Defibrillating electrode with QUIK-CHARSE control (CHARGE) and second discharge push button, suslly placed oar cords apes Nsw shrves ts ott tive £€e elacivode uring UiT=LGOE pad’ mont Corng. ® | aanse Honentary pushbutton to charge DefibriTar (QUIK-CHARGE tor from APEX paddle. control) ® Charge Indicator Iluminated indicator flashes during charge cycle and glows steadily when energy has reached preselected level. Discharge Push buttons Push buttons to discharge Defibrillator. Both buttons must be depressed simultaneous Ty to deliver energy to the paddles. ILL NOT BE DELIVERED UNLESS THE DEFIBRILLA- TOR IS FULLY CHARGED TO PRESELECTED LEVEL. (Numbers in “Eneray Display window on steadily, AVAILABLE ENERGY illuminated, ang Charge” ‘Indicator iTluminated steadily.) © Test Load (Under Paddtes) 50 ohm Defibrillator test load. Metal Contacts for receiving defibrillation pulse from paddles. ® Cassette Receptacle Receptacle for cassette which allow use of auxiliary paddles or pacing. 2.10 ©ppR. 1985 PHYSIO-CONTROLSection 2 Operat on LEFT BLANK INTENTIONALLY an ©npr. 1985 PHYSTO-CONTROL,Section 2 Operation FIGURE 2-4. DEFIBRILLATOR REAR PANEL CONTROLS eae npr. 1985 PHYSTO-cONTROLSection 2 that label on bottom of instrument matches available voltage/frequency. Operation TABLE 4 OEFTRRILLATOR REAR PANEL CONTROLS Freure | conTROL oR FUNCTION wer no. | MorcaTor @ | xan vo Totary control to increase or decrease volune of DeFibritator tones. Cannot be adjusted for no tone. @ MAINS POWER Rocker switch to select ac line power (ON) or battery power (OFF). @ | sme tur TuxtTfary connection for cable to Honitor for SYNC capacity. (Necessary only” when LIFEPAK “8 Wonitor. is not Joined. through latching fin” assembly ‘to_deftbritlator.) @ | saw ruse AG voltage/current overload protectors. SPARE Domestic only. @® | sreuna Equipotentia! ground tie point. © Power Cord Connect. to grounded ac receptacle. Check VOLTAGE Selector Slide switch to select 110Vac or 220vac Vine power. (Under label.) 213 ©npr. 1985 PHYSTO-CONTROL