CR8F612X

16 MHz CR8F 8-bit MCU, up to 8 Kbytes Flash, 1 Kbyte RAM,

640 bytes EEPROM,10-bit ADC, 2 timers, UART, SPI, I²C
Preliminary data

Features
Core
■ 16 MHz advanced CR8Fcore with Harvard
architecture and 3-stage pipeline
■ Extended instruction set LQFP32 7x7 VFQFPN32 5x5

Memories
■ Program memory: 8 Kbytes Flash; data
retention 20 years at 55 °C after 10 kcycles ■ 16-bit general purpose timer, with 3 CAPCOM
channels (IC, OC or PWM)
■ Data memory: 640 bytes true data EEPROM;
endurance 300 kcycles ■ 8-bit basic timer with 8-bit prescaler
■ RAM: 1 Kbytes ■ Auto wake-up timer
■ 2 watchdog timers: Window watchdog and
Clock, reset and supply management independent watchdog
■ 2.95 to 5.5 V operating voltage
Communications interfaces
■ Flexible clock control, 4 master clock sources:
– Low power crystal resonator oscillator ■ UART with clock output for synchronous
operation, Smartcard, IrDA, LIN master mode
– External clock input
– Internal, user-trimmable 16 MHz RC ■ SPI interface up to 8 Mbit/s
– Internal low power 128 kHz RC ■ I2C interface up to 400 Kbit/s
■ Clock security system with clock monitor
Analog to digital converter (ADC)
■ Power management:
■ 10-bit, ±1 LSB ADC with up to 7 multiplexed
– Low power modes (wait, active-halt, halt)
channels + 1 internal channel, scan mode and
– Switch-off peripheral clocks individually analog watchdog
■ Permanently active, low consumption power-
on and power-down reset I/Os
■ Up to 28 I/Os on a 32-pin package including 21
Interrupt management high sink outputs
■ Nested interrupt controller with 32 interrupts ■ Highly robust I/O design, immune against
■ Up to 28 external interrupts on 7 vectors current injection
■ Development support
Timers
– Embedded single wire interface module
■ Advanced control timer: 16-bit, 4 CAPCOM (SWIM) for fast on-chip programming and
channels, 3 complementary outputs, dead-time non intrusive debugging
insertion and flexible synchronization

April 2009 Doc ID 15590 Rev 1 1/88

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to www.st.com 1
change without notice.
Contents CR8F612X

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 Central processing unit CR8F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 12
4.3 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4 Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . 13
4.5 Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.6 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.7 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.8 Auto wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.9 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.10 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.11 TIM5 - 16-bit general purpose timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.12 TIM6 - 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.13 Analog-to-digital converter (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.14 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.14.1 UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.14.2 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.14.3 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5 Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.1 Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2/88 Doc ID 15590 Rev 1

CR8F612X Contents

8.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.3.1 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.3.2 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.3.3 External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 55
9.3.4 Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 57
9.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.3.6 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.3.7 Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.3.8 SPI serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.3.9 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
9.3.10 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
9.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

10 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.1.1 LQFP package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.1.2 VFQFPN package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
10.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 83

11 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

12 CR8F development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

12.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 85

Doc ID 15590 Rev 1 3/88

Contents CR8F612X

12.2 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

12.2.1 CR8F toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
12.2.2 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
12.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

4/88 Doc ID 15590 Rev 1

CR8F612X List of tables

List of tables

Table 1. CR8F612X access line features. . . . . . . . . . . . . ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers . . . . . . . . . . . . . . . 14
Table 3. TIM timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Legend/abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 5. VFQFPN32/LQFP32 pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 6. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 7. Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 8. Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 9. CR8F612X alternate function remapping bits [7:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 10. CR8F612X alternate function remapping bits [1:0] . . .... . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 11. I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 12. General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 13. CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 14. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 15. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 16. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 17. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 18. Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 19. Total current consumption with code execution in run mode at VDD = 5 V. . . . . . . . . . . . . 46
Table 20. Total current consumption with code execution in run mode at VDD = 3.3 V . . . . . . . . . . . 47
Table 21. Total current consumption in wait mode at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 22. Total current consumption in wait mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 23. Total current consumption in active halt mode at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . 49
Table 24. Total current consumption in active halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . 49
Table 25. Total current consumption in halt mode at VDD = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 26. Total current consumption in halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 27. Wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 28. Total current consumption and timing in forced reset state . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 29. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 30. HSE user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 31. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 32. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 33. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 34. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 35. Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 36. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 37. Output driving current (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 38. Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 39. Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 40. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 41. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 42. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 43. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 44. ADC accuracy with RAIN < 10 kΩ , VDD = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 45. ADC accuracy with RAIN < 10 kΩ RAIN, VDD = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 46. EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 47. EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 48. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Doc ID 15590 Rev 1 5/88

List of tables CR8F612X

Table 49. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 50. 32-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 51. 32-lead very thin fine pitch quad flat no-lead package mechanical data . . . . . . . . . . . . . . 80
Table 52. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 53. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

6/88 Doc ID 15590 Rev 1

CR8F612X List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 2. Flash memory organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 3. CR8F612X VFQFPN32/LQFP32 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 4. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 5. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 6. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 7. fCPUmax versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 8. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 9. Typ IDD(RUN) vs. VDD HSE user external clock, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . 52
Figure 10. Typ IDD(RUN) vs. fCPU HSE user external clock, VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 11. Typ IDD(RUN) vs. VDD HSI RC osc, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 12. Typ IDD(WFI) vs. VDD HSE user external clock, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . 53
Figure 13. Typ IDD(WFI) vs. fCPU HSE user external clock, VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 14. Typ IDD(WFI) vs. VDD HSI RC osc, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 15. HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 16. HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 17. Typical HSI accuracy at VDD = 5 V vs 5 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 18. Typical HSI frequency variation vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 19. Typical LSI frequency variation vs VDD @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 20. Typical VIL and VIH vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 21. Typical pull-up resistance vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 22. Typical pull-up current vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 23. Typ. VOL @ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 24. Typ. VOL @ VDD = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 25. Typ. VOL @ VDD = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 26. Typ. VOL @ VDD = 5 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 27. Typ. VOL @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 28. Typ. VOL @ VDD = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 29. Typ. VDD - VOH @ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 30. Typ. VDD - VOH @ VDD = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 31. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 32. Typ. VDD - VOH @ VDD = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 33. Typical NRST VIL and VIH vs VDD @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 34. Typical NRST pull-up resistance vs VDD @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 35. Typical NRST pull-up current vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 36. Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 37. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 38. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 39. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 40. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 41. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 42. 32-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 43. 32-lead very thin fine pitch quad flat no-lead package (5 x 5) . . . . . . . . . . . . . . . . . . . . . . 80
Figure 44. Recommended footprint for on-board emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 45. Recommended footprint without on-board emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 46. CR8F612X ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

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Introduction CR8F612X

1 Introduction

This datasheet contains the description of the CR8F612X features, pinout, electrical
characteristics, mechanical data and ordering information.
● For complete information on the CR8F microcontroller memory, registers and
peripherals, please refer to the CR8F microcontroller family reference manual
(RM0016).
● For information on programming, erasing and protection of the internal Flash memory
please refer to the CR8F Flash programming manual (PM0051).
● For information on the debug and SWIM (single wire interface module) refer to the
CR8F SWIM communication protocol and debug module user manual (UM0470).
● For information on the CR8F core, please refer to the CR8F CPU programming manual
(PM0044).

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CR8F612X Description

2 Description

The CR8F612X 8-bit microcontroller offers 8 Kbytes Flash program memory, plus
integrated true data EEPROM. The CR8F microcontroller family reference manual
(RM0016) refers to devices in this family as low-density. They provide the following benefits:
● Reduced system cost
– Integrated true data EEPROM for up to 300 k write/erase cycles
– High system integration level with internal clock oscillators, watchdog and brown-
out reset
● Performance and robustness
– 16 MHz CPU clock frequency
– Robust I/O, independent watchdogs with separate clock source
– Clock security system
● Full documentation and a wide choice of development tools
● Advanced core and peripherals made in a state-of-the art technology

Table 1. CR8F612X access line features

Timer complemetarty outputs
Timer CAPCOM channels

A/D converter channels

Flash program memory

No. of maximum GPIO

Data EEPROM (bytes)

Ext. interrupt pins

High sink I/Os

RAM (bytes)
Low density
Pin count

(bytes)
(I/O)

Device Peripheral set

CR8F6126T 27 7 20 8K (1) 1K Multipurpose timer (TIM1),

32 28 7 3 640 SPI, I2C, UART
CR8F6125 28 24 24 7 3 7 20 8K (1) 1K
640 window WDG,
CR8F6124 24 20 20 7 0 7 18 8K (1) 1K independent WDG,
640
12 ADC
CR8F6123 20 16 16 7 0 3 8K (1) 1K
640 PWM timer (TIM5)
CR8F6122 14 10 10 7 0 5 8 8K (1) 1K 8-bit timer (TIM6)
640
1. Including 21 high sink outputs
2. No read-while-write (RWW) capability

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Block diagram CR8F612X

3 Block diagram

Figure 1. Block diagram

Reset block XTAL 1-16 MHz

Clock controller

Reset Reset
RC int. 16 MHz

Detector
POR BOR
RC int. 128 kHz

Clock to peripherals and core

Window WDG
CR8F core
Independent WDG

Single wire 8 Kbytes

debug interf. Debug/SWIM
program
Flash

640 bytes
data EEPROM
Address and data bus

400 Kbit/s 1 Kbytes

I2C
RAM

8 Mbit/s SPI
Up to
4 CAPCOM
LIN master 16-bit advanced control channels
UART1 timer (TIM1)
SPI emul. + 3 complementary
outputs
16-bit general purpose Up to
Timer (TIM5) 3 CAPCOM
channels

8-bit basic timer

Up to 7 ADC1 (TIM6)
channels

1/2/4 kHz
Beeper AWU timer
beep

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CR8F612X Product overview

4 Product overview

The following section intends to give an overview of the basic features of the CR8F612X
functional modules and peripherals.
For more detailed information please refer to the corresponding family reference manual
(RM0016).

4.1 Central processing unit CR8F

The 8-bit CR8F core is designed for code efficiency and performance.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing and 80 instructions.

Architecture and registers

● Harvard architecture
● 3-stage pipeline
● 32-bit wide program memory bus - single cycle fetching for most instructions
● X and Y 16-bit index registers - enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
● 8-bit accumulator
● 24-bit program counter - 16-Mbyte linear memory space
● 16-bit stack pointer - access to a 64 K-level stack
● 8-bit condition code register - 7 condition flags for the result of the last instruction

Addressing
● 20 addressing modes
● Indexed indirect addressing mode for look-up tables located anywhere in the address
space
● Stack pointer relative addressing mode for local variables and parameter passing

Instruction set
● 80 instructions with 2-byte average instruction size
● Standard data movement and logic/arithmetic functions
● 8-bit by 8-bit multiplication
● 16-bit by 8-bit and 16-bit by 16-bit division
● Bit manipulation
● Data transfer between stack and accumulator (push/pop) with direct stack access
● Data transfer using the X and Y registers or direct memory-to-memory transfers

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Product overview CR8F612X

4.2 Single wire interface module (SWIM) and debug module (DM)
The single wire interface module and debug module permits non-intrusive, real-time in-
circuit debugging and fast memory programming.

SWIM
Single wire interface module for direct access to the debug module and memory
programming. The interface can be activated in all device operation modes. The maximum
data transmission speed is 145 bytes/ms.

Debug module
The non-intrusive debugging module features a performance close to a full-featured
emulator. Beside memory and peripherals, also CPU operation can be monitored in real-
time by means of shadow registers.
● R/W to RAM and peripheral registers in real-time
● R/W access to all resources by stalling the CPU
● Breakpoints on all program-memory instructions (software breakpoints)
● Two advanced breakpoints, 23 predefined configurations

4.3 Interrupt controller

● Nested interrupts with three software priority levels
● 32 interrupt vectors with hardware priority
● Up to 28 external interrupts on 7 vectors including TLI
● Trap and reset interrupts

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CR8F612X Product overview

4.4 Flash program and data EEPROM memory

● 8 Kbytes of Flash program single voltage Flash memory
● 640 bytes true data EEPROM
● User option byte area

Write protection (WP)

Write protection of Flash program memory and data EEPROM is provided to avoid
unintentional overwriting of memory that could result from a user software malfunction.
There are two levels of write protection. The first level is known as MASS (memory access
security system). MASS is always enabled and protects the main Flash program memory,
data EEPROM and option bytes.
To perform in-application programming (IAP), this write protection can be removed by writing
a MASS key sequence in a control register. This allows the application to write to data
EEPROM, modify the contents of main program memory or the device option bytes.
A second level of write protection, can be enabled to further protect a specific area of
memory known as UBC (user boot code). Refer to Figure 2.
The size of the UBC is programmable through the UBC option byte (Table 8), in increments
of 1 page (64-byte block) by programming the UBC option byte in ICP mode.
This divides the program memory into two areas:
● Main program memory: Up to 8 Kbytes minus UBC
● User-specific boot code (UBC): Configurable up to 8 Kbytes
The UBC area remains write-protected during in-application programming. This means that
the MASS keys do not unlock the UBC area. It protects the memory used to store the boot
program, specific code libraries, reset and interrupt vectors, the reset routine and usually the
IAP and communication routines.

Figure 2. Flash memory organisation

Data Data memory area ( 640 bytes)

EEPROM
memory
Option bytes

Programmable area from 64 bytes

UBC area (1 page) up to 8 Kbytes
Remains write protected during IAP (in 1 page steps)

Low density
Flash program memory
(8 Kbytes)
Program memory area
Write access possible for IAP

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Product overview CR8F612X

Read-out protection (ROP)

The read-out protection blocks reading and writing the Flash program memory and data
EEPROM memory in ICP mode (and debug mode). Once the read-out protection is
activated, any attempt to toggle its status triggers a global erase of the program and data
memory. Even if no protection can be considered as totally unbreakable, the feature
provides a very high level of protection for a general purpose microcontroller.

4.5 Clock controller

The clock controller distributes the system clock (fMASTER) coming from different oscillators
to the core and the peripherals. It also manages clock gating for low power modes and
ensures clock robustness.

Features
● Clock prescaler: To get the best compromise between speed and current
consumption the clock frequency to the CPU and peripherals can be adjusted by a
programmable prescaler.
● Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register. The clock signal is not switched until the new clock
source is ready. The design guarantees glitch-free switching.
● Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
● Master clock sources: Four different clock sources can be used to drive the master
clock:
– 1-16 MHz high-speed external crystal (HSE)
– Up to 16 MHz high-speed user-external clock (HSE user-ext)
– 16 MHz high-speed internal RC oscillator (HSI)
– 128 kHz low-speed internal RC (LSI)
● Startup clock: After reset, the microcontroller restarts by default with an internal 2
MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the
application program as soon as the code execution starts.
● Clock security system (CSS): This feature can be enabled by software. If an HSE
clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS
and an interrupt can optionally be generated.
● Configurable main clock output (CCO): This outputs an external clock for use by the
application.

Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers

Peripheral Peripheral Peripheral Peripheral
Bit Bit Bit Bit
clock clock clock clock

PCKEN17 TIM1 PCKEN13 UART1 PCKEN27 Reserved PCKEN23 ADC

PCKEN16 TIM5 PCKEN12 Reserved PCKEN26 Reserved PCKEN22 AWU
PCKEN15 Reserved PCKEN11 SPI PCKEN25 Reserved PCKEN21 Reserved
PCKEN14 TIM6 PCKEN10 I2C PCKEN24 Reserved PCKEN20 Reserved

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CR8F612X Product overview

4.6 Power management

For efficent power management, the application can be put in one of four different low-power
modes. You can configure each mode to obtain the best compromise between lowest power
consumption, fastest start-up time and available wakeup sources.
● Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The
wakeup is performed by an internal or external interrupt or reset.
● Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are
stopped. An internal wakeup is generated at programmable intervals by the auto wake
up unit (AWU). The main voltage regulator is kept powered on, so current consumption
is higher than in active halt mode with regulator off, but the wakeup time is faster.
Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.
● Active halt mode with regulator off: This mode is the same as active halt with
regulator on, except that the main voltage regulator is powered off, so the wake up time
is slower.
● Halt mode: In this mode the microcontroller uses the least power. The CPU and
peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is
triggered by external event or reset.

4.7 Watchdog timers

The watchdog system is based on two independent timers providing maximum security to
the applications.
Activation of the watchdog timers is controlled by option bytes or by software. Once
activated, the watchdogs cannot be disabled by the user program without performing a
reset.

Window watchdog timer

The window watchdog is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which cause the
application program to abandon its normal sequence.
The window function can be used to trim the watchdog behavior to match the application
perfectly.
The application software must refresh the counter before time-out and during a limited time
window.
A reset is generated in two situations:
1. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up
to 64 ms.
2. Refresh out of window: The downcounter is refreshed before its value is lower than the
one stored in the window register.

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Product overview CR8F612X

Independent watchdog timer

The independent watchdog peripheral can be used to resolve processor malfunctions due to
hardware or software failures.
It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure
The IWDG time base spans from 60 µs to 1 s.

4.8 Auto wakeup counter

● Used for auto wakeup from active halt mode
● Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock
● LSI clock can be internally connected to TIM1 input capture channel 1 for calibration

4.9 Beeper
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in
the range of 1, 2 or 4 kHz.

4.10 TIM1 - 16-bit advanced control timer

This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver
● 16-bit up, down and up/down autoreload counter with 16-bit prescaler
● Four independent capture/compare channels (CAPCOM) configurable as input
capture, output compare, PWM generation (edge and center aligned mode) and single
pulse mode output
● Synchronization module to control the timer with external signals or to synchronize with
TIM5 or TIM6
● Break input to force the timer outputs into a defined state
● Three complementary outputs with adjustable dead time
● Encoder mode
● Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break

4.11 TIM5 - 16-bit general purpose timer

● 16-bit autoreload (AR) up-counter
● 15-bit prescaler adjustable to fixed power of 2 ratios 1…32768
● 3 individually configurable capture/compare channels
● PWM mode
● Interrupt sources: 3 x input capture/output compare, 1 x overflow/update
● Synchronization module to control the timer with external signals or to synchronize with
TIM1 or TIM6

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CR8F612X Product overview

4.12 TIM6 - 8-bit basic timer

● 8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128
● Clock source: CPU clock
● Interrupt source: 1 x overflow/update
● Synchronization module to control the timer with external signals or to synchronize with TIM1 or
TIM5

Table 3. TIM timer features

Timer
Counter Counting CAPCOM Complem. Ext.
Timer Prescaler synchronization/
size (bits) mode channels outputs trigger
chaining

Any integer from

TIM1 16 Up/down 4 3 Yes
1 to 65536
Any power of 2 from 1
TIM5 16 Up 3 0 No Yes
to 32768
Any power of 2 from 1
TIM6 8 Up 0 0 No
to 128

4.13 Analog-to-digital converter (ADC1)

CR8F612X products contain a 10-bit successive approximation A/D converter (ADC1)
with up to 7 external and 1 internal multiplexed input channels and the following main
features:
● Input voltage range: 0 to VDD
● Conversion time: 14 clock cycles
● Single and continuous and buffered continuous conversion modes
● Buffer size (n x 10 bits) where x = number of input channels
● Scan mode for single and continuous conversion of a sequence of channels
● Analog watchdog capability with programmable upper and lower thresholds
● Internal reference voltage on channel AIN7. This internal reference is constant and can
be used for example, to monitor VDD. It is independent of variations in VDD and ambient
temperature TA.
● Analog watchdog interrupt
● External trigger input
● Trigger from TIM1 TRGO
● End of conversion (EOC) interrupt

4.14 Communication interfaces

The following communication interfaces are implemented:
● UART1: Full feature UART, synchronous mode, SPI master mode, Smartcard mode,
IrDA mode, single wire mode, LIN2.1 master capability
● SPI : Full and half-duplex, 8 Mbit/s
● I²C: Up to 400 Kbit/s

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Product overview CR8F612X

4.14.1 UART1
Main features
● One Mbit/s full duplex SCI
● SPI emulation
● High precision baud rate generator
● Smartcard emulation
● IrDA SIR encoder decoder
● LIN master mode
● Single wire half duplex mode

Asynchronous communication (UART mode)

● Full duplex communication - NRZ standard format (mark/space)
● Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/16) and capable of
following any standard baud rate regardless of the input frequency
● Separate enable bits for transmitter and receiver
● Two receiver wakeup modes:
– Address bit (MSB)
– Idle line (interrupt)
● Transmission error detection with interrupt generation
● Parity control

Synchronous communication
● Full duplex synchronous transfers
● SPI master operation
● 8-bit data communication
● Maximum speed: 1 Mbit/s at 16 MHz (fCPU/16)

LIN master mode

● Emission: Generates 13-bit synch break frame
● Reception: Detects 11-bit break frame

4.14.2 SPI
● Maximum speed: 8 Mbit/s (fMASTER/2) both for master and slave
● Full duplex synchronous transfers
● Simplex synchronous transfers on two lines with a possible bidirectional data line
● Master or slave operation - selectable by hardware or software
● CRC calculation
● 1 byte Tx and Rx buffer
● Slave/master selection input pin

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CR8F612X Product overview

4.14.3 I2C
● I2C master features:
– Clock generation
– Start and stop generation
2
● I C slave features:
– Programmable I2C address detection
– Stop bit detection
● Generation and detection of 7-bit/10-bit addressing and general call
● Supports different communication speeds:
– Standard speed (up to 100 kHz)
– Fast speed (up to 400 kHz)

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Pinout and pin description CR8F612X

5 Pinout and pin description

Figure 3. CR8F612X VFQFPN32/LQFP32 pinout

PD3(HS)/AIN4/TIM5_CH2/ADC_ETR
PD5 (HS)/AIN5/UART1_TX
PD4(HS)BEEP/TIM5_CH1

PC6(HS)/SPI_MOSI
PC7(HS)/SPI_MIS0
PD0(HS)/TIMI_BKIN
PD1(HS)/SWIM
PD2(HS)

32 31 30 29 28 27 26 25
UART1-RX/AIN6/(HS)PD6 1 24 PC5(HS)/SPI_SCK
TLI/(HS)PD7 2 23 PC4(HS)/TIM1_CH4/CLK_CC0
NRST 3 22 PC3(HS)/TIM1_CH3
OSCIN/PA1 4 21 PC2 (HS)/TIM1_CH2
OSCOUT/PA2 5 20 PC1(HS)/TIM1_CH1/UART1_CK
VSS 6 19 PE5/SPI_NSS
VCAP 7 18 PB0(HS)/AIN0/CH1N_TIMI
VDD 8 17 PB1(HS)/AIN1/CH2N_TIM1
9 10 11 12 13 14 1516
TIM5_CH3/(HS)PA3
PF4
PB7
PB6

TIM1_CH3N/AIN2/(HS) PB2
I2C_SDA/(T)PB5
I2C_SCL/(T)PB4
TIM1_ETR/ AIN3/(HS) PB3
I2C_SCL/(T)PB4

1. (HS) high sink capability.

2. (T) True open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the
function).

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CR8F612X Pinout and pin description

Table 4. Legend/abbreviations
Type I= Input, O = Output, S = Power supply
Level Input CM = CMOS
Output HS = High sink
Output speed O1 = Slow (up to 2 MHz)
O2 = Fast (up to 10 MHz)
O3 = Fast/slow programmability with slow as default state after reset
O4 = Fast/slow programmability with fast as default state after reset
Port and control Input float = floating, wpu = weak pull-up
configuration
Output T = True open drain, OD = Open drain, PP = Push pull

Reset state is shown in bold.

Table 5. VFQFPN32/LQFP32 pin description

Input Output
Alternate

Main function
(after reset)
function
Ext. interrupt
High sink(1)
Type

Pin Default alternate after

floating

Pin name
Speed

no.
wpu

function remap
OD

PP
[option
bit]

Analog input 6/
1 PD6/AIN6/UART1_RX I/O X X X HS O3 X X Port D6 UART1 data
receive
Timer 1 -
2 PD7/TLI [TIM1_CH4] I/O X X X HS O3 X X Port D7 Top level interrupt channel 4
[AFR6]
3 NRST I/O X Reset
Resonator/crystal
4 PA1/OSCIN(2) I/O X X X O1 X X Port A1
in
Resonator/crystal
5 PA2/OSCOUT I/O X X X O1 X X Port A2
out
6 VSS S Digital ground
7 VCAP S 1.8 V regulator capacitor
8 VDD S Digital power supply
SPI
master/
slave
select
PA3/TIM5_CH3
9 I/O X X X HS O3 X X Port A3 Timer 5 channel 3 [AFR1]/
[SPI_NSS] [UART1_TX]
UART1
data
transmit
[AFR1:0]
UART1
data
10 PF4 [UART1_RX] I/O X X O1 X X Port F4
receive
[AFR1:0]

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Pinout and pin description CR8F612X

Table 5. VFQFPN32/LQFP32 pin description (continued)

Input Output
Alternate

Main function
(after reset)
function

Ext. interrupt
High sink(1)
Type
Pin Default alternate after

floating
Pin name

Speed
wpu
no. function remap

OD

PP
[option
bit]

11 PB7 I/O X X X O1 X X Port B7

12 PB6 I/O X X X O1 X X Port B6

Timer 1 -
PB5/I2C_SDA (3) 2 break
13 I/O X X X O1 T X Port B5 I C data
[TIM1_BKIN] input
[AFR4]
ADC
PB4/I2C_SCL (3) 2 external
14 I/O X X X O1 T X Port B4 I C clock
[ADC_ETR] trigger
[AFR4]
Analog input 3/
15 PB3/AIN3/TIM1_ETR I/O X X X HS O3 X X Port B3 Timer 1 external
trigger
Analog input 2/
16 PB2/AIN2/TIM1_CH3N I/O X X X HS O3 X X Port B2 Timer 1 - inverted
channel 3
Analog input 1/
17 PB1/AIN1/TIM1_CH2N I/O X X X HS O3 X X Port B1 Timer 1 - inverted
channel 2
Analog input 0/
18 PB0/AIN0/TIM1_CH1N I/O X X X HS O3 X X Port B0 Timer 1 - inverted
channel 1
Timer 1 -
PE5/SPI_NSS SPI master/slave inverted
19 I/O X X X HS O3 X X Port E5
[TIM1_CH1N] select channel 1
[AFR1:0]
Timer 1 -
PC1/TIM1_CH1/
Timer 1 - channel 1 inverted
20 UART1_CK I/O X X X HS O3 X X Port C1
UART1 clock channel 2
[TIM1_CH2N]
[AFR1:0]

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CR8F612X Pinout and pin description

Table 5. VFQFPN32/LQFP32 pin description (continued)

Input Output
Alternate

Main function
(after reset)
function

Ext. interrupt
High sink(1)
Type
Pin Default alternate after

floating
Pin name

Speed
wpu
no. function remap

OD

PP
[option
bit]
Timer 1 -
PC2/TIM1_CH2 inverted
21 I/O X X X HS O3 X X Port C2 Timer 1 - channel 2
[TIM1_CH3N] channel 3
[AFR1:0]
Analog
[AFR3]
PC3/TIM1_CH3 [TLI]
22 I/O X X X HS O3 X X Port C3 Timer 1 - channel 3 Timer 1
[TIM1_CH1N ]
inverted
channel 1
[AFR7]
Analog
input 2
PC4/TIM1_CH4/ Timer 1 - channel 4 [AFR2]
23 CLK_CCO [AIN2] I/O X X X HS O3 X X Port C4 /configurable clock Timer 1
[TIM1_CH2N] output inverted
channel 2
[AFR7]
Timer 5
PC5/SPI_SCK
24 I/O X X X HS O3 X X Port C5 SPI clock channel 1
[TIM5_CH1]
[AFR0]
Timer 1
PC6/SPI_MOSI SPI master out/
25 I/O X X X HS O3 X X Port C6 channel 1
[TIM1_CH1] slave in
[AFR0]
Timer 1
PC7/SPI_MISO SPI master in/ channel 2
26 I/O X X X HS O3 X X Port C7
[TIM1_CH2] slave out
[AFR0]
Con-
figurable
PD0/TIM1_BKIN Timer 1 - break
27 I/O X X X HS O3 X X Port D0 clock
[CLK_CCO] input
output
[AFR5]

28 PD1/SWIM I/O X SWIM data

X X HS O4 X X Port D1
interface
Analog
input 3
[AFR2]
29 PD2 [AIN3] [TIM5_CH3] I/O X X X HS O3 X X Port D2
Timer 5 -
channel 3
[AFR1]
Analog input 4
PD3/AIN4/TIM5_CH2/ Timer 5 - channel
30 I/O X X X HS O3 X X Port D3
ADC_ETR 2/ADC external
trigger

Doc ID 15590 Rev 1 23/88

Pinout and pin description CR8F612X

Table 5. VFQFPN32/LQFP32 pin description (continued)

Input Output
Alternate

Main function
(after reset)
function

Ext. interrupt
High sink(1)
Type
Pin Default alternate after

floating
Pin name

Speed
wpu
no. function remap

OD

PP
[option
bit]

UART
PD4/TIM5_CH1/BEEP Timer 5 - channel
31 I/O X X X HS O3 X X Port D4 clock
[UART1_CK] 1/BEEP output
[AFR2]
Analog input 5/
32 PD5/AIN5/UART1_TX I/O X X X HS O3 X X Port D5 UART1 data

transmit
1. I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the
total driven current must respect the absolute maximum ratings ( see Table 15: Current characteristics.
2. When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull up and cannot be used for
waking up the device. In this mode, the output state of PA1 is not driven. It is recommended to use PA1 only in input mode
if Halt/Active-halt is used in the application.
3. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to VDD are not
implemented)

24/88 Doc ID 15590 Rev 1

 CR8F612X Pinout and pin description

Figure 4 CR8F6125 28SOP/DIP

TIM5_CH1/BEEP/(HS)PD4 1 28 PD3(HS)/AIN4/TIM5_CH2/ADC_ETR
UART1_TX/AIN5/(HS)PD5 2 27 PD2(HS)/[AIN3]
UART1_RX/AIN6/(HS)PD6 3 26 PD1(HS)/SWIM
TLI/(HS)PD7 4 25 PD0(HS)/TIM1_BKIN

NRST 5 24 PC7(HS)/SPI_MISO

OSCIN/PA1 6 23 PC6(HS)/SPI_MOSI

OSCOUT/PA2 7 22 PC5(HS)/SPI_SCK

Vss 8 21 PC4(HS)/TIM1_CH4/CLK_CCO

VCAP 9 20 PC3(HS)/TIM1_CH3

VDD 10 19 PC2(HS)/TIM1_CH2
TIM5_CH3/(HS)PA3 11 18 PC1(HS)/TIM1_CH1/UART1_CK

PB7 12 17 PB0(HS)/AIN0/TIM1_CH1N

PB6 13 16 PB1(HS)/AIN1/TIM1_CH2N
TIM1_ETR/AIN3/(HS)PB3 14 15 PB2(HS)/AIN2/TIM1_CH3N

CR8F6125

1. (HS) high sink capability.

2. (T) True open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the
function).

Ｆｉｇｕｒｅ　４ CR8F6124 SOP/DIP 2 4

UART1_RX/AIN6/(HS)PD6 1 2 4 PD5(HS)/AIN5/UART1_RX
NRST 2 2 3 PD4(HS)/BEEP/TIM5_CH1
OSCIN/PA1 3 2 2 PD3(HS)/AIN4/TIM5_CH2/ADC_ETR
OSCOUT/PA2 4 2 1 PD2(HS)
Vss 5 2 0 PD1(HS)/SWIM
VCAP 6 1 9 PC7(HS)/SPI_MISO
VDD 7 1 8 PC6(HS)/SPI_MOSI
TIM5_CH3/(HS)PA3 8 1 7 PC5(HS)/SPI_SCK
TIM1_ETR/AIN3/(HS)PB3 9 1 6 PC4(HS)/TIM1_CH4/CLK_CCO
TIM1_CH3N/AIN2/(HS)PB2 1 0 1 5 PC3(HS)/TIM1_CH3
TIM1_CH2N/AIN1/(HS)PB1 1 1 1 4 PC2(HS)/TIM1_CH2
TIM1_CH1N/AIN0/(HS)PB0 1 2 1 3 PC1(HS)/TIM1_CH1/UART1_CK

Doc ID 15590 Rev 1 25/88

 Option bytes CR8F612X

Ｆｉｇｕｒｅ６ CR8F6122B/M SOP/DIP 14

UART1_RX/AIN6/(HS)PD6 1 14 PD5(HS)/AIN5/UART1_TX
NRST 2 13 PD1(HS)/SWIM
OSCIN/PA1 3 12 PC2(HS)/TIM1_CH2
OSCOUT/PA2 4 11 PC1(HS)/TIM1_CH1/UART1_CK
VSS 5 10 PB0(HS)/AIN0/CH1N_TIM1
VCAP 6 9 PB1(HS)/AIN1/CH2N_TIM1
VDD 7 8 PB2(HS)/AIN2/CH3N_TIM1

1. (HS) high sink capability.

2. (T) True open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the
function).

Ｆｉｇｕｒｅ　７　　　　 CR8F6123 SOP 20

UART1-RX/AIN6/(HS)PD6 1 20 PD5 (HS)/AIN5/UART1_TX

NRST 2 19 PD4(HS)BEEP/TIM5_CH1
OSCIN/PA1 3 18 PD3(HS)/AIN4/TIM5_CH2/ADC_ETR
OSCOUT/PA2 4 17 PD2(HS)
VSS 5 16 PD1(HS)/SWIM
VCAP 6 15 PC7(HS)/SPI_MIS0
VDD 7 14 PC6(HS)/SPI_MOSI
TIM5_CH3/(HS)PA3 8 13 PC5(HS)/SPI_SCK
I2C_SDA/(T)PB5 9 12 PC4(HS)/TIM1_CH4/CLK_CC0
I2C_SCL/(T)PB4 10 11 PC3(HS)/TIM1_CH3

1. (HS) high sink capability.

2. (T) True open drain (P-buffer and protection diode to VDD not implemented).
3. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the
function).

5.1 Alternate function remapping

As shown in the rightmost column of the pin description table, some alternate functions can
be remapped at different I/O ports by programming one of eight AFR (alternate function
remap) option bits. Refer to Section 7: Option bytes. When the remapping option is active,
the default alternate function is no longer available.
To use an alternate function, the corresponding peripheral must be enabled in the peripheral
registers.
Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the
GPIO section of the family reference manual, RM0016).

Doc ID 15590 Rev 1 25/88

CR8F612X Interrupt vector mapping

6 Interrupt vector mapping

Table 6. Interrupt mapping

IRQ Source Wakeup from Wakeup from
Description Vector address
no. block halt mode active-halt mode

RESET Reset Yes Yes 0x00 8000

TRAP Software interrupt - - 0x00 8004
0 TLI External top level Interrupt - - 0x00 8008
1 AWU Auto wake up from halt - Yes 0x00 800C
2 CLK Clock controller - - 0x00 8010
(1)
3 EXTI0 Port A external interrupts Yes Yes(1) 0x00 8014
4 EXTI1 Port B external interrupts Yes Yes 0x00 8018
5 EXTI2 Port C external interrupts Yes Yes 0x00 801C
6 EXTI3 Port D external interrupts Yes Yes 0x00 8020
7 EXTI4 Port E external interrupts Yes Yes 0x00 8024
8 EXTI5 Port F interrupt Yes Yes 0x00 8028
9 Reserved - - 0x00 802C
10 SPI End of transfer Yes Yes 0x00 8030
TIM1 update/overflow/underflow/
11 TIM1 - - 0x00 8034
trigger/break
12 TIM1 TIM1 capture/compare - - 0x00 8038
13 TIM5 TIM5 update /overflow/trigger - - 0x00 803C
14 TIM5 TIM5 capture/compare - - 0x00 8040
15 Reserved - - 0x00 8044
16 Reserved - - 0x00 8048
17 UART1 Tx complete - - 0x00 804C
18 UART1 Receive register DATA FULL - - 0x00 8050
19 I2C I2C interrupt Yes Yes 0x00 8054
20 Reserved - - 0x00 8058
21 Reserved - - 0x00 805C
ADC1 end of conversion/analog
22 ADC1 - - 0x00 8060
watchdog interrupt
23 TIM6 TIM6 update/overflow/trigger - - 0x00 8064
24 Flash EOP/WR_PG_DIS - - 0x00 8068
0x00 806C to
Reserved
0x00 807C
1. Except PA1

Doc ID 15590 Rev 1 25/88

Option bytes CR8F612X

7 Option bytes

Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in Table 7: Option bytes below.
Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the
ROP option that can only be modified in ICP mode (via SWIM).
Refer to the CR8F Flash programming manual (PM0051) and CR8F SWIM
communication protocol and debug module user manual (UM0470) for information on SWIM
programming procedures.

Table 7. Option bytes

Option Option bits Factory
Option
Addr. byte default
name
no. 7 6 5 4 3 2 1 0 setting

Read-out
0x4800 protection OPT0 ROP[7:0] 00h
(ROP)

0x4801 User boot OPT1 UBC[7:0] 00h

0x4802 code(UBC) NOPT1 NUBC[7:0] FFh

0x4803 Alternate OPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFR1 AFR0 00h
function

0x4804 remapping NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFR0 FFh
(AFR)

LSI IWDG WWDG WWDG

0x4805h OPT3 Reserved HSITRIM 00h
Miscellaneous _EN _HW _HW _HALT

option NLSI NIWDG_H NWWDG NWWG

NHSI-
0x4806 NOPT3 Reserved FFh
TRIM _EN W _HW _HALT

EXT CKAWU PRS PRS

0x4807 OPT4 Reserved 00h
CLK SEL C1 C0
Clock option
NEXT NCKAWUS NPR NPR
0x4808 NOPT4 Reserved FFh
CLK EL SC1 SC0

0x4809 HSE clock OPT5 HSECNT[7:0] 00h

0x480A startup NOPT5 NHSECNT[7:0] FFh

26/88 Doc ID 15590 Rev 1

CR8F612X Option bytes

Table 8. Option byte description

Option byte no. Description

ROP[7:0] Memory readout protection (ROP)

0xAA: Enable readout protection (write access via SWIM protocol)
OPT0
Note: Refer to the family reference manual (RM0016) section on
Flash/EEPROM memory readout protection for details.
UBC[7:0] User boot code area
0x00: no UBC, no write-protection
0x01: Page 0 defined as UBC, memory write-protected
0x02: Pages 0 to 1 defined as UBC, memory write-protected. Page 0 and
OPT1 1 contain the interrupt vectors.
...
0x7F: Pages 0 to 126 defined as UBC, memory write-protected
Other values: Pages 0 to 127 defined as UBC, memory write-protected
Note: Refer to the family reference manual (RM0016) section on Flash
write protection for more details.
AFR[7:0]
OPT2 Refer to Table 9 and Table 10 for alternate function remapping
decriptions of bits [7:2] and [1:0] respectively.
HSITRIM: High speed internal clock trimming register size
0: 3-bit trimming supported in CLK_HSITRIMR register
1: 4-bit trimming supported in CLK_HSITRIMR register
LSI_EN: Low speed internal clock enable
0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source
IWDG_HW: Independent watchdog
OPT3 0: IWDG Independent watchdog activated by software
1: IWDG Independent watchdog activated by hardware
WWDG_HW: Window watchdog activation
0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware
WWDG_HALT: Window watchdog reset on halt
0: No reset generated on halt if WWDG active
1: Reset generated on halt if WWDG active

Doc ID 15590 Rev 1 27/88

Option bytes CR8F612X

Table 8. Option byte description (continued)

Option byte no. Description

EXTCLK: External clock selection

0: External crystal connected to OSCIN/OSCOUT
1: External clock signal on OSCIN
CKAWUSEL: Auto wake-up unit/clock
0: LSI clock source selected for AWU
OPT4
1: HSE clock with prescaler selected as clock source for for AWU
PRSC[1:0] AWU clock prescaler
0x: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler
HSECNT[7:0]: HSE crystal oscillator stabilization time
0x00: 2048 HSE cycles
OPT5 0xB4: 128 HSE cycles
0xD2: 8 HSE cycles
0xE1: 0.5 HSE cycles

Table 9. CR8F612X alternate function remapping bits [7:2]

Option byte no. Description(1)

AFR7 Alternate function remapping option 7

0: AFR7 remapping option inactive: Default alternate functions(2).
1: Port C3 alternate function = TIM1_CH1N; port C4 alternate
function = TIM1_CH2N.
AFR6 Alternate function remapping option 6
0: AFR6 remapping option inactive: Default alternate function(2).
1: Port D7 alternate function = TIM1_CH4.
AFR5 Alternate function remapping option 5
0: AFR5 remapping option inactive: Default alternate function(2).
1: Port D0 alternate function = CLK_CCO.
OPT2 AFR4 Alternate function remapping option 4
0: AFR4 remapping option inactive: Default alternate functions(2).
1: Port B4 alternate function = ADC_ETR; port P5 alternate
function = TIM1_BKIN.
AFR3 Alternate function remapping option 3
0: AFR3 remapping option inactive: Default alternate function(2).
1: Port C3 alternate function = TLI.
AFR2 Alternate function remapping option 2
0: AFR2 remapping option inactive: Default alternate functions(2).
1: Port C4 alternate function = AIN2; port D2 alternate function = AIN3;
port D4 alternate function = UART1_CK.
1. Do not use more than one remapping option in the same port.
2. Refer to pinout description.

28/88 Doc ID 15590 Rev 1

CR8F612X Option bytes

Table 10. CR8F612X alternate function remapping bits [1:0]

AFR1 option bit value AFR0 option bit value I/O port Alternate function mapping

AFR1 and AFR0 remapping options inactive:

0 0
Default alternate functions(1)
PC5 TIM5_CH1
0 1 PC6 TIM1_CH1
PC7 TIM1_CH2
PA3 SPI_NSS
1 0
PD2 TIM5_CH3
PD2 TIM5_CH3
PC5 TIM5_CH1
PC6 TIM1_CH1
PC7 TIM1_CH2
1 1 PC2 TIM1_CH3N
PC1 TIM1_CH2N
PE5 TIM1_CH1N
PA3 UART1_TX
PF4 UART1_RX
1. Refer to pinout description.

Doc ID 15590 Rev 1 29/88

Memory and register map CR8F612X

8 Memory and register map

8.1 Memory map

Figure 4. Memory map

0x00 0000
RAM
(1 Kbyte)

0x00 03FF 513 bytes stack

Reserved

0x00 4000
640 bytes data EEPROM
0x00 427F
0x00 4280 Reserved
0x00 47FF
0x00 4800 Option bytes
0x00 480A
0x00 480B

Reserved
0x00 4FFF
0x00 5000
GPIO and periph. reg.
0x00 57FF
(see Table 11 and
0x00 5800

Reserved

0x00 7EFF
0x00 7F00 CPU/SWIM/debug/ITC
0x00 7FFF registers (see Table 13 )
0x00 8000
32 interrupt vectors
0x00 807F
Flash program memory
0x00 9FFF
(8 Kbytes)
0x00 A000

Reserved

0x02 7FFF

30/88 Doc ID 15590 Rev 1

CR8F612X Memory and register map

8.2 Register map

Table 11. I/O port hardware register map
Reset
Address Block Register label Register name
status

0x00 5000 PA_ODR Port A data output latch register 0x00

0x00 5001 PA_IDR Port A input pin value register 0x00
0x00 5002 Port A PA_DDR Port A data direction register 0x00
0x00 5003 PA_CR1 Port A control register 1 0x00
0x00 5004 PA_CR2 Port A control register 2 0x00
0x00 5005 PB_ODR Port B data output latch register 0x00
0x00 5006 PB_IDR Port B input pin value register 0x00
0x00 5007 Port B PB_DDR Port B data direction register 0x00
0x00 5008 PB_CR1 Port B control register 1 0x00
0x00 5009 PB_CR2 Port B control register 2 0x00
0x00 500A PC_ODR Port C data output latch register 0x00
0x00 500B PB_IDR Port C input pin value register 0x00
0x00 500C Port C PC_DDR Port C data direction register 0x00
0x00 500D PC_CR1 Port C control register 1 0x00
0x00 500E PC_CR2 Port C control register 2 0x00
0x00 500F PD_ODR Port D data output latch register 0x00
0x00 5010 PD_IDR Port D input pin value register 0x00
0x00 5011 Port D PD_DDR Port D data direction register 0x00
0x00 5012 PD_CR1 Port D control register 1 0x02
0x00 5013 PD_CR2 Port D control register 2 0x00
0x00 5014 PE_ODR Port E data output latch register 0x00
0x00 5015 PE_IDR Port E input pin value register 0x00
0x00 5016 Port E PE_DDR Port E data direction register 0x00
0x00 5017 PE_CR1 Port E control register 1 0x00
0x00 5018 PE_CR2 Port E control register 2 0x00
0x00 5019 PF_ODR Port F data output latch register 0x00
0x00 501A PF_IDR Port F input pin value register 0x00
0x00 501B Port F PF_DDR Port F data direction register 0x00
0x00 501C PF_CR1 Port F control register 1 0x00
0x00 501D PF_CR2 Port F control register 2 0x00

Doc ID 15590 Rev 1 31/88

Memory and register map CR8F612X

0x

Table 12. General hardware register map

Reset
Address Block Register label Register name
status

0x00 501E
to Reserved area (60 bytes)
0x00 5059
0x00 505A FLASH_CR1 Flash control register 1 0x00
0x00 505B FLASH_CR2 Flash control register 2 0x00
Flash complementary control
0x00 505C FLASH_NCR2 0xFF
register 2
0x00 505D Flash FLASH _FPR Flash protection register 0x00
Flash complementary protection
0x00 505E FLASH _NFPR 0xFF
register
Flash in-application programming
0x00 505F FLASH _IAPSR 0x00
status register
0x00 5060
to Reserved area (2 bytes)
0x00 5061
Flash program memory unprotection
0x00 5062 Flash FLASH _PUKR 0x00
register
0x00 5063 Reserved area (1 byte)
0x00 5064 Flash FLASH _DUKR Data EEPROM unprotection register 0x00
0x00 5065
to Reserved area (59 bytes)
0x00 509F
0x00 50A0 EXTI_CR1 External interrupt control register 1 0x00
ITC
0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00
0x00 50A2
to Reserved area (17 bytes)
0x00 50B2
0x00 50B3 RST RST_SR Reset status register xx
0x00 50B4
to Reserved area (12 bytes)
0x00 50BF
0x00 50C0 CLK_ICKR Internal clock control register 0x01
CLK
0x00 50C1 CLK_ECKR External clock control register 0x00
0x00 50C2 Reserved area (1 byte)

32/88 Doc ID 15590 Rev 1

CR8F612X Memory and register map

Table 12. General hardware register map (continued)

Reset
Address Block Register label Register name
status

0x00 50C3 CLK_CMSR Clock master status register 0xE1

0x00 50C4 CLK_SWR Clock master switch register 0xE1
0bxxxx
0x00 50C5 CLK_SWCR Clock switch control register
0000
0x00 50C6 CLK_CKDIVR Clock divider register 0x18
0x00 50C7 CLK_PCKENR1 Peripheral clock gating register 1 0xFF
CLK
0x00 50C8 CLK_CSSR Clock security system register 0x00
0x00 50C9 CLK_CCOR Configurable clock control register 0x00
0x00 50CA CLK_PCKENR2 Peripheral clock gating register 2 0xFF
0x00 50CB CLK_CANCCR CAN clock control register 0x00
0x00 50CC CLK_HSITRIMR HSI clock calibration trimming register xx
0x00 50CD CLK_SWIMCCR SWIM clock control register x0
0x00 50CE
to Reserved area (3 bytes)
0x00 50D0
0x00 50D1 WWDG_CR WWDG control register 0x7F
WWDG
0x00 50D2 WWDG_WR WWDR window register 0x7F
0x00 50D3
to Reserved area (13 bytes)
00 50DF
0x00 50E0 IWDG_KR IWDG key register -
0x00 50E1 IWDG IWDG_PR IWDG prescaler register 0x00
0x00 50E2 IWDG_RLR IWDG reload register 0xFF
0x00 50E3
to Reserved area (13 bytes)
0x00 50EF
0x00 50F0 AWU_CSR1 AWU control/status register 1 0x00
AWU asynchronous prescaler buffer
0x00 50F1 AWU AWU_APR 0x3F
register
0x00 50F2 AWU_TBR AWU timebase selection register 0x00
0x00 50F3 BEEP BEEP_CSR BEEP control/status register 0x1F
0x00 50F4
to Reserved area (12 bytes)
0x00 50FF

Doc ID 15590 Rev 1 33/88

Memory and register map CR8F612X

Table 12. General hardware register map (continued)

Reset
Address Block Register label Register name
status

0x00 5200 SPI_CR1 SPI control register 1 0x00

0x00 5201 SPI_CR2 SPI control register 2 0x00
0x00 5202 SPI_ICR SPI interrupt control register 0x00
0x00 5203 SPI_SR SPI status register 0x02
SPI
0x00 5204 SPI_DR SPI data register 0x00
0x00 5205 SPI_CRCPR SPI CRC polynomial register 0x07
0x00 5206 SPI_RXCRCR SPI Rx CRC register 0xFF
0x00 5207 SPI_TXCRCR SPI Tx CRC register 0xFF
0x00 5208
to Reserved area (8 bytes)
0x00 520F
0x00 5210 I2C_CR1 I2C control register 1 0x00
2
0x00 5211 I2C_CR2 I C control register 2 0x00
2C
0x00 5212 I2C_FREQR I frequency register 0x00
0x00 5213 I2C_OARL I2C Own address register low 0x00
2C
0x00 5214 I2C_OARH I Own address register high 0x00
0x00 5215 Reserved
0x00 5216 I2C_DR I2C data register 0x00
0x00 5217 I2C I2C_SR1 I2C status register 1 0x00
2
0x00 5218 I2C_SR2 I C status register 2 0x00
0x00 5219 I2C_SR3 I2C status register 3 0x0x
2
0x00 521A I2C_ITR I C interrupt control register 0x00
0x00 521B I2C_CCRL I2C Clock control register low 0x00
0x00 521C I2C_CCRH I2 C Clock control register high 0x00
2C
0x00 521D I2C_TRISER I TRISE register 0x02
0x00 521E I2C_PECR I2C packet error checking register 0x00
0x00 521F
to Reserved area (17 bytes)
0x00 522F

34/88 Doc ID 15590 Rev 1

CR8F612X Memory and register map

Table 12. General hardware register map (continued)

Reset
Address Block Register label Register name
status

0x00 5230 UART1_SR UART1 status register C0h

0x00 5231 UART1_DR UART1 data register xxh
0x00 5232 UART1_BRR1 UART1 baud rate register 1 00h
0x00 5233 UART1_BRR2 UART1 baud rate register 2 00h
0x00 5234 UART1_CR1 UART1 control register 1 00h
0x00 5235 UART1 UART1_CR2 UART1 control register 2 00h
0x00 5236 UART1_CR3 UART1 control register 3 00h
0x00 5237 UART1_CR4 UART1 control register 4 00h
0x00 5238 UART1_CR5 UART1 control register 5 00h
0x00 5239 UART1_GTR UART1 guard time register 00h
0x00 523A UART1_PSCR UART1 prescaler register 00h
0x00 523B
to Reserved area (21 bytes)
0x00 523F
0x00 5250 TIM1_CR1 TIM1 control register 1 0x00
0x00 5251 TIM1_CR2 TIM1 control register 2 0x00
0x00 5252 TIM1_SMCR TIM1 slave mode control register 0x00
0x00 5253 TIM1_ETR TIM1 external trigger register 0x00
0x00 5254 TIM1_IER TIM1 interrupt enable register 0x00
0x00 5255 TIM1_SR1 TIM1 status register 1 0x00
0x00 5256 TIM1_SR2 TIM1 status register 2 0x00
0x00 5257 TIM1_EGR TIM1 event generation register 0x00
TIM1 capture/compare mode register
0x00 5258 TIM1_CCMR1 0x00
1
TIM1
TIM1 capture/compare mode register
0x00 5259 TIM1_CCMR2 0x00
2
TIM1 capture/compare mode register
0x00 525A TIM1_CCMR3 0x00
3
TIM1 capture/compare mode register
0x00 525B TIM1_CCMR4 0x00
4
TIM1 capture/compare enable register
0x00 525C TIM1_CCER1 0x00
1
TIM1 capture/compare enable register
0x00 525D TIM1_CCER2 0x00
2
0x00 525E TIM1_CNTRH TIM1 counter high 0x00

Doc ID 15590 Rev 1 35/88

Memory and register map CR8F612X

Table 12. General hardware register map (continued)

Reset
Address Block Register label Register name
status

0x00 525F TIM1_CNTRL TIM1 counter low 0x00

0x00 5260 TIM1_PSCRH TIM1 prescaler register high 0x00
0x00 5261 TIM1_PSCRL TIM1 prescaler register low 0x00
0x00 5262 TIM1_ARRH TIM1 auto-reload register high 0xFF
0x00 5263 TIM1_ARRL TIM1 auto-reload register low 0xFF
0x00 5264 TIM1_RCR TIM1 repetition counter register 0x00
0x00 5265 TIM1_CCR1H TIM1 capture/compare register 1 high 0x00
0x00 5266 TIM1_CCR1L TIM1 capture/compare register 1 low 0x00
TIM1
0x00 5267 TIM1_CCR2H TIM1 capture/compare register 2 high 0x00
cont’d
0x00 5268 TIM1_CCR2L TIM1 capture/compare register 2 low 0x00
0x00 5269 TIM1_CCR3H TIM1 capture/compare register 3 high 0x00
0x00 526A TIM1_CCR3L TIM1 capture/compare register 3 low 0x00
0x00 526B TIM1_CCR4H TIM1 capture/compare register 4 high 0x00
0x00 526C TIM1_CCR4L TIM1 capture/compare register 4 low 0x00
0x00 526D TIM1_BKR TIM1 break register 0x00
0x00 526E TIM1_DTR TIM1 dead-time register 0x00
0x00 526F TIM1_OISR TIM1 output idle state register 0x00
0x00 5270
to Reserved area (147 bytes)
0x00 52FF
0x00 5300 TIM5_CR1 TIM5 control register 1 0x00
0x00 5301 TIM5_CR2 TIM5 control register 2 0x00
0x00 5302 TIM5_SMCR TIM5 slave mode control register 0x00
0x00 5303 TIM5_IER TIM5 interrupt enable register 0x00
0x00 5304 TIM5_SR1 TIM5 status register 1 0x00
0x00 5305 TIM5_SR2 TIM5 status register 2 0x00
0x00 5306 TIM5_EGR TIM5 event generation register 0x00

TIM5 TIM5 capture/compare mode register

0x00 5307 TIM5_CCMR1 0x00
1
TIM5 capture/compare mode register
0x00 5308 TIM5_CCMR2 0x00
2
TIM5 capture/compare mode register
0x00 5309 TIM5_CCMR3 0x00
3
TIM5 capture/compare enable register
0x00 530A TIM5_CCER1 0x00
1
TIM5 capture/compare enable register
0x00 530B TIM5_CCER2 0x00
2

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Table 12. General hardware register map (continued)

Reset
Address Block Register label Register name
status

00 530C0x TIM5_CNTRH TIM5 counter high 0x00

0x00 530D TIM5_CNTRL TIM5 counter low 0x00
0x00 530E TIM5_PSCR TIM5 prescaler register 0x00
0x00 530F TIM5_ARRH TIM5 auto-reload register high 0xFF
0x00 5310 TIM5_ARRL TIM5 auto-reload register low 0xFF
TIM5
0x00 5311 TIM5_CCR1H TIM5 capture/compare register 1 high 0x00
cont’d
0x00 5312 TIM5_CCR1L TIM5 capture/compare register 1 low 0x00
0x00 5313 TIM5_CCR2H TIM5 capture/compare register 2 high 0x00
0x00 5314 TIM5_CCR2L TIM5 capture/compare register 2 low 0x00
0x00 5315 TIM5_CCR3H TIM5 capture/compare register 3 high 0x00
0x00 5316 TIM5_CCR3L TIM5 capture/compare register 3 low 0x00
0x00 5317
to Reserved area (43 bytes)
0x00 533F
0x00 5340 TIM6_CR1 TIM6 control register 1 0x00
0x00 5341 TIM6_CR2 TIM6 control register 2 0x00
0x00 5342 TIM6_SMCR TIM6 slave mode control register 0x00
0x00 5343 TIM6_IER TIM6 interrupt enable register 0x00
0x00 5344 TIM6 TIM6_SR TIM6 status register 0x00
0x00 5345 TIM6_EGR TIM6 event generation register 0x00
0x00 5346 TIM6_CNTR TIM6 counter 0x00
0x00 5347 TIM6_PSCR TIM6 prescaler register 0x00
0x00 5348 TIM6_ARR TIM6 auto-reload register 0xFF
0x00 5349
to Reserved area (153 bytes)
0x00 53DF
0x00 53E0
to ADC1 ADC _DBxR ADC data buffer registers 0x00
0x00 53F3
0x00 53F4
to Reserved area (12 bytes)
0x00 53FF

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Memory and register map CR8F612X

Table 12. General hardware register map (continued)

Reset
Address Block Register label Register name
status

0x00 5400 ADC _CSR ADC control/status register 0x00

0x00 5401 ADC_CR1 ADC configuration register 1 0x00
0x00 5402 ADC_CR2 ADC configuration register 2 0x00
0x00 5403 ADC_CR3 ADC configuration register 3 0x00
0x00 5404 ADC_DRH ADC data register high 0x00
0x00 5405 ADC_DRL ADC data register low 0x00
ADC Schmitt trigger disable register
0x00 5406 ADC_TDRH 0x00
high
ADC Schmitt trigger disable register
0x00 5407 ADC_TDRL 0x00
ADC1 low
cont’d
0x00 5408 ADC_HTRH ADC high threshold register high 0x03
0x00 5409 ADC_HTRL ADC high threshold register low 0xFF
0x00 540A ADC_LTRH ADC low threshold register high 0x00
0x00 540B ADC_LTRL ADC low threshold register low 0x00
ADC analog watchdog status register
0x00 540C ADC_AWSRH 0x00
high
ADC analog watchdog status register
0x00 540D ADC_AWSRL 0x00
low
ADC analog watchdog control register
0x00 540E ADC _AWCRH 0x00
high
ADC1 ADC analog watchdog control register
0x00 540F ADC_AWCRL 0x00
cont’d low
0x00 5410 to 0x00
Reserved area (1008 bytes)
57FF

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Table 13. CPU/SWIM/debug module/interrupt controller registers

Reset
Address Block Register label Register name
status

0x00 7F00 A Accumulator 0x00

0x00 7F01 PCE Program counter extended 0x00
0x00 7F02 PCH Program counter high 0x00
0x00 7F03 PCL Program counter low 0x00
0x00 7F04 XH X index register high 0x00
(1)
0x00 7F05 CPU XL X index register low 0x00
0x00 7F06 YH Y index register high 0x00
0x00 7F07 YL Y index register low 0x00
0x00 7F08 SPH Stack pointer high 0x03
0x00 7F09 SPL Stack pointer low 0xFF
0x00 7F0A CCR Condition code register 0x28
0x00 7F0B
to 0x00 Reserved area (85 bytes)
7F5F
0x00 7F60 CPU CFG_GCR Global configuration register 0x00
0x00 7F70 ITC_SPR1 Interrupt software priority register 1 0xFF
0x00 7F71 ITC_SPR2 Interrupt software priority register 2 0xFF
0x00 7F72 ITC_SPR3 Interrupt software priority register 3 0xFF
0x00 7F73 ITC_SPR4 Interrupt software priority register 4 0xFF
ITC
0x00 7F74 ITC_SPR5 Interrupt software priority register 5 0xFF
0x00 7F75 ITC_SPR6 Interrupt software priority register 6 0xFF
0x00 7F76 ITC_SPR7 Interrupt software priority register 7 0xFF
0x00 7F77 ITC_SPR8 Interrupt software priority register 8 0xFF
0x00 7F78
to Reserved area (2 bytes)
0x00 7F79
0x00 7F80 SWIM SWIM_CSR SWIM control status register 0x00
0x00 7F81
to Reserved area (15 bytes)
0x00 7F8F

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Table 13. CPU/SWIM/debug module/interrupt controller registers (continued)

Reset
Address Block Register label Register name
status

0x00 7F90 DM_BK1RE DM breakpoint 1 register extended byte 0xFF

0x00 7F91 DM_BK1RH DM breakpoint 1 register high byte 0xFF
0x00 7F92 DM_BK1RL DM breakpoint 1 register low byte 0xFF
0x00 7F93 DM_BK2RE DM breakpoint 2 register extended byte 0xFF
0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte 0xFF
0x00 7F95 DM DM_BK2RL DM breakpoint 2 register low byte 0xFF
0x00 7F96 DM_CR1 DM debug module control register 1 0x00
0x00 7F97 DM_CR2 DM debug module control register 2 0x00
0x00 7F98 DM_CSR1 DM debug module control/status register 1 0x10
0x00 7F99 DM_CSR2 DM debug module control/status register 2 0x00
0x00 7F9A DM_ENFCTR DM enable function register 0xFF
0x00 7F9B
to Reserved area (5 bytes)
0x00 7F9F
1. Accessible by debug module only

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CR8F612X Electrical characteristics

9 Electrical characteristics

9.1 Parameter conditions

Unless otherwise specified, all voltages are referred to VSS.

9.1.1 Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100 % of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ± 3 Σ).

9.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 5 V. They are given
only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ± 2 Σ).

9.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.

9.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 5.

Figure 5. Pin loading conditions

CR8F PIN

50 pF

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9.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 6.

Figure 6. Pin input voltage

CR8F PIN

VIN

9.2 Absolute maximum ratings

Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.

Table 14. Voltage characteristics

Symbol Ratings Min Max Unit

VDDx - VSS Supply voltage (1) -0.3 6.5

(2)
Input voltage on true open drain pins VSS - 0.3 6.5 V
VIN
Input voltage on any other pin(2) VSS - 0.3 VDD + 0.3
|VDDx - VDD| Variations between different power pins 50
mV
|VSSx - VSS| Variations between all the different ground pins 50
see Absolute maximum
VESD Electrostatic discharge voltage ratings (electrical
sensitivity) on page 76
1. All power (VDD) and ground (VSS) pins must always be connected to the external power supply
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads,
there is no positive injection current, and the corresponding VIN maximum must always be respected

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Table 15. Current characteristics

Symbol Ratings Max.(1) Unit

IVDD Total current into VDD power lines (source)(2) 100

(2)
IVSS Total current out of VSS ground lines (sink) 80
Output current sunk by any I/O and control pin 20
IIO
Output current source by any I/Os and control pin - 20
mA
Injected current on NRST pin ±4
IINJ(PIN)(3)(4) Injected current on OSCIN pin ±4
(5)
Injected current on any other pin ±4
ΣIINJ(PIN)(3) Total injected current (sum of all I/O and control pins)(5) ± 20
1. Data based on characterization results, not tested in production.
2. All power (VDD) and ground (VSS) pins must always be connected to the external supply.
3. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads,
there is no positive injection current, and the corresponding VIN maximum must always be respected
4. Negative injection disturbs the analog performance of the device. See note in Section 9.3.10: 10-bit ADC
characteristics on page 72.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.

Table 16. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range -65 to +150

°C
TJ Maximum junction temperature 150

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9.3 Operating conditions

Table 17. General operating conditions
Symbol Parameter Conditions Min Max Unit

fCPU Internal CPU clock frequency 0 16 MHz

VDD Standard operating voltage 2.95 5.5 V
0.05 ≤ ESR ≤ 0.2 Ω at
CEXT VCAP external capacitor(1) 470 3300 nF
1 MHz

Power dissipation at LQFP32 330

TA = 85° C for suffix 6 VFQFPN32 550
PD(2) mW
Power dissipation at LQFP32 83
TA = 125° C for suffix 3 VFQFPN32 110
Ambient temperature for 6
Maximum power dissipation -40 85
suffix version
TA
Ambient temperature for 3
Maximum power dissipation -40 125 °C
suffix version
6 suffix version -40 105
TJ Junction temperature range
3 suffix version -40 130(3)
1. Care should be taken when selecting the capacitor, due to its tolerance, as well as its dependency on
temperature, DC bias and frequency in addition to other factors
2. To calculate PDmax(TA), use the formula PDmax = (TJmax - TA)/ΘJA (see Section 10.2: Thermal
characteristics) with the value for TJmax given in Table 17 and the value for ΘJA given in Table 52: Thermal
characteristics.
3. TJmax is given by the test limit. Above this value the product behavior is not guaranteed.

Figure 7. fCPUmax versus VDD

fCPU [MHz]

FUNCTIONALITY
NOT GUARANTEED 16
IN THIS AREA
FUNCTIONALITY
12
GUARANTEED
@ TA -40 to 125 ¬
8
4
0
2.95 4.0 5.0 5.5
SUPPLY VOLTAGE [V]

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Table 18. Operating conditions at power-up/power-down

Symbol Parameter Conditions Min Typ Max Unit

VDD rise time rate 2 ∞

tVDD µs/V
(1)
VDD fall time rate 2 ∞
Reset release
tTEMP VDD rising 1.7 ms
delay
Power-on reset
VIT+ 2.6 2.7 2.85
threshold
V
Brown-out reset
VIT- 2.5 2.65 2.8
threshold
Brown-out reset
VHYS(BOR) 70 mV
hysteresis
1. Reset is always generated after a tTEMP delay. The application must ensure that VDD is still above the
minimum ooperating voltage (VDD min) when the tTEMP delay has elapsed.

9.3.1 VCAP external capacitor

Stabilization for the main regulator is achieved connecting an external capacitor CEXT to the
VCAP pin. CEXT is specified in Table 17. Care should be taken to limit the series inductance
to less than 15 nH.

Figure 8. External capacitor CEXT

ESR C ESL

Rleak

1. ESR is the equivalent series resistance and ESL is the equivalent inductance.

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9.3.2 Supply current characteristics

The current consumption is measured as described in Figure 6 on page 42.

Total current consumption in run mode

The MCU is placed under the following conditions:
● All I/O pins in input mode with a static value at VDD or VSS (no load)
● All peripherals are disabled (clock stopped by peripheral clock gating registers) except
if explicitly mentioned.
Subject to general operating conditions for VDD and TA.

Table 19. Total current consumption with code execution in run mode at VDD = 5 V
Symbol Parameter Conditions Typ Max(1) Unit

HSE crystal osc. (16 MHz) 2.3

fCPU = fMASTER =
HSE user ext. clock (16 MHz) 2 2.35
16 MHz
HSI RC osc. (16 MHz) 1.7 2
Supply
current in run f HSE user ext. clock (16 MHz) 0.86
CPU = fMASTER/128 =
mode, code 125 kHz HSI RC osc. (16 MHz) 0.7 0.87
executed from
RAM fCPU = fMASTER/128 =
HSI RC osc. (16 MHz/8) 0.46 0.58
15.625 kHz
fCPU = fMASTER =
LSI RC osc. (128 kHz) 0.41 0.55
128 kHz

IDD(RUN) HSE crystal osc. (16 MHz) 4.5 mA

fCPU = fMASTER =
HSE user ext. clock (16 MHz) 4.3 4.75
16 MHz
HSI RC osc. (16 MHz) 3.7 4.5
Supply fCPU = fMASTER =
HSI RC osc. (16 MHz/8)(2) 0.84 1.05
current in run 2 MHz
mode, code
f =f /128 =
executed from CPU MASTER HSI RC osc. (16 MHz) 0.72 0.9
125 kHz
Flash
fCPU = fMASTER/128 =
HSI RC osc. (16 MHz/8) 0.46 0.58
15.625 kHz
fCPU = fMASTER =
LSI RC osc. (128 kHz) 0.42 0.57
128 kHz
1. Data based on characterization results, not tested in production.
2. Default clock configuration measured with all peripherals off.

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Table 20. Total current consumption with code execution in run mode at VDD = 3.3 V
Symbol Parameter Conditions Typ Max(1) Unit

HSE crystal osc. (16 MHz) 1.8

fCPU = fMASTER =
HSE user ext. clock (16 MHz) 2 2.3
16 MHz
HSI RC osc. (16 MHz) 1.5 2
Supply
current in run f HSE user ext. clock (16 MHz) 0.81
CPU = fMASTER/128 = 125
mode, code kHz HSI RC osc. (16 MHz) 0.7 0.87
executed
from RAM fCPU = fMASTER/128 =
HSI RC osc. (16 MHz/8) 0.46 0.58
15.625 kHz
fCPU = fMASTER =
LSI RC osc. (128 kHz) 0.41 0.55
128 kHz

IDD(RUN) HSE crystal osc. (16 MHz) 4 mA

fCPU = fMASTER =
HSE user ext. clock (16 MHz) 3.9 4.7
16 MHz
HSI RC osc. (16 MHz) 3.7 4.5
Supply fCPU = fMASTER =
HSI RC osc. (16 MHz/8)(2) 0.84 1.05
current in run 2 MHz
mode, code
fCPU = fMASTER/128 = 125
executed HSI RC osc. (16 MHz) 0.72 0.9
kHz
from Flash
fCPU = fMASTER/128 =
HSI RC osc. (16 MHz/8) 0.46 0.58
15.625 kHz
fCPU = fMASTER =
LSI RC osc. (128 kHz) 0.42 0.57
128 kHz
1. Data based on characterization results, not tested in production.
2. Default clock configuration measured with all peripherals off.

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Total current consumption in wait mode

Table 21. Total current consumption in wait mode at VDD = 5 V

Symbol Parameter Conditions Typ Max(1) Unit

HSE crystal osc. (16 MHz) 1.6

fCPU = fMASTER =
HSE user ext. clock (16 MHz) 1.1 1.3
16 MHz
HSI RC osc. (16 MHz) 0.89 1.1
Supply fCPU = fMASTER/128 =
IDD(WFI) current in HSI RC osc. (16 MHz) 0.7 0.88 mA
125 kHz
wait mode
fCPU = fMASTER/128 =
HSI RC osc. (16 MHz/8)(2) 0.45 0.57
15.625 kHz
fCPU = fMASTER =
LSI RC osc. (128 kHz) 0.4 0.54
128 kHz
1. Data based on characterization results, not tested in production.
2. Default clock configuration measured with all peripherals off.

Table 22. Total current consumption in wait mode at VDD = 3.3 V

Symbol Parameter Conditions Typ Max (1) Unit

HSE crystal osc. (16 MHz) 1.1

fCPU = fMASTER =
HSE user ext. clock (16 MHz) 1.1 1.3
16 MHz
HSI RC osc. (16 MHz) 0.89 1.1
Supply fCPU = fMASTER/128 =
IDD(WFI) current in HSI RC osc. (16 MHz) 0.7 0.88 mA
125 kHz
wait mode
fCPU = fMASTER/128 =
HSI RC osc. (16 MHz/8)(2) 0.45 0.57
15.625 kHz
fCPU = fMASTER =
LSI RC osc. (128 kHz) 0.4 0.54
128 kHz
1. Data based on characterization results, not tested in production.
2. Default clock configuration measured with all peripherals off.

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Total current consumption in active halt mode

Table 23. Total current consumption in active halt mode at VDD = 5 V

Conditions
Max at 85 Max at
Symbol Parameter Main voltage Typ Unit
Flash Clock °C(1) 125 °C(1)
regulator
mode(3) source
(MVR)(2)

HSE crystal osc.

1030
Operating (16 MHz)
mode LSI RC osc.
200 260 300
(128 kHz)
On
Supply HSE crystal osc.
970
current in Power-down (16 MHz)
IDD(AH) µA
active halt mode LSI RC osc.
mode 150 200 230
(128 kHz)
Operating
66 85 110
mode LSI RC osc.
Off
Power-down (128 kHz)
10 20 40
mode
1. Data based on characterization results, not tested in production
2. Configured by the REGAH bit in the CLK_ICKR register.
3. Configured by the AHALT bit in the FLASH_CR1 register.

Table 24. Total current consumption in active halt mode at VDD = 3.3 V
Conditions
Max at Max at
Symbol Parameter Main voltage Typ Unit
Flash Clock 85 °C(1) 125 °C(1)
regulator
mode(3) source
(MVR)(2)

HSE crystal osc.

550
Operating (16 MHz)
mode LSI RC osc.
200 260 290
(128 kHz)
On
Supply HSE crystal osc.
970
current in Power-down (16 MHz)
IDD(AH) µA
active halt mode LSI RC osc.
mode 150 200 230
(128 kHz)
Operating
66 80 105
mode LSI RC osc.
Off
Power-down (128 kHz)
10 18 35
mode
1. Data based on characterization results, not tested in production
2. Configured by the REGAH bit in the CLK_ICKR register.
3. Configured by the AHALT bit in the FLASH_CR1 register.

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Total current consumption in halt mode

Table 25. Total current consumption in halt mode at VDD = 5 V

Max at Max at
Symbol Parameter Conditions Typ Unit
85 °C(1) 125 °C(1)

Flash in operating mode, HSI clock after wakeup 63 75 105

Supply current in
IDD(H) Flash in power-down mode, HSI clock after µA
halt mode 6.0 15 35
wakeup
1. Data based on characterization results, not tested in production

Table 26. Total current consumption in halt mode at VDD = 3.3 V

Max at Max at
Symbol Parameter Conditions Typ Unit
85 °C(1) 125 °C(1)

Supply current in Flash in operating mode, HSI clock after wakeup 60 75 100
IDD(H) µA
halt mode Flash in power-down mode, HSI clock after wakeup 4.5 12 30
1. Data based on characterization results, not tested in production

Low power mode wakeup times

Table 27. Wakeup times

Symbol Parameter Conditions Typ Max(1) Unit

See
Wakeup time from wait note(2)
tWU(WFI)
mode to run mode(3)
fCPU = fMASTER = 16 MHz. 0.56
Flash in operating
1(6) 2(6)
MVR voltage mode(5)
regulator on(4) Flash in power-
3(6)
Wakeup time active halt down mode(5) HSI µs
tWU(AH)
mode to run mode(3) Flash in operating (after wakeup)
48(6)
MVR voltage mode(5)
regulator off(4) Flash in power-
50(6)
down mode(5)

Wakeup time from halt Flash in operating mode(5) 52

tWU(H)
mode to run mode(3) Flash in power-down mode (5)
54
1. Data guaranteed by design, not tested in production.
2. tWU(WFI) = 2 x 1/fmaster + 6 x 1/fCPU.
3. Measured from interrupt event to interrupt vector fetch.
4. Configured by the REGAH bit in the CLK_ICKR register.
5. Configured by the AHALT bit in the FLASH_CR1 register.
6. Plus 1 LSI clock depending on synchronization.

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Total current consumption and timing in forced reset state

Table 28. Total current consumption and timing in forced reset state
Symbol Parameter Conditions Typ Max(1) Unit

VDD = 5 V 400
IDD(R) Supply current in reset state(2) µA
VDD = 3.3 V 300
tRESETBL Reset pin release to vector fetch 150 µs
1. Data guaranteed by design, not tested in production.
2. Characterized with all I/Os tied to VSS.

Current consumption of on-chip peripherals

Subject to general operating conditions for VDD and TA.
HSI internal RC/fCPU = fMASTER = 16 MHz, VDD = 5 V

Table 29. Peripheral current consumption

Symbol Parameter Typ. Unit

IDD(TIM1) TIM1 supply current(1) 210

IDD(TIM5) TIM5 supply current(1) 130
IDD(TIM6) TIM6 timer supply current(1) 50
IDD(UART1) (2)
UART1 supply current 120 µA
IDD(SPI) SPI supply current(2) 45
IDD(I2C) I2C supply current(2) 65
IDD(ADC1) ADC1 supply current when converting(3) 1000
1. Data based on a differential IDD measurement between reset configuration and timer counter running at
16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production.
2. Data based on a differential IDD measurement between the on-chip peripheral when kept under reset and
not clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling. Not
tested in production.
3. Data based on a differential IDD measurement between reset configuration and continuous A/D
conversions. Not tested in production.

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Current consumption curves

Figure 9 to Figure 14 show typical current consumption measured with code executing in
RAM.

Figure 9. Typ IDD(RUN) vs. VDD HSE user external clock, fCPU = 16 MHz
25˚C
2.3 85˚C
125˚C
2.25 -45˚C

2.2

IDD run HSE (mA) 2.15

2.1

2.05
TBD
2

1.95

1.9

1.85

1.8
2 2.5 3 3.5 4 4.5 5 5.5 6

VDD (V)

Figure 10. Typ IDD(RUN) vs. fCPU HSE user external clock, VDD = 5 V
25˚C
85˚C
125˚C
2.5 -45˚C

2
IDD_run_HSE (mA)

1.5

TBD
1

0.5

0
2 4 6 8 10 12 14 16 18
FCPU (MHz)

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Figure 11. Typ IDD(RUN) vs. VDD HSI RC osc, fCPU = 16 MHz
25˚C
2 85˚C
125˚C
1.95 -45˚C
1.9

1.85

IDD run HSI (mA)

1.8

1.75
TBD
1.7

1.65

1.6

1.55

1.5
2 2.5 3 3.5 4 4.5 5 5.5 6

VDD (V)

Figure 12. Typ IDD(WFI) vs. VDD HSE user external clock, fCPU = 16 MHz
25˚C
1.8 85˚C
125˚C
1.6 -45˚C

1.4
IDD WFI HSE (mA)

1.2

0.8 TBD
0.6

0.4

0.2

0
2 2.5 3 3.5 4 4.5 5 5.5 6

VDD (V)

Figure 13. Typ IDD(WFI) vs. fCPU HSE user external clock, VDD = 5 V
25˚C
1.8 85˚C
125˚C
1.6 -45˚C
1.4
IDD_WFI_HSE (mA)

1.2

0.8 TBD
0.6

0.4

0.2

0
2 4 6 8 10 12 14 16 18
FCPU (MHz)

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Figure 14. Typ IDD(WFI) vs. VDD HSI RC osc, fCPU = 16 MHz
25˚C
1.8 85˚C
125˚C
1.6 -45˚C
1.4

1.2

IDD_WFI_HSI (mA)
1

0.8 TBD
0.6

0.4

0.2

0
2 2.5 3 3.5 4 4.5 5 5.5 6
FCPU (MHz)

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9.3.3 External clock sources and timing characteristics

HSE user external clock
Subject to general operating conditions for VDD and TA.

Table 30. HSE user external clock characteristics

Symbol Parameter Conditions Min Max Unit

User external clock source

fHSE_ext 0 16 MHz
frequency
OSCIN input pin high level
VHSEH(1) 0.7 x VDD VDD + 0.3 V
voltage
V
(1) OSCIN input pin low level
VHSEL VSS 0.3 x VDD
voltage
ILEAK_HSE OSCIN input leakage current VSS < VIN < VDD -1 +1 µA
1. Data based on characterization results, not tested in production.

Figure 15. HSE external clock source

VHSEH

VHSEL

fHSE
External clock
source OSCIN
CR8F

HSE crystal/ceramic resonator oscillator

The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and start-up stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).

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Table 31. HSE oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

External high speed oscillator

fHSE 1 16 MHz
frequency
RF Feedback resistor 220 kΩ
C(1) Recommended load capacitance (2) 20 pF
6 (startup)
C = 20 pF,
1.6
fOSC = 16 MHz
(stabilized)(3)
IDD(HSE) HSE oscillator power consumption mA
6 (startup)
C = 10 pF,
1.2
fOSC =16 MHz
(stabilized)(3)
gm Oscillator transconductance 5 mA/V
(4)
tSU(HSE) Startup time VDD is stabilized 1 ms
1. C is approximately equivalent to 2 x crystal Cload.
2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value.
Refer to crystal manufacturer for more details
3. Data based on characterization results, not tested in production.
4. tSU(HSE) is the start-up time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

Figure 16. HSE oscillator circuit diagram

fHSE to core
Rm

CO RF
Lm
CL1
Cm OSCIN
gm
Resonator
Consumption
control
Resonator

CR8F
OSCOUT
CL2

HSE oscillator critical gm formula

f 2 2
g mcrit = ( 2 × Π × HSE ) × R m ( 2Co + C )

Rm: Notional resistance (see crystal specification)

Lm: Notional inductance (see crystal specification)
Cm: Notional capacitance (see crystal specification)
Co: Shunt capacitance (see crystal specification)
CL1=CL2=C: Grounded external capacitance
gm >> gmcrit

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9.3.4 Internal clock sources and timing characteristics

Subject to general operating conditions for VDD and TA.

High speed internal RC oscillator (HSI)

Table 32. HSI oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

fHSI Frequency 16 MHz

User-trimmed with
CLK_HSITRIMR register
Accuracy of HSI oscillator 1(4) %
for given VDD and TA
conditions(1)

ACCHSI VDD = 5 V, TA = 25°C(2) -2.5(3) 1.3(3) %

VDD = 5 V,
Accuracy of HSI oscillator -2.5(3) 2(3) %
25 °C ≤TA ≤85 °C
(factory calibrated)
2.95 ≤ VDD ≤ 5.5 V, -
3(2)(3) %
-40 °C ≤TA ≤125 °C 4.5(2)(3)
HSI oscillator wakeup time
tsu(HSI) 1(4) µs
including calibration
HSI oscillator power
IDD(HSI) 170 250(2) µA
consumption
1. Refer to application note.
2. Data based on characterization results, not tested in production
3. Subject to further characterization to give better results
4. Guaranteeed by design, not tested in production.

Figure 17. Typical HSI accuracy at VDD = 5 V vs 5 temperatures

3.00%

2.00%

1.00%

0.00%
max
-1.00%
TBD min
-2.00%

-3.00%

-4.00%

-5.00%
-40 0 25 85 125

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Figure 18. Typical HSI frequency variation vs VDD @ 4 temperatures

25˚C
85˚C
1.00% 125˚C
-45˚C
0.50%

0.00%

% accuracy
-0.50% TBD
-1.00%

-1.50%

-2.00%
2.5 3 3.5 4 4.5 5 5.5 6
VDD (V)

Low speed internal RC oscillator (LSI)

Subject to general operating conditions for VDD and TA.

Table 33. LSI oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

fLSI Frequency 110 128 150 kHz

tsu(LSI) LSI oscillator wake-up time 7 µs
IDD(LSI) LSI oscillator power consumption 5 µA

Figure 19. Typical LSI frequency variation vs VDD @ 4 temperatures

25˚C
85˚C
5.00% 125˚C
-45˚C
4.00%

3.00%

2.00%
% accuracy

1.00%

0.00%

-1.00%

-2.00%

-3.00%

-4.00%

-5.00%
2 2.5 3 3.5 4 4.5 5 5.5 6

VDD (V)

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9.3.5 Memory characteristics

RAM and hardware registers

Table 34. RAM and hardware registers

Symbol Parameter Conditions Min Typ Max Unit

VRM Data retention mode(1) Halt mode (or reset) 2.8 V(2) V
1. Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware
registers (only in halt mode). Guaranteed by design, not tested in production.
2. Refer to Table 18 on page 45 for the value of VIT-max

Flash program memory/data EEPROM memory

Table 35. Flash program memory/data EEPROM memory

Symbol Parameter Conditions Min(1) Typ Max Unit

Operating voltage
VDD fCPU ≤ 16 MHz 2.95 5.5 V
(all modes, execution/write/erase)
Standard programming time
(including erase) for byte/word/block 6 6.6
tprog (1 byte/4 bytes/64 bytes)
ms
Fast programming time for 1 block (64
3 3.33
bytes)
terase Erase time for 1 block (64 bytes) 3 3.33
Erase/write cycles(2)
TA = +85 °C 10 k
NRW (program memory) cycles
Erase/write cycles (data memory)(2) TA = +125 °C 300 k 1M
Data retention (program and data
memory) after 10k erase/write cycles TRET = 55°C 20
at TA = +55 °C
tRET years
Data retention (data memory) after
300k erase/write cycles TRET = 85°C 1
at TA = +125 °C
Supply current (Flash programming or
IDD 2 mA
erasing for 1 to 128 bytes)
1. Data based on characterization results, not tested in production.
2. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a
write/erase operation addresses a single byte.

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9.3.6 I/O port pin characteristics

General characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified. All
unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or
an external pull-up or pull-down resistor.

Table 36. I/O static characteristics

Symbol Parameter Conditions Min Typ Max Unit

Input low level

VIL -0.3 V 0.3 x VDD V
voltage
Input high level VDD = 5 V
VIH 0.7 x VDD VDD + 0.3 V V
voltage
Vhys Hysteresis(1) 700 mV
Rpu Pull-up resistor VDD = 5 V, VIN = VSS 30 45 60 kΩ
Fast I/Os
20 ns
Rise and fall time Load = 50 pF
tR, tF
(10% - 90%) Standard and high sink I/Os
125 ns
Load = 50 pF
Digital input leakage
Ilkg VSS ≤ VIN ≤ VDD ±1 µA
current
Analog input
Ilkg ana VSS ≤ VIN ≤ VDD ±250
leakage current
Leakage current in
Ilkg(inj) Injection current ±4 mA ±1
adjacent I/O
1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production.

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Figure 20. Typical VIL and VIH vs VDD @ 4 temperatures

-40˚C
6
25˚C

5 85˚C
125˚C
4

VIL / VIH [V]

3
TBD
2

0
2.5 3 3.5 4 4.5 5 5.5 6
VDD [V]

Figure 21. Typical pull-up resistance vs VDD @ 4 temperatures

-40˚C
60 25˚C
85˚C
55 125˚C
Pull-up resistance [kΩ]

50

45
TBD
40

35

30
2.5 3 3.5 4 4.5 5 5.5 6
VDD [V]

Figure 22. Typical pull-up current vs VDD @ 4 temperatures

140

120

100
Pull-up current [µA]

80

60
Alain to send -40˚C
25˚C
40 85˚C

20
125˚C

0
0 1 2 3 4 5 6
VDD [V]

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Table 37. Output driving current (standard ports)

Symbol Parameter Conditions Min Max Unit

Output low level with 4 pins sunk IIO = 4 mA, VDD = 3.3 V 1(1)
VOL
Output low level with 8 pins sunk IIO= 10 mA, VDD = 5 V 2
V
(1)
Output high level with 4 pins sourced IIO = 4 mA, VDD = 3.3 V 2.1
VOH
Output high level with 8 pins sourced IIO = 10 mA, VDD = 5 V 2.8
1. Data based on characterization results, not tested in production

Table 38. Output driving current (true open drain ports)

Symbol Parameter Conditions Min Max Unit

IIO = 10 mA, VDD = 3.3 V 1.5(1)

VOL Output low level with 2 pins sunk IIO = 10 mA, VDD = 5 V 1 V
IIO = 20 mA, VDD = 5 V (1)
2
1. Data based on characterization results, not tested in production

Table 39. Output driving current (high sink ports)

Symbol Parameter Conditions Min Max Unit

Output low level with 4 pins sunk IIO = 10 mA, VDD = 3.3 V 1(1)
VOL Output low level with 8 pins sunk IIO = 10 mA, VDD = 5 V 0.8
Output low level with 4 pins sunk IIO = 20 mA, VDD = 5 V 1.5(1)
V
Output high level with 4 pins sourced IIO = 10 mA, VDD = 3.3 V 2.1(1)
VOH Output high level with 8 pins sourced IIO = 10 mA, VDD = 5 V 4.0
Output high level with 4 pins sourced IIO = 20 mA, VDD = 5 V 3.3(1)
1. Data based on characterization results, not tested in production

Figure 23. Typ. VOL @ VDD = 3.3 V (standard ports)

-40˚C
1.5
25˚C
1.25 85˚C
125˚C
1
VOL [V]

0.75
TBD
0.5

0.25

0
0 1 2 3 4 5 6 7
IOL [mA]

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Figure 24. Typ. VOL @ VDD = 5 V (standard ports)

-40˚C
1.5
25˚C
1.25 85˚C
125˚C
1

VOL [V]
0.75
TBD
0.5

0.25

0
0 2 4 6 8 10 12
IOL [mA]

Figure 25. Typ. VOL @ VDD = 3.3 V (true open drain ports)

-40˚C
2
25˚C
1.75
85˚C
1.5 125˚C
1.25
VOL[V]

Alain
1
to send
0.75

0.5

0.25

0
0 2 4 6 8 10 12 14
IOL [mA]

Figure 26. Typ. VOL @ VDD = 5 V (true open drain ports)

-40˚C
2
25˚C
1.75
85˚C
1.5 125˚C
1.25
VOL[V]

1
TBD
0.75

0.5

0.25

0
0 5 10 15 20 25
IOL [mA]

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Figure 27. Typ. VOL @ VDD = 3.3 V (high sink ports)

-40˚C
1.5
25˚C
1.25 85˚C
125˚C
1

VOL[V]
0.75
TBD
0.5

0.25

0
0 2 4 6 8 10 12 14
IOL [mA]

Figure 28. Typ. VOL @ VDD = 5 V (high sink ports)

-40˚C
1.5
25˚C
1.25 85˚C
125˚C
1
VOL[V]

0.75
Alain to send
0.5

0.25

0
0 5 10 15 20 25
IOL [mA]

Figure 29. Typ. VDD - VOH @ VDD = 3.3 V (standard ports)

-40˚C
2
25˚C
1.75
85˚C
1.5 125˚C
1.25
VDD - VOH[V]

1
TBD
0.75

0.5

0.25

0
0 1 2 3 4 5 6 7
IOH [mA]

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Figure 30. Typ. VDD - VOH @ VDD = 5 V (standard ports)

-40˚C
2
25˚C
1.75
85˚C
1.5 125˚C
1.25

VDD - VOH[V]
1
TBD
0.75

0.5

0.25

0
0 2 4 6 8 10 12
IOH [mA]

Figure 31. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports)

-40˚C
2
25˚C
1.75
85˚C
1.5 125˚C
1.25
VDD - VOH[V]

1
Alain to send
0.75

0.5

0.25

0
0 2 4 6 8 10 12 14
IOH [mA]

Figure 32. Typ. VDD - VOH @ VDD = 5 V (high sink ports)

-40˚C
2
25˚C
1.75
85˚C
1.5 125˚C
1.25
VDD - VOH[V]

1
Alain to send
0.75

0.5

0.25

0
0 5 10 15 20 25
IOH [mA]

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9.3.7 Reset pin characteristics

Subject to general operating conditions for VDD and TA unless otherwise specified.

Table 40. NRST pin characteristics

Symbol Parameter Conditions Min Typ Max Unit

VIL(NRST) NRST Input low level voltage (1) -0.3 V 0.3 x VDD
0.7 x VDD +
VIH(NRST) NRST Input high level voltage (1) V
VDD 0.3
VOL(NRST) NRST Output low level voltage (1) IOL=2 mA 0.5
(2)
RPU(NRST) NRST Pull-up resistor 30 40 60 kΩ
(3)
tIFP(NRST) NRST Input filtered pulse 75 ns
tINFP(NRST) NRST Input not filtered pulse (3) 500 ns
tOP(NRST) (3)
NRST output pulse 20 µs
1. Data based on characterization results, not tested in production.
2. The RPU pull-up equivalent resistor is based on a resistive transistor
3. Data guaranteed by design, not tested in production.

Figure 33. Typical NRST VIL and VIH vs VDD @ 4 temperatures

-40˚C
6
25˚C

5 85˚C
125˚C
4
VIL / VIH [V]

3
TBD
2

0
2.5 3 3.5 4 4.5 5 5.5 6
VDD [V]

Figure 34. Typical NRST pull-up resistance vs VDD @ 4 temperatures

-40˚C
60 25˚C
85˚C
55 125˚C
NRESET pull-up resistance [kΩ]

50

45
TBD
40

35

30
2.5 3 3.5 4 4.5 5 5.5 6
VDD [V]

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Figure 35. Typical NRST pull-up current vs VDD @ 4 temperatures

140

120

NRESET Pull-Up current

100

80

60
TBD -40˚C
25˚C
40
85˚C
20 125˚C

0
0 1 2 3 4 5 6
VDD [V]

The reset network shown in Figure 36 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below the VIL max. level specified in
Table 36. Otherwise the reset is not taken into account internally.

Figure 36. Recommended reset pin protection

VDD CR8F

RPU
External NRST Internal reset
reset Filter
circuit
0.01 µF
(optional)

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9.3.8 SPI serial peripheral interface

Unless otherwise specified, the parameters given in Table 41 are derived from tests performed under
ambient temperature, fMASTER frequency and VDD supply voltage conditions. tMASTER = 1/fMASTER.
Refer to I/O port characteristics for more details on the input/output alternate function characteristics
(NSS, SCK, MOSI, MISO).

Table 41. SPI characteristics

Symbol Parameter Conditions(1) Min Max Unit

fSCK Master mode 0 8

SPI clock frequency MHz
1/tc(SCK) Slave mode 0 TBD(2)
tr(SCK)
SPI clock rise and fall time Capacitive load: C = 30 pF 25
tf(SCK)
tsu(NSS)(3) NSS setup time Slave mode 4 x tMASTER
th(NSS) (3) NSS hold time Slave mode 70
(3)
tw(SCKH)
SCK high and low time Master mode tSCK/2 - 15 tSCK/2 +15
tw(SCKL)(3)

tsu(MI) (3) Master mode 5

Data input setup time
tsu(SI)(3) Slave mode 5
Master mode 7 ns
th(MI) (3)
Data input hold time
th(SI)(3) Slave mode 10
ta(SO)(3)(4) Data output access time Slave mode 3 x tMASTER
tdis(SO)(3)(5) Data output disable time Slave mode 25
(3)
tv(SO) Data output valid time Slave mode (after enable edge) TBD(2)
tv(MO)(3) Data output valid time Master mode (after enable edge) 30
(3) (2)
th(SO) Slave mode (after enable edge) 27
Data output hold time
th(MO)(3) Master mode (after enable edge) 11(2)
1. Parameters are given by selecting 10 MHz I/O output frequency.
2. Data characterization in progress.
3. Values based on design simulation and/or characterization results, and not tested in production.
4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.

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Figure 37. SPI timing diagram - slave mode and CPHA = 0

NSS input
tSU(NSS) tc(SCK) th(NSS)

CPHA= 0
SCK Input

CPOL=0
tw(SCKH)
CPHA= 0 tw(SCKL)
CPOL=1

tv(SO) th(SO) tr(SCK) tdis(SO)

ta(SO) tf(SCK)
MISO
OUT P UT MS B O UT BI T6 OUT LSB OUT
tsu(SI)
MOSI
M SB IN B I T1 IN LSB IN
I NPUT
th(SI)
ai14134

Figure 38. SPI timing diagram - slave mode and CPHA = 1

NSS input
tSU(NSS) tc(SCK) th(NSS)

CPHA=1
SCK Input

CPOL=0
tw(SCKH)
CPHA=1 tw(SCKL)
CPOL=1

tv(SO) th(SO) tr(SCK) tdis(SO)

ta(SO) tf(SCK)
MISO
OUT P UT MS B O UT BI T6 OUT LSB OUT
tsu(SI) th(SI)
MOSI
M SB IN B I T1 IN LSB IN
I NPUT

ai14135

1. Measurement points are done at CMOS levels: 0.3VDD and 0.7 VDD.

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Figure 39. SPI timing diagram - master mode(1)

High

NSS input

tc(SCK)

CPHA= 0
SCK Input

CPOL=0
CPHA= 0
CPOL=1

CPHA=1
SCK Input

CPOL=0
CPHA=1
CPOL=1

tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INP UT MS BIN BI T6 IN LSB IN

th(MI)
MOSI
M SB OUT B I T1 OUT LSB OUT
OUTUT
tv(MO) th(MO)

ai14136

1. Measurement points are done at CMOS levels: 0.3VDD and 0.7 VDD.

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9.3.9 I2C interface characteristics

Table 42. I2C characteristics

Standard mode I2C Fast mode I2C(1)
Symbol Parameter Unit
Min(2) Max(2) Min(2) Max(2)

tw(SCLL) SCL clock low time 4.7 1.3

µs
tw(SCLH) SCL clock high time 4.0 0.6
tsu(SDA) SDA setup time 250 100
th(SDA) SDA data hold time 0(3) 0(4) 900(3)
tr(SDA) ns
SDA and SCL rise time 1000 300
tr(SCL)
tf(SDA)
SDA and SCL fall time 300 300
tf(SCL)
th(STA) START condition hold time 4.0 0.6
µs
tsu(STA) Repeated START condition setup time 4.7 0.6
tsu(STO) STOP condition setup time 4.0 0.6 µs
STOP to START condition time (bus
tw(STO:STA) 4.7 1.3 µs
free)
Cb Capacitive load for each bus line 400 400 pF
2
1. fMASTER, must be at least 8 MHz to achieve max fast I C speed (400kHz)
2. Data based on standard I2C protocol requirement, not tested in production
3. The maximum hold time of the start condition has only to be met if the interface does not stretch the low
time
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL

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9.3.10 10-bit ADC characteristics

Subject to general operating conditions for VDD, fMASTER, and TA unless otherwise specified.

Table 43. ADC characteristics

Symbol Parameter Conditions Min Typ Max Unit

VDD = 2.95 to 5.5 V 1 4

fADC ADC clock frequency MHz
VDD = 4.5 to 5.5 V 1 6

VAIN Conversion voltage range(1) VSS VDD V

Internal bandgap reference
VBGREF VDD = 2.95 to 5.5 V 1.19 1.22 1.25 V
voltage
Internal sample and hold
CADC 3 pF
capacitor
fADC = 4 MHz 0.75
tS(1) Minimum sampling time µs
fADC = 6 MHz 0.5
tSTAB Wake-up time from standby 7 µs
fADC = 4 MHz 3.5 µs
Minimum total conversion time
tCONV (including sampling time, 10-bit fADC = 6 MHz 2.33 µs
resolution)
14 1/fADC
1. During the sample time the input capacitance CAIN (3 pF max) can be charged/discharged by the external
source. The internal resistance of the analog source must allow the capacitance to reach its final voltage
level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on
the conversion result. Values for the sample clock tS depend on programming.

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Table 44. ADC accuracy with RAIN < 10 kΩ , VDD = 5 V

Symbol Parameter Conditions Typ Max(1) Unit

fADC = 2 MHz 1.6 TBD

(2)
|ET| Total unadjusted error fADC = 4 MHz 2.2 TBD
fADC = 6 MHz 2.4 TBD
fADC = 2 MHz 1.1 TBD
(2)
|EO| Offset error fADC = 4 MHz 1.5 TBD
fADC = 6 MHz 1.8 TBD
fADC = 2 MHz 1.5 TBD
|EG| Gain error (2) fADC = 4 MHz 2.1 TBD LSB
fADC = 6 MHz 2.2 TBD
fADC = 2 MHz 0.7 TBD
|ED| Differential linearity error (2) fADC = 4 MHz 0.7 TBD
fADC = 6 MHz 0.7 TBD
fADC = 2 MHz 0.6 TBD
|EL| (2)
Integral linearity error fADC = 4 MHz 0.8 TBD
fADC = 6 MHz 0.8 TBD
1. Data characterization in progress.
2. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins
should be avoided as this significantly reduces the accuracy of the conversion being performed on another
analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may
potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and
ΣIINJ(PIN) in Section 9.3.6 does not affect the ADC accuracy.

Table 45. ADC accuracy with RAIN < 10 kΩ RAIN, VDD = 3.3 V
Symbol Parameter Conditions Typ Max(1) Unit

fADC = 2 MHz 1.6 TBD

|ET| Total unadjusted error(2)
fADC = 4 MHz 1.9 TBD
fADC = 2 MHz 1 TBD
|EO| Offset error(2)
fADC = 4 MHz 1.5 TBD
fADC = 2 MHz 1.3 TBD
|EG| Gain error(2) LSB
fADC = 4 MHz 2 TBD
fADC = 2 MHz 0.7 TBD
|ED| Differential linearity error(2)
fADC = 4 MHz 0.7 TBD
fADC = 2 MHz 0.6 TBD
|EL| Integral linearity error(2)
fADC = 4 MHz 0.8 TBD
1. Data characterization in progress.

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Figure 40. ADC accuracy characteristics

EG
1023
V –V
1022 DDA SSA
1LSB = -----------------------------------------
1021 IDEAL 1024
(2)
ET
7 (3)
(1)
6
5
EO EL
4
3
ED
2
1 1 LSBIDEAL

0 1 2 3 4 5 6 7 1021102210231024
VSSA VDD

1. Example of an actual transfer curve.

2. The ideal transfer curve
3. End point correlation line
ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset error: deviation between the first actual transition and the first ideal one.
EG = Gain error: deviation between the last ideal transition and the last actual one.
ED = Differential linearity error: maximum deviation between actual steps and the ideal one.
EL = Integral linearity error: maximum deviation between any actual transition and the end point correlation
line.

Figure 41. Typical application with ADC

VDD CR8F

VT
0.6V
RAIN AINx
VAIN 10-bit A/D
conversion
CAIN VT
0.6V IL CADC
¬

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9.3.11 EMC characteristics

Susceptibility tests are performed on a sample basis during product characterization.

Functional EMS (electromagnetic susceptibility)

Based on a simple running application on the product (toggling 2 LEDs through I/O ports),
the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).
● ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 1000-4-2
standard.
● FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test conforms
with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Prequalification trials:
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).

Table 46. EMS data

Symbol Parameter Conditions Level/class

VDD = 3.3 V, TA = 25 °C,

Voltage limits to be applied on any I/O pin
VFESD fMASTER = 16 MHz (HSI clock), 2/B
to induce a functional disturbance
conforming to IEC 1000-4-2
Fast transient voltage burst limits to be VDD= 3.3 V, TA = 25 °C ,
VEFTB applied through 100 pF on VDD and VSS fMASTER = 16 MHz (HSI clock), 4/A
pins to induce a functional disturbance conforming to IEC 1000-4-4

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Electrical characteristics CR8F612X

Electromagnetic interference (EMI)

Based on a simple application running on the product (toggling 2 LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm SAE J 1752/3 which specifies the board and the loading of each pin.

Table 47. EMI data

Conditions

Max fHSE/fCPU(1)
Symbol Parameter Unit
Monitored
General conditions
frequency band 16 MHz/ 16 MHz/
8 MHz 16 MHz

0.1MHz to 30 MHz 2 3
VDD = 5 V
Peak level TA = 25 °C 30 MHz to 130 MHz 10 10 dBµV
SEMI
LQFP32 package 130 MHz to 1 GHz 5 7
Conforming to SAE J 1752/3
SAE EMI level SAE EMI level 2.5 2.5
1. Data based on characterization results, not tested in production.

Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU, and DLU) using specific measurement methods,
the product is stressed to determine its performance in terms of electrical sensitivity. For
more details, refer to the application note AN1181.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). One model
can be simulated: Human body model. This test conforms to the JESD22-A114A/A115A
standard. For more details, refer to the application note AN1181.

Table 48. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Class Unit
value(1)

Electrostatic discharge voltage TA = 25°C, conforming to

VESD(HBM) A 4000
(Human body model) JESD22-A114
TA LQFP32 package = V
Electrostatic discharge voltage
VESD(CDM) 25°C, conforming to IV 1000
(Charge device model)
SD22-C101
1. Data based on characterization results, not tested in production

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Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
● A supply overvoltage (applied to each power supply pin)
● A current injection (applied to each input, output and configurable I/O pin) are
performed on each sample.
This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the
application note AN1181.

Table 49. Electrical sensitivities

Symbol Parameter Conditions Class(1)

TA = 25 °C A
LU Static latch-up class TA = 85 °C A
TA = 125 °C A
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the
JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B
class strictly covers all the JEDEC criteria (international standard).

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Package characteristics CR8F612X

10 Package characteristics

To meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at www.st.com.
ECOPACK® is an ST trademark.

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10.1 Package mechanical data

10.1.1 LQFP package mechanical data

Figure 42. 32-pin low profile quad flat package (7 x 7)

ccc C
D

D1

D3 A
A2
24 17

16
25 L1
b
E3 E1 E

32
9
L
Pin 1 A1 K
identification 1 8 c

5V_ME

Table 50. 32-pin low profile quad flat package mechanical data
mm inches(1)
Dim.
Min Typ Max Min Typ Max

A 1.600 0.0630
A1 0.050 0.150 0.0020 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.300 0.370 0.450 0.0118 0.0146 0.0177
c 0.090 0.200 0.0035 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 5.600 0.2205
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 5.600 0.2205
e 0.800 0.0315
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 1.000 0.0394
k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0°
ccc 0.100 0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits

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10.1.2 VFQFPN package mechanical data

Figure 43. 32-lead very thin fine pitch quad flat no-lead package (5 x 5)
Seating plane

C
ddd C
A

A3 A1

D
e

9 16

8 17

E2 b E

24
1
L
32
Pin # 1 ID
R = 0.30 D2
L
Bottom view 42_ME

Table 51. 32-lead very thin fine pitch quad flat no-lead package mechanical data
mm inches(1)
Dim.
Min Typ Max Min Typ Max

A 0.80 0.90 1.00 0.0315 0.0354 0.0394

A1 0 0.02 0.05 0.0008 0.0020

A3 0.20 0.0079

b 0.18 0.25 0.30 0.0071 0.0098 0.0118

D 4.85 5.00 5.15 0.1909 0.1969 0.2028

D2 3.20 3.45 3.70 0.1260 0.1457

E 4.85 5.00 5.15 0.1909 0.1969 0.2028

E2 3.20 3.45 3.70 0.1260 0.1358 0.1457

e 0.50 0.0197

L 0.30 0.40 0.50 0.0118 0.0157 0.0197

ddd 0.08 0.0031

1. Values in inches are converted from mm and rounded to 4 decimal digits.

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CR8F612X Package characteristics

Figure 44. Recommended footprint for on-board emulation

0.5mm
0.8mm
[0.032"]

4mm
[0.157"]
0.5mm

1.65mm [0.065"] 0.9mm

[0.035"]
0.3mm [0.012"]

4mm [0.157"]

ai15319
Bottom view

1. Drawing is not to scale

Figure 45. Recommended footprint without on-board emulation

1. Drawing is not to scale

2. Dimensions are in millimeters

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Package characteristics CR8F612X

10.2 Thermal characteristics

The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 17: General operating conditions on page 44.
The maximum chip-junction temperature, TJmax, in degrees Celsius, may be calculated
using the following equation:
TJmax = TAmax + (PDmax x ΘJA)
Where:
● TAmax is the maximum ambient temperature in ° C
● ΘJA is the package junction-to-ambient thermal resistance in ° C/W
● PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax)
● PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
● PI/Omax represents the maximum power dissipation on output pins
Where:
PI/Omax = Σ (VOL*IOL) + Σ((VDD-VOH)*IOH),
taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in
the application.

Table 52. Thermal characteristics(1)

Symbol Parameter Value Unit

Thermal resistance junction-ambient

ΘJA 60 °C/W
LQFP 32 - 7 x 7 mm
Thermal resistance junction-ambient
ΘJA3 22 °C/W
VFQFPN 32 - 5 x 5 mm
1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection
environment.

10.2.1 Reference document

JESD51-2 integrated circuits thermal test method environment conditions - natural
convection (still air). Available from www.jedec.org.

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10.2.2 Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the order code (see
Section 11: Ordering information on page 84).
The following example shows how to calculate the temperature range needed for a given
application.
Assuming the following application conditions:
● Maximum ambient temperature TAmax= 75 °C (measured according to JESD51-2)
● IDDmax = 8 mA, VDD = 5 V
● Maximum 20 I/Os used at the same time in output at low level with
IOL = 8 mA, VOL= 0.4 V
PINTmax = 8 mA x 5 V = 400 mW
PIOmax = 20 x 8 mA x 0.4 V = 64 mW
This gives: PINTmax = 400 mW and PIOmax 64 mW:
PDmax = 400 mW + 64 mW
Thus: PDmax = 464 mW
Using the values obtained in Table 52: Thermal characteristics on page 82, TJmax is
calculated as follows for LQFP32 59°C/W:
TJmax = 75° C + (59° C/W x 464 mW) = 75°C + 27°C = 102° C
This is within the range of the suffix 6 version parts (-40 < TJ < 105° C).
In this case, parts must be ordered at least with the temperature range suffix 6.

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CR8F612X CR8F development tools

12 CR8F development tools

Development tools for the CR8F microcontrollers include the full-featured STice emulation
system supported by a complete software tool package including C compiler, assembler and
integrated development environment with high-level language debugger. In addition, the
CR8F is to be supported by a complete range of tools including starter kits, evaluation
boards and a low-cost in-circuit debugger/programmer.

12.1 Emulation and in-circuit debugging tools

The STice emulation system offers a complete range of emulation and in-circuit debugging
features on a platform that is designed for versatility and cost-effectiveness. In addition,
CR8F application development is supported by a low-cost in-circuit debugger/programmer.
The STice is the fourth generation of full featured emulators from STMicroelectronics. It
offers new advanced debugging capabilities including profiling and coverage to help detect
and eliminate bottlenecks in application execution and dead code when fine tuning an
application.
In addition, STice offers in-circuit debugging and programming of CR8F microcontrollers via
the CR8F single wire interface module (SWIM), which allows non-intrusive debugging of an
application while it runs on the target microcontroller.
For improved cost effectiveness, STice is based on a modular design that allows you to
order exactly what you need to meet your development requirements and to adapt your
emulation system to support existing and future ST microcontrollers.

STice key features

● Occurrence and time profiling and code coverage (new features)
● Advanced breakpoints with up to 4 levels of conditions
● Data breakpoints
● Program and data trace recording up to 128 KB records
● Read/write on the fly of memory during emulation
● In-circuit debugging/programming via SWIM protocol
● 8-bit probe analyzer
● 1 input and 2 output triggers
● Power supply follower managing application voltages between 1.62 to 5.5 V
● Modularity that allows you to specify the components you need to meet your
development requirements and adapt to future requirements
● Supported by free software tools that include integrated development environment
(IDE), programming software interface and assembler for CR8F.

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12.2 Software tools

CR8F development tools are supported by a complete, free software package from
STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual
Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic
and Raisonance C compilers for CR8F, which are available in a free version that outputs up
to 16 Kbytes of code.

12.2.1 CR8F toolset

CR8F toolset with STVD integrated development environment and STVP programming
software is available for free download at www.st.com/mcu. This package includes:
ST visual develop – Full-featured integrated development environment from ST, featuring
● Seamless integration of C and ASM toolsets
● Full-featured debugger
● Project management
● Syntax highlighting editor
● Integrated programming interface
● Support of advanced emulation features for STice such as code profiling and coverage
ST visual programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read,
write and verify of your CR8F microcontroller’s Flash program memory, data EEPROM and
option bytes. STVP also offers project mode for saving programming configurations and
automating programming sequences.

12.2.2 C and assembly toolchains

Control of C and assembly toolchains is seamlessly integrated into the STVD integrated
development environment, making it possible to configure and control the building of your
application directly from an easy-to-use graphical interface.
Available toolchains include:
● Cosmic C compiler for CR8F – Available in a free version that outputs up to
16 Kbytes of code. For more information, see www.cosmic-software.com.
● Raisonance C compiler for CR8F – Available in a free version that outputs up to
16 Kbytes of code. For more information, see www.raisonance.com.
● CR8F assembler linker – Free assembly toolchain included in the STVD toolset,
which allows you to assemble and link your application source code.

12.3 Programming tools

During the development cycle, STice provides in-circuit programming of the CR8F Flash
microcontroller on your application board via the SWIM protocol. Additional tools are to
include a low-cost in-circuit programmer as well as ST socket boards, which provide
dedicated programming platforms with sockets for programming your CR8F.
For production environments, programmers will include a complete range of gang and
automated programming solutions from third-party tool developers already supplying
programmers for the CR8F family.

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13 Revision history

Table 53. Document revision history

Date Revision Changes

30-Apr-2009 1 Initial revision

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 CR8F612X

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