1 2 3 4 5 6 7 8

VCC_CORE BL5M Block Diagram

CLOCK GENERATOR
+1.5V
HDMI CEC HDMI Level Shift Intel CK505
Page 19 Page 21
PENRYN ICS9LPR363
Page 2
A
+1.05V uFCPGA A

CRT
Page 20
Page 3,4
+1.25V
INT MIC LCD PANEL FSB(667/800MHZ) CRT
Page 19 Page 19 VGA CONNECTOR
HDMI
SDVO (FOX)
+1.8VSUS LCD/LED
+1.8V PCI-E 16X Lan Page 18
CRT NB
+3VPCU CANTIGA
+3V_S5 LVDS DDRII-SODIMM1
533/ 667 MHZ DDR II
+3VSUS SATA
DDRII-SODIMM2
+3V SATA - HDD Page 5,7,8,9,10,11 Page 16, 17

+5VPCU Page 22

+5V_S5 SATA
+5V SATA - ODD DMI(x2/x4) MINI CARD-3 MINI CARD-4
+SMDDR_VTERM Page 22 UMA HD-DVD ROBSON
+SMDDR_VREF Page 25 (FTB) Page 25
B B
USB-0
DAUGHTER PCIE-2 PCIE-4
BOARD
LAN/B USB PCI-Express
Page 26
PCIE-6 PCIE-3 PCIE-1 PCIE-5
USB-3
Camera
Page 19 MINI CARD-1 MINI CARD-2 LAN
NEW CARD
WLAN UMA TV/ROBSON Connector
USB-5 USB 2.0 SB Page 25 Page 25 Page 27 Page 26
WLAN
Page 25 ICH9M LAN/RJ11/RJ45/USB/RF DAUGHTER BOARD

USB-1
DAUGHTER
Finger Printer
BOARD
(FTB) Page 26
Marvell LAN
PCI Bus
10/100/Giga
Azalia
USB-2 88E8040T/88E8055
Bluetooth Page 12, 13, 14, 15
Page 26
PCMCIA Card
USB-9
New Card LPC 32.768KHz
Controller Reader/1394
Page 27 (CB 1410) (OZ129T) Transformer
Page 23 Page 24
C USB-7 C
M/B USB2
Page 27
RJ45 RJ11 USB RF
PCMCIA 5 IN 1 1394
USB-4 WPC8763LDG Page 23 Page 24 Page 24
DAUGHTER
BOARD
Felica
(FTB) Page 26 LED Board
Page 28 Page 26
USB-6
M/B USB
Page 27
Low Cost Board
USB-8
TV/ROBSON Page 26
Page 25
DAUGHTER
Port-A
HP Key FLASH MMB Board BOARD
Port-B VR FAN Kill SW CIR G-Sensor
Page 30 Board ROM Page 26
AUDIO CODEC Page 30 Page 3 Page 27 Page 26 Page 28 Page 28 Page 22
(CX20561)
MIC JACK Page 29 Power Board
Page 30 Page 26
Port-C
D D

INT SPK SPK AMP

Page 29 Page 29 FM TUNER Touch Pad
Reserve FM
& MDC Page 29
Board Page 26
Page 29
Reserve MIC
Page 29
Quanta Computer Inc.
MDC Board RJ11 PROJECT : BL5M Montevina
Reserve MIC Size Document Number Rev
1A
Page 29 Block Diagram
Date: Tuesday, March 04, 2008 Sheet 1 of 37
1 2 3 4 5 6 7 8

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 5 4 3 2 1

Clock +1.05V_VDD
BOM Option Table

Generator
Reference Description
PBY160808T-301Y-N_6 L18 +1.05V IV@ INT VGA

L19 PBY160808T-301Y-N_6 VDD_CK_VDD_48 C265 0.1u/10V_4 C257 C268 C276 C238 C274 C227 C278 C242
EV@ EXT VGA
+3V
*10u/10V_8 10u/10V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4
C286
C279 0.1u/10V_4
10u/10V_8
C275 10u/10V_8

+3V

D D
C240 0.1u/10V_4 11/01 Modify U12
2 48 PM_STPPCI# R247 2.2K_4
C277 0.1u/10V_4 VDD_PCI IO_VOUT
9
VDD_48 CGCLK_SMB
16 64
VDD_PLL3 SCLK CGDAT_SMB PM_STPCPU# R248 2.2K_4
61 63
VDD_REF SDA
C241 0.1u/10V_4 VDD_CK_VDD_48
CK505 PM_STPPCI#
39 38 PM_STPPCI# (16)
VDD_SRC SRC5/PCI_STOP# PM_STPCPU# NEW_CLKREQ#_R R305
55
VDD_CPU SRC5#/CPU_STOP#
37 PM_STPCPU# (16) To SB 10K_4

12 54 CLK_CPU_BCLK_R RP34 1 2 0X2

+1.05V_VDD VDD_96_IO CPU0 CLK_CPU_BCLK (3)
C239 0.1u/10V_4 20 53 CLK_CPU_BCLK#_R 3 4 To CPU
VDD_PLL3_IO CPU0# CLK_CPU_BCLK# (3)
26
VDD_SRC_IO_1 CLK_MCH_BCLK_R RP35
45 51 1 2 0X2 CLK_MCH_BCLK (5)
VDD_SRC_IO_3 CPU1 CLK_MCH_BCLK#_R
36
VDD_SRC_IO_2 CPU1#
50 3 4 CLK_MCH_BCLK# (5) To NB
49
VDD_CPU_IO CLK_PCIE_MINI3_R RP36
47 1 2 IV@0X2 CLK_PCIE_MINI3 (25)
SRC8/ITP CLK_PCIE_MINI3#_R
SRC8#/ITP#
46 3 4 CLK_PCIE_MINI3# (25) To MINI3
PCLK_DEBUG R294 33_4 PCLK_DEBUG_R 1 35 CLK_PCIE_3GPLL#_R RP39 1 2 0X2
(25) PCLK_DEBUG PCI0/CR#_A SRC10# CLK_PCIE_3GPLL_R CLK_PCIE_3GPLL# (6)
SRC10
34 3 4 CLK_PCIE_3GPLL (6) To NB
R306 *33_4 PCLK_PCM_R 3
T84 PCI1/CR#_B CLK_MCH_OE#_R
33 R261 475/F_4 CLK_MCH_OE# (6)
PCLK_OZ129 R307 33_4 PCLK_OZ129_R SRC11/CR#_H NEW_CLKREQ#_R R300 475/F_4
(23) PCLK_OZ129 4 32 NEW_CLKREQ# (28)
PCI2/TME SRC11#/CR#_G
C234 27p_4 CG_XIN R308 10K_4 PCI_CLK_SIO_R 5 30 CLK_PCIE_NEW_R RP41 3 4 0X2
PCI3 SRC9 CLK_PCIE_NEW_R# CLK_PCIE_NEW (28)
SRC9#
31 1 2 CLK_PCIE_NEW# (28) To New Card
2

Y3 PCLK_591 R309 33_4 PCLK_591_R 6

(29) PCLK_591 PCI4/SRC5_EN CLK_PCIE_MINI2_R
CL=20p SRC7/CR#_F
44 RP37 1 2 0X2 CLK_PCIE_MINI2 (25)
14.318MHZ PCLK_ICH R310 33_4 PCLK_ICH_R 7 43 CLK_PCIE_MINI2#_R 3 4 To MINI2
(15) PCLK_ICH PCIF5/ITP_EN SRC7#/CR#_E CLK_PCIE_MINI2# (25)
1

C258 27p_4 CG_XOUT CG_XIN 60 41 CLK_PCIE_MINI_R RP38 1 2 0X2

XTAL_IN SRC6 CLK_PCIE_MINI#_R CLK_PCIE_MINI (25)
SRC6#
40 3 4 CLK_PCIE_MINI# (25) To WLAN
CG_XOUT 59
XTAL_OUT CLK_PCIE_LAN_R RP40
27 3 4 0X2 CLK_PCIE_LAN (24)
FSA SRC4 CLK_PCIE_LAN#_R
(16) CLKUSB_48
R316 33_4 10
USB_48/FSA SRC4#
28 1 2 CLK_PCIE_LAN# (24) To LAN
C
10/30 Change Value and need change PN C
CLK_BSEL0 R311 2.2K_4 FSB 57 24 CLK_PCIE_ICH_R RP42 3 4 0X2
FSB/TEST/MODE SRC3/CR#_C CLK_PCIE_ICH#_R CLK_PCIE_ICH (15)
SRC3#/CR#_D
25 1 2 CLK_PCIE_ICH# (15) To SB
FSC 62
CLK_BSEL1 REF0/FSC/TESTSEL CLK_PCIE_SATA_R RP45
21 3 4 0X2 CLK_PCIE_SATA (14)
SRC2/SATA CLK_PCIE_SATA#_R
8
VSS_PCI SRC2#/SATA#
22 1 2 CLK_PCIE_SATA# (14) To SB
11
CLK_BSEL2 R245 10K_4 VSS_48 DREFSSCLK_R
15 17
VSS_IO SRC1/SE1 DREFSSCLK#_R
19 18
R246 33_4 VSS_PLL3 SRC1#/SE2
(16) 14M_ICH 52
VSS_CPU DREFCLK_R RP43
23 13 3 4 IV@0X2 DREFCLK (6)
VSS_SRC1 SRC0/DOT96 DREFCLK#_R
29
VSS_SRC2 SRC0#/DOT96#
14 1 2 DREFCLK# (6) To NB
42
VSS_SRC3
58 56 CK_PWRGD (16)
VSS_REF CKPWRGD/PWRDWN#
ICS9LPRS365BGLFT

ICS9LPRS365 RTM875T-606 R318 10K_4 PCLK_OZ129 <MAIN>:ICS9LPRS365BGLFT QCI:ALPRS365K13

+3V
(ALPRS365K13) (AL000875K06) PULL HIGH PULL DOWN
<SECOND>:SLG8SP512TTR: QCI:AL8SP512K05
PCI2/TME R319 *10K_4
Pin 4 PCI2/TME internal PD NO OVERCLOCKING (default) NORMAL RUN

PCI-3/SRC5_EN PIN37/38 IS
Pin 5 PCI-3 internal PD PIN37/38 IS SRC5 PCI_STOP/CPU_STOP (default) R325 *10K_4 PCLK_591 DREFSSCLK_R RP44 1 2 IV@0X2
+3V DREFSSCLK (6)
HIGH 27MHz DREFSSCLK#_R 3 4 To NB
PCI-4/27M_SEL PIN 17/18 LOW SRC DREFSSCLK# (6)
Pin 6 PCI-4/27M_SEL internal PD PIN 17/18 IS 27MHz IS SRC/DOT (default) R321 10K_4
3 4 CLK_MXM (19)
PCIF-5/ITP_EN 1 2 To VGA Card
Pin 7 PCIF-5/ITP_EN internal PD PIN 46/47 IS CPUITP PIN 46/47 IS SRC8 (default) PCLK_ICH RP47 EV@0X2 CLK_MXM# (19)
+3V R326 *10K_4

R317 10K_4

B B

+3V

FREQ. SEL
TABLE Clock Gen Q19 R254
I2C 11/01 Del C3195

2
R331 0_4 CLK_BSEL0 RHU002N06 10K_4
(3) CPU_BSEL0 MCH_BSEL0 (6)
3 1 CGDAT_SMB
(16,21,25,28) SDATA CGDAT_SMB (13)
+1.05V R327 *56_4

PCLK_591 C291 *33p/50V_4

BSEL Frequency Select Table R322 1K_4 +3V

FSC FSB FSA Frequency CLKUSB_48 C293 *33p/50V_4

0 0 0 266Mhz Q21 R253 14M_ICH C231 *33p/50V_4

R241 0_4 CLK_BSEL1
(3) CPU_BSEL1 MCH_BSEL1 (6)

2
RHU002N06 10K_4
0 0 1 133Mhz PCLK_ICH C300 *33p/50V_4
R255 *0_4 3 1 CGCLK_SMB
(16,21,25,28) SCLK CGCLK_SMB (13)
A PCLK_DEBUG C269 *33p/50V_4 A
0 1 1 166Mhz
+1.05V R240 1K_4

0 1 0 200Mhz

1 1 0 400Mhz R242 0_4 CLK_BSEL2

(3) CPU_BSEL2 MCH_BSEL2 (6)

1 1 1 Reserved R244 *0_4

Quanta Computer Inc.
1 0 1 100Mhz R243 1K_4
+1.05V PROJECT : BL5M Montevina
Size Document Number Rev
1A
1 0 0 333Mhz CLK. GEN./ CK505
Date: Monday, March 10, 2008 Sheet 2 of 37
5 4 3 2 1

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 5 4 3 2 1

(5) H_A#[3..16] H_D#[0..63]

BOM Option Table
U24A
H_A#3 H_ADS# H_D#[0..63] (5)
J4 A[3]# ADS# H1 H_ADS# (5) Reference Description

ADDR GROUP_0
H_A#4 L5 E2 H_BNR#
A[4]# BNR# H_BNR# (5)
H_A#5 L4 G5 H_BPRI#
H_A#6 A[5]# BPRI# H_BPRI# (5) N/A N/A
K5 U24B
H_A#7 A[6]# H_DEFER#
M3 A[7]# DEFER# H5 H_DEFER# (5)
H_A#8 N2 F21 H_DRDY# H_D#0 E22 Y22 H_D#32
A[8]# DRDY# H_DRDY# (5) D[0]# D[32]#
H_A#9 J1 E1 H_DBSY# H_D#1 F24 AB24 H_D#33
A[9]# DBSY# H_DBSY# (5) D[1]# D[33]#
H_A#10 N3 H_D#2 E26 V24 H_D#34
A[10]# D[2]# D[34]#

DATA GRP 0
H_A#11 P5 F1 H_BREQ# ZS2 Default no use this function H_D#3 G22 V26 H_D#35
A[11]# BR0# H_BREQ# (5) D[3]# D[35]#

DATA GRP 2
H_A#12 P2 H_D#4 F23 V23 H_D#36
A[12]# D[4]# D[36]#

CONTROL
H_A#13 L2 D20 H_IERR# R472 56_4 H_D#5 G25 T22 H_D#37
A[13]# IERR# +1.05V D[5]# D[37]#
H_A#14 P4 B3 H_INIT# H_D#6 E25 U25 H_D#38
A[14]# INIT# H_INIT# (14) D[6]# D[38]#
H_A#15 P1 H_D#7 E23 U23 H_D#39
H_A#16 A[15]# H_LOCK# H_D#8 D[7]# D[39]# H_D#40
R1 H4 H_LOCK# (5) K24 Y25
H_ADSTB#0 A[16]# LOCK# H_D#9 D[8]# D[40]# H_D#41
D (5) H_ADSTB#0 M1
ADSTB[0]# 11/01 Modify G24
D[9]# D[41]#
W22 D
C1 H_CPURST# H_D#10 J24 Y23 H_D#42
(5) H_REQ#[0..4] RESET# H_CPURST# (5) D[10]# D[42]#
H_REQ#0 K3 F3 H_RS#0 H_D#11 J23 W24 H_D#43
REQ[0]# RS[0]# H_RS#0 (5) D[11]# D[43]#
H_REQ#1 H2 F4 H_RS#1 H_D#12 H22 W25 H_D#44
REQ[1]# RS[1]# H_RS#1 (5) D[12]# D[44]#
H_REQ#2 K2 G3 H_RS#2 H_D#13 F26 AA23 H_D#45
REQ[2]# RS[2]# H_RS#2 (5) D[13]# D[45]#
H_REQ#3 J3 G2 H_TRDY# H_D#14 K22 AA24 H_D#46
H_REQ#4 REQ[3]# TRDY# H_TRDY# (5) H_D#15 D[14]# D[46]# H_D#47
L1 H23 AB25
REQ[4]# H_HIT# H_DSTBN#0 D[15]# D[47]# H_DSTBN#2
(5) H_A#[17..35] G6 H_HIT# (5) (5) H_DSTBN#0 J26 Y26 H_DSTBN#2 (5)
H_A#17 HIT# H_HITM# H_DSTBP#0 DSTBN[0]# DSTBN[2]# H_DSTBP#2
Y2 E4 H_HITM# (5) (5) H_DSTBP#0 H26 AA26 H_DSTBP#2 (5)
H_A#18 A[17]# HITM# H_DINV#0 DSTBP[0]# DSTBP[2]# H_DINV#2
U5 (5) H_DINV#0 H25 U22 H_DINV#2 (5)
H_A#19 A[18]# XDP_BPM#0 T56 DINV[0]# DINV[2]#
R3 AD4
A[19]# BPM[0]#

ADDR GROUP_1
H_A#20 W6 AD3 XDP_BPM#1 T57
H_A#21 A[20]# BPM[1]# XDP_BPM#2 T66 H_D#16 H_D#48
U4 AD1 N22 AE24
H_A#22 A[21]# BPM[2]# XDP_BPM#3 Connect it to CPU DBR# is for ITP debug port H_D#17 D[16]# D[48]# H_D#49
Y5
A[22]# BPM[3]#
AC4 T62 K25
D[17]# D[49]#
AD24 Quad Core

XDP/ITP SIGNALS
H_A#23 U1 AC2 XDP_BPM#4 T64 or CPU interposer (like ICE) to reset the system H_D#18 P26 AA21 H_D#50
H_A#24 A[23]# PRDY# XDP_BPM#5 H_D#19 D[18]# D[50]# H_D#51
R4
A[24]# PREQ#
AC1 T67 R23
D[19]# D[51]#
AB22 COMP0,COMP2 : 24.9 1% ohm
H_A#25 T5 AC5 XDP_TCK H_D#20 L23 AB21 H_D#52
A[25]# TCK D[20]# D[52]#

DATA GRP 1
H_A#26 T3 AA6 XDP_TDI H_D#21 M24 AC26 H_D#53 COMP1,COMP3 : 49.9 1% ohm
A[26]# TDI D[21]# D[53]#

DATA GRP 3
H_A#27 W2 AB3 XDP_TDO H_D#22 L22 AD20 H_D#54
H_A#28 A[27]# TDO XDP_TMS H_D#23 D[22]# D[54]# H_D#55
W5
A[28]# TMS
AB5 M23
D[23]# D[55]#
AE22 Dual Core
H_A#29 Y4 AB6 XDP_TRST# H_D#24 P25 AF23 H_D#56
H_A#30 A[29]# TRST# XDP_DBRESET# 0_4 SYS_RST# H_D#25 D[24]# D[56]# H_D#57
U2
A[30]# DBR#
C20 R467
SYS_RST# (16) 11/01 Modify P23
D[25]# D[57]#
AC25 COMP0,COMP2 : 27.4 1% ohm
H_A#31 V4 H_D#26 P22 AE21 H_D#58
H_A#32 A[31]# H_D#27 D[26]# D[58]# H_D#59
W3
A[32]# +1.05V
T24
D[27]# D[59]#
AD21 COMP1,COMP3 : 54.9 1% ohm
H_A#33 AA4 THERMAL Layout note: H_D#28 R24 AC22 H_D#60
H_A#34 A[33]# H_D#29 D[28]# D[60]# H_D#61
AB2 H_GTLREF: Zo=55 ohm,L<0.5" L25 AD23
H_A#35 A[34]# H_PROCHOT#_D H_D#30 D[29]# D[61]# H_D#62
AA3 D21 2/3*VCCP+-2% T25 AF22
H_ADSTB#1 A[35]# PROCHOT# H_THERMDA H_D#31 D[30]# D[62]# H_D#63
(5) H_ADSTB#1 V1
ADSTB[1]# THERMDA
A24 N25
D[31]# D[63]#
AC23 Layout note:
B25 H_THERMDC R57 H_DSTBN#1 L26 AE25 H_DSTBN#3
H_A20M# THERMDC (5) H_DSTBN#1
H_DSTBP#1 DSTBN[1]# DSTBN[3]# H_DSTBP#3
H_DSTBN#3 (5) comp0,2: Zo=27.4ohm, L<0.5"
(14) H_A20M# A6 1K/F_4 (5) H_DSTBP#1 M26 AF24 H_DSTBP#3 (5)
A20M# DSTBP[1]# DSTBP[3]# comp1,3: Zo=55ohm, L<0.5"
ICH

H_FERR# A5 C7 CPU_PM_THRMTRIP# H_DINV#1 N24 AC20 H_DINV#3

(14) H_FERR# H_IGNNE# FERR# THERMTRIP# (5) H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 (5)
(14) H_IGNNE# C4
IGNNE# H_GTLREF COMP0 R61 27.4/F_6
AD26 R26
R214 0_4 CPU_TEST1 GTLREF COMP[0] COMP1 R59 54.9/F_4
(14) H_STPCLK# D5
STPCLK# T18 C23
TEST1 MISC COMP[1]
U26
H_INTR C6 H CLK +1.05V CPU_TEST2 D25 AA1 COMP2 R200 27.4/F_6
(14) H_INTR LINT0 T14 TEST2 COMP[2]
H_NMI B4 A22 CLK_CPU_BCLK R58 CPU_TEST3 C24 Y1 COMP3 R201 54.9/F_4
(14) H_NMI H_SMI# LINT1 BCLK[0] CLK_CPU_BCLK# CLK_CPU_BCLK (2) T13 CPU_TEST4 TEST3 COMP[3]
C
(14) H_SMI# A3 A21 CLK_CPU_BCLK# (2) 2K/F_4 T16 AF26 C
SMI# BCLK[1] CPU_TEST5 TEST4 ICH_DPRSTP#
12/22 REV_2A Add T65 AF1
TEST5 DPRSTP#
E5 ICH_DPRSTP# (6,14,32)
T59 M4 R412 CPU_TEST6 A26 B5 H_DPSLP#
RSVD[01] +3V T113 TEST6 DPSLP# H_DPSLP# (14)
T58 N5 *1K/F_4 CPU_TEST7 C3 D24 H_DPWR#
RSVD[02] T55 TEST7 DPWR# H_DPWR# (5)
T61 T2 CPU_BSEL0 B22 D6 H_PWRGD
RSVD[03] (2) CPU_BSEL0 CPU_BSEL1 BSEL[0] PWRGOOD H_CPUSLP# H_PWRGD (14)
T60 V3 B23 D7
RSVD[04] +1.05V (2) CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# (5)
RESERVED

T132 B2 H_GTLREF2 CPU_BSEL2 C21 AE6 PSI#

RSVD[05] (2) CPU_BSEL2 BSEL[2] PSI# PSI# (32)
T133 D2 R101
T15 H_GTLREF2 RSVD[06] *100K/F_4 Penryn_1p0
D22
RSVD[07]

3
R654 *51/F_4 D3 R393
R637 *51/F_4 RSVD[08] R643
+1.05V F6 *2K/F_4
RSVD[09] *10K/F_4 Layout note:
2 ICH_DPRSTP# , Daisy Chain 12/22 REV_2A Del R215
12/22 REV_2A Add (SB>PowerIC>NB>CPU)

3
Q56
Penryn_1p0 GTLREF_CTL R653 *10K/F_4 2 Q27 *2N7002
(4) GTLREF_CTL
MMBT3904

1
1
11/01 Modify

Thermal Trip +1.05V +1.05V

XDP CPU Thermal monitor
11/01 Modify
3

+1.05V 11/01 Modify

+3V +3V +3V

2 Q41 R466 D30 Reserve 1K for XDP function +1.05V

(6,16,32) DELAY_VR_PWRGOOD
1

R213 R456 200_6 LM86VCC C428 0.1u/10V_4

FDV301N *10K_4 *BAS316 XDP_TDO R199 *51/F_4

2
11/01 Modify *51/F_4 XDP_TDI R197 56_4
B B
XDP_TMS R203 54.9/F_4 Q38 R446 R444
1

(29) 2ND_MBCLK 3 1
2

XDP_TCK R196 56_4 10K_4 10K_4

+1.05V H_CPURST# XDP_TRST# R202 56_4 RHU002N06 U22
R473 R462 H_THERMDA

2
1K_4 100K_6 2ND_MBCLK# 8 1
SCLK VCC
R478 12/22 REV_2A Del R212 3 1 2ND_MBDATA# 7 2 C430
(29) 2ND_MBDATA SDA DXP
Q40 10/23 Add
2

56.2/F_4 MMBT3904 Q37 RHU002N06 6 3 2200p/50V_4

ALERT# DXN
CPU_PM_THRMTRIP# 1 3 SYS_SHDN# 4 5 H_THERMDC
SYS_SHDN# (31) OVERT# GND

NS LM95245 PU this pin *MAX6657

R475 *0_4 PM_THRMTRIP#
PM_THRMTRIP# (6,14) +3V R442 10K_4 ADDRESS:
98H

CPU FAN (16) THERM_ALERT# R443 *0_4 THERM_ALERT#_R

No use Thermal trip CPU side still PU 56ohm.
Use Thermal trip can share PU at SB side 10/30 Add ESD solution.
CTRL +3V R453 10K_4

2
*VPORT_6
+3V R451 330_4

Processor D4

2
+3V

1
11/01 Modify
hot 10/14 Change reference to follow BL5S (31) SYS_SHDN# 3 1 THER_SHD#
2

+1.05V R435 Q39 MMBT3904

VPORT_6
No use PROCHOT CPU side still PU 56ohm. 10K_4
Use PROCHOT to optional receiver CPU side PU D29
1

68ohm and through isolat 2.2K ohm to receiver +5V FANSIG CN17
R468 (29) FANSIG
A side U1 A
56_4 C11 2.2u/6.3V_6 2 3 TH_FAN_POWER
VIN VO 1 U21
GND 5 2
R465 *2.2K_4 R7 0_4 1
/FON GND
6
3
2ND_MBDATA# 7
SDAT OVT
4 THER_SHD#
NS LM95245 : AL095245000
1

(19) SYSFANON# C416 C417 D3 C415 2ND_MBCLK#

7 8
GND SCLK
H_PROCHOT#_D R461 *0_4
H_PROCHOT# (32) (29) VFAN
4
VSET GND
8
10u/10V_8 0.01u/16V_4 VPORT_6 *0.01u/16V_4 LM86VCC ALERT
6 THERM_ALERT#_R
SCMC EMC1402 : AL001402000
1 VCC
G995 FAN_CON 2 H_THERMDA
FANPWR = 1.6*VSET DXP
2

5 3 H_THERMDC
12/18 REV_2A R415 DNI GND
LM95245
DXN Quanta Computer Inc.
PROJECT : BL5M Montevina
Size Document Number Rev
1A
CLK. GEN./ CK505
Date: Monday, March 10, 2008 Sheet 3 of 37
5 4 3 2 1

PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com

 5 4 3 2 1

BOM Option Table

Reference Description
N/A N/A

Need NC 20PCS 10u before A1 BOM released(A0 all stuff)

Place these parts reference Layout Note:

D to Intel demo board. VCC_CORE D
Inside CPU center cavity in 2 rows
U24D
A4 P6 VCC_CORE VCC_CORE
VSS[001] VSS[082]
A8 VSS[002] VSS[083] P21
A11 P24 U24C
VSS[003] VSS[084] +1.05V
A14 VSS[004] VSS[085] R2 A7 VCC[001] VCC[068] AB20 11/01 Modify
A16 VSS[005] VSS[086] R5 A9 VCC[002] VCC[069] AB7
A19 R22 C456 C479 C166 C478 C160 C475 C466 C142 C126 A10 AC7
VSS[006] VSS[087] VCC[003] VCC[070]
A23 VSS[007] VSS[088] R25 A12 VCC[004] VCC[071] AC9
AF2 T1 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 A13 AC12
VSS[008] VSS[089] VCC[005] VCC[072] C174 C107 C108
B6 VSS[009] VSS[090] T4 A15 VCC[006] VCC[073] AC13
B8 VSS[010] VSS[091] T23 A17 VCC[007] VCC[074] AC15
B11 T26 A18 AC17 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4
VSS[011] VSS[092] VCC_CORE VCC[008] VCC[075]
B13 VSS[012] VSS[093] U3 A20 VCC[009] VCC[076] AC18
B16 VSS[013] VSS[094] U6 B7 VCC[010] VCC[077] AD7
B19 VSS[014] VSS[095] U21 B9 VCC[011] VCC[078] AD9
B21 VSS[015] VSS[096] U24 B10 VCC[012] VCC[079] AD10
B24 VSS[016] VSS[097] V2 B12 VCC[013] VCC[080] AD12 11/01 Modify +1.05V
C5 VSS[017] VSS[098] V5 B14 VCC[014] VCC[081] AD14
C8 VSS[018] VSS[099] V22 B15 VCC[015] VCC[082] AD15
C11 V25 C454 C159 C127 C153 C477 C476 C117 C161 C128 B17 AD17
VSS[019] VSS[100] VCC[016] VCC[083]
C14 VSS[020] VSS[101] W1 B18 VCC[017] VCC[084] AD18
C16 W4 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 B20 AE9
VSS[021] VSS[102] VCC[018] VCC[085] C172 C173 C106
C19 VSS[022] VSS[103] W23 C9 VCC[019] VCC[086] AE10
C2 VSS[023] VSS[104] W26 C10 VCC[020] VCC[087] AE12
C22 Y3 C12 AE13 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4
VSS[024] VSS[105] VCC_CORE VCC[021] VCC[088]
C25 VSS[025] VSS[106] Y6 C13 VCC[022] VCC[089] AE15
D1 VSS[026] VSS[107] Y21 C15 VCC[023] VCC[090] AE17
D4 VSS[027] VSS[108] Y24 C17 VCC[024] VCC[091] AE18
D8 VSS[028] VSS[109] AA2 C18 VCC[025] VCC[092] AE20
C
D11 VSS[029] VSS[110] AA5 D9 VCC[026] VCC[093] AF9 C
D13 VSS[030] VSS[111] AA8 D10 VCC[027] VCC[094] AF10 11/01 Del R3033
D16 VSS[031] VSS[112] AA11 D12 VCC[028] VCC[095] AF12
D19 AA14 C455 C452 C141 C146 C481 C165 C140 C162 C453 D14 AF14
VSS[032] VSS[113] VCC[029] VCC[096]
D23 VSS[033] VSS[114] AA16 D15 VCC[030] VCC[097] AF15
D26 AA19 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 D17 AF17 +1.05V
VSS[034] VSS[115] VCC[031] VCC[098]
E3 VSS[035] VSS[116] AA22 D18 VCC[032] VCC[099] AF18
E6 VSS[036] VSS[117] AA25 E7 VCC[033] VCC[100] AF20
E8 VSS[037] VSS[118] AB1 E9 VCC[034]
E11 AB4 VCC_CORE E10 G21 CPU_G21 R121 0_4
VSS[038] VSS[119] VCC[035] VCCP[01]
E14 VSS[039] VSS[120] AB8 E12 VCC[036] VCCP[02] V6
E16 VSS[040] VSS[121] AB11 E13 VCC[037] VCCP[03] J6
E19 AB13 E15 K6 + C462
VSS[041] VSS[122] VCC[038] VCCP[04] VCCP Bulk CAP
E21 VSS[042] VSS[123] AB16 E17 VCC[039] VCCP[05] M6
E24 AB19 E18 J21 270u/2V_7343 close to Pin
VSS[043] VSS[124] VCC[040] VCCP[06]
F5 VSS[044] VSS[125] AB23 E20 VCC[041] VCCP[07] K21
CTL F8 AB26 C470 C468 C480 C450 C464 C467 C465 C469 C451 F7 M21
VSS[045] VSS[126] VCC[042] VCCP[08]
F11 VSS[046] VSS[127] AC3 F9 VCC[043] VCCP[09] N21
F13 AC6 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 10u/10V_8 F10 N6
VSS[047] VSS[128] VCC[044] VCCP[10]
F16 VSS[048] VSS[129] AC8 F12 VCC[045] VCCP[11] R21
F19 VSS[049] VSS[130] AC11 F14 VCC[046] VCCP[12] R6
F2 VSS[050] VSS[131] AC14 F15 VCC[047] VCCP[13] T21
F22 AC16 F17 T6 +1.5V
VSS[051] VSS[132] VCC[048] VCCP[14]
F25 VSS[052] VSS[133] AC19 F18 VCC[049] VCCP[15] V21
G4 AC21 VCC_CORE F20 W21
VSS[053] VSS[134] VCC[050] VCCP[16]
G1 VSS[054] VSS[135] AC24 AA7 VCC[051]
G23 AD2 AA9 B26 +VCCA_PROC R53 0_6
VSS[055] VSS[136] VCC[052] VCCA[01]
G26 VSS[056] VSS[137] AD5 AA10 VCC[053] VCCA[02] C26
H3 VSS[057] VSS[138] AD8 AA12 VCC[054]
H6 AD11 C138 C137 VCC_CORE Bulk CAPs place AA13 AD6 H_VID0 (32)
C58 C56
VSS[058] VSS[139] + + VCC[055] VID[0]
H21 VSS[059] VSS[140] AD13 to BOT of CPU centeral AA15 VCC[056] VID[1] AF5 H_VID1 (32)
B H24 AD16 330u/2.5V_7343 330u/2.5V_7343 AA17 AE5 0.01u/16V_4 10u/10V_8 B
VSS[060] VSS[141] VCC[057] VID[2] H_VID2 (32) Place 0.01u
J2 VSS[061] VSS[142] AD19 AA18 VCC[058] VID[3] AF4 H_VID3 (32)
J5 AD22 AA20 AE3 H_VID4 (32)
near pin-B26
VSS[062] VSS[143] VCC[059] VID[4]
J22 VSS[063] VSS[144] AD25 AB9 VCC[060] VID[5] AF3 H_VID5 (32)
J25 VSS[064] VSS[145] AE1 AC10 VCC[061] VID[6] AE2 H_VID6 (32)
K1 VSS[065] VSS[146] AE4 12/18 REV_2A Add C137,C138 AB10 VCC[062]
K4 VSS[066] VSS[147] AE8 AB12 VCC[063]
K23 VSS[067] VSS[148] AE11 AB14 VCC[064] VCCSENSE AF7
K26 AE14 CTL R656 *0_4 GTLREF_CTL AB15
VSS[068] VSS[149] GTLREF_CTL (3) VCC[065]
L3 VSS[069] VSS[150] AE16 AB17 VCC[066]
L6 AE19 R657 0_4 AB18 AE7
VSS[070] VSS[151] VCC[067] VSSSENSE VCC_CORE
L21 VSS[071] VSS[152] AE23
L24 AE26 12/22 REV_2A Add R657 Penryn_1p0
VSS[072] VSS[153]
M2 VSS[073] VSS[154] A2 .
M5 AF6 R161
Penryn CPU Power Status and max current table
VSS[074] VSS[155]
M22 VSS[075] VSS[156] AF8
M25 AF11 100/F_6
VSS[076] VSS[157]
N1 VSS[077] VSS[158] AF13 POWER PLANE S0 S3 S4/S5 Voltage I(max) Note
N4 VSS[078] VSS[159] AF16
N23 VSS[079] VSS[160] AF19 VCC_CORE O X X VID 47A Standard Voltage CPU VCCSENSE (32)
N26 VSS[080] VSS[161] AF21
P3 VSS[081] VSS[162] A25 VCC_CORE O X X VID 50A SV Design Target VSSSENSE (32)
VSS[163] AF25
VCC_CORE O X X VID TBD Extreme Edition CPU
Penryn_1p0 R155 Layout Note:
. VCC_CORE O X X VID 67A EE Design Target Route VCCSENSE and VSSSENSE traces at
100/F_6 27.4 Ohms with 50 mil spacing.
VCCA O X X +1.5V 130mA Place PU and PD within 1 inch of CPU.

VCCP O X X +1.05V 4.5A Before VCC Stable

A A
VCCP O X X +1.05V 2.5A After VCC Stable

(See Penryn EMTS Rev:1.0 Table7,8 for voltage and current)

(See Penryn EMTS Rev:1.0 Table-3 for VID table)
Quanta Computer Inc.
PROJECT : BL5M Montevina
Size Document Number Rev
1A
CLK. GEN./ CK505
Date: Monday, March 10, 2008 Sheet 4 of 37
5 4 3 2 1

PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com

 5 4 3 2 1

BOM Option Table

Reference Description
N/A N/A
H_A#[35..3] (3)
U23A
(3) H_D#[63..0]
A14 H_A#3
H_D#0 H_A#_3 H_A#4
F2 H_D#_0 H_A#_4 C15
H_D#1 G8 F16 H_A#5
H_D#2 H_D#_1 H_A#_5 H_A#6
F8 H_D#_2 H_A#_6 H13
D H_D#3 E6 C18 H_A#7 D
H_D#4 H_D#_3 H_A#_7 H_A#8
G2 H_D#_4 H_A#_8 M16
H_D#5 H6 J13 H_A#9
H_D#6 H_D#_5 H_A#_9 H_A#10
H2 H_D#_6 H_A#_10 P16
H_D#7 F6 R16 H_A#11
H_D#8 H_D#_7 H_A#_11 H_A#12
D4 H_D#_8 H_A#_12 N17
H_D#9 H3 M13 H_A#13
H_D#10 H_D#_9 H_A#_13 H_A#14
M9 H_D#_10 H_A#_14 E17
H_D#11 M11 P17 H_A#15
H_D#12 H_D#_11 H_A#_15 H_A#16
J1 H_D#_12 H_A#_16 F17
11/01 Modify H_D#13 J2 G20 H_A#17
H_D#14 H_D#_13 H_A#_17 H_A#18
N12 H_D#_14 H_A#_18 B19
H_D#15 J6 J16 H_A#19
H_D#16 H_D#_15 H_A#_19 H_A#20
P2 H_D#_16 H_A#_20 E20
H_D#17 L2 H16 H_A#21
+1.05V H_D#18 H_D#_17 H_A#_21 H_A#22
0.3125*VCCP R2 H_D#_18 H_A#_22 J20
W:10,S:20 , L<0.5" H_D#19 N9 L17 H_A#23
H_D#20 H_D#_19 H_A#_23 H_A#24
L6 H_D#_20 H_A#_24 A17
H_D#21 M5 B17 H_A#25
H_D#22 H_D#_21 H_A#_25 H_A#26
J3 H_D#_22 H_A#_26 L16
R441 H_D#23 N2 C21 H_A#27
H_D#24 H_D#_23 H_A#_27 H_A#28
R1 H_D#_24 H_A#_28 J17
221/F_4 H_D#25 N5 H20 H_A#29
H_D#26 H_D#_25 H_A#_29 H_A#30
N6 H_D#_26 H_A#_30 B18
H_SWING H_D#27 P13 K17 H_A#31
H_D#28 H_D#_27 H_A#_31 H_A#32
N8 H_D#_28 H_A#_32 B20
C H_D#29 L7 F21 H_A#33 C
R440 C423 H_D#30 H_D#_29 H_A#_33 H_A#34
N10 H_D#_30 H_A#_34 K21
H_D#31 M3 L20 H_A#35
100/F_4 0.1u/10V_4 H_D#32 H_D#_31 H_A#_35
Y3 H_D#_32
H_D#33 AD14 H12 H_ADS#
H_D#_33 H_ADS# H_ADS# (3)
H_D#34 Y6 B16 H_ADSTB#0
H_D#_34 H_ADSTB#_0 H_ADSTB#0 (3)
H_D#35 Y10 G17 H_ADSTB#1
H_D#_35 H_ADSTB#_1 H_ADSTB#1 (3)
H_D#36 Y12 A9 H_BNR#
H_D#_36 H_BNR# H_BNR# (3)
H_D#37 Y14 F11 H_BPRI#
H_D#_37 H_BPRI# H_BPRI# (3)
H_D#38 Y7 G12 H_BREQ#

HOST
H_D#_38 H_BREQ# H_BREQ# (3)
H_D#39 W2 E9 H_DEFER#
H_D#_39 H_DEFER# H_DEFER# (3)
H_D#40 AA8 B10 H_DBSY#
H_D#_40 H_DBSY# H_DBSY# (3)
H_D#41 Y9 AH7 CLK_MCH_BCLK
H_D#_41 HPLL_CLK CLK_MCH_BCLK (2)
W:10,S:20 , L<0.5" H_D#42 AA13 AH6 CLK_MCH_BCLK#
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# (2)
H_D#43 AA9 J11 H_DPWR#
H_D#_43 H_DPWR# H_DPWR# (3)
H_D#44 AA11 F9 H_DRDY#
H_D#_44 H_DRDY# H_DRDY# (3)
H_D#45 AD11 H9 H_HIT#
H_D#_45 H_HIT# H_HIT# (3)
H_D#46 AD10 E12 H_HITM#
H_D#_46 H_HITM# H_HITM# (3)
H_RCOMP H_D#47 AD13 H11 H_LOCK#
H_D#_47 H_LOCK# H_LOCK# (3)
H_D#48 AE12 C9 H_TRDY#
H_D#_48 H_TRDY# H_TRDY# (3)
H_D#49 AE9
R45 H_D#50 H_D#_49
AA2 H_D#_50
H_D#51 AD8
24.9/F_4 H_D#52 H_D#_51
AA3 H_D#_52 H_DINV#[3..0] (3)
H_D#53 AD3 J8 H_DINV#0
H_D#54 H_D#_53 H_DINV#_0 H_DINV#1
AD7 H_D#_54 H_DINV#_1 L3
B H_D#55 AE14 Y13 H_DINV#2 B
H_D#56 H_D#_55 H_DINV#_2 H_DINV#3
AF3 H_D#_56 H_DINV#_3 Y1
H_D#57 AC1 H_D#_57 H_DSTBN#[3..0] (3)
H_D#58 AE3 L10 H_DSTBN#0
H_D#59 H_D#_58 H_DSTBN#_0 H_DSTBN#1
AC3 H_D#_59 H_DSTBN#_1 M7
11/01 Modify H_D#60 AE11 AA5 H_DSTBN#2
H_D#61 H_D#_60 H_DSTBN#_2 H_DSTBN#3
AE8 H_D#_61 H_DSTBN#_3 AE6
H_D#62 AG2 H_D#_62 H_DSTBP#[3..0] (3)
H_D#63 AD6 L9 H_DSTBP#0
+1.05V H_D#_63 H_DSTBP#_0 H_DSTBP#1
2/3*VCCP H_DSTBP#_1 M8
W:10,S:20 , L<0.5" AA6 H_DSTBP#2
H_SWING H_DSTBP#_2 H_DSTBP#3
C5 H_SWING H_DSTBP#_3 AE5
H_RCOMP E3 H_RCOMP H_REQ#[4..0] (3)
R447 B15 H_REQ#0
H_REQ#_0 H_REQ#1
H_REQ#_1 K13
1K/F_4 F13 H_REQ#2
H_REQ#_2 H_REQ#3
H_REQ#_3 B13
H_AVREF H_CPURST# C12 B14 H_REQ#4
(3) H_CPURST# H_CPURST# H_REQ#_4
H_CPUSLP# E11
(3) H_CPUSLP# H_CPUSLP# H_RS#[2..0] (3)
B6 H_RS#0
R448 R449 0_4 H_DVREF H_RS#_0 H_RS#1
H_RS#_1 F12
C8 H_RS#2
2K/F_4 H_AVREF H_RS#_2
A11 H_AVREF
H_DVREF B11 H_DVREF
CANTIGA_1p2
A A

Quanta Computer Inc.

PROJECT : BL5M Montevina
Size Document Number Rev
1A
CLK. GEN./ CK505
Date: Monday, March 10, 2008 Sheet 5 of 37
5 4 3 2 1

PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com

 5 4 3 2 1

BOM Option Table

U23B
Reference Description

MCH_RSVD1
IV@ INT VGA
T42 M36
MCH_RSVD2 RSVD1 M_CLK_DDR0
N36 AP24 EV@ EXT VGA

DDR CLK/ CONTROL/COMPENSATION

T34 RSVD2 SA_CK_0 M_CLK_DDR0 (13)
MCH_RSVD3 R33 AT21 M_CLK_DDR1
T33 RSVD3 SA_CK_1 M_CLK_DDR1 (13)
MCH_RSVD4 T33 AV24 M_CLK_DDR3
T44
MCH_RSVD5 RSVD4 SB_CK_0 M_CLK_DDR4
M_CLK_DDR3 (13) IHM@ INT HDMI
T9 AH9 AU20 M_CLK_DDR4 (13)
MCH_RSVD6 RSVD5 SB_CK_1
T11 AH10 EV_IV@ EV&IV diff. value
MCH_RSVD7 RSVD6 M_CLK_DDR#0
T12 AH12 AR24 M_CLK_DDR#0 (13)
MCH_RSVD8 RSVD7 SA_CK#_0 M_CLK_DDR#1
T17 AH13 AR21 M_CLK_DDR#1 (13)
MCH_RSVD9 RSVD8 SA_CK#_1 M_CLK_DDR#3
T10 K12 AU24 M_CLK_DDR#3 (13)
RSVD9 SB_CK#_0 M_CLK_DDR#4
AV20 M_CLK_DDR#4 (13)
SB_CK#_1
BC28 M_CKE0
SA_CKE_0 M_CKE0 (12,13)
AY28 M_CKE1 U23C
SA_CKE_1 M_CKE1 (12,13)
MCH_RSVD14 T24 AY36 M_CKE3 L<0.5" , If PCIE not support
T27 RSVD14 SB_CKE_0 M_CKE3 (12,13) +1.05V_VCC_PEG
BB36 M_CKE4 LVDS I/F still connect to +VCC_PEG
SB_CKE_1 M_CKE4 (12,13)

RSVD
D MCH_RSVD15 B31 D
T32 RSVD15
BA17 M_CS#0 INT_LVDS_PWM L32
SA_CS#_0 M_CS#0 (12,13) (18) INT_LVDS_PWM L_BKLT_CTRL
MCH_RSVD17 M1 AY16 M_CS#1 INT_LVDS_BLON G32 T37 EXP_A_COMPX R150 49.9/F_4
T5 RSVD17 SA_CS#_1 M_CS#1 (12,13) (18) INT_LVDS_BLON L_BKLT_EN PEG_COMPI
AV16 M_CS#2 L_CTRL_CLK M32 T36
SB_CS#_0 M_CS#2 (12,13) L_CTRL_CLK PEG_COMPO
AR13 M_CS#3
SB_CS#_1 M_CS#3 (12,13)
MCH_RSVD20 AY21 L_CTRL_DATA M33
T25 RSVD20 L_CTRL_DATA
BD17 M_ODT0 INT_LVDS_EDIDCLK K33 H44 PEG_RXN0
SA_ODT_0 M_ODT0 (12,13) (18) INT_LVDS_EDIDCLK L_DDC_CLK PEG_RX#_0 PEG_RXN0 (19)
AY17 M_ODT1 INT_LVDS_EDIDDATA J33 J46 PEG_RXN1
SA_ODT_1 M_ODT1 (12,13) (11,18) INT_LVDS_EDIDDATA L_DDC_DATA PEG_RX#_1 PEG_RXN1 (19)
MCH_RSVD21 B2 BF15 M_ODT2 L44 PEG_RXN2
T6 RSVD21 SB_ODT_0 M_ODT2 (12,13) PEG_RX#_2 PEG_RXN2 (19)
MCH_RSVD22 BG23 AY13 M_ODT3 L40 PEG_RXN3
T116 RSVD22 SB_ODT_1 M_ODT3 (12,13) PEG_RX#_3 PEG_RXN3 (19)
MCH_RSVD23 BF23 INT_LVDS_DIGON M29 N41 PEG_RXN4
T26 RSVD23 (18) INT_LVDS_DIGON L_VDD_EN PEG_RX#_4 PEG_RXN4 (19)
MCH_RSVD24 BH18 BG22 M_RCOMP LVDS_IBG C44 P48 PEG_RXN5
T114 RSVD24 SM_RCOMP LVDS_IBG PEG_RX#_5 PEG_RXN5 (19)
MCH_RSVD25 BF18 BH21 M_RCOMP# LVDS_VBG B43 N44 PEG_RXN6
T115 RSVD25 SM_RCOMP# T51 LVDS_VBG PEG_RX#_6 PEG_RXN6 (19)
LVDS_VREFH E37 T43 PEG_RXN7
LVDS_VREFH PEG_RX#_7 PEG_RXN7 (19)
BF28 SM_RCOMP_VOH LVDS_VREFL E38 U43 PEG_RXN8
SM_RCOMP_VOH LVDS_VREFL PEG_RX#_8 PEG_RXN8 (19)

LVDS
BH28 SM_RCOMP_VOL INT_TXLCLKOUT- C41 Y43 PEG_RXN9
SM_RCOMP_VOL (18) INT_TXLCLKOUT- LVDSA_CLK# PEG_RX#_9 PEG_RXN9 (19)
INT_TXLCLKOUT+ C40 Y48 PEG_RXN10
(18) INT_TXLCLKOUT+ LVDSA_CLK PEG_RX#_10 PEG_RXN10 (19)
AV42 SM_VREF INT_TXUCLKOUT- B37 Y36 PEG_RXN11
SM_VREF (18) INT_TXUCLKOUT- LVDSB_CLK# PEG_RX#_11 PEG_RXN11 (19)
AR36 SM_PWROK INT_TXUCLKOUT+ A37 AA43 PEG_RXN12
SM_PWROK (18) INT_TXUCLKOUT+ LVDSB_CLK PEG_RX#_12 PEG_RXN12 (19)
BF17 SM_REXT SM_DRAMRST# only for AD37 PEG_RXN13
SM_REXT PEG_RX#_13 PEG_RXN13 (19)
BC36 MCH_SM_DRAMRST# DDR3.(DDR2 NC). INT_TXLOUT0- H47 AC47 PEG_RXN14
SM_DRAMRST# T38 (18) INT_TXLOUT0- LVDSA_DATA#_0 PEG_RX#_14 PEG_RXN14 (19)
INT_TXLOUT1- E46 AD39 PEG_RXN15
(18) INT_TXLOUT1- LVDSA_DATA#_1 PEG_RX#_15 PEG_RXN15 (19)
B38 DREFCLK INT_TXLOUT2- G40
DPLL_REF_CLK DREFCLK (2) (18) INT_TXLOUT2- LVDSA_DATA#_2
A38 DREFCLK# INT_TXLOUT3- A40 H43 PEG_RXP0
DPLL_REF_CLK# DREFCLK# (2) T122 LVDSA_DATA#_3 PEG_RX_0 PEG_RXP0 (19)
DREFSSCLK PEG_RXP1

GRAPHICS
DPLL_REF_SSCLK E41 DREFSSCLK (2) PEG_RX_1 J44 PEG_RXP1 (19)
F41 DREFSSCLK# INT_TXLOUT0+ H48 L43 PEG_RXP2
DPLL_REF_SSCLK# DREFSSCLK# (2) (18) INT_TXLOUT0+ LVDSA_DATA_0 PEG_RX_2 PEG_RXP2 (19)
INT_TXLOUT1+ D45 L41 PEG_RXP3
(18) INT_TXLOUT1+ LVDSA_DATA_1 PEG_RX_3 PEG_RXP3 (19)

ME JTAG
F43 CLK_PCIE_3GPLL INT_TXLOUT2+ F40 N40 PEG_RXP4

CLK
PEG_CLK CLK_PCIE_3GPLL (2) (18) INT_TXLOUT2+ LVDSA_DATA_2 PEG_RX_4 PEG_RXP4 (19)
JTAG_TCK AL34 E43 CLK_PCIE_3GPLL# INT_TXLOUT3+ B40 P47 PEG_RXP5
T37 ME_JTAG_TCK PEG_CLK# CLK_PCIE_3GPLL# (2) T123 LVDSA_DATA_3 PEG_RX_5 PEG_RXP5 (19)
N43 PEG_RXP6
PEG_RX_6 PEG_RXP6 (19)
JTAG_TDI AK34 INT_TXUOUT0- A41 T42 PEG_RXP7
T39 ME_JTAG_TDI (18) INT_TXUOUT0- LVDSB_DATA#_0 PEG_RX_7 PEG_RXP7 (19)
INT_TXUOUT1- H38 U42 PEG_RXP8
DMI_TXN[3:0] (15) (18) INT_TXUOUT1- LVDSB_DATA#_1 PEG_RX_8 PEG_RXP8 (19)
JTAG_TDO AN35 AE41 DMI_TXN0 INT_TXUOUT2- G37 Y42 PEG_RXP9
T45 ME_JTAG_TDO DMI_RXN_0 (18) INT_TXUOUT2- LVDSB_DATA#_2 PEG_RX_9 PEG_RXP9 (19)
AE37 DMI_TXN1 INT_TXUOUT3- J37 W47 PEG_RXP10
DMI_RXN_1 T49 LVDSB_DATA#_3 PEG_RX_10 PEG_RXP10 (19)
JTAG_TMS AM35 AE47 DMI_TXN2 Y37 PEG_RXP11
T47 ME_JTAG_TMS DMI_RXN_2 PEG_RX_11 PEG_RXP11 (19)
AH39 DMI_TXN3 INT_TXUOUT0+ B42 AA42 PEG_RXP12
DMI_RXN_3 (18) INT_TXUOUT0+ LVDSB_DATA_0 PEG_RX_12 PEG_RXP12 (19)
INT_TXUOUT1+ G38 AD36 PEG_RXP13
DMI_TXP[3:0] (15) (18) INT_TXUOUT1+ LVDSB_DATA_1 PEG_RX_13 PEG_RXP13 (19)
AE40 DMI_TXP0 INT_TXUOUT2+ F37 AC48 PEG_RXP14
DMI_RXP_0 (18) INT_TXUOUT2+ LVDSB_DATA_2 PEG_RX_14 PEG_RXP14 (19)
MCH_BSEL0 T25 AE38 DMI_TXP1 INT_TXUOUT3+ K37 AD40 PEG_RXP15

PCI-EXPRESS
(2) MCH_BSEL0 CFG_0 DMI_RXP_1 T48 LVDSB_DATA_3 PEG_RX_15 PEG_RXP15 (19)
MCH_BSEL1 R25 AE48 DMI_TXP2
(2) MCH_BSEL1 CFG_1 DMI_RXP_2
MCH_BSEL2 P25 AH40 DMI_TXP3 J41 C_PEG_TXN0_H C505 [email protected]/10V_4
(2) MCH_BSEL2 CFG_2 DMI_RXP_3 PEG_TX#_0 PEG_TXN0 (19)
MCH_CFG_3 P20 M46 C_PEG_TXN1_H C191 [email protected]/10V_4
T20 CFG_3 DMI_RXN[3:0] (15) PEG_TX#_1 PEG_TXN1 (19)
MCH_CFG_4 P24 AE35 DMI_RXN0 F25 M47 C_PEG_TXN2_H C500 [email protected]/10V_4
C T28 CFG_4 DMI_TXN_0 T54 TVA_DAC PEG_TX#_2 PEG_TXN2 (19) C
(11) MCH_CFG_5 MCH_CFG_5 C25 AE43 DMI_RXN1 INT_TV_Y/G H25 M40 C_PEG_TXN3_H C193 [email protected]/10V_4
CFG_5 DMI_TXN_1 (22) INT_TV_Y/G TVB_DAC PEG_TX#_3 PEG_TXN3 (19)
(11) MCH_CFG_6 MCH_CFG_6 N24 AE46 DMI_RXN2 INT_TV_C/R K25 M42 C_PEG_TXN4 C202 [email protected]/10V_4 PEG_TXN4
CFG_6 DMI_TXN_2 (22) INT_TV_C/R TVC_DAC PEG_TX#_4 PEG_TXN4 (19)

TV
(11) MCH_CFG_7 MCH_CFG_7 M24 AH42 DMI_RXN3 R48 C_PEG_TXN5 C195 [email protected]/10V_4 PEG_TXN5
CFG_7 DMI_TXN_3 PEG_TX#_5 PEG_TXN5 (19)
MCH_CFG_8 E21 H24 N38 C_PEG_TXN6 C197 [email protected]/10V_4 PEG_TXN6
T23 CFG_8 DMI_RXP[3:0] (15) TV_RTN PEG_TX#_6 PEG_TXN6 (19)
CFG

MCH_CFG_9 DMI_RXP0 C_PEG_TXN7 C209 [email protected]/10V_4 PEG_TXN7

DMI
(11) MCH_CFG_9 C23 AD35 T40 PEG_TXN7 (19)
MCH_CFG_10 CFG_9 DMI_TXP_0 DMI_RXP1 PEG_TX#_7 C_PEG_TXN8 C211 [email protected]/10V_4 PEG_TXN8
(11) MCH_CFG_10 C24 CFG_10 DMI_TXP_1 AE44 PEG_TX#_8 U37 PEG_TXN8 (19)
MCH_CFG_11 N21 AF46 DMI_RXP2 U40 C_PEG_TXN9 C181 [email protected]/10V_4 PEG_TXN9
T19 CFG_11 DMI_TXP_2 PEG_TX#_9 PEG_TXN9 (19)
(11) MCH_CFG_12 MCH_CFG_12 P21 AH43 DMI_RXP3 TV_DCONSEL_0 C31 Y40 C_PEG_TXN10 C183 [email protected]/10V_4 PEG_TXN10
CFG_12 DMI_TXP_3 TV_DCONSEL_0 PEG_TX#_10 PEG_TXN10 (19)
(11) MCH_CFG_13 MCH_CFG_13 T21 TV_DCONSEL_1 E32 AA46 C_PEG_TXN11 C205 [email protected]/10V_4 PEG_TXN11
CFG_13 TV_DCONSEL_1 PEG_TX#_11 PEG_TXN11 (19)
MCH_CFG_14 R20 RP49 3 4 EV@0X2 DREFCLK AA37 C_PEG_TXN12 C185 [email protected]/10V_4 PEG_TXN12
T22 CFG_14 PEG_TX#_12 PEG_TXN12 (19)
MCH_CFG_15 M20 1 2 DREFCLK# AA40 C_PEG_TXN13 C207 [email protected]/10V_4 PEG_TXN13
T21 CFG_15 PEG_TX#_13 PEG_TXN13 (19)
(11) MCH_CFG_16 MCH_CFG_16 L21 AD43 C_PEG_TXN14 C503 [email protected]/10V_4 PEG_TXN14
CFG_16 PEG_TX#_14 PEG_TXN14 (19)
MCH_CFG_17 H21 3 4 DREFSSCLK AC46 C_PEG_TXN15 C499 [email protected]/10V_4 PEG_TXN15
T24 CFG_17 PEG_TX#_15 PEG_TXN15 (19)
MCH_CFG_18 DREFSSCLK#
GRAPHICS VID

T31 P29 CFG_18 1 2

MCH_CFG_19 RP27 EV@0X2 INT_CRT_BLU C_PEG_TXP0_H C504 [email protected]/10V_4
(11) MCH_CFG_19
MCH_CFG_20
R28 CFG_19 CRT I/F (18) INT_CRT_BLU E28 CRT_BLUE PEG_TX_0 J42
C_PEG_TXP1_H C190 [email protected]/10V_4
PEG_TXP0 (19)
(11) MCH_CFG_20 T28 CFG_20 GFX_VID_0 B33 T36 PEG_TX_1 L46 PEG_TXP1 (19)
B32 INT_CRT_GRN G28 M48 C_PEG_TXP2_H C501 [email protected]/10V_4
GFX_VID_1 T41 (18) INT_CRT_GRN CRT_GREEN PEG_TX_2 PEG_TXP2 (19)
G33 M39 C_PEG_TXP3_H C192 [email protected]/10V_4
GFX_VID_2 T35 PEG_TX_3 PEG_TXP3 (19)
F33 INT_CRT_RED J28 M43 C_PEG_TXP4 C203 [email protected]/10V_4 PEG_TXP4
GFX_VID_3 T43 (18) INT_CRT_RED CRT_RED PEG_TX_4 PEG_TXP4 (19)

VGA
R74 0_4 PM_SYNC#_R R29 E33 10/14 Add R47 C_PEG_TXP5 C194 [email protected]/10V_4 PEG_TXP5
(16) PM_SYNC# PM_SYNC# GFX_VID_4 T46 PEG_TX_5 PEG_TXP5 (19)
R445 0_4 ICH_DPRSTP#_R B7 CRT_IRTN G29 N37 C_PEG_TXP6 C196 [email protected]/10V_4 PEG_TXP6
(3,14,32) ICH_DPRSTP# PM_DPRSTP# CRT_IRTN PEG_TX_6 PEG_TXP6 (19)
(13) PM_EXTTS#0 PM_EXTTS#0 R141 0_4 PM_EXTTS#0_1_EC_R N33 T39 C_PEG_TXP7 C208 [email protected]/10V_4 PEG_TXP7
PM_EXT_TS#_0 PEG_TX_7 PEG_TXP7 (19)
(13) PM_EXTTS#1 PM_EXTTS#1 R135 0_4 TS#DIMM0_1_R P32 INT_CRT_DDCCLK H32 U36 C_PEG_TXP8 C210 [email protected]/10V_4 PEG_TXP8
PM_EXT_TS#_1 (18) INT_CRT_DDCCLK CRT_DDC_CLK PEG_TX_8 PEG_TXP8 (19)
PM

R158 0_4 AT40 C34 INT_CRT_DDCDAT J32 U39 C_PEG_TXP9 C180 [email protected]/10V_4 PEG_TXP9
(3,16,32) DELAY_VR_PWRGOOD PWROK GFX_VR_EN T40 (18) INT_CRT_DDCDAT CRT_DDC_DATA PEG_TX_9 PEG_TXP9 (19)
R49 100_4 RST_IN#_MCH AT11 INT_HSYNC R126 [email protected]/F_4 HSYNC_A J29 Y39 C_PEG_TXP10 C182 [email protected]/10V_4 PEG_TXP10
(15) PLT_RST#_NB RSTIN# (18) INT_HSYNC CRT_HSYNC PEG_TX_10 PEG_TXP10 (19)
(3,14) PM_THRMTRIP# R66 *0_4 THRMTRIP#_R T20 CRTIREF E29 Y46 C_PEG_TXP11 C204 [email protected]/10V_4 PEG_TXP11
THERMTRIP# CRT_TVO_IREF PEG_TX_11 PEG_TXP11 (19)
R91 0_4 DPRSLPVR_R R32 INT_VSYNC R128 [email protected]/F_4 VSYNC_A L29 AA36 C_PEG_TXP12 C184 [email protected]/10V_4 PEG_TXP12
(16,32) PM_DPRSLPVR DPRSLPVR (18) INT_VSYNC CRT_VSYNC PEG_TX_12 PEG_TXP12 (19)
AA39 C_PEG_TXP13 C206 [email protected]/10V_4 PEG_TXP13
PEG_TX_13 PEG_TXP13 (19)
AH37 CL_CLK0 For IV @ Connect to 30.1ohm AD42 C_PEG_TXP14 C502 [email protected]/10V_4 PEG_TXP14
CL_CLK CL_CLK0 (16) PEG_TX_14 PEG_TXP14 (19)
AH36 CL_DATA0 HSYNC/VSYNC serial R place close to NB AD46 C_PEG_TXP15 C498 [email protected]/10V_4 PEG_TXP15
CL_DATA CL_DATA0 (16) For EV@ NC PEG_TX_15 PEG_TXP15 (19)
T124 TP_MCH_NC1 BG48 AN36 MPWROK
NC_1 CL_PWROK MPWROK (16)
NB Thermal trip pin T125 TP_MCH_NC2 BF48 AJ35 CL_RST#0
NC_2 CL_RST# CL_RST#0 (16)
ME

No use Thermal trip NB side can T127 TP_MCH_NC3 BD48 AH34 MCH_CLVREF_R CANTIGA_1p2
NC.(NB has ODT) TP_MCH_NC4 NC_3 CL_VREF
T128 BC48
TP_MCH_NC5 NC_4
T121 BH47
TP_MCH_NC6 NC_5 DDPC_CTRL for HDMI port C
T52 BG47
PM_DPRSTP#
The Daisy chain topology should
T126
T120
TP_MCH_NC7
TP_MCH_NC8
BE47
BH46
NC_6
NC_7
NC_8
DDPC_CTRLCLK
DDPC_CTRLDATA
N28
M28
DDPC_CTRLCLK
DDPC_CTRLDATA
T30
SDVO_CTRL for HDMI port B

DDPC_CTRLDATA (11)
To HDMI
be routed from ICH9M to IMVP , T53 TP_MCH_NC9 BF46 G36 SDVO_CTRLCLK C_PEG_TXN0_H C188 [email protected]/10V_4 TMDSB_DATA2#
NC_9 SDVO_CTRLCLK SDVO_CTRLCLK (20) TMDSB_DATA2# (20)
NC

then to (G)MCH and CPU, in that T119 TP_MCH_NC10 BG45 E36 SDVO_CTRLDATA
NC_10 SDVO_CTRLDATA SDVO_CTRLDATA (11,20)
order. T118 TP_MCH_NC11 BH44 K36 CLK_MCH_OE# C_PEG_TXP0_H C189 [email protected]/10V_4 TMDSB_DATA2
NC_11 CLKREQ# CLK_MCH_OE# (2) TMDSB_DATA2 (20)
T117 TP_MCH_NC12 BH43 H36 MCH_ICH_SYNC#
NC_12 ICH_SYNC# MCH_ICH_SYNC# (16)
B T111 TP_MCH_NC13 BH6 B
MISC

TP_MCH_NC14 NC_13
T107 BH5
TP_MCH_NC15 NC_14 TSATN#
T103 BG4 B12
TP_MCH_NC16 NC_15 TSATN# C_PEG_TXN2_H C186 [email protected]/10V_4 TMDSB_DATA0#
T110 BH3 TMDSB_DATA0# (20)
TP_MCH_NC17 NC_16
T8 BF3
TP_MCH_NC18 NC_17 NOTE: C_PEG_TXP2_H C187 [email protected]/10V_4 TMDSB_DATA0
T106 BH2 TMDSB_DATA0 (20)
TP_MCH_NC19 NC_18 HDA_BIT_CLK_HDMI If (G)MCH's HD Audio signals are connected to ICH9M for
T7 BG2 B28 HDA_BIT_CLK_HDMI (14)
TP_MCH_NC20 NC_19 HDA_BCLK HDA_RST#_HDMI iHDMI, VCCHDA and VCCSUSHDA on ICH9M should be
T105 BE2 B30 HDA_RST#_HDMI (14)
TP_MCH_NC21 NC_20 HDA_RST# HDA_SDIN_HDMI
T102 BG1 B29 HDA_SDIN_HDMI (14) only on 1.5V. These power pins on ICH9M can be supplied
TP_MCH_NC22 NC_21 HDA_SDI HDA_SDOUT_HDMI
T109 BF1 C29 HDA_SDOUT_HDMI (14) with 3.3V if and only if (G)MCH's HDA is not connected to
TP_MCH_NC23 NC_22 HDA_SDO HDA_SYNC_HDMI C_PEG_TXN1_H C219 [email protected]/10V_4 TMDSB_DATA1#
T108 BD1 A28 ICH9M. Consequently, only 1.5V audio/modem codecs can
HDA

NC_23 HDA_SYNC HDA_SYNC_HDMI (14) TMDSB_DATA1# (20)

T104 TP_MCH_NC24 BC1 be used on the platform.
TP_MCH_NC25 NC_24 C_PEG_TXP1_H C216 [email protected]/10V_4 TMDSB_DATA1
T4 F1 TMDSB_DATA1 (20)
NC_25

CANTIGA_1p2

C_PEG_TXN3_H C224 [email protected]/10V_4 TMDSB_CLK#

TMDSB_CLK# (20)
C_PEG_TXP3_H C222 [email protected]/10V_4 TMDSB_CLK
TMDSB_CLK (20)

<Checklist ver0.8> IV&EV Dis/Enable LVDS setting(See DG 1.0 P190 Table 103)
Check list note : CL_REF=0.35V SM_VREF.Default use voltage divider for poor layout cause +SMDDR_VREF not For EV@ For IV@ UMA iHDMI I/F
+1.05V If TSATN# is not used, then it must be terminated
meet spec.And Intel circuit PU/PD is 1K,But Check list PU/PD is 10K. with a 56- pull-up resistor to VCCP. +1.05V R145 IV@0_4
CRT R/G/B CRT R/G/B
LVDS_VREFH 12/22 REV_2A Swap net
LVDS_VREFL USE 0 ohm R USE 150 1%ohm R
TSATN# 56_4 R450 PEG_RXP3 R229 IHM@0_4 Port-B_HPD#
Port-B_HPD# (20)
R140 R156 *0_6 +SMDDR_VREF
R160 [email protected]/F_4 LVDS_IBG
1K/F_4 +3V

MCH_CLVREF_R SM_VREF R147 10K/F_4 +1.8VSUS CLK_MCH_OE# 10K_4 R144 +3V R104 IV@10K_4 L_CTRL_CLK R92 150/F_4 INT_CRT_BLU

PM_EXTTS#0 10K_4 R142 R103 IV@10K_4 L_CTRL_DATA R123 150/F_4 INT_CRT_GRN

C121 R139
R154 PM_EXTTS#1 10K_4 R136 R124 150/F_4 INT_CRT_RED
0.1u/10V_4 511/F_6 10K/F_4 R102 EV@0_4 03/14 REV_3A Add
10/14 Add
R105 EV@0_4
SM_REXT R65 499/F_4
R94 R95 R95
12/19 REV_2A Chanhe net to +1.8VSUS IV&EV Dis/Enable CRT setting(See DG 1.0 P190 Table 103) R94 75/F_4 INT_TV_COMP
A A

SM_PWROK only for DDR3.(DDR2 PD only) R95 150/F_4 INT_TV_Y/G UMA W/ TV 75/F 150/F 150/F
+3V R90 [email protected]_4
+1.8VSUS +1.8VSUS R476 1K/F_4 SM_RCOMP_VOH R96 150/F_4 INT_TV_C/R
+1.8VSUS HWPG_1.8V (29,34) 10/14 Add
R89 [email protected]_4 UMA W/O TV 75/F 75/F 75/F
C440 C444
R470 R149 R122 EV@0_4 TV_DCONSEL_0
R464 R460 0.01u/16V_4 2.2u/6.3V_6 *12K/F_4 Discrete 75/F 75/F 75/F
3.01K/F_4 R133 EV@0_4 TV_DCONSEL_1
80.6/F_4 *20/F_4
SM_PWROK
M_RCOMP M_RCOMP# SM_RCOMP_VOL R137 EV@0_4 INT_CRT_DDCCLK

R463 R459 R471 C435 C438

R143 R138 EV@0_4 INT_CRT_DDCDAT
R129 1K_4 CRTIREF
Quanta Computer Inc.
10K/F_6

*20/F_4 80.6/F_4 1K/F_4 0.01u/16V_4 2.2u/6.3V_6 R125 EV@0_4 HSYNC_A PROJECT : BL5M Montevina
For IV@ USE 1.02K ohm R Size Document Number Rev
R127 EV@0_4 VSYNC_A 1A
For EV@ USE 0 ohm R CLK. GEN./ CK505
Date: Friday, March 14, 2008 Sheet 6 of 37
5 4 3 2 1

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 5 4 3 2 1

BOM Option Table

Reference Description
N/A N/A

(13) M_B_DQ[63:0]
(13) M_A_DQ[63:0]
D D

U23D U23E
M_A_DQ0 AJ38 BD21 M_A_BS#0 M_B_DQ0 AK47 BC16 M_B_BS#0
SA_DQ_0 SA_BS_0 M_A_BS#0 (12,13) SB_DQ_0 SB_BS_0 M_B_BS#0 (12,13)
M_A_DQ1 AJ41 BG18 M_A_BS#1 M_B_DQ1 AH46 BB17 M_B_BS#1
SA_DQ_1 SA_BS_1 M_A_BS#1 (12,13) SB_DQ_1 SB_BS_1 M_B_BS#1 (12,13)
M_A_DQ2 AN38 AT25 M_A_BS#2 M_B_DQ2 AP47 BB33 M_B_BS#2
SA_DQ_2 SA_BS_2 M_A_BS#2 (12,13) SB_DQ_2 SB_BS_2 M_B_BS#2 (12,13)
M_A_DQ3 AM38 M_B_DQ3 AP46
M_A_DQ4 SA_DQ_3 M_A_RAS# M_B_DQ4 SB_DQ_3
AJ36 SA_DQ_4 SA_RAS# BB20 M_A_RAS# (12,13) AJ46 SB_DQ_4
M_A_DQ5 AJ40 BD20 M_A_CAS# M_B_DQ5 AJ48 AU17 M_B_RAS#
SA_DQ_5 SA_CAS# M_A_CAS# (12,13) SB_DQ_5 SB_RAS# M_B_RAS# (12,13)
M_A_DQ6 AM44 AY20 M_A_WE# M_B_DQ6 AM48 BG16 M_B_CAS#
SA_DQ_6 SA_WE# M_A_WE# (12,13) SB_DQ_6 SB_CAS# M_B_CAS# (12,13)
M_A_DQ7 AM42 M_B_DQ7 AP48 BF14 M_B_WE#
SA_DQ_7 SB_DQ_7 SB_WE# M_B_WE# (12,13)
M_A_DQ8 AN43 M_B_DQ8 AU47
M_A_DQ9 SA_DQ_8 M_B_DQ9 SB_DQ_8
AN44 SA_DQ_9 AU46 SB_DQ_9
M_A_DQ10 AU40 M_B_DQ10 BA48
SA_DQ_10 M_A_DM[7:0] (13) SB_DQ_10
M_A_DQ11 AT38 AM37 M_A_DM0 M_B_DQ11 AY48
SA_DQ_11 SA_DM_0 SB_DQ_11 M_B_DM[7:0] (13)
M_A_DQ12 AN41 AT41 M_A_DM1 M_B_DQ12 AT47 AM47 M_B_DM0
M_A_DQ13 SA_DQ_12 SA_DM_1 M_A_DM2 M_B_DQ13 SB_DQ_12 SB_DM_0 M_B_DM1
AN39 SA_DQ_13 SA_DM_2 AY41 AR47 SB_DQ_13 SB_DM_1 AY47
M_A_DQ14 AU44 AU39 M_A_DM3 M_B_DQ14 BA47 BD40 M_B_DM2
M_A_DQ15 SA_DQ_14 SA_DM_3 M_A_DM4 M_B_DQ15 SB_DQ_14 SB_DM_2 M_B_DM3
AU42 SA_DQ_15 SA_DM_4 BB12 BC47 SB_DQ_15 SB_DM_3 BF35
M_A_DQ16 AV39 AY6 M_A_DM5 M_B_DQ16 BC46 BG11 M_B_DM4
M_A_DQ17 SA_DQ_16 SA_DM_5 M_A_DM6 M_B_DQ17 SB_DQ_16 SB_DM_4 M_B_DM5
AY44 SA_DQ_17 SA_DM_6 AT7 BC44 SB_DQ_17 SB_DM_5 BA3

A
M_A_DQ18 BA40 AJ5 M_A_DM7 M_B_DQ18 BG43 AP1 M_B_DM6

B
M_A_DQ19 SA_DQ_18 SA_DM_7 M_B_DQ19 SB_DQ_18 SB_DM_6 M_B_DM7
BD43 SA_DQ_19 M_A_DQS[7:0] (13) BF43 SB_DQ_19 SB_DM_7 AK2
M_A_DQ20 AV41 AJ44 M_A_DQS0 M_B_DQ20 BE45
SA_DQ_20 SA_DQS_0 SB_DQ_20 M_B_DQS[7:0] (13)
C M_A_DQ21 AY43 AT44 M_A_DQS1 M_B_DQ21 BC41 AL47 M_B_DQS0 C
M_A_DQ22 SA_DQ_21 SA_DQS_1 M_A_DQS2 M_B_DQ22 SB_DQ_21 SB_DQS_0 M_B_DQS1
BB41 SA_DQ_22 SA_DQS_2 BA43 BF40 SB_DQ_22 SB_DQS_1 AV48
MEMORY
M_A_DQ23 M_A_DQS3 M_B_DQ23 M_B_DQS2

MEMORY
BC40 SA_DQ_23 SA_DQS_3 BC37 BF41 SB_DQ_23 SB_DQS_2 BG41
M_A_DQ24 AY37 AW12 M_A_DQS4 M_B_DQ24 BG38 BG37 M_B_DQS3
M_A_DQ25 SA_DQ_24 SA_DQS_4 M_A_DQS5 M_B_DQ25 SB_DQ_24 SB_DQS_3 M_B_DQS4
BD38 SA_DQ_25 SA_DQS_5 BC8 BF38 SB_DQ_25 SB_DQS_4 BH9
M_A_DQ26 AV37 AU8 M_A_DQS6 M_B_DQ26 BH35 BB2 M_B_DQS5
M_A_DQ27 SA_DQ_26 SA_DQS_6 M_A_DQS7 M_B_DQ27 SB_DQ_26 SB_DQS_5 M_B_DQS6
AT36 SA_DQ_27 SA_DQS_7 AM7 M_A_DQS#[7:0] (13) BG35 SB_DQ_27 SB_DQS_6 AU1
M_A_DQ28 AY38 AJ43 M_A_DQS#0 M_B_DQ28 BH40 AN6 M_B_DQS7
SA_DQ_28 SA_DQS#_0 SB_DQ_28 SB_DQS_7 M_B_DQS#[7:0] (13)
M_A_DQ29 BB38 AT43 M_A_DQS#1 M_B_DQ29 BG39 AL46 M_B_DQS#0
M_A_DQ30 SA_DQ_29 SA_DQS#_1 M_A_DQS#2 M_B_DQ30 SB_DQ_29 SB_DQS#_0 M_B_DQS#1
AV36 SA_DQ_30 SA_DQS#_2 BA44 BG34 SB_DQ_30 SB_DQS#_1 AV47
M_A_DQ31 AW36 BD37 M_A_DQS#3 M_B_DQ31 BH34 BH41 M_B_DQS#2
M_A_DQ32 SA_DQ_31 SA_DQS#_3 M_A_DQS#4 M_B_DQ32 SB_DQ_31 SB_DQS#_2 M_B_DQS#3
BD13 SA_DQ_32 SA_DQS#_4 AY12 BH14 SB_DQ_32 SB_DQS#_3 BH37
M_A_DQ33 AU11 BD8 M_A_DQS#5 M_B_DQ33 BG12 BG9 M_B_DQS#4
M_A_DQ34 SA_DQ_33 SA_DQS#_5 M_A_DQS#6 M_B_DQ34 SB_DQ_33 SB_DQS#_4 M_B_DQS#5
BC11 SA_DQ_34 SA_DQS#_6 AU9 BH11 SB_DQ_34 SB_DQS#_5 BC2
M_A_DQ35 BA12 AM8 M_A_DQS#7 M_B_DQ35 BG8 AT2 M_B_DQS#6
SYSTEM

M_A_DQ36 SA_DQ_35 SA_DQS#_7 M_B_DQ36 SB_DQ_35 SB_DQS#_6 M_B_DQS#7

SYSTEM
AU13 SA_DQ_36 M_A_A[14:0] (12,13) BH12 SB_DQ_36 SB_DQS#_7 AN5
M_A_DQ37 AV13 BA21 M_A_A0 M_B_DQ37 BF11
SA_DQ_37 SA_MA_0 SB_DQ_37 M_B_A[14:0] (12,13)
M_A_DQ38 BD12 BC24 M_A_A1 M_B_DQ38 BF8 AV17 M_B_A0
M_A_DQ39 SA_DQ_38 SA_MA_1 M_A_A2 M_B_DQ39 SB_DQ_38 SB_MA_0 M_B_A1
BC12 SA_DQ_39 SA_MA_2 BG24 BG7 SB_DQ_39 SB_MA_1 BA25
M_A_DQ40 BB9 BH24 M_A_A3 M_B_DQ40 BC5 BC25 M_B_A2
M_A_DQ41 SA_DQ_40 SA_MA_3 M_A_A4 M_B_DQ41 SB_DQ_40 SB_MA_2 M_B_A3
BA9 SA_DQ_41 SA_MA_4 BG25 BC6 SB_DQ_41 SB_MA_3 AU25
M_A_DQ42 AU10 BA24 M_A_A5 M_B_DQ42 AY3 AW25 M_B_A4
M_A_DQ43 SA_DQ_42 SA_MA_5 M_A_A6 M_B_DQ43 SB_DQ_42 SB_MA_4 M_B_A5
AV9 SA_DQ_43 SA_MA_6 BD24 AY1 SB_DQ_43 SB_MA_5 BB28
M_A_DQ44 BA11 BG27 M_A_A7 M_B_DQ44 BF6 AU28 M_B_A6
M_A_DQ45 SA_DQ_44 SA_MA_7 M_A_A8 M_B_DQ45 SB_DQ_44 SB_MA_6 M_B_A7
BD9 SA_DQ_45 SA_MA_8 BF25 BF5 SB_DQ_45 SB_MA_7 AW28
M_A_DQ46 AY8 AW24 M_A_A9 M_B_DQ46 BA1 AT33 M_B_A8
M_A_DQ47 SA_DQ_46 SA_MA_9 M_A_A10 M_B_DQ47 SB_DQ_46 SB_MA_8 M_B_A9
BA6 SA_DQ_47 SA_MA_10 BC21 BD3 SB_DQ_47 SB_MA_9 BD33
M_A_DQ48 M_A_A11 M_B_DQ48 M_B_A10
DDR

B
AV5 SA_DQ_48 SA_MA_11 BG26 AV2 SB_DQ_48 SB_MA_10 BB16 B
M_A_DQ49 M_A_A12 M_B_DQ49 M_B_A11

DDR
AV7 SA_DQ_49 SA_MA_12 BH26 AU3 SB_DQ_49 SB_MA_11 AW33
M_A_DQ50 AT9 BH17 M_A_A13 M_B_DQ50 AR3 AY33 M_B_A12
M_A_DQ51 SA_DQ_50 SA_MA_13 M_A_A14 M_B_DQ51 SB_DQ_50 SB_MA_12 M_B_A13
AN8 SA_DQ_51 SA_MA_14 AY25 AN2 SB_DQ_51 SB_MA_13 BH15
M_A_DQ52 AU5 M_B_DQ52 AY2 AU33 M_B_A14
M_A_DQ53 SA_DQ_52 M_B_DQ53 SB_DQ_52 SB_MA_14
AU6 SA_DQ_53 AV1 SB_DQ_53
M_A_DQ54 AT5 M_B_DQ54 AP3
M_A_DQ55 SA_DQ_54 M_B_DQ55 SB_DQ_54
AN10 SA_DQ_55 AR1 SB_DQ_55
M_A_DQ56 AM11 M_B_DQ56 AL1
M_A_DQ57 SA_DQ_56 M_B_DQ57 SB_DQ_56
AM5 SA_DQ_57 AL2 SB_DQ_57
M_A_DQ58 AJ9 M_B_DQ58 AJ1
M_A_DQ59 SA_DQ_58 M_B_DQ59 SB_DQ_58
AJ8 SA_DQ_59 AH1 SB_DQ_59
M_A_DQ60 AN12 M_B_DQ60 AM2
M_A_DQ61 SA_DQ_60 M_B_DQ61 SB_DQ_60
AM13 SA_DQ_61 AM3 SB_DQ_61
M_A_DQ62 AJ11 M_B_DQ62 AH3
M_A_DQ63 SA_DQ_62 M_B_DQ63 SB_DQ_62
AJ12 SA_DQ_63 AJ3 SB_DQ_63
CANTIGA_1p2 CANTIGA_1p2

A A

Quanta Computer Inc.

PROJECT : BL5M Montevina
Size Document Number Rev
1A
CLK. GEN./ CK505
Date: Monday, March 10, 2008 Sheet 7 of 37
5 4 3 2 1

PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com

 5 4 3 2 1

BOM Option Table

Reference Description
IV@ INT VGA
EV@ EXT VGA
12/19 REV_2A Chanhe net to +1.8VSUS
12/19 REV_2A Del R101
+1.8VSUS +1.8VSUS
+1.8VSUS +VGFX_CORE_INT

U23F U23G
+1.05V_VCC_GMCH

D AP33 W28 C460 C449 C61 + C111 D

VCC_SM_1 VCC_AXG_NCTF_1
AG34 AN33 V28 Close to GMCH
VCC_1 VCC_SM_2 VCC_AXG_NCTF_2 10u/6.3V_8 10u/6.3V_8 0.1u/10V_4 330u/2.5V_7343
AC34 BH32 W26
VCC_2 VCC_SM_3 VCC_AXG_NCTF_3
AB34 BG32 V26
VCC_3 VCC_SM_4 VCC_AXG_NCTF_4
AA34 BF32 W25
VCC_4 VCC_SM_5 VCC_AXG_NCTF_5
Y34 BD32 V25
VCC_5 VCC_SM_6 VCC_AXG_NCTF_6
V34 BC32 W24
VCC_6 VCC_SM_7 VCC_AXG_NCTF_7
U34 BB32 V24
VCC_7 VCC_SM_8 VCC_AXG_NCTF_8 +1.05V_VCC_GMCH +1.05V
AM33 BA32 W23
VCC_8 VCC_SM_9 VCC_AXG_NCTF_9
AK33 AY32 V23
VCC_9 VCC_SM_10 VCC_AXG_NCTF_10 R52 0_1206
AJ33 AW32 AM21
VCC_10 VCC_SM_11 VCC_AXG_NCTF_11
AG33 AV32 AL21
VCC_11 VCC_SM_12 VCC_AXG_NCTF_12
AF33 AU32 AK21
VCC_12 VCC_SM_13 VCC_AXG_NCTF_13 C104 C116 C96 C113 + C64
AT32 W21
VCC_SM_14 VCC_AXG_NCTF_14
AE33 AR32 V21
VCC_13 VCC_SM_15 VCC_AXG_NCTF_15 0.1u/10V_4 0.22u/6.3V_4 0.22u/6.3V_4 22u/6.3V_8 270u/2V_7343
VCC CORE

AC33 AP32 U21

POWER
VCC_14 VCC_SM_16 VCC_AXG_NCTF_16
AA33 AN32 AM20
VCC_15 VCC_SM_17 VCC_AXG_NCTF_17
Y33 BH31 AK20
VCC_16 VCC_SM_18 VCC_AXG_NCTF_18
W33 BG31 W20
VCC_17 VCC_SM_19 VCC_AXG_NCTF_19
V33 BF31 U20
VCC_18 VCC_SM_20 VCC_AXG_NCTF_20
U33 BG30 AM19 Close to GMCH
VCC_19 VCC_SM_21 VCC_AXG_NCTF_21
AH28 BH29 AL19
VCC_20 VCC_SM_22 VCC_AXG_NCTF_22
AF28 BG29 AK19
VCC_21 VCC_SM_23 VCC_AXG_NCTF_23 +VGFX_CORE_INT +1.05V
AC28 BF29 AJ19
VCC_22 VCC_SM_24 VCC_AXG_NCTF_24
AA28 BD29 AH19
VCC_23 VCC_SM_25 VCC_AXG_NCTF_25

VCC SM
AJ26
VCC_24
BC29
VCC_SM_26 VCC_AXG_NCTF_26
AG19 See Page 9 EV&IV table
AG26 BB29 AF19 R48 IV@0_1206
VCC_25 VCC_SM_27 VCC_AXG_NCTF_27
AE26 BA29 AE19
VCC_26 VCC_SM_28 VCC_AXG_NCTF_28
AC26 AY29 AB19
VCC_27 VCC_SM_29 VCC_AXG_NCTF_29 C89 C72 C67 C73 C63 C71
AH25 AW29 AA19
VCC_28 VCC_SM_30 VCC_AXG_NCTF_30 R83 R84 R100
AG25 AV29 Y19
VCC_29 VCC_SM_31 VCC_AXG_NCTF_31 [email protected]/6.3V_4 IV@1u/16V_6 IV@10u/10V_8 IV@10u/6.3V_8 [email protected]/10V_4 [email protected]/10V_4
AF25 AU29 W19
VCC_30 VCC_SM_32 VCC_AXG_NCTF_32 EV@0_6 EV@0_6 EV@0_6
AG24 AT29 V19
VCC_31 VCC_SM_33 VCC_AXG_NCTF_33
AJ23 AR29 U19
VCC_32 +1.05V_VCC_GMCH VCC_SM_34 VCC_AXG_NCTF_34
AH23 AP29 AM17 DR8
C VCC_33 VCC_SM_35 VCC_AXG_NCTF_35 C
AF23 AK17
POWER

VCC_34 VCC_AXG_NCTF_36 DR9

AM32 BA36 AH17
VCC_NCTF_1 VCC_SM_36/NC VCC_AXG_NCTF_37
T32 AL32 BB24 AG17
VCC_35 VCC_NCTF_2 VCC_SM_37/NC VCC_AXG_NCTF_38
AK32 BD16 AF17
R134 VCC_NCTF_3 VCC_SM_38/NC VCC_AXG_NCTF_39
VCC_NCTF_4
AJ32 BB21
VCC_SM_39/NC VCC_AXG_NCTF_40
AE17 Place close to the GMCH
0_4 AH32 AW16 AC17 +VGFX_CORE_INT
VCC_NCTF_5 VCC_SM_40/NC VCC_AXG_NCTF_41 and different location
AG32 AW13 AB17
VCC_NCTF_6 VCC_SM_41/NC VCC_AXG_NCTF_42
AE32 AT13 Y17
VCC_NCTF_7 VCC_SM_42/NC VCC_AXG_NCTF_43
AC32 W17
VCC_NCTF_8 +VGFX_CORE_INT VCC_AXG_NCTF_44
AA32 V17
VCC_NCTF_9 VCC_AXG_NCTF_45

VCC GFX NCTF

Y32 AM16
VCC_NCTF_10 VCC_AXG_NCTF_46 + C43 + C42
W32 Y26 AL16
VCC_NCTF_11 VCC_AXG_1 VCC_AXG_NCTF_47
U32 AE25 AK16
VCC_NCTF_12 VCC_AXG_2 VCC_AXG_NCTF_48 IV@330u/2.5V_7343 IV@330u/2.5V_7343
AM30 AB25 AJ16
VCC_NCTF_13 VCC_AXG_3 VCC_AXG_NCTF_49
AL30 AA25 AH16
VCC_NCTF_14 VCC_AXG_4 VCC_AXG_NCTF_50
AK30 AE24 AG16
VCC_NCTF_15 VCC_AXG_5 VCC_AXG_NCTF_51
VCC_NCTF_16
AH30 AC24
VCC_AXG_6 VCC_AXG_NCTF_52
AF16 Close to GMCH
AG30 AA24 AE16
VCC_NCTF_17 VCC_AXG_7 VCC_AXG_NCTF_53
AF30 Y24 AC16
VCC_NCTF_18 VCC_AXG_8 VCC_AXG_NCTF_54
AE30 AE23 AB16
VCC_NCTF_19 VCC_AXG_9 VCC_AXG_NCTF_55
AC30 AC23 AA16
VCC_NCTF_20 VCC_AXG_10 VCC_AXG_NCTF_56
AB30 AB23 Y16
VCC_NCTF_21 VCC_AXG_11 VCC_AXG_NCTF_57
AA30 AA23 W16
VCC_NCTF_22 VCC_AXG_12 VCC_AXG_NCTF_58
VCC_NCTF_23
Y30
W30
AJ21
AG21
VCC_AXG_13 VCC_AXG_NCTF_59
V16
U16 NB Power Status and max current table(1/3)
VCC_NCTF_24 VCC_AXG_14 VCC_AXG_NCTF_60
VCC NCTF

V30 AE21 POWER PLANE S0 S3 S4/S5 Voltage I(max) Note

VCC_NCTF_25 VCC_AXG_15
U30 AC21
VCC_NCTF_26 VCC_AXG_16
AL29 AA21 VCC(EXT_VGA) O X X +1.05V 2178mA
VCC_NCTF_27 VCC_AXG_17
AK29 Y21
VCC_NCTF_28 VCC_AXG_18
VCC_NCTF_29 AJ29 AH20 VCC_AXG_19 VCC(INT_VGA) O X X +1.05V 2899mA
AH29 AF20
VCC_NCTF_30 VCC_AXG_20
AG29 AE20 VCC_AXG O X X +1.05V 8700mA Graphics Core
VCC_NCTF_31 VCC_AXG_21
VCC_NCTF_32 AE29 AC20 VCC_AXG_22
AC29 AB20 VCC_SM(800) O O X +1.8VSUS 3A (DDRII-667) 2.6A
VCC_NCTF_33 VCC_AXG_23
AA29 AA20
B VCC_NCTF_34 VCC_AXG_24 B
Y29 T17 VCC_SM(Standby) O O X +1.8VSUS 1mA Self Refresh during S3
VCC_NCTF_35 VCC_AXG_25
VCC_NCTF_36 W29 T16 VCC_AXG_26
V29 AM15
VCC_NCTF_37 VCC_AXG_27
VCC_NCTF_38 AL28 AL15 VCC_AXG_28 (See NB EDS Rev:1.0 Section 10.1 for max current)
AK28 AE15
VCC_NCTF_39 VCC_AXG_29
VCC_NCTF_40
AL26 AJ15
VCC_AXG_30 (See NB EDS Rev:1.0 Section 12.2 for DC voltage)
AK26 AH15
VCC_NCTF_41 VCC_AXG_31
AK25 AG15
VCC_NCTF_42 VCC_AXG_32
AK24 AF15
VCC_NCTF_43 VCC_AXG_33
AK23 AB15
VCC_NCTF_44 VCC_AXG_34
AA15 VCC_AXG_35
VCC GFX

Y15
VCC_AXG_36
V15
VCC_AXG_37
U15 VCC_AXG_38 Close to each pins
AN14
VCC_AXG_39 1.8V Internal connect to power
AM14
CANTIGA_1p2 VCC_AXG_40 VCCSM_LF1
U14 VCC_AXG_41 VCC_SM_LF1 AV44
VCCSM_LF2
VCC SM LF

T14 BA37
VCC_AXG_42 VCC_SM_LF2 VCCSM_LF3
AM40
VCC_SM_LF3 VCCSM_LF4
VCC_SM_LF4 AV21
AY5 VCCSM_LF5
VCC_SM_LF5 VCCSM_LF6
AM10
+VGFX_CORE_INT VCC_SM_LF6 VCCSM_LF7
VCC_SM_LF7 BB13

C62 C57 C53 C79 C134 C133 C144

R63 IV@10/F_6 AJ14
R55 IV@10/F_6 VCC_AXG_SENSE 0.1u/10V_4 0.1u/10V_4 0.22u/6.3V_4 0.22u/6.3V_4 0.47u/10V_6 1u/16V_6 1u/16V_6
AH14
VSS_AXG_SENSE

1. Route VCC_AXG_SENSE and VSS_AXG_SENSE differentially

2. VCC_AXG_SENSE PU to +VGFX_CORE_INT with 10ohm
A and VSS_AXG_SENSE PD with 10ohm for Intel suggest A
CANTIGA_1p2

Quanta Computer Inc.

PROJECT : BL5M Montevina
Size Document Number Rev
1A
CLK. GEN./ CK505
Date: Tuesday, March 04, 2008 Sheet 8 of 37
5 4 3 2 1

PDF created with FinePrint pdfFactory Pro trial version http://www.fineprint.com

 5 4 3 2 1

BOM Option Table

Reference Description
+3V_A_TV_CRT +3V_A_TV_CRT
IV@ INT VGA
L33 IV@BLM18PG181SN1D_6
+3V EV@ EXT VGA
C427 C433 C434 R469 C437 C436
IHM@ INT HDMI
IV@10u/10V_8 [email protected]/10V_4 [email protected]/16V_4 EV@0_4 [email protected]/10V_4 [email protected]/16V_4

DR1
DR7

D D
+1.05V L36 IV@10uh_8 +1.05V L11 IV@10uh_8 +1.05VM_DPLLA
R165 R164
C175 + C488 C130 + C169
EV@0_4 EV@0_4 11/01 Del R3432
IV@220u/2.5V_7343 [email protected]/10V_4 IV@220u/2.5V_7343 [email protected]/10V_4
DR11 DR10

U23H
+1.05VM_DPLLB
VTT_1 U13 +1.05V
VTT_2 T13
+1.05V R37 0_6 +1.05VM_MCH_PLL2 R44 0_6 +1.05VM_HPLL B27 VCCA_CRT_DAC_1 VTT_3 U12 C52 C420 C422 C419 + C421
A26 VCCA_CRT_DAC_2 VTT_4 T12
C48 C50 U11 0.47u/6.3V_4 2.2u/6.3V_6 4.7u/10V_6 4.7u/10V_6 270u/2V_7343
VTT_5
VTT_6 T11
4.7u/10V_6 0.1u/10V_4 A25 U10

CRT
VCCA_DAC_BG VTT_7
B25 VSSA_DAC_BG VTT_8 T10
VTT_9 U9
VTT_10 T9
VTT_11 U8
L5 BLM18PG181SN1D_6 +1.05VM_MPLL +1.05VM_DPLLA F47 VCCA_DPLLA VTT_12 T8
U7

VTT
+1.05VM_DPLLB VTT_13 +1.05VM_AXF L31 0.1uh_8
L48 VCCA_DPLLB VTT_14 T7 +1.05V
VTT_15 U6
+1.05VM_HPLL AD1 T6 C424 C426

PLL
VCCA_HPLL VTT_16
VTT_17 U5
R42 *0.5/F_6 +1.05VM_MPLL_RC +1.05VM_MPLL AE1 VCCA_MPLL VTT_18 T5 1u/6.3V_4 *10u/10V_8
VTT_19 V3
C49 C38 U3
+1.8VSUS_TXLVDS VTT_20
J48 VCCA_LVDS VTT_21 V2
0.1u/10V_4 *22u/6.3V_8 U2

A LVDS
C487 VTT_22
J47 VSSA_LVDS VTT_23 T2
VTT_24 V1
IV@1000p/50V_4
VTT_25 U1 +1.8VSUS_VCC_SM_CK L32 1uh_8 +1.8VSUS

+1.5V R492 0_8 +1.5V_VCCA_PEG_BG AD48 VCCA_PEG_BG C429

+1.05V R39 0_6 +1.05VM_A_SM C492 1/F_4 R452 +1.8VSUS_SMCK_RC 12/19 REV_2A Chanhe net to +1.8VSUS
0.1u/10V_4

A PEG
C36 C77 C68 C66 C60 0.1u/10V_4
C C
+ +1.05VM_PEGPLL AA48 C425
100u/10V_7343 *10u/6.3V_8 10u/6.3V_8 4.7u/10V_6 1u/6.3V_4 VCCA_PEG_PLL
10u/10V_8

+1.05VM_A_SM AR20 VCCA_SM_1

AP20 VCCA_SM_2
AN20
AR17
AP17
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
POWER +1.8VSUS_TXLVDS L38 [email protected]_8 +1.8VSUS
AN17 VCCA_SM_6
+1.05V R109 0_6 +1.05VM_A_SM_CK AT16 VCCA_SM_7
AR16 R489 C493 C486

A SM
VCCA_SM_8
AP16 VCCA_SM_9
C92 C91 C86 EV@0_4 IV@1000p/50V_4 IV@10u/6.3V_8

*2.2u/6.3V_6 10u/6.3V_8 0.1u/10V_4 DR3 +1.05V

DR4

2
+1.05VM_A_SM_CK AP28 VCCA_SM_CK_1 +1.05VM_AXF CH751H-40PT
AN28 VCCA_SM_CK_2 VCC_AXF_1 B22
R458 IV@0_6 +3V_TV_DAC AP25 B21 D31

AXF
+3V VCCA_SM_CK_3 VCC_AXF_2
AN25 A21

1
VCCA_SM_CK_4 VCC_AXF_3
AN24 VCCA_SM_CK_5
C432 C431 R457 AM28 12/22 REV_2A Change D31 P/N
VCCA_SM_CK_NCTF_1 R481 10_4 +1.05V_SD
AM26

A CK
[email protected]/10V_4 [email protected]/16V_4 EV@0_4 VCCA_SM_CK_NCTF_2
AM25 VCCA_SM_CK_NCTF_3
AL25 BF21 +1.8VSUS_VCC_SM_CK
VCCA_SM_CK_NCTF_4 VCC_SM_CK_1 +3V_VCC_HV 0_6 R482
DR5 AM24 BH20

SM CK
VCCA_SM_CK_NCTF_5 VCC_SM_CK_2 +3V
AL24 VCCA_SM_CK_NCTF_6 VCC_SM_CK_3 BG20
AM23 BF20 C463
VCCA_SM_CK_NCTF_7 VCC_SM_CK_4
AL23 VCCA_SM_CK_NCTF_8 0.1u/10V_4

+1.5V R479 IV@0_6 +1.5V_VCC_HDA VCC_TX_LVDS K47 +1.8VSUS_TXLVDS +1.05V_VCC_PEG

+3V_TV_DAC B24
C459 R480 VCCA_TV_DAC_1 +3V_VCC_HV
IF iHDMI not used,HDA A24 VCCA_TV_DAC_2 VCC_HV_1 C35
+1.05V_VCC_PEG

TV
B35 R491 0_8 +1.05V
[email protected]/10V_4 EV@0_4 connect ot GND(DG1.0 P277) VCC_HV_2
A35

HV
VCC_HV_3 C164 C176
DR12 +1.5V_VCC_HDA A32 + C177
VCC_HDA

HDA
V48 +1.05V_VCC_PEG 4.7u/10V_6 10u/6.3V_8
VCC_PEG_1 220u/2.5V_7343
VCC_PEG_2 U48
B 02/28 REV_3A Modify V47 B

PEG
VCC_PEG_3
VCC_PEG_4 U47
+1.5V_TVDAC

D TV/CRT
+1.5V R474 0_6 +1.5V_TVDAC M25 U46
VCCD_TVDAC VCC_PEG_5
+1.5V_QDAC L28
C443 C442 VCCD_QDAC +1.05V_VCC_DMI +1.05V_VCC_DMI R183 0_8
AH48 +1.05V_VCC_PEG
+1.05VM_MCH_PLL2 VCC_DMI_1
AF1 VCCD_HPLL VCC_DMI_2 AF48
0.1u/10V_4 0.01u/16V_4 AH47 C491

DMI
+1.05VM_PEGPLL VCC_DMI_3
AA47 AG47
VCCD_PEG_PLL VCC_DMI_4 0.1u/10V_4
C45
+1.8VSUS_DLVDS M38 VCCD_LVDS_1

LVDS
0.1u/10V_4 L37 A8 *91nh_32X25
VCCD_LVDS_2 VTTLF1 L37
VTTLF2 L1 +1.05V
+1.5V_QDAC

VTTLF
+1.5V L34 IV@BLM18PG181SN1D_6 AB2
VTTLF3 C482
C47 C46 C51 C495 +
C457 C446 C447 R477 *220u/2.5V_7343
CANTIGA_1p2 0.47u/6.3V_4 0.47u/6.3V_4 0.47u/6.3V_4 *10u/10V_8
IV@10u/6.3V_8 [email protected]/10V_4 [email protected]/16V_4 EV@0_4

DR6

NB Power Status and max current table(2/3)(NB left side) EXT&INT VGA Power Plane Option table NB Power Status and max current table(3/3)(NB Right side)
POWER PLANE S0 S3 S4/S5 Voltage I(max) Note POWER PLANE EXT VGA INT VGA MARK POWER PLANE S0 S3 S4/S5 Voltage I(max) Note
+1.05V L35 BLM18PG181SN1D_6 +1.05VM_PEGPLL VCCA_CRT_DAC O X X +3.3V 73mA VCCA_CRT_DAC GND +3V DR1 VTT O X X +1.05V 852mA FSB at 1067MHz
C494 C485 O X X GND DR2 O X X
VCCA_DAC_BG +3.3V 5mA VCCD_LVDS +1.8VSUS VCCA_AXF +1.05V 322mA
0.1u/10V_4 0.1u/10V_4 O X X GND DR3 O O X
VCCA_DPLLA +1.05V 64.8mA VCC_TX_LVDS +1.8VSUS VCC_SM_CK(800) +1.8VSUS 124mA (DDRII-667) 120mA
VCCA_DPLLB O X X +1.05V 64.8mA VCCA_LVDS GND +1.8VSUS DR4 VCC_TX_LVDS O O X +1.8VSUS 119mA
VCCA_HPLL O X X +1.05V 24mA VCCD_TVDAC +1.5V +1.5V VCC_HV O X X +3V 106mA
R490 1/F_4 +1.05VM_PEGPLL_RC VCCA_MPLL O X X +1.05V 139.2mA VCCA_TV_DAC GND +3V DR5 VCC_PEG O X X +1.05V 1782mA
C490 O O X GND DR6 O X X
VCCA_LVDS +1.8VSUS 13.2mA VCCD_QDAC +1.5V VCC_DMI +1.05V 456mA
10u/10V_8 O X X GND DR7
VCCA_PEG_BG +1.5V 414uA VCCA_DAC_BG +3V
A (See NB EDS Rev:1.0 Section 10.1 for max current) A
VCCA_PEG_PLL O X X +1.05V 50mA VCC_AXG GND +1.05V DR8 Page 8
(See NB EDS Rev:1.0 Section 12.2 for DC voltage)
VCCA_SM(DDRII-800) O X X +1.05V 720mA (DDRII-667) 480mA VCC_AXG_NCTF GND +1.05V DR9 Page 8
+1.8VSUS R484 IV@0_6 +1.8VSUS_DLVDS VCCA_SM_CK(800) O X X +1.05V 26mA (DDRII-667) 24mA VCCA_DPLLA GND +1.05V DR10
VCCA_TV_DAC O X X +3.3V 79mA VCCA_DPLLB GND +1.05V DR11
C471 R483
VCC_HDA O X X +1.5V 50mA VCC_HDA GND +1.5V DR12 For iHDMI
IV@1u/6.3V_4 EV@0_4
VCCD_TVDAC O X X +1.5V 35mA
DR2 EXT VGA->Disable TV/CRT/LVDS/HDMI(See DG 1.0 P190 Table 103)
O X X
VCCD_QDAC +1.5V 125uA
INT VGA->Disable TV/Enable CRT( See DG1.0 P208 Table 118) Quanta Computer Inc.
VCCD_HPLL O X X +1.05V 157mA
INT VGA->Disable HDMI(See DG 1.0 P277 section 3.10.4) PROJECT : BL5M Montevina
VCCD_PEG_PLL O X X +1.05V 50mA Size Document Number Rev
1A
VCCD_LVDS O O X +1.8VSUS 60mA CLK. GEN./ CK505
Date: Tuesday, March 04, 2008 Sheet 9 of 37
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 5 4 3 2 1

BOM Option Table

U23I U23J
Reference Description
BG21 VSS_199 VSS_297 AH8 N/A N/A
AU48 VSS_1 VSS_100 AM36 L12 VSS_200 VSS_298 Y8
AR48 VSS_2 VSS_101 AE36 AW21 VSS_201 VSS_299 L8
AL48 VSS_3 VSS_102 P36 AU21 VSS_202 VSS_300 E8
BB47 VSS_4 VSS_103 L36 AP21 VSS_203 VSS_301 B8
AW47 VSS_5 VSS_104 J36 AN21 VSS_204 VSS_302 AY7
AN47 VSS_6 VSS_105 F36 AH21 VSS_205 VSS_303 AU7
AJ47 VSS_7 VSS_106 B36 AF21 VSS_206 VSS_304 AN7
AF47 AH35 AB21 AJ7
VSS_8 VSS_107 VSS_207 VSS_305
AD47 AA35 R21 AE7
D VSS_9 VSS_108 VSS_208 VSS_306 D
AB47 Y35 M21 AA7
VSS_10 VSS_109 VSS_209 VSS_307
Y47 U35 J21 N7
VSS_11 VSS_110 VSS_210 VSS_308
T47 T35 G21 J7
VSS_12 VSS_111 VSS_211 VSS_309
N47 BF34 BC20 BG6
VSS_13 VSS_112 VSS_212 VSS_310
L47 AM34 BA20 BD6
VSS_14 VSS_113 VSS_213 VSS_311
G47 AJ34 AW20 AV6
VSS_15 VSS_114 VSS_214 VSS_312
BD46 AF34 AT20 AT6
VSS_16 VSS_115 VSS_215 VSS_313
BA46 AE34 AJ20 AM6
VSS_17 VSS_116 VSS_216 VSS_314
AY46 W34 AG20 M6
VSS_18 VSS_117 VSS_217 VSS_315
AV46 B34 Y20 C6
VSS_19 VSS_118 VSS_218 VSS_316
AR46 A34 N20 BA5
VSS_20 VSS_119 VSS_219 VSS_317
AM46 BG33 K20 AH5
VSS_21 VSS_120 VSS_220 VSS_318
V46 BC33 F20 AD5
VSS_22 VSS_121 VSS_221 VSS_319
R46 BA33 C20 Y5
VSS_23 VSS_122 VSS_222 VSS_320
P46 AV33 A20 L5
VSS_24 VSS_123 VSS_223 VSS_321
H46 AR33 BG19 J5
VSS_25 VSS_124 VSS_224 VSS_322
F46 AL33 A18 H5
VSS_26 VSS_125 VSS_225 VSS_323
BF44 AH33 BG17 F5
VSS_27 VSS_126 VSS_226 VSS_324
AH44 AB33 BC17 BE4
VSS_28 VSS_127 VSS_227 VSS_325
AD44 P33 AW17
VSS_29 VSS_128 VSS_228
AA44 L33 AT17 BC3
Y44
U44
VSS_30
VSS_31
VSS_32
VSS_129
VSS_130
VSS_131
H33
N32
R17
M17
VSS_229
VSS_230
VSS_231
VSS VSS_327
VSS_328
VSS_329
AV3
AL3
T44 K32 H17 R3
M44
F44
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
F32
C32
C17
VSS_232
VSS_233
VSS_330
VSS_331
VSS_332
P3
F3
BC43 A31 BA16 BA2
VSS_36 VSS_135 VSS_235 VSS_333
AV43 AN29 AW2
VSS_37 VSS_136 VSS_334
AU43 T29 AU16 AU2
C
VSS_38 VSS_137 VSS_237 VSS_335
AM43 N29 AN16 AR2 C
VSS_39 VSS_138 VSS_238 VSS_336
J43 K29 N16 AP2
VSS_40 VSS_139 VSS_239 VSS_337
C43 H29 K16 AJ2
VSS_41 VSS_140 VSS_240 VSS_338
BG42 F29 G16 AH2
VSS_42 VSS_141 VSS_241 VSS_339
AY42 A29 E16 AF2
VSS_43 VSS_142 VSS_242 VSS_340
AT42 BG28 BG15 AE2
VSS_44 VSS_143 VSS_243 VSS_341
AN42 BD28 AC15 AD2
VSS_45 VSS_144 VSS_244 VSS_342
AJ42 BA28 W15 AC2
VSS_46 VSS_145 VSS_245 VSS_343
AE42 AV28 A15 Y2
VSS_47 VSS_146 VSS_246 VSS_344
N42 AT28 BG14 M2
VSS_48 VSS_147 VSS_247 VSS_345
L42 AR28 AA14 K2
VSS_49 VSS_148 VSS_248 VSS_346
BD41 AJ28 C14 AM1
VSS_50 VSS_149 VSS_249 VSS_347
AU41 AG28 BG13 AA1
VSS_51 VSS_150 VSS_250 VSS_348
AM41 AE28 BC13 P1
VSS_52 VSS_151 VSS_251 VSS_349
AH41 AB28 BA13 H1
VSS_53 VSS_152 VSS_252 VSS_350
AD41 Y28
VSS_54 VSS_153 MCH_VSS_351 R106 0_4
AA41 P28 U24
VSS_55 VSS_154 VSS_351 MCH_VSS_352 R120 0_4
Y41 K28 AN13 U28
VSS_56 VSS_155 VSS_255 VSS_352 MCH_VSS_353 R97 0_4
U41 H28 AJ13 U25
VSS_57 VSS_156 VSS_256 VSS_353 MCH_VSS_354 R130 0_4
T41 F28 AE13 U29
VSS_58 VSS_157 VSS_257 VSS_354 MCH_VSS_355 R46 0_4
M41 C28 N13 AJ6
VSS_59 VSS_158 VSS_258 VSS_355
G41 BF26 L13
VSS_60 VSS_159 VSS_259
B41 AH26 G13 AF32
VSS_61 VSS_160 VSS_260 VSS_NCTF_1
BG40 AF26 E13 AB32
VSS_62 VSS_161 VSS_261 VSS_NCTF_2
BB40 AB26 BF12 V32
VSS_63 VSS_162 VSS_262 VSS_NCTF_3
AV40 VSS_64 VSS_163 AA26 AV12 VSS_263 VSS_NCTF_4 AJ30
AN40 VSS_65 VSS_164 C26 AT12 VSS_264 VSS_NCTF_5 AM29
H40 B26 AM12 AF29
VSS_66 VSS_165 VSS_265 VSS_NCTF_6
E40 BH25 AA12 AB29

VSS NCTF
VSS_67 VSS_166 VSS_266 VSS_NCTF_7
AT39 BD25 J12 U26
B VSS_68 VSS_167 VSS_267 VSS_NCTF_8 B
AM39 VSS_69 VSS_168 BB25 A12 VSS_268 VSS_NCTF_9 U23
AJ39 VSS_70 VSS_169 AV25 BD11 VSS_269 VSS_NCTF_10 AL20
AE39 AR25 BB11 V20
VSS_71 VSS_170 VSS_270 VSS_NCTF_11
N39 VSS_72 VSS_171 AJ25 AY11 VSS_271 VSS_NCTF_12 AC19
L39 AC25 AN11 AL17
VSS_73 VSS_172 VSS_272 VSS_NCTF_13
B39 VSS_74 VSS_173 Y25 AH11 VSS_273 VSS_NCTF_14 AJ17
BH38 N25 AA17
VSS_75 VSS_174 VSS_NCTF_15
BC38 VSS_76 VSS_175 L25 Y11 VSS_275 VSS_NCTF_16 U17
BA38 J25 N11
VSS_77 VSS_176 VSS_276
AU38 VSS_78 VSS_177 G25 G11 VSS_277 VSS_SCB_1 BH48
AH38 E25 C11 BH1

VSS SCB
VSS_79 VSS_178 VSS_278 VSS_SCB_2
AD38 VSS_80 VSS_179 BF24 BG10 VSS_279 VSS_SCB_3 A48
AA38 AD12 AV10 C1
VSS_81 VSS_180 VSS_280 VSS_SCB_4
Y38 VSS_82 VSS_181 AY24 AT10 VSS_281
U38 AT24 AJ10 A3
VSS_83 VSS_182 VSS_282 VSS_SCB_6
T38 VSS_84 VSS_183 AJ24 AE10 VSS_283
J38 AH24 AA10 E1
VSS_85 VSS_184 VSS_284 NC_26
F38 VSS_86 VSS_185 AF24 M10 VSS_285 NC_27 D2
C38 AB24 BF9 C3
VSS_87 VSS_186 VSS_286 NC_28
BF37 VSS_88 VSS_187 R24 BC9 VSS_287 NC_29 B4
BB37 L24 AN9 A5
VSS_89 VSS_188 VSS_288 NC_30
AW37 VSS_90 VSS_189 K24 AM9 VSS_289 NC_31 A6
AT37 J24 AD9 A43
VSS_91 VSS_190 VSS_290 NC_32
AN37 VSS_92 VSS_191 G24 G9 VSS_291 NC_33 A44
AJ37 F24 B9 B45
NC
VSS_93 VSS_192 VSS_292 NC_34
H37 E24 BH8 C46
VSS_94 VSS_193 VSS_293 NC_35
C37 BH23 BB8 D47
VSS_95 VSS_194 VSS_294 NC_36
BG36 VSS_96 VSS_195 AG23 AV8 VSS_295 NC_37 B47
BD36 Y23 AT8 A46
A
VSS_97 VSS_196 VSS_296 NC_38
AK15 VSS_98 VSS_197 B23 NC_39 F48 A
AU36 A23 E48
VSS_99 VSS_198 NC_40
C48
NC_41
B48
CANTIGA_1p2 NC_42
A47
NC_43
CANTIGA_1p2
Quanta Computer Inc.
PROJECT : BL5M Montevina
Size Document Number Rev
1A
CLK. GEN./ CK505
Date: Tuesday, March 04, 2008 Sheet 10 of 37
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 5 4 3 2 1

North Bridge Strap Pin Configuration Table BOM Option Table

Reference Description
(See DG 1.0 P295 Table 184) N/A N/A
(See NB EDS 1.0 P187 Table 74)

Pin Name Strap description Configuration PU<4.02K> PD <2.21K> Note

D CFG[2:0] FSB Frequency Select [000]= FSB 1066MHz [010] = FSB 800MHz [011] = FSB 667MHz See Page 2 FSB selection table D

CFG[4:3] Reserved

DMI X2 Select 0 = DMI X2 R93 *4.02K/F_4

CFG5 (6) MCH_CFG_5
1 = DMI X4(Default)

iTPM Host Interface 0 = iTPM Host Interface is enabled R99 *10K/F_4

CFG6 (6) MCH_CFG_6
1 = iTPM Host Interface is disabled(Default)

0 = AMT Firmware will use TLS cipher suite with no confidentiality R98 *4.02K/F_4
CFG7 ME TLS Confidentiality (6) MCH_CFG_7
1 = AMT Firmware will use TLS cipher suite with confidentiality(Default)

CFG8 Reserved

PCI Express Graphics 0 = Reverse Lanes R454 *4.02K/F_4

CFG9 (6) MCH_CFG_9
Lane Reversal 1 = Normal operation(Default)

PCIE Loopback enable 0 = Enabled R455 *4.02K/F_4

C CFG10 (6) MCH_CFG_10 C
1 = Disabled (Default)

CFG11 Reserved

ALLZ 0 = ALLZ mode enable R76 *4.02K/F_4

CFG12 (6) MCH_CFG_12
1 = disable(Default)

XOR 0 = XOR mode enable R77 *4.02K/F_4

CFG13 (6) MCH_CFG_13
1 = disable(Default)

CFG[15:14] Reserved

FSB Dynamic ODT 0 = Dynamic ODT disable R75 *4.02K/F_4

CFG16 (6) MCH_CFG_16
1 = Dynamic ODT Enable(Default)

CFG[18:17] Reserved

DMI Lane Reversal 0 = Normal (Default) R72 *4.02K/F_4

B CFG19 (6) MCH_CFG_19 +3V B
1 = Lanes Reversed

0 = Only Digital Display port (SDVO/DP/iHDMI) or PCIE is

Digital Display Port
operational (Default) R73 *4.02K/F_4
CFG20 (SDVO/DP/iHDMI) (6) MCH_CFG_20 +3V
1 = Digital Display port (SDVO/DP/iHDMI) and PCIE are operating
Concurrent with PCIE
simultaneously via PEG port

SDVO Present 0 = No SDVO/HDMI/DP Device Present(Default) R146 *2.2K/F_4

SDVO_CTRLDATA (6,20) SDVO_CTRLDATA +3V
1 = SDVO/HDMI/DP Device present

L_DDC_DATA Local Flat Panel(LFP) Present 0 = LFP Disable(Default) R166 *2.2K/F_4

(6,18) INT_LVDS_EDIDDATA +3V
1 = LFP Card Present;PCIE disable

DDPC_CTRLDATA Digital Display Present 0 = Digital display(HDMI/DP) device absent(Default) R71 *2.2K/F_4
(6) DDPC_CTRLDATA +3V
1 = Digital display(HDMI/DP) device present

Enable iTPM Table

A A

PAGE Net Name PU & PD NOTE

11 MCH_CFG_6 PD 10K to GND NB Strap pin
13 SPI_MOSI PU 20K to +3V_S5 SB Strap pin
Quanta Computer Inc.
14 CLGPIO5 PU 10K to +3V_S5 SB Strap pin
PROJECT : BL5M Montevina
Size Document Number Rev
1A
CLK. GEN./ CK505
Date: Monday, March 10, 2008 Sheet 11 of 37
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 1 2 3 4 5 6 7 8

DDR2 Dual channel A/B PU

A A
M_A_A[13..0]
M_A_A[13..0] (7,13)
M_B_A[13..0]
M_B_A[13..0] (7,13)
DDRII A CHANNEL DDRII B CHANNEL
+SMDDR_VTERM +SMDDR_VTERM

C83 C131 C90 C168 C125 C150 C85 C94 C135 C156 C84 C157 C87 C167 C143 C88 C102 C93 C152 C163 C171 C124 C101 C147 C158 C122

0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4

B B

M_A_A3 RP17 1 2 56X2 +SMDDR_VTERM

M_A_A1 3 4

M_A_A9 RP22 1 2 56X2 M_A_A7 RP23 1 2 56X2 +SMDDR_VTERM

M_A_A8 3 4 M_A_A11 3 4

M_A_A2 RP20 1 2 56X2 M_B_A9 RP31 1 2 56X2

M_A_A4 3 4 3 4
(6,13) M_CKE3

RP29 1 2 56X2 RP6 1 2 56X2

(6,13) M_CKE1 (6,13) M_ODT1
M_A_A6 3 4 3 4
(6,13) M_CS#1

RP25 1 2 56X2
(7,13) M_A_BS#2
M_A_A5 3 4 RP7 1 2 56X2
(6,13) M_ODT3
(6,13) M_CS#3 3 4

M_A_A12 RP30 1 2 56X2

3 4 RP16 1 2 56X2
(6,13) M_CKE0 (7,13) M_A_BS#0
M_A_A10 3 4
M_A_A0 RP15 1 2 56X2
3 4 RP12 1 2 56X2
(7,13) M_A_BS#1 (7,13) M_A_WE#
(7,13) M_A_CAS# 3 4
C C
RP11 1 2 56X2
(6,13) M_CS#0
(7,13) M_A_RAS# 3 4
M_B_A10 RP14 1 2 56X2 +SMDDR_VTERM
3 4 (7,13) M_B_WE# RP10 1 2 56X2
(7,13) M_B_BS#0
(7,13) M_B_CAS# 3 4

M_B_A3 RP19 1 2 56X2

M_B_A5 3 4 RP28 1 2 56X2
(6,13) M_CKE4
M_B_A6 3 4

RP13 1 2 56X2
(7,13) M_B_BS#1 M_B_A0 3 4 (6,13) M_ODT2 RP9 1 2 56X2
(7,13) M_B_RAS# 3 4
M_B_A7 RP21 1 2 56X2
M_B_A11 3 4 M_A_A13 RP5 1 2 56X2
(6,13) M_ODT0 3 4
M_B_A8 RP24 1 2 56X2
M_B_A1 3 4 RP8 1 2 56X2
(6,13) M_CS#2
M_B_A13 3 4
M_B_A4 RP18 1 2 56X2
M_B_A2 3 4

(7,13) M_B_BS#2 RP26 1 2 56X2

D M_B_A12 3 4 D

R151 56_4 +SMDDR_VTERM

Quanta Computer Inc.
(7,13) M_A_A14
R148 56_4
(7,13) M_B_A14 PROJECT : BL5M Montevina
Size Document Number Rev
1A
DDR RES. ARRAY
Date: Monday, March 10, 2008 Sheet 12 of 37
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 1 2 3 4 5 6 7 8

DDR2 Dual channel A/B

SMDDR_VREF_DIMM
M_A_DM[0..7] (7)
SMDDR_VREF_DIMM
M_B_DM[0..7] (7)

CONN
M_A_DQ[0..63] (7) M_B_DQ[0..63] (7)
+1.8VSUS
M_A_DQS[0..7] (7) M_B_DQS[0..7] (7)
+1.8VSUS +1.8VSUS +1.8VSUS +1.8VSUS
M_A_DQS#[0..7] (7) M_B_DQS#[0..7] (7)
CN21
M_A_A[0..13] (7,12) M_B_A[0..13] (7,12)
CN22 1 2
VREF VSS46 M_B_DQ4
1 VREF VSS46 2 3 VSS47 DQ4 4
3 4 M_A_DQ1 M_B_DQ5 5 6 M_B_DQ1
M_A_DQ4 VSS47 DQ4 M_A_DQ5 M_B_DQ0 DQ0 DQ5 + C441 C149 C119 C461 C458 C105
5 DQ0 DQ5 6 7 DQ1 VSS15 8
M_A_DQ0 7 8 9 10 M_B_DM0
DQ1 VSS15 M_A_DM0 M_B_DQS#0 VSS37 DM0 *330u/2.5V_3528 2.2u/6.3V_6 2.2u/6.3V_6 2.2u/6.3V_6 2.2u/6.3V_6 2.2u/6.3V_6
9 VSS37 DM0 10 11 DQS#0 VSS5 12
M_A_DQS#0 11 12 M_B_DQS0 13 14 M_B_DQ7
M_A_DQS0 DQS#0 VSS5 M_A_DQ2 DQS0 DQ6 M_B_DQ2
13 14 15 16
DQS0 DQ6 M_A_DQ3 M_B_DQ3 VSS48 DQ7 +3V
15 16 17 18
M_A_DQ7 VSS48 DQ7 M_B_DQ6 DQ2 VSS16 M_B_DQ8 +1.8VSUS
17 18 19 20
A M_A_DQ6 DQ2 VSS16 M_A_DQ9 DQ3 DQ12 M_B_DQ9 A
19 20 21 22
DQ3 DQ12 M_A_DQ8 M_B_DQ13 VSS38 DQ13
21 22 23 24
M_A_DQ13 VSS38 DQ13 M_B_DQ12 DQ8 VSS17 M_B_DM1 C34 C32
23 24 25 26
M_A_DQ12 DQ8 VSS17 M_A_DM1 DQ9 DM1 C95 C123 C445 C103
25 26 27 28
DQ9 DM1 M_B_DQS#1 VSS49 VSS53 2.2u/6.3V_6 0.1u/10V_4
27 28 29 30 M_CLK_DDR3 (6)
M_A_DQS#1 VSS49 VSS53 M_B_DQS1 DQS#1 CK0 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4
29 30 M_CLK_DDR0 (6) 31 32 M_CLK_DDR#3 (6)
M_A_DQS1 DQS#1 CK0 DQS1 CK0#
31 32 M_CLK_DDR#0 (6) 33 34
DQS1 CK0# M_B_DQ11 VSS39 VSS41 M_B_DQ14
33 34 35 36
M_A_DQ14 VSS39 VSS41 M_A_DQ11 M_B_DQ10 DQ10 DQ14 M_B_DQ15 SMDDR_VREF_DIMM
35 36 37 38
M_A_DQ15 DQ10 DQ14 M_A_DQ10 DQ11 DQ15
37 38 39 40
DQ11 DQ15 VSS50 VSS54
39 40
VSS50 VSS54
41 42

PC4800 DDR2 SDRAM

M_B_DQ16 VSS18 VSS20 M_B_DQ17 C217 C213
41 42 43 44
M_A_DQ21 VSS18 VSS20 M_A_DQ20 M_B_DQ19 DQ16 DQ20 M_B_DQ20
43 44 45 46
M_A_DQ16 DQ16 DQ20 M_A_DQ17 DQ17 DQ21 0.1u/10V_4 2.2u/6.3V_6

PC4800 DDR2 SDRAM

45 46 47 48
DQ17 DQ21 M_B_DQS#2 VSS1 VSS6
47 48 49 50 PM_EXTTS#1 (6)
M_A_DQS#2 VSS1 VSS6 M_B_DQS2 DQS#2 NC3 M_B_DM2
49
DQS#2 NC3
50 PM_EXTTS#0 (6) 51
DQS2 DM2
52 Close to DIMM0
M_A_DQS2 51 52 M_A_DM2 53 54
SO-DIMM (200P)
DQS2 DM2 M_B_DQ22 VSS19 VSS21 M_B_DQ18
53 54 55 56
M_A_DQ23 VSS19 VSS21 M_A_DQ19 M_B_DQ23 DQ18 DQ22 M_B_DQ21
55 56 57 58
M_A_DQ18 DQ18 DQ22 M_A_DQ22 DQ19 DQ23

SO-DIMM (200P)
57 58 59 60
DQ19 DQ23 M_B_DQ24 VSS22 VSS24 M_B_DQ28
59 60 61 62
M_A_DQ25 VSS22 VSS24 M_A_DQ29 M_B_DQ25 DQ24 DQ28 M_B_DQ29
61 62 63 64
M_A_DQ24 DQ24 DQ28 M_A_DQ28 DQ25 DQ29 +1.8VSUS
63 64 65 66
DQ25 DQ29 M_B_DM3 VSS23 VSS25 M_B_DQS#3
65 66 67 68
M_A_DM3 VSS23 VSS25 M_A_DQS#3 DM3 DQS#3 M_B_DQS3
67 68 69 70
DM3 DQS#3 M_A_DQS3 NC4 DQS3
69 70 71 72
NC4 DQS3 M_B_DQ26 VSS9 VSS10 M_B_DQ30
71 72 73 74
M_A_DQ26 VSS9 VSS10 M_A_DQ30 M_B_DQ27 DQ26 DQ30 M_B_DQ31 + C448 C474 C439 C136 C472 C129
73 74 75 76
M_A_DQ27 DQ26 DQ30 M_A_DQ31 DQ27 DQ31
75 76 77 78
DQ27 DQ31 VSS4 VSS8 *330u/2.5V_3528 2.2u/6.3V_6 2.2u/6.3V_6 2.2u/6.3V_6 2.2u/6.3V_6 2.2u/6.3V_6
77 78 (6,12) M_CKE3 79 80 M_CKE4 (6,12)
VSS4 VSS8 CKE0 CKE1
(6,12) M_CKE0 79 80 M_CKE1 (6,12) 81 82
B CKE0 CKE1 VDD7 VDD8 B
81 82 83 84
VDD7 VDD8 NC1 A15
83 84 (7,12) M_B_BS#2 85 86 M_B_A14 (7,12)
NC1 A15 A16_BA2 A14 +3V
(7,12) M_A_BS#2 85 86 M_A_A14 (7,12) 87 88
A16_BA2 A14 M_B_A12 VDD9 VDD11 M_B_A11
87 88 89 90
M_A_A12 VDD9 VDD11 M_A_A11 M_B_A9 A12 A11 M_B_A7
89 90 91 92
M_A_A9 A12 A11 M_A_A7 M_B_A8 A9 A7 M_B_A6 +1.8VSUS
91 92 INTEL FAE (08/17) 93 94
M_A_A8 A9 A7 M_A_A6 A8 A6 C35 C33
93 94 95 96
95
A8 A6
96
ADD MA14 FOR DUAL LAYERS RAM M_B_A5 97
VDD5 VDD4
98 M_B_A4
M_A_A5 VDD5 VDD4 M_A_A4 M_B_A3 A5 A4 M_B_A2 2.2u/6.3V_6 0.1u/10V_4
97 98 99 100
M_A_A3 A5 A4 M_A_A2 M_B_A1 A3 A2 M_B_A0 C112 C145 C132 C154 SMDDR_VREF_DIMM
99 100 101 102
M_A_A1 A3 A2 M_A_A0 A1 A0
101 102 103 104
A1 A0 M_B_A10 VDD10 VDD12 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4
103 104 105 106 M_B_BS#1 (7,12)
M_A_A10 VDD10 VDD12 A10/AP BA1
105 106 M_A_BS#1 (7,12) (7,12) M_B_BS#0 107 108 M_B_RAS# (7,12)
A10/AP BA1 BA0 RAS# C214 C212
(7,12) M_A_BS#0 107 108 M_A_RAS# (7,12) (7,12) M_B_WE# 109 110 M_CS#2 (6,12)
BA0 RAS# WE# S0#
(7,12) M_A_WE# 109 110 M_CS#0 (6,12) 111 112
WE# S0# VDD2 VDD1 0.1u/10V_4 2.2u/6.3V_6
111 112 (7,12) M_B_CAS# 113 114 M_ODT2 (6,12)
VDD2 VDD1 CAS# ODT0 M_B_A13
(7,12) M_A_CAS# 113 114 M_ODT0 (6,12) (6,12) M_CS#3 115 116
CAS# ODT0 M_A_A13 S1# A13
(6,12) M_CS#1 115
S1# A13
116 117
VDD3 VDD6
118 Close to DIMM1
117 118 (6,12) M_ODT3 119 120
VDD3 VDD6 ODT1 NC2
(6,12) M_ODT1 119 120 121 122
ODT1 NC2 M_B_DQ37 VSS11 VSS12 M_B_DQ32
121 122 123 124
M_A_DQ36 VSS11 VSS12 M_A_DQ32 M_B_DQ33 DQ32 DQ36 M_B_DQ36
123 124 125 126
M_A_DQ37 DQ32 DQ36 M_A_DQ33 DQ33 DQ37
125 126 127 128
DQ33 DQ37 M_B_DQS#4 VSS26 VSS28 M_B_DM4
127 128 129 130
M_A_DQS#4 VSS26 VSS28 M_A_DM4 M_B_DQS4 DQS#4 DM4
129 130 131 132
M_A_DQS4 DQS#4 DM4 DQS4 VSS42 M_B_DQ38
131 132 133 134
DQS4 VSS42 M_A_DQ38 M_B_DQ39 VSS2 DQ38 M_B_DQ34
133 VSS2 DQ38 134 135 DQ34 DQ39 136
M_A_DQ35 135 136 M_A_DQ39 M_B_DQ35 137 138
M_A_DQ34 DQ34 DQ39 DQ35 VSS55 M_B_DQ40
137 138 139 140
DQ35 VSS55 M_A_DQ44 M_B_DQ45 VSS27 DQ44 M_B_DQ41
139 VSS27 DQ44 140 141 DQ40 DQ45 142
M_A_DQ41 141 142 M_A_DQ45 M_B_DQ44 143 144
M_A_DQ40 DQ40 DQ45 DQ41 VSS43 M_B_DQS#5
143 DQ41 VSS43 144 145 VSS29 DQS#5 146
C 145 146 M_A_DQS#5 M_B_DM5 147 148 M_B_DQS5 C
M_A_DM5 VSS29 DQS#5 M_A_DQS5 DM5 DQS5
147 DM5 DQS5 148 149 VSS51 VSS56 150
149 150 M_B_DQ47 151 152 M_B_DQ42
M_A_DQ47 VSS51 VSS56 M_A_DQ46 M_B_DQ46 DQ42 DQ46 M_B_DQ43
151 152 153 154
M_A_DQ43 DQ42 DQ46 M_A_DQ42 DQ43 DQ47
153 DQ43 DQ47 154 155 VSS40 VSS44 156
155 156 M_B_DQ53 157 158 M_B_DQ48
M_A_DQ49 VSS40 VSS44 M_A_DQ53 M_B_DQ49 DQ48 DQ52 M_B_DQ52
157 DQ48 DQ52 158 159 DQ49 DQ53 160
M_A_DQ48 159 160 M_A_DQ52 161 162 CGCLK_SMB CGCLK_SMB (2)
DQ49 DQ53 VSS52 VSS57
161 162 163 164 M_CLK_DDR4 (6)
VSS52 VSS57 NCTEST CK1 CGDAT_SMB
163 NCTEST CK1 164 M_CLK_DDR1 (6) 165 VSS30 CK1# 166 M_CLK_DDR#4 (6) CGDAT_SMB (2)
165 166 M_B_DQS#6 167 168
VSS30 CK1# M_CLK_DDR#1 (6) DQS#6 VSS45
M_A_DQS#6 167 168 M_B_DQS6 169 170 M_B_DM6
M_A_DQS6 DQS#6 VSS45 M_A_DM6 DQS6 DM6
169 170 171 172
DQS6 DM6 M_B_DQ54 VSS31 VSS32 M_B_DQ50
171 VSS31 VSS32 172 173 DQ50 DQ54 174
M_A_DQ50 173 174 M_A_DQ55 M_B_DQ51 175 176 M_B_DQ55
M_A_DQ51 DQ50 DQ54 M_A_DQ54 DQ51 DQ55
175 176 177 178
DQ51 DQ55 M_B_DQ56 VSS33 VSS35 M_B_DQ60
177 VSS33 VSS35 178 179 DQ56 DQ60 180
M_A_DQ60 179 180 M_A_DQ57 M_B_DQ61 181 182 M_B_DQ57
M_A_DQ61 DQ56 DQ60 M_A_DQ56 DQ57 DQ61
181 DQ57 DQ61 182 183 VSS3 VSS7 184
183 184 M_B_DM7 185 186 M_B_DQS#7
M_A_DM7 VSS3 VSS7 M_A_DQS#7 DM7 DQS#7 M_B_DQS7
185 DM7 DQS#7 186 187 VSS34 DQS7 188
187 188 M_A_DQS7 M_B_DQ58 189 190
M_A_DQ58 VSS34 DQS7 M_B_DQ63 DQ58 VSS36 M_B_DQ59
189 190 191 192
M_A_DQ59 DQ58 VSS36 M_A_DQ63 DQ59 DQ62 M_B_DQ62 SMDDR_VREF_DIMM
191 DQ59 DQ62 192 193 VSS14 DQ63 194
193 194 M_A_DQ62 CGDAT_SMB 195 196
CGDAT_SMB VSS14 DQ63 CGCLK_SMB SDA VSS13 R38 10K_4
195 196 197 198
CGCLK_SMB SDA VSS13 R36 10K_4 +3V SCL SA0 R35 10K_4
197 198 199 200
+3V SCL SA0 R34 10K_4 VDD(SPD) SA1
+3V 199 200
VDD(SPD) SA1 TYCO_292532-4 R221 0_6
+3V +SMDDR_VREF
TYCO_1775803-2
SO-DIMM0 SPD Address is 0xA0 SO-DIMM1 SPD Address is 0xA4
SO-DIMM0 TS Address is 0x30 SO-DIMM1 TS Address is 0x34 R222 *10K_4 R220 *10K_4 +1.8VSUS
D D

Standard Type H: 6.5mm Standard Type H: 11mm

CLOCK 0,1 CLOCK 3,4
CKE 0,1 CKE 2,3 Quanta Computer Inc.
PROJECT : BL5M Montevina
Size Document Number Rev
1A
DDR SO-DIMM(200P)
Date: Monday, March 10, 2008 Sheet 13 of 37
1 2 3 4 5 6 7 8

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 5 4 3 2 1

RTC Layout note:

BOM Option Table
CRYSTAL DPRSTP# , Daisy Chain
(SB>Power>NB>CPU)
Reference Description
LDRQ0/1# : Internal PU IHM@ INT HDMI
C248 10p/50V_4 CLK_32KX1 U35A
CLK_32KX1 C23 K5 LAD0
RTCX1 FWH0/LAD0 LAD0 (25,29)

2
1
CLK_32KX2 C24 K4 LAD1
RTCX2 FWH1/LAD1 LAD1 (25,29)
R288 L6 LAD2
32.768KHZ FWH2/LAD2 LAD2 (25,29) +1.05V_ICH_IO
RTC_RST# A25 K2 LAD3
Y2 RTCRST# FWH3/LAD3 LAD3 (25,29)
10M_6 SRTC_RST#

RTC
LPC
F20 SRTCRST#
SM_INTRUDER# C22 K3 LFRAME#
LFRAME# (25,29)
3
4
C235 10p/50V_4 CLK_32KX2 INTRUDER# FWH4/LFRAME#
B22 J3 LDRQ#0
D INTVRMEN LDRQ0# T88 +1.05V_ICH_IO D
ICH_INTVRMEN A22 J1 LDRQ#1 R608 R378
LAN100_SLP LDRQ1#/GPIO23 LDRQ#1 (25)
*56_4 *56_4
E25 N7 GATEA20 GATEA20 (29)
GLAN_CLK A20GATE H_A20M#
A20M# AJ27 H_A20M# (3)
C13 R607
LAN_RSTSYNC
RESET F14
DPRSTP# AJ25
AE23
H_DPRSTP#_R
H_DPSLP#_R
R588
R367
0_4
0_4
ICH_DPRSTP# (3,6,32) 56_4

LAN / GLAN
LAN_RXD0 DPSLP# H_DPSLP# (3)
JUMP G13
D14
LAN_RXD1
AJ26 H_FERR#_R R587 56_4 H_FERR#
VCCRTC LAN_RXD2 FERR# H_FERR# (3)
An RC delay circuit with a time delay in the range
of 18 ms to 25 ms should be provided D13 AD22 H_PWRGD
LAN_TXD0 CPUPWRGD H_PWRGD (3)
D12 LAN_TXD1
R527 20K_6 RTC_RST# E13 AF25 H_IGNNE# +3V
LAN_TXD2 IGNNE# H_IGNNE# (3)

CPU
1

C520 ICH_GPIO56 B10 AE22 H_INIT#

GPIO56 INIT# H_INIT# (3) +1.05V_ICH_IO
G2 AG25 H_INTR GATEA20 R329 8.2K_4
INTR H_INTR (3)
1u/6.3V_4 *SHORT_ PAD B28 L3 RCIN# RCIN# (29)
GLAN_COMP GLAN_COMPI RCIN# RCIN# R545 10K_4
B27
2

GLAN_COMPO H_NMI
NMI AF23 H_NMI (3)
HDA_BIT_CLK_R AF6 AF24 H_SMI#_R R370 0_4 H_SMI# R606
HDA_BIT_CLK SMI# H_SMI# (3)
HDA_SYNC_R AH4 56_4
VCCRTC HDA_SYNC H_STPCLK#
STPCLK# AH27 H_STPCLK# (3)
HDA_RST#_R AE7 HDA_RST# H_THERMTRIP_R R586 56_4 H_THERMTRIP_RR R585 *0_4 PM_THRMTRIP#
THRMTRIP# AG26 PM_THRMTRIP# (3,6)
R250 20K_6 SRTC_RST# ACZ_SDIN0 AF4
(26) ACZ_SDIN0 HDA_SDIN0
HDA_SDIN1 AG4 AG27 ICH_TP12
HDA_SDIN1 TP12 T150
1

HDA_SDIN2

IHDA
AH3 HDA_SDIN2 Layout note:
C233 G1 HDA_SDIN3 AE5 PU R needs to placed within 2" of ICH9-M,
1u/6.3V_4 T95 HDA_SDIN3 SATA_RXN4_C
*SHORT_ PAD SATA4RXN AH11 series R must be placed within 2"of PU R w/o stub.
HDA_SDOUT_R AG5 AJ11 SATA_RXP4_C
2

HDA_SDOUT SATA4RXP SATA_TXN4_C

SATA4TXN AG12
ICH_GPIO33 AG7 AF12 SATA_TXP4_C
C T146 ICH_GPIO34 HDA_DOCK_EN#/GPIO33 SATA4TXP C
AE8 HDA_DOCK_RST#/GPIO34
T93 AH9 SATA_RXN5_C 02/14 REV_3A Swap SATA chennal
SATA_LED# SATA5RXN SATA_RXP5_C
(22) SATA_LED# AG8 SATALED# SATA5RXP AJ9
AE10 SATA_TXN5_C
SATA_RXN0_C SATA5TXN SATA_TXP5_C
AJ16 SATA0RXN SATA5TXP AF10 12/18 REV_2A Swap SATA chennal
SATA_RXP0_C AH16
SATA I/F

SATA
SATA_TXN0_C SATA0RXP CLK_PCIE_SATA# SATA_RXN0 C572 3900p/25V_4 SATA_RXN4_C
AF17 SATA0TXN SATA_CLKN AH18 CLK_PCIE_SATA# (2) (22) SATA_RXN0
VCCRTC SATA_TXP0_C AG17 SATA0TXP SATA_CLKP AJ18 CLK_PCIE_SATA
CLK_PCIE_SATA (2) To 2'nd SATA HDD (22) SATA_RXP0
SATA_RXP0 C571 3900p/25V_4 SATA_RXP4_C
(DG 1.0 Table-292) SATA_TXN0 C569 3900p/25V_4 SATA_TXN4_C
(22) SATA_TXN0
R530 1M_4 SM_INTRUDER# SATA_RXN1_C AH13 AJ7 SATA_TXP0 C570 3900p/25V_4 SATA_TXP4_C
SATA1RXN SATARBIAS# (22) SATA_TXP0
Internal VRM enabled for SATA_RXP1_C AJ13 AH7 SATA_RBIAS_PN
R262 332K/F_4 ICH_INTVRMEN SATA_TXN1_C SATA1RXP SATARBIAS
VccSus1_05, VccSus1_5, AG14
SATA_TXP1_C SATA1TXN
VccCL1_5, VccLAN1_05 and AF14 SATA1TXP R596 SATA_RXN1 C568 3900p/25V_4 SATA_RXN0_C
VccCL1_05. (22) SATA_RXN1
ICH9M REV 1.0 To 1'st SATA HDD (22) SATA_RXP1
SATA_RXP1 C567 3900p/25V_4 SATA_RXP0_C
SATA_RBIAS_PN<0.5".Avoid routing 24.9/F_4 SATA_TXN1 C565 3900p/25V_4 SATA_TXN0_C
(22) SATA_TXN1
next to clock/high speed signals SATA_TXP1 C566 3900p/25V_4 SATA_TXP0_C
+3V_S5 (22) SATA_TXP1

R525 10K_4 ICH_GPIO56

(22) SATA_RXN4 SATA_RXN4 C348 3900p/25V_4 SATA_RXN1_C
To SATA ODD (22) SATA_RXP4 SATA_RXP4 C347 3900p/25V_4 SATA_RXP1_C
SATA_TXN4 C365 3900p/25V_4 SATA_TXN1_C
(22) SATA_TXN4
SATA_TXP4 C366 3900p/25V_4 SATA_TXP1_C
(22) SATA_TXP4

+1.5V_PCIE_ICH
SATA_RXN5 C350 3900p/25V_4 SATA_RXN5_C
(19) SATA_RXN5
R293 24.9/F_4 GLAN_COMP 24.9 Ohm pull up to 1.5V for To E-SATA (19) SATA_RXP5
SATA_RXP5 C349 3900p/25V_4 SATA_RXP5_C
GLAN_COMPI/O is required, no SATA_TXN5 C352 3900p/25V_4 SATA_TXN5_C
(19) SATA_TXN5
matter intel LAN is used or not. SATA_TXP5 C351 3900p/25V_4 SATA_TXP5_C
(19) SATA_TXP5
B B

HD Audio I/F(CODEC& iHDMI)

HDA_BIT_CLK_HDMI BIT_CLK_AUDIO RTC
R602 IHM@33_4 BATTERY +3VPCU VCCRTC
HDA_SDOUT_HDMI (6)
HDA_SDIN2 R575 IHM@*0_4
HDA_SDOUT_R R604 33_4 R369 R368 2 1
ACZ_SDOUT_AUDIO (26)
HDA_SDIN1 R576 IHM@0_4 D33 RB500V
HDA_SDIN_HDMI (6)
*22_4 *22_4
R599 IHM@33_4 R_3VRTC 2 1
HDA_SYNC_HDMI (6)
R597 IHM@33_4 D32 RB500V
HDA_RST#_HDMI (6)
HDA_SYNC_R R600 33_4 C522 02/12 REV_3A Change
ACZ_SYNC_AUDIO (26)
HDA_RST#_R R598 33_4 C353 C354
ACZ_RST#_AUDIO (26)
1u/10V_6 R528,R529,R532 value
R611 IHM@33_4 *22p/50V_4 *22p/50V_4 R533
HDA_BIT_CLK_HDMI (6)
HDA_BIT_CLK_R R610 33_4 10/14 Add 1K_4 +5VPCU
BIT_CLK_AUDIO (26)
South Bridge Strap Pin (1/3)
RTC_N02 1 3 R528 2K/F_4 R529 2K/F_4

Pin Name Strap description Sampled Configuration PU/PD Q44

MMBT3904

2
R532
0 = The Flash Descriptor Security will be overridden.
HDA_DOCK_EN/ Flash Descriptor Security This strap should only be enabled in manufacturing
PWROK 1 = The security measures defined CN28 6.8K/F_4
GPIO33 Override Strap environments using an external pull-up resistor.
in the Flash Descriptor will be in effect 1 1
2 2
A RTC_N03 R535 15K_4 A

PCI Express Lane Reversal RTC CONN

SATALED# PWROK Internal PU
(Lanes 1-4)

ICH_TP3 HDA_SDOUT Description

TP3 XOR Chain Entrance PWROK ICH_TP3 R264 *1K_4
0 0 RSVD
(16) ICH_TP3
Quanta Computer Inc.
0 1 Enter XOR Chain PROJECT : BL5M Montevina
XOR Chain Entrance /PCI Express*
HDA_SDOUT Port Config 1 bit 1(Port 1-4) PWROK 1 0 Normal opration(Default) HDA_SDOUT_R R582 *1K_4 +3V_HDA_IO_ICH Size Document Number Rev
1A
1 1 Set PCIE port config bit 1 PU +1.5V CLK. GEN./ CK505
Date: Monday, March 10, 2008 Sheet 14 of 37
5 4 3 2 1

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 5 4 3 2 1

PCI/PCI-E/USB/DMI/SPI
BOM Option Table
Reference Description
IV@ INT VGA
(23) AD[0..31] EV@ EXT VGA
U35B
AD0 D11 F1 REQ0# U35D
AD0 REQ0# REQ0# (23)
AD1 GNT0# DMI_RXN0
AD2
C8
D9
AD1 PCI GNT0# G4
B6 REQ1#
GNT0# (23) (25) PCIE_RXN1 N29
N28
PERN1 DMI0RXN V27
V26 DMI_RXP0
DMI_RXN0 (6)
AD2 REQ1#/GPIO50 T135 (25) PCIE_RXP1 PERP1 DMI0RXP DMI_RXP0 (6)

Direct Media Interface

AD3 E12 A7 GNT1# T137 (25) PCIE_TXN1 C313 0.1u/10V_4 PCIE_TXN1_C P27 U29 DMI_TXN0
AD3 GNT1#/GPIO51 PETN1 DMI0TXN DMI_TXN0 (6)
AD4 E9 F13 REQ2# T76 (25) PCIE_TXP1 C314 0.1u/10V_4 PCIE_TXP1_C P26 U28 DMI_TXP0
AD4 REQ2#/GPIO52 PETP1 DMI0TXP DMI_TXP0 (6)
AD5 C9 F12 GNT2# T83
AD6 AD5 GNT2#/GPIO53 REQ3# DMI_RXN1
E10 E6 T81 (24) PCIE_RXN2 L29 Y27 DMI_RXN1 (6)
D AD7 AD6 REQ3#/GPIO54 GNT3# PERN2 DMI1RXN DMI_RXP1 D
B7 F6 T134 (24) PCIE_RXP2 L28 Y26 DMI_RXP1 (6)
AD8 AD7 GNT3#/GPIO55 C307 0.1u/10V_4 PCIE_TXN2_C PERP2 DMI1RXP DMI_TXN1
C7 (24) PCIE_TXN2 M27 W29 DMI_TXN1 (6)
AD9 AD8 CBE0# C308 0.1u/10V_4 PCIE_TXP2_C PETN2 DMI1TXN DMI_TXP1
C5 D8 CBE0# (23) (24) PCIE_TXP2 M26 W28 DMI_TXP1 (6)
AD10 AD9 C/BE0# CBE1# PETP2 DMI1TXP
G11 B4 CBE1# (23)
AD11 AD10 C/BE1# CBE2# DMI_RXN2
F8 D6 CBE2# (23) (25) PCIE_RXN3 J29 AB27 DMI_RXN2 (6)
AD12 AD11 C/BE2# CBE3# PERN3 DMI2RXN DMI_RXP2
F11 A5 CBE3# (23) (25) PCIE_RXP3 J28 AB26 DMI_RXP2 (6)

PCI-Express
AD13 AD12 C/BE3# C292 0.1u/10V_4 PCIE_TXN3_C PERP3 DMI2RXP DMI_TXN2
E7 (25) PCIE_TXN3 K27 AA29 DMI_TXN2 (6)
AD14 AD13 IRDY# C298 0.1u/10V_4 PCIE_TXP3_C PETN3 DMI2TXN DMI_TXP2
A3 D3 IRDY# (23) (25) PCIE_TXP3 K26 AA28 DMI_TXP2 (6)
AD15 AD14 IRDY# PAR PETP3 DMI2TXP
D2 E3 PAR (23)
AD16 AD15 PAR PCIRST# DMI_RXN3 +1.5V_PCIE_ICH
F10 R1 PCIRST# (23) (28) PCIE_RXN4 G29 AD27 DMI_RXN3 (6)
AD17 AD16 PCIRST# DEVSEL# PERN4 DMI3RXN DMI_RXP3
D5 C6 DEVSEL# (23) (28) PCIE_RXP4 G28 AD26 DMI_RXP3 (6)
AD18 AD17 DEVSEL# PERR# C287 0.1u/10V_4 PCIE_TXN4_C PERP4 DMI3RXP DMI_TXN3
D10 E4 (28) PCIE_TXN4 H27 AC29 DMI_TXN3 (6)
AD19 AD18 PERR# LOCK# C281 0.1u/10V_4 PCIE_TXP4_C PETN4 DMI3TXN DMI_TXP3
B3 C2 (28) PCIE_TXP4 H26 AC28 DMI_TXP3 (6)
AD20 AD19 PLOCK# SERR# PETP4 DMI3TXP R353
F7 J4
AD21 AD20 SERR# STOP# CLK_PCIE_ICH#
C3 A4 STOP# (23) (25) PCIE_RXN5 E29 T26 CLK_PCIE_ICH# (2) 24.9/F_4
AD22 AD21 STOP# TRDY# PERN5 DMI_CLKN CLK_PCIE_ICH
F3 F5 TRDY# (23) (25) PCIE_RXP5 E28 T25 CLK_PCIE_ICH (2)
AD23 AD22 TRDY# FRAME# C273 [email protected]/10V_4 PCIE_TXN5_C PERP5 DMI_CLKP
F4 D7 FRAME# (23) (25) PCIE_TXN5 F27
AD24 AD23 FRAME# C271 [email protected]/10V_4 PCIE_TXP5_C PETN5
C1 (25) PCIE_TXP5 F26 AF29
AD25 AD24 PLT_RST-R# PETP5 DMI_ZCOMP DMI_IRCOMP_R
G7 C14 AF28
AD26 AD25 PLTRST# PCLK_ICH DMI_IRCOMP
H7 D4 PCLK_ICH (2) T139 C29
AD27 AD26 PCICLK PCI_PME# PERN6/GLAN_RXN USBP0-
D1 R2 PCI_PME# (23) T140 C28 AC5 USBP0- (19)
AD28 AD27 PME# C264 0.1u/10V_4 PCIE_TXN6_C PERP6/GLAN_RXP USBP0N USBP0+
G5
AD28 T78 D27
PETN6/GLAN_TXN USBP0P
AC4 USBP0+ (19) To USB BOARD
AD29 H6 C636 T80 C270 0.1u/10V_4 PCIE_TXP6_C D26 AD3 USBP1-
AD29 PETP6/GLAN_TXP USBP1N USBP1- (19)
AD30 G1 AD2 USBP1+ To USB BOARD
AD30 USBP1P USBP1+ (19)
AD31 H3 0.1u/10V_4 SPI_CLK D23 AC1 USBP2-
AD31 SPI_CLK USBP2N USBP2- (18)
SPI_CS0# D24 AC2 USBP2+ To Camera
SPI_CS0# USBP2P USBP2+ (18)
12/22 REV_2A Add C636 11/01 Add SPI_CS1# USBP3-
R531 0_4 INTA#_R J5
Interrupt I/F H4 INTE#
F23
SPI_CS1#/GPIO58/CLGPIO6 USBP3N
AA5
AA4 USBP3+
USBP3- (25)
To WLAN
(23) INTA# PIRQA# PIRQE#/GPIO2 USBP3P USBP3+ (25)
R534 *0_4 INTB#_R E1 K6 INTF# SPI_MOSI D25 AB2 USBP4-
PIRQB# PIRQF#/GPIO3 SPI_MOSI USBP4N USBP4- (28)

SPI
T82 INTC#_R J6 F2 INTG# SPI_MISO E23 AB3 USBP4+ To Finger Printer
PIRQC# PIRQG#/GPIO4 SPI_MISO USBP4P USBP4+ (28)
T77 INTD#_R C4 G2 INTH# CRT_SENSE# (18,29) AA1 USBP5-
PIRQD# PIRQH#/GPIO5 USBP5N USBP5- (28)
(19,29) USBOC#0 N4 AA2 USBP5+ To Bluetooth
C OC0#/GPIO59 USBP5P USBP5+ (28) C
ICH9M REV 1.0 R315 *0_4 USBOC#0_C N5 W5 USBP6-
OC1#/GPIO40 USBP6N USBP6- (28)
R332 0_4 USBOC#2 USBP6+ To New Card
USBOC#3
N6
P6
OC2#/GPIO41 USB USBP6P
W4
Y3 USBP9-
USBP6+ (28)
OC3#/GPIO42 USBP7N USBP9- (19)
USBOC#4 M1 Y2 USBP9+ To M/B USB
OC4#/GPIO43 USBP7P USBP9+ (19)
12/22 REV_2A Add USBOC#5 N2 W1 USBP8-
OC5#/GPIO29 USBP8N USBP8- (28)
USBOC#6 M4 W2 USBP8+ To Felica
OC6#/GPIO30 USBP8P USBP8+ (28)
(19,29) USBOC#1 USBOC#7 M3 V2 USBP7-
OC7#/GPIO31 USBP9N USBP7- (19)
USBOC#8 N3 V3 USBP7+ To eSATA
OC8#/GPIO44 USBP9P USBP7+ (19)
R381 EV@0_4 GFXRST# R330 0_4 N1 U5 USBP10- T142
GFXRST# (19) OC9#/GPIO45 USBP10N
USBOC#10 P5 U4 USBP10+ T145
USBOC#11 OC10#/GPIO46 USBP10P USBP11- T143
P3 U1
OC11#/GPIO47 USBP11N
PLT_RST-R# R380 0_4 PLT_RST#_NB
PLT_RST#_NB (6) PCI ROUTING USBP11P
U2 USBP11+ T144

TABLE IDSEL INTERUPT DEVICE USBRBIAS_PN AG2

USBRBIAS
AG1
USBRBIAS#
+3V_S5
REQ0# / GNT0# AD17 INTA#/INTB# OZ129T R354 ICH9M REV 1.0
03/07 REV_3A Swap USB port
22.6/F_4

C346

0.1u/50V_6 iTPM SERIAL 03/03 REV_3A Change to 512K

EEPROM
U14 +3V_SPI
5

2 U10
4 PLTRST# SPI_MISO R281 15_4 SPI_MSIO_R 2 8 +3V_SPI
PLTRST# (21,24,25,28,29) SO VDD
1
R377 SPI_MOSI R279 15_4 SPI_MOSI_R 5 7 C226 R237 *0_6 +3VPCU
TC7SH08FU R616 SI HOLD
3

SPI_CLK R278 15_4 SPI_CLK_R 6 3 0.1u/10V_4 R228 0_4 +3V_S5

100K_4 *100K_6 SCK WP
SPI_CS0# R280 15_4 SPI_CS0#_R 1 4
B CE VSS B
W25X40VSSIG

South Bridge Strap Pin (2/3) PCI USBOC#

PULL-UP PULL-UP
Pin Name Strap description Sampled Configuration PU/PD RP55
+3V
RP57
REQ1# 6 5 USBOC#5 6 5 +3V_S5
PCI Express Port 0 = Default REQ3# 7 4 STOP# USBOC#7 7 4 USBOC#0_C
HDA_SYNC PWROK DEVSEL# 8 3 LOCK# USBOC#4 8 3 USBOC#3
Config 1 bit 0 (Port 1-4) 1 = Setting bit 0 TRDY# 9 2 IRDY# USBOC#6 9 2
+3V 10 1 PERR# +3V_S5 10 1 USBOC#2

PCI Express Port 0 = Setting bit 2 8.2K_10P8R

10K_10P8R
GNT2# / GPIO53 PWROK
Config 2 bit 2 (Port 5-6) 1 = Default
11/29 REV_2A Add
0 = DMI for ESI-compatible +3V RP48
GNT1# / GPIO51 ESI Strap(Server Only) PWROK RP56 REQ0# PU 8 7 +3V_S5
1 = Default INTD#_R 6 5 USBOC#8 6 5
INTB#_R 7 4 INTG# USBOC#11 4 3
8 3 REQ0# USBOC#10 2 1
0 = "top-block swap" mode 9 2 INTH#
GNT3# / GPIO55 Top-Block Swap Override PWROK GNT3# R511 *1K_4 +3V 10 1 INTE# 10K_8P4R
1 = Default
8.2K_10P8R

A
Enable iTPM A
SPI_MOSI Integrated TPM Enable 0 = INT TPM disable(Default) SPI_MOSI R295 *20K_4
CLPWROK 1 = INT TPM enable +3V_S5
+3V
RP54
PCI_GNT#0 SPI_CS#1 Boot Location INTA#_R 6 5
GNT0# Boot BIOS Selection 0 PWROK GNT0# R304 *1K_4 INTF# 7 4 REQ2#
INTC#_R 8 3 SERR#
0 1 SPI(Default) 9 2 FRAME# Quanta Computer Inc.
+3V 10 1

1 0 PCI 8.2K_10P8R PROJECT : BL5M Montevina

SPI_CS1# / SPI_CS1# R314 *1K_4 Size Document Number Rev
Boot BIOS Selection 1 CLPWROK
GPIO58 / CLGPIO6 CLK. GEN./ CK505 1A
1 1 LPC
Date: Monday, March 10, 2008 Sheet 15 of 37
5 4 3 2 1

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 5 4 3 2 1

BOM Option Table

+3V_S5
Reference Description

R312 2.2K_4 SCLK

N/A N/A
U35C
R522 2.2K_4 SDATA SCLK G16 SMBCLK AH23 BOARD_ID3
(2,21,25,28) SCLK SATA0GP/GPIO21
SDATA A13 SMBDATA AF19 BOARD_ID2
(2,21,25,28) SDATA SATA1GP/GPIO19
R256 10K_4 ICH_GPIO60 ICH_GPIO60 E17 LINKALERT#/GPIO60/CLGPIO4 AE21 ICH_GPIO36

SATA
GPIO
SMB_CLK_ME SATA4GP/GPIO36 ICH_GPIO37

SMB
C17 SMLINK0 SATA5GP/GPIO37 AD20
R519 10K_4 SMB_CLK_ME SMB_DATA_ME B18 SMLINK1
H1 14M_ICH
CLK14 14M_ICH (2)
R518 10K_4 SMB_DATA_ME RI# F19 AF3 CLKUSB_48 +3V

Clocks
RI# CLK48 CLKUSB_48 (2)
R267 10K_4 RI# T90 SUS_STAT# R4 P1 SUSCLK T141
D SUS_STAT#/LPCPD# SUSCLK D
SYS_RST# G19 ICH_GPIO36 R372 10K_4
(3) SYS_RST# SYS_RESET#
R268 10K_4 SYS_RST# C16 SUSBR# R266 0_4 SUSB#
SLP_S3# SUSB# (29)
PM_SYNC# M6 E16 SUSCR# R257 0_4 SUSC# ICH_GPIO37 R373 10K_4
(6) PM_SYNC# PMSYNC#/GPIO0 SLP_S4# SUSC# (29)
R520 10K_4 SMB_ALERT# G17 SLP_S5#
SMB_ALERT# SLP_S5# T85 +3V_S5
A17
SMBALERT#/GPIO11 ICH_GPIO26
C10
+3V PM_STPPCI# S4_STATE#/GPIO26 T74 PM_BATLOW# R523 8.2K_4
(2) PM_STPPCI# A14
PM_STPCPU# STP_PCI# ICH_PWROK

SYS GPIO
(2) PM_STPCPU# E19 G20
R287 *10K_4 PM_STPPCI# STP_CPU# PWROK DNBSWON# R345 10K_4
CLKRUN# L4 M2 PM_DPRSLPVR_R R546 0_4 PM_DPRSLPVR
(23,29) CLKRUN# CLKRUN# DPRSLPVR/GPIO16 PM_DPRSLPVR (6,32)
R286 *10K_4 PM_STPCPU#
PCIE_WAKE# E20 B13 PM_BATLOW# PM_LAN_ENABLE_R R258 0_4

Power MGT
(24,25,28) PCIE_WAKE# WAKE# BATLOW#
R542 8.2K_4 CLKRUN# SERIRQ M5
(25,29) SERIRQ SERIRQ
THERM_ALERT# AJ23 R3 DNBSWON#
+3V_S5 (3) THERM_ALERT# THRM# PWRBTN# DNBSWON# (29)
02/12 REV_3A Mount R345
VR_PWRGD_CLKEN D21 D20 PM_LAN_ENABLE_R R263 *0_4 PM_RSMRST#_R
R302 10K_4 PCIE_WAKE# VRMPWRGD LAN_RST#
ICH_TP11 A20 D22 PM_RSMRST#_R
+3V T136 TP11 RSMRST#
C637 0.1u/10V_4 12/22 REV_2A Add C637
KBSMI#_ICH AG19 R5 CK_PWRGD
GPIO1 CK_PWRGD CK_PWRGD (2)
R334 10K_4 SERIRQ Port_C# AH21
(26) Port_C# GPIO6
SB_GPIO7 AG21 R6 ECPWROK R336 0_4
(27) SB_GPIO7 GPIO7 CLPWROK MPWROK (6)
R591 8.2K_4 THERM_ALERT# SCI# A21 +3V +3V
(29) SCI# GPIO8
FM_DET C12 B16 SLP_M#
R376 10K_4 KBSMI#_ICH ICH_GPIO13 GPIO12 SLP_M# T138
T70 C21
BOARD_ID0 GPIO13 CL_CLK0
AE18 F24 CL_CLK0 (6)
BOARD_ID1 GPIO17 CL_CLK0 CL_CLK1 R512 R328
K1 B19 CL_CLK1 (25)
LOW_DET GPIO18 CL_CLK1
AF8
R265 *10K_4 SCI# BOARD_ID4 GPIO20 CL_DATA0 3.24K/F_6 *3.24K/F_6
AJ22 F22 CL_DATA0 (6)
SB_GPIO27 SCLOCK/GPIO22 CL_DATA0 CL_DATA1
(27) SB_GPIO27 A9 C19 CL_DATA1 (25)

GPIO
GPIO27 CL_DATA1

Controller Link
R544 10K_4 ICH_GPIO35 FM_INT D19 CL_VREF0_SB CL_VREF1_SB
(27) FM_INT GPIO28
ICH_GPIO35 L1 C25 CL_VREF0_SB
R352 10K_4 ICH_GPIO38 ICH_GPIO38 SATACLKREQ#/GPIO35 CL_VREF0 CL_VREF1_SB
AE19 A19
C ICH_GPIO39 SLOAD/GPIO38 CL_VREF1 C519 R516 C299 R323 C
AG22
R371 10K_4 ICH_GPIO39 ICH_GPIO48 SDATAOUT0/GPIO39 CL_RST#0
T94 AF21 F21 CL_RST#0 (6)
DMI_TERM_SEL SDATAOUT1/GPIO48 CL_RST0# CL_RST#1 0.1u/10V_4 453/F_4 *0.1u/10V_4 *453/F_4
AH24 D18 CL_RST#1 (25)
CLGPIO5 GPIO49 CL_RST1#
A8
GPIO57/CLGPIO5 ICH_GPIO24
A16
SPKR MEM_LED/GPIO24 HDPACT
SCI#(PU to MAIN or S5) (26) SPKR M7
SPKR GPIO10/SUS_PWR_ACK
C18
+3V_S5 R609 0_4 MCH_ICH_SYNC#_R AJ24 C11 ICH_GPIO14 T75
leakage issue (6) MCH_ICH_SYNC#
ICH_TP3 MCH_SYNC# GPIO14/AC_PRESENT HDPINT
(14) ICH_TP3 B21 C20
R259 10K_4 SCI# ICH_TP8 TP3 WOL_EN/GPIO9 T71

MISC
T149 AH20
ICH_TP9 TP8
T148 AJ20
ICH_TP10 TP9
T147 AJ21
TP10
+3V_S5 ICH9M REV 1.0 +3V_S5
Enable iTPM(PU to PCU or S5?)
R510 *10K_4 CLGPIO5

R526 *100/F_4 11/29 REV_2A DNI R510 ICH_GPIO24 R521 *10K_4

HDPACT R251 *10K_4

ICH_GPIO14 R296 10K_4

+3V +3V_S5
C225 HDPINT R297 *10K_4
R590 *10K_4 MCH_ICH_SYNC#_R
DELAY_VR_PWRGOOD need PU 2K to +3V. R291 *10K_4
0.1u/16V_4
ZS2 PU at power side(NEED CHECK PWR CKT)

5
DELAY_VR_PWRGOOD 1 U8
(3,6,32) DELAY_VR_PWRGOOD
4 ICH_PWROK
ECPWROK 2
(29) ECPWROK
TC7SH08FU
3

B R232 B
10K_4
R236 100K_4

+3V LOW COST SEL

PIN R605 *0_4
C230
+3V_S5 R524 Always mount +3V R594 Always mount

R594 Q46
0.1u/10V_4 R524 MMBT3906
12/22 REV_2A Change footprint and P/N 10K_4
10K_4 PM_RSMRST#_R 3 1 RSMRST# (29)
U6
1 5 FM_DET LOW_DET
FM_DET (27) LOW_DET (28)
VR_PWRGD_CK410# 2

2
(32) VR_PWRGD_CK410#
3 4 VR_PWRGD_CLKEN R603
R509 High : W/O FM 10K_4 R583 4.7K_4 +3V_S5
NC7SZ04 R595
Low : W/ FM High : Main Strem

2
R230
*0_4 D43
100K_4
*10K_4
Low : Low Cost 3 BAV99

1
2
Board ID Table
South Bridge Strap Pin (3/3) BOARD_ID3 of TE1M always keep
low, TE1 hasn't support TV +3V +3V +3V +3V +3V 3
D42
BAV99

A Pin Name Strap description Sampled Configuration PU/PD Board ID ID4 ID3 ID2 ID1 ID0 R580 A

1
R613 R612 R375 R541 R347 2.2K_4
NEW CARD H 10K_4 *10K_4 *10K_4 10K_4 10K_4
CARD BUS L
GPIO20 Reserved PWROK
BOARD_ID4 BOARD_ID3 BOARD_ID2 BOARD_ID1 BOARD_ID0
CCFL Panel H
LED Panel L
0 = Default
SPKR No Reboot PWROK
1 = No Reboot mode
SPKR R324 *1K_4 +3V
W/ G-SENSOR
W/O G-SENSOR
H
L R593 R592 R374 R539 R350 Quanta Computer Inc.
*10K_4 10K_4 10K_4 *10K_4 *10K_4
W/ TV H PROJECT : BL5M Montevina
0 = for desktop applications W/O TV L Size Document Number Rev
DMI Termination 1 = for mobile applications
GPIO49 PWROK DMI_TERM_SEL R589 *1K_4
W/ HDMI H CLK. GEN./ CK505 1A
Voltage Internal PU W/O HDMI L Date: Monday, March 17, 2008 Sheet 16 of 37
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 5 4 3 2 1

BOM Option Table

Reference Description
N/A N/A

U35F
VCCRTC VCCRTC A23 A15 +1.05V_ICH R339 0_8 +1.05V
VCCRTC VCC1_05[1]
VCC1_05[2]
B15 02/12 REV_3A Add D48
C252 C251 +SB_V5REF A6 C15 C320 C302
V5REF VCC1_05[3] U35E
D15
VCC1_05[4] D48
0.1u/10V_4 0.1u/10V_4 +5VPCU_ICH_V5REF_SUS AE1 E15 0.1u/10V_4 0.1u/10V_4 2 1 VPORT_6 AA26 H5
V5REF_SUS VCC1_05[5] VSS[1] VSS[107]
F15 AA27 J23
VCC1_05[6] VSS[2] VSS[108]
12/22 REV_2A Change D15,D17 P/N AA24
VCC1_5_B[1] VCC1_05[7]
L11 AA3
VSS[3] VSS[109]
J26
AA25 L12 AA6 J27
VCC1_5_B[2] VCC1_05[8] +1.5V_ICH_VCCDMIPLL L20 1uh_6 VSS[4] VSS[110]
AB24 L14 +1.5V AB1 AC22
VCC1_5_B[3] VCC1_05[9] VSS[5] VSS[111]
AB25 L16 AA23 K28
VCC1_5_B[4] VCC1_05[10] C315 C316 VSS[6] VSS[112]
AC24 L17 AB28 K29
D D15 CH751H-40PT VCC1_5_B[5] VCC1_05[11] VSS[7] VSS[113] D
+3V 2 1 AC25 L18 AB29 L13
VCC1_5_B[6] VCC1_05[12] 0.01u/16V_4 10u/10V_8 VSS[8] VSS[114]
AD24 M11 AB4 L15
C250 VCC1_5_B[7] VCC1_05[13] VSS[9] VSS[115]
AD25 M18 AB5 L2
VCC1_5_B[8] VCC1_05[14] VSS[10] VSS[116]
AE25 P11 AC17 L26
R285 100/F_6 1u/10V_4 VCC1_5_B[9] VCC1_05[15] VSS[11] VSS[117]
+5V AE26 P18 AC26 L27
VCC1_5_B[10] VCC1_05[16] VSS[12] VSS[118]
AE27 T11 AC27 L5
VCC1_5_B[11] VCC1_05[17] +1.05V_ICH_DMI R335 0_6 +1.05V_ICH VSS[13] VSS[119]
AE28 T18 AC3 L7
VCC1_5_B[12] VCC1_05[18] VSS[14] VSS[120]
AE29 U11 AD1 M12

CORE
VCC1_5_B[13] VCC1_05[19] C312 C311 VSS[15] VSS[121]
F25 U18 AD10 M13
VCC1_5_B[14] VCC1_05[20] VSS[16] VSS[122]
G25 V11 AD12 M14
D17 CH751H-40PT VCC1_5_B[15] VCC1_05[21] 4.7u/10V_6 10u/6.3V_8 VSS[17] VSS[123]
+3V_S5 2 1 H24 V12 AD13 M15
VCC1_5_B[16] VCC1_05[22] VSS[18] VSS[124]
H25 V14 AD14 M16
C339 VCC1_5_B[17] VCC1_05[23] VSS[19] VSS[125]
J24 V16 AD17 M17
VCC1_5_B[18] VCC1_05[24] +1.05V_ICH_IO VSS[20] VSS[126]
J25 V17 AD18 M23
R351 100/F_6 1u/10V_4 VCC1_5_B[19] VCC1_05[25] VSS[21] VSS[127]
+5V_S5 K24 V18 AD21 M28
VCC1_5_B[20] VCC1_05[26] +1.05V_ICH_IO R340 0_6 VSS[22] VSS[128]
K25 +1.05V AD28 M29
VCC1_5_B[21] VSS[23] VSS[129]
L23 R29 AD29 N11
VCC1_5_B[22] VCCDMIPLL VSS[24] VSS[130]
L24 AD4 N12
VCC1_5_B[23] C328 C326 C332 VSS[25] VSS[131]
L25 W23 AD5 N13
VCC1_5_B[24] VCC_DMI[1] VSS[26] VSS[132]
03/18 REV_3A Change R285,R351,C250,C339 +1.5V_PCIE_ICH
M24
VCC1_5_B[25] VCC_DMI[2]
Y23 AD6
VSS[27] VSS[133]
N14
M25 0.1u/10V_4 0.1u/10V_4 4.7u/10V_6 AD7 N15
VCC1_5_B[26] VSS[28] VSS[134]
N23 AB23 AD9 N16
L21 VCC1_5_B[27] V_CPU_IO[1] VSS[29] VSS[135]
+1.5V 1 2 BLM21PG221SN1D_8 +1.5V_PCIE_ICH N24 AC23 AE12 N17
VCC1_5_B[28] V_CPU_IO[2] VSS[30] VSS[136]
N25 AE13 N18
VCC1_5_B[29] +3V_DMI_ICH R356 0_6 VSS[31] VSS[137]
P24 AG29 +3V AE14 N26
+ C321 C335 C309 C301 VCC1_5_B[30] VCC3_3[1] VSS[32] VSS[138]
P25 AE16 N27
VCC1_5_B[31] VSS[33] VSS[139]

VCCA3GP
R24 AJ6 +3V_SATA_ICH C338 AE17 P12
220u/2.5V_7343 10u/6.3V_8 10u/6.3V_8 2.2u/6.3V_6 VCC1_5_B[32] VCC3_3[2] VSS[34] VSS[140]
R25 AE2 P13
VCC1_5_B[33] 0.1u/10V_4 VSS[35] VSS[141]
R26 AC10 AE20 P14
VCC1_5_B[34] VCC3_3[7] VSS[36] VSS[142]
R27 AE24 P15
VCC1_5_B[35] VSS[37] VSS[143]
T24 AD19 AE3 P16
VCC1_5_B[36] VCC3_3[3] R601 0_6 VSS[38] VSS[144]
T27 AF20 AE4 P17

VCCP_CORE
VCC1_5_B[37] VCC3_3[4] +3V VSS[39] VSS[145]
T28 AG24 AE6 P2
VCC1_5_B[38] VCC3_3[5] +3V_VCCPCORE_ICH C564 VSS[40] VSS[146]
T29 AC20 AE9 P23
VCC1_5_B[39] VCC3_3[6] VSS[41] VSS[147]
U24 AF13 P28
VCC1_5_B[40] 0.1u/10V_4 VSS[42] VSS[148]
U25 B9 AF16 P29
VCC1_5_B[41] VCC3_3[8] VSS[43] VSS[149]
V24 F9 AF18 P4
VCC1_5_B[42] VCC3_3[9] VSS[44] VSS[150]
V25 G3 AF22 P7
VCC1_5_B[43] VCC3_3[10] +3V_PCI_ICH VSS[45] VSS[151]
U23 G6 AH26 R11
VCC1_5_B[44] VCC3_3[11] R346 0_6 VSS[46] VSS[152]
W24 J2 +3V AF26 R12
C VCC1_5_B[45] VCC3_3[12] VSS[47] VSS[153] C
W25

PCI
J7 AF27 R13
VCC1_5_B[46] VCC3_3[13] +3V_HDA_IO_ICH C334 VSS[48] VSS[154]
K23 K7 AF5 R14
VCC1_5_B[47] VCC3_3[14] VSS[49] VSS[155]
Y24 AF7 R15
VCC1_5_B[48] +3V_HDA_IO_ICH 0.1u/10V_4 VSS[50] VSS[156]
Y25 AJ4 AF9 R16
VCC1_5_B[49] VCCHDA VSS[51] VSS[157]
AG13 R17
R355 0_8 +1.5V_SATA_ICH L22 10uh_8 +1.5V_APLL_ICH +3V_VCCSUSHDA VSS[52] VSS[158]
+1.5V AJ19 AJ3 AG16 R18
VCCSATAPLL VCCSUSHDA VSS[53] VSS[159]
AG18 R28
C340 C344 +TP_VCCSUS1_05_ICH_1 T91 R290 0_8 VSS[54] VSS[160]
AC16 AC8 +3V AG20 T12
VCC1_5_A[1] VCCSUS1_05[1] +TP_VCCSUS1_05_ICH_2 T87 VSS[55] VSS[161]
AD15 F17 AG23 T13
10u/10V_8 1u/6.3V_4 VCC1_5_A[2] VCCSUS1_05[2] C283 C284 C294 VSS[56] VSS[162]
AD16 AG3 T14
VCC1_5_A[3] VSS[57] VSS[163]

ARX
AE15 AD8 +TP_VCCSUS1_5_ICH_1 T92 AG6 T15
VCC1_5_A[4] VCCSUS1_5[1] 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 VSS[58] VSS[164]
AF15 AG9 T16
VCC1_5_A[5] +VCCSUS1_5_INT_ICH VSS[59] VSS[165]
AG15 F18 AH12 T17
+1.5V_SATA_ICH VCC1_5_A[6] VCCSUS1_5[2] VSS[60] VSS[166]
AH15 AH14 T23
VCC1_5_A[7] VSS[61] VSS[167]
AJ15 AH17 B26
C285 VCC1_5_A[8] +3VPCU_ICH C280 R358 0_6 VSS[62] VSS[168]
A18 AH19 U12

VCCPSUS
VCCSUS3_3[1] +1.5V VSS[63] VSS[169]
AC11 D16 AH2 U13
1u/6.3V_4 VCC1_5_A[9] VCCSUS3_3[2] 0.1u/10V_4 C342 VSS[64] VSS[170]
AD11 D17 AH22 U14
VCC1_5_A[10] VCCSUS3_3[3] VSS[65] VSS[171]
AE11 E22 AH25 U15
VCC1_5_A[11] VCCSUS3_3[4] VSS[66] VSS[172]

ATX
AF11 0.1u/10V_4 AH28 U16
VCC1_5_A[12] VSS[67] VSS[173]
AG10 AH5 U17
+1.5V_SATA_ICH VCC1_5_A[13] VSS[68] VSS[174]
AG11 AF1 AH8 AD23
VCC1_5_A[14] VCCSUS3_3[5] R359 0_6 VSS[69] VSS[175]
AH10 +1.5V_S5 AJ12 U26
C333 VCC1_5_A[15] VSS[70] VSS[176]
AJ10 T1 AJ14 U27
VCC1_5_A[16] VCCSUS3_3[6] C343 VSS[71] VSS[177]
T2 AJ17 U3
1u/6.3V_4 VCCSUS3_3[7] VSS[72] VSS[178]
AC9 T3 AJ8 V1
VCC1_5_A[17] VCCSUS3_3[8] 0.1u/10V_4 VSS[73] VSS[179]
T4 B11 V13
VCCSUS3_3[9] VSS[74] VSS[180]
AC18 T5 B14 V15
+1.5V_SATA_ICH VCC1_5_A[18] VCCSUS3_3[10] VSS[75] VSS[181]
AC19 T6 B17 V23
VCC1_5_A[19] VCCSUS3_3[11] R301 0_6 VSS[76] VSS[182]
VCCPUSB U6 +3V_S5 B2 V28
VCCSUS3_3[12] VSS[77] VSS[183]
AC21 U7 B20 V29
VCC1_5_A[20] VCCSUS3_3[13] +3VPCU_USB_ICH R337 0_8 VSS[78] VSS[184]
V6 B23 V4
VCCSUS3_3[14] VSS[79] VSS[185]
G10 V7 B5 V5
R344 0_8 +1.5V_USB_ICH VCC1_5_A[21] VCCSUS3_3[15] C336 C319 C318 VSS[80] VSS[186]
+1.5V G9 W6 B8 W26
VCC1_5_A[22] VCCSUS3_3[16] VSS[81] VSS[187]
W7 C26 W27
C323 VCCSUS3_3[17] 0.022u/16V_4 0.022u/16V_4 0.1u/10V_4 VSS[82] VSS[188]
AC12 Y6 C27 W3
VCC1_5_A[23] VCCSUS3_3[18] Check list: VSS[83] VSS[189]
AC13 Y7 E11 Y1
0.1u/10V_4 VCC1_5_A[24] VCCSUS3_3[19] 0.1U for Pin AF1 VSS[84] VSS[190]
AC14 T7 E14 Y28
VCC1_5_A[25] VCCSUS3_3[20] VSS[85] VSS[191]
E18 Y29
+VCCCL1_05_INT_ICH VSS[86] VSS[192]
AJ5 G22 E2 Y4
B VCCUSBPLL VCCCL1_05 VSS[87] VSS[193] B
E21 Y5
+1.5V_USB_ICH +VCCCL1_5_INT_ICH VSS[88] VSS[194]
AA7 G23 E24 AG28
VCC1_5_A[26] VCCCL1_5 VSS[89] VSS[195]
USB CORE

AB6 E5 AH6
C324 VCC1_5_A[27] C289 C288 C282 VSS[90] VSS[196]
AB7 A24 E8 AF2
VCC1_5_A[28] VCCCL3_3[1] VSS[91] VSS[197]
AC6 B24 F16 B25
0.1u/10V_4 VCC1_5_A[29] VCCCL3_3[2] *0.1u/10V_4 *0.1u/10V_4 0.1u/10V_4 VSS[92] VSS[198]
AC7 F28
VCC1_5_A[30] VSS[93]
F29 A1
VSS[94] VSS_NCTF[1]
A10 G12 A2
C518 0.1u/10V_4 +VCCLAN1_05_INT_ICH VCCLAN1_05[1] VSS[95] VSS_NCTF[2]
A11 G14 A28
VCCLAN1_05[2] VSS[96] VSS_NCTF[3]
G18 A29
VSS[97] VSS_NCTF[4]
A12 G21 AH1
R289 0_6 +3VM_VCCPAUX VCCLAN3_3[1] +3VM_VCCCL3_ICH R292 0_6 VSS[98] VSS_NCTF[5]
+3V B12 +3V G24 AH29
VCCLAN3_3[2] VSS[99] VSS_NCTF[6]
G26 AJ1
C253 +1.5V_ICH_GLANPLL_R VSS[100] VSS_NCTF[7]
A27 G27 AJ2
VCCGLANPLL VSS[101] VSS_NCTF[8]
G8 AJ28
VSS[102] VSS_NCTF[9]
GLAN POWER

0.1u/10V_4 D28 H2 AJ29

VCCGLAN1_5[1] VSS[103] VSS_NCTF[10]
D29 H23 B1
VCCGLAN1_5[2] VSS[104] VSS_NCTF[11]
E26 H28 B29
+1.5V_PCIE_ICH VCCGLAN1_5[3] VSS[105] VSS_NCTF[12]
E27 H29
VCCGLAN1_5[4] VSS[106]
+SB_VCCGLAN3_3 A26 ICH9M REV 1.0
VCCGLAN3_3

+1.5V L17 1uh_6 ICH9M REV 1.0

C255 C254

10u/10V_8 2.2u/6.3V_6

SB Power Status and max current table(1/2)(SB left SB Power Status and max current table(2/2)(SB right
side)
POWER PLANE S0 S3 S4/S5 Voltage I(max) Note side)
POWER PLANE S0 S3 S4/S5 Voltage I(max) Note
+1.5V_PCIE_ICH VCCRTC X X X +VCCRTC 6uA 6uA@G3 VCC1_05 O X X +1.05V 1.634A
C330 O X X O X X
V5REF +5V 2mA VCCDMIPLL +1.5V 23mA
4.7u/10V_6 O O O 2mA O X X
V5REF_SUS +5V_S5 1mA@S3/S4/S5 VCC_DMI +1.05V 48mA
VCC1_5_B O X X +1.5V 646mA V_CPU_IO O X X +1.05V 2mA

A
VCCSATAPLL O X X +1.5V 47mA VCC3_3 O X X +3V 308mA A
R517 0_6 O X X O X X
+3V VCC1_5_A +1.5V 1.342A VCCHDA +1.5V 11mA
VCCUSBPLL O X X +1.5V 11mA VCCSUSHDA O O O +1.5V_S5 11mA 1mA@S3/S4/S5
VCCLAN1_05 O X X +1.05V X Powered by Vcc1_05 in S0 VCCSUS1_05 O O O +1.05V X Powered by Vcc1_05 in S0
VCCLAN3_3 O X X +3V 19mA Tied to +3V,not +3VSUS VCCSUS1_5 O O O +1.5V X Powered by Vcc1_5_A in S0
VCCGLANPLL O X X +1.5V 23mA VCCSUS3_3 O O O +3VSUS 212mA 52mA@S3/S4/S5
O X X O X X Powered by Vcc1_05 in S0
VCCGLAN1_5 +1.5V 80mA VCCCL1_05 +1.05V X Quanta Computer Inc.
VCCGLAN3_3 O X X +3V 1mA VCCCL1_5 O X X +1.5V X Powered by Vcc1_5_A in S0
O X X 19mA
PROJECT : BL5M Montevina
VCCCL3_3 +3V Tied to +3V,not +3VSUS Size Document Number Rev
1A
Note:VCCSUS1_05 , VCCSUS1_5 are powered by VccSus3_3 in S3/S4/S5 CLK. GEN./ CK505
Date: Tuesday, March 18, 2008 Sheet 17 of 37
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 5 4 3 2 1
BOM Option Table

CRT PORT 03/08 REV_3A Chage L2,L3,L4 P/N to CX8BA470003

Reference
IV@
Description
INT VGA

R206 EV@0_4 CRT_R

EV@ EXT VGA
(19) EV_CRT_R
C1 0.1u/10V_4
R198 EV@0_4 CRT_G D1 SSM14 F1
IHM@ INT HDMI
(19) EV_CRT_G
5V_CRT2 CN16

16
+5V 2 1 2 1 EV_IV@ EV&IV diff. value
R194 EV@0_4 CRT_B
(19) EV_CRT_B
FUSE1A6V_POLY-1A-6V 25 MIL CRT_DSUB-070549FR015SX03CX-15P-V
R210 EV@0_4 HSYNC 6
(19) EV_CRT_HSYNC
CRT_R L4 BLM18BA470SN1_6 CRT_R1 1 11 D2 *MTW355 CRT_SENSE# (15,29)
R218 EV@0_4 VSYNC 7
(19) EV_CRT_VSYNC
CRT_G L3 BLM18BA470SN1_6 CRT_G1 2 12
R234 EV@0_4 DDCCLK 8
(19) EV_CRT_DDCCLK CRT_B CRT_B1
D L2 BLM18BA470SN1_6 3 13 D
R239 EV@0_4 DDCDAT 9
(19) EV_CRT_DDCDAT
4 14
R5 C8 R4 C6 R1 C4 C3 C5 C7 10
150/F_4 6.8p_4 150/F_4 6.8p_4 150/F_4 6.8p_4 6.8p_4 6.8p_4 6.8p_4 5 15

R195 IV@0_4
(6) INT_CRT_RED

17
R186 IV@0_4
(6) INT_CRT_GRN
03/08 REV_3A Chage C8,C6,C4,C3,C5,C7 P/N to CH-686T0B07
R185 IV@0_4
(6) INT_CRT_BLU
R207 IV@0_4 U20
(6) INT_HSYNC
5V_CRT2 1 16 VSYNC1 R429 39_4 VSYNC1_CRT L29 BLM18BA220SN1 CRTVSYNC
R209 IV@0_4 VCC_SYNC SYNC_OUT2 HSYNC1 R430 39_4 HSYNC1_CRT L30 CRTHSYNC
(6) INT_VSYNC +5V 14
SYNC_OUT1 BLM18BA220SN1
7
R233 IV@0_4 C412 0.22u/10V_68 VCC_DDC C408 C410
(6) INT_CRT_DDCCLK BYP
15 VSYNC
R238 IV@0_4 SYNC_IN2 HSYNC 5V_CRT2 10p_4 10p_4
(6) INT_CRT_DDCDAT +3V 2 13
VCC_VIDEO SYNC_IN1
R427 R431
CRT_R1 3 10 DDCCLK
CRT_G1 VIDEO_1 DDC_IN1 DDCDAT 2.7K_4 2.7K_4
4 11
CRT_B1 VIDEO_2 DDC_IN2
5
VIDEO_3 CRTDCLK
9
DDC_OUT1 CRTDDAT
6 12
GND DDC_OUT2
CM2009
C407 C411

R407 100K_4 H=1.75mm 10p_4 10p_4

DDCCLK R2 2.2K_4
+3VPCU +5V +3V +3V
DDCDAT R3 2.2K_4

C413 C414
C 1 2 LID591# 0.1u/10V_4 0.1u/10V_4 C

+3V 02/12 MR1 10/30 Change Value

C396 PT3661-BB
REV_3A
3

Reserve 0.1u/10V_4
R403 DISPON to
1K_4
EC 03/07 REV_3A Del RP1

DISPON D23 BAS316 INT_MIC

LID591# (29) +15V MIC_DATA
+3V USBP2+ MIC_GND 2
USBP2+ (15) 1
1

+3V USBP2-
DISPON (29) USBP2- (15)
D49 R425 65mil C10 C9 CN2

3
VPORT_6
DISPON 330K_6 Q31
R652 AO3404 *1000p_4 *1000p_4
2

LCDONG 2 LCDVCC
3

10K_4
02/12 REV_3A Add D49 +3VPCU L28
0_6
2 BL# C409 LCDVCC1

1
12/18 REV_2A Del D28,R412 R31 65mil 65mil LCD PANEL MODULE

3
Q53 12/18 REV_2A Add Q53,Q54,R652 0.01u_4
3

2N7002 100K_4 C400 C399 C401

R424
1

2 0.1u/16V_4 0.01u_4 10u/6.3V_6

2 R406 IV@0_4
INT_LVDS_BLON (6)
22_8 10/23 Add
Q32
Q54 R405 EV@0_4 2N7002 LCDDISCHG CN1
EV_LVDS_BLON (19)

3
2N7002 Q36 INVCC0 LCDVCC

1
1 2
3
R411 PDTC143TT
1

3 4 LCD_EDIDDATA
100K_4 R433 EV@0_4 LCDON# 5 6 LCD_EDIDCLK
(19) EV_LVDS_BL_BRGHT 2 2 +3V 7 8
CCD_POWER LVDS_VADJ
R432 IV@0_4 Q33 MIC_GND 9 10
B (6) INT_LVDS_DIGON 11 12 B
2N7002 VIN MIC_DATA USBP2+
1

R434 0_8 R423 INVCC0 DISPON 13 14 USBP2-

1
15 16
17 18

1
100K_4 C403 C402 TXLCLKOUT+ TXUCLKOUT+
DISPON TXLCLKOUT- 19 20 TXUCLKOUT-
+
21 22
3

10u/25V_1206 1000p_4 C628 TXLOUT0+ 23 24 TXUOUT0+

2
TXLOUT0- 25 26 TXUOUT0-
2 EC_FPBACK# (29)
560p_4 27 28
TXLOUT1+ 29 30 TXUOUT1+
Q29 TXLOUT1- 31 32 TXUOUT1-
1

33 34
TXLOUT2+ 35 36 TXUOUT2+
DTC144EU 12/18 REV_2A Add C628 37 38
TXLOUT2- TXUOUT2-
39 40

HALL SENSOR
41 42
12/18 REV_2A Add
R8 IV@*0_4 LVDS_VADJ +3V
(6) INT_LVDS_PWM
ACES_88242-40XX_LVDS
R6 0_4 8/14 Modify Pin Define
(29) CONTRAST
C14 0.1u/10V_4

CAMERA MODULE 02/12 REV_3A Add C640 for EMI

02/12 REV_3A Mount C14 for EMI
R499

2.2K_4
C640 TXLCLKOUT+ LCD_EDIDCLK
RN15 2 1 IV@0X2 R501 EV@0_4
INT_TXLCLKOUT+ (6) (19) EV_LVDS_DDCCLK
CM@0_8 R428 TXLCLKOUT- 4 3
+3V +5V INT_TXLCLKOUT- (6)
R494 IV@0_4 C633
(6) INT_LVDS_EDIDCLK
TXLOUT0- RN16 4 3 IV@0X2 TXUCLKOUT- RN14 2 1 IV@0X2
0.1u/10V_4 INT_TXLOUT0- (6) INT_TXUCLKOUT- (6)
TXLOUT0+ 2 1 TXUCLKOUT+ 4 3 +3V
CCD_POWER INT_TXLOUT0+ (6) INT_TXUCLKOUT+ (6)
+5V 1 3 220p/50V_4
TXLOUT1+ RN12 2 1 IV@0X2 TXUOUT0+ RN13 4 3 IV@0X2
INT_TXLOUT1+ (6) INT_TXUOUT0+ (6)
TXLOUT1- TXUOUT0-
+

C404 CM@*10u/10V_8 4 3 2 1 R498

INT_TXLOUT1- (6) INT_TXUOUT0- (6)
Q34 R426
2

CM@*AO3413 C406 CM@*1000p_4 CM@*4.7K_4 TXLOUT2- RN11 4 3 IV@0X2 TXUOUT1- RN10 2 1 IV@0X2
TXLOUT2+ INT_TXLOUT2- (6) TXUOUT1+ INT_TXUOUT1- (6)
2 1 4 3 2.2K_4
INT_TXLOUT2+ (6) INT_TXUOUT1+ (6)
A C405 CM@*0.1u/10V_4 R500 EV@0_4 LCD_EDIDDATA A
(19) EV_LVDS_DDCDAT
TXUOUT2+ RN9 4 3 IV@0X2 INT_TXUOUT2+ (6)
TXUOUT2- 2 1 R493 IV@0_4 C634
INT_TXUOUT2- (6) (6,11) INT_LVDS_EDIDDATA
3

220p/50V_4
RN23 1 2 EV@0X2 RN22 1 2 EV@0X2
EV_LVDS_LCLK (19) EV_LVDS_UCLK# (19)
2 CCD_POWERON (29) 3 4 EV_LVDS_LCLK# (19) 3 4 EV_LVDS_UCLK (19)
RN24 3 4 EV@0X2 RN21 3 4 EV@0X2
EV_LVDS_LTX#0 (19) EV_LVDS_UTX0 (19)
Q35 1 2 1 2
Quanta Computer Inc.
1

EV_LVDS_LTX0 (19) EV_LVDS_UTX#0 (19)

CM@*DTC144EU
RN20 1 2 EV@0X2 RN19 1 2 EV@0X2
EV_LVDS_LTX1 (19) EV_LVDS_UTX#1 (19)
3 4 EV_LVDS_LTX#1 (19) 3 4 EV_LVDS_UTX1 (19) PROJECT : BL5M Montevina
RN18 3 4 EV@0X2 RN17 3 4 EV@0X2 Size Document Number Rev
EV_LVDS_LTX#2 (19) EV_LVDS_UTX2 (19)
1A
1 2 EV_LVDS_LTX2 (19) 1 2 EV_LVDS_UTX#2 (19) LCD/CRT/LID/CAMERA
Date: Monday, March 10, 2008 Sheet 18 of 37
5 4 3 2 1

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 5 4 3 2 1

CN25 +5VPCU F3 USBPOWER

VGA (6) PEG_TXN15
(6) PEG_TXP15
PEG_TXN15
PEG_TXP15
2
4
2
4
1
3
1
3
PEG_RXN15
PEG_RXP15
PEG_RXN15 (6)
PEG_RXP15 (6)
USB POLY SWITCH 1.5A/6V_1206 C394
6 6 5 5
PEG_TXN14 8 7 PEG_RXN14 4.7u/10V_6 U19
(6) PEG_TXN14 8 7 PEG_RXN14 (6)
PEG_TXP14 10 9 PEG_RXP14 RT9711BPF
(6) PEG_TXP14 10 9 PEG_RXP14 (6)
12 11 2 8 USBPWR0
PEG_TXN13 12 11 PEG_RXN13 3ND_MBCLK IN1 OUT3
(6) PEG_TXN13 14 14 13 13 PEG_RXN13 (6) 09/21 REV_A1 Modify 3 IN2 OUT2 7
PEG_TXP13 16 15 PEG_RXP13 6
(6) PEG_TXP13 16 15 PEG_RXP13 (6) OUT1
18 18 17 17 (29) USB_EN# 4 EN# USBOC#0 (15,29)
PEG_TXN12 20 19 PEG_RXN12 1
(6) PEG_TXN12 20 19 PEG_RXN12 (6) GND
PEG_TXP12 22 21 PEG_RXP12 9 5 R402 *100K_6 +5VPCU 09/20 REV_A1 Modify
(6) PEG_TXP12 22 21 PEG_RXP12 (6) GND-C OC#
D 24 24 23 23 D
PEG_TXN11 26 25 PEG_RXN11
(6) PEG_TXN11 26 25 PEG_RXN11 (6)
PEG_TXP11 28 27 PEG_RXP11
(6) PEG_TXP11 28 27 PEG_RXP11 (6)
30 29 C630
PEG_TXN10 30 29 PEG_RXN10
(6) PEG_TXN10 32 32 31 31 PEG_RXN10 (6) 47p_4
PEG_TXP10 34 33 PEG_RXP10
(6) PEG_TXP10 34 33 PEG_RXP10 (6)
36 36 35 35
PEG_TXN9 38 37 PEG_RXN9
(6) PEG_TXN9 38 37 PEG_RXN9 (6)
PEG_TXP9 40 39 PEG_RXP9 3ND_MBDATA R658 R659 R660 R661
(6) PEG_TXP9 40 39 PEG_RXP9 (6)
42 41 *1K_4 *1K_4 *1K_4 1K_4
PEG_TXN8 42 41 PEG_RXN8
(6) PEG_TXN8 44 44 43 43 PEG_RXN8 (6)
PEG_TXP8 46 45 PEG_RXP8 02/15 REV_3A Add R680,R681
(6) PEG_TXP8 46 45 PEG_RXP8 (6)
48 47 R662 2 1 *0_4
PEG_TXN7 48 47 PEG_RXN7 R663 EN_A
(6) PEG_TXN7 50 50 49 49 PEG_RXN7 (6) 2 1 *0_4
PEG_TXP7 52 51 PEG_RXP7 +1.8V
(6) PEG_TXP7 52 51 PEG_RXP7 (6)
54 53 EN_B Close IC, no stub at
54 53

R664
PEG_TXN6 56 55 PEG_RXN6 C629
(6) PEG_TXN6 56 55 PEG_RXN6 (6) high-speed trace on

1
PEG_TXP6 58 57 PEG_RXP6 47p_4 R680 10K_4 EN_A
(6) PEG_TXP6 58 57 PEG_RXP6 (6) PCB layout.

37
36
35
34
33
32
31
30
29
60 60 59 59
PEG_TXN5 62 61 PEG_RXN5 R681 10K_4 EN_B +1.8V U42 +1.8V *0_4
(6) PEG_TXN5 62 61 PEG_RXN5 (6)
PEG_TXP5 64 63 PEG_RXP5 12/18 REV_2A Add C627

GND

SEL0_A
SEL1_A
SEL2_A
SEL3_A
EN_A
EN_B
NC2
NC1
(6) PEG_TXP5 64 63 PEG_RXP5 (6)
66 65

2
PEG_TXN4 66 65 PEG_RXN4 C669 4.7nF/16V_4
(6) PEG_TXN4 68 68 67 67 PEG_RXN4 (6) 1 VDD VDD 28
PEG_TXP4 70 69 PEG_RXP4 (14) SATA_TXP5 SATA_TX2+ 2 27 eSATA_TX2+_R 1 2 eSATA_TX2+
(6) PEG_TXP4 70 69 PEG_RXP4 (6) A+ AO+
72 71 (14) SATA_TXN5 SATA_TX2- 3 26 eSATA_TX2-_R 1 2 eSATA_TX2-
PEG_TXN3 72 71 PEG_RXN3 A- AO-
(6) PEG_TXN3 74 74 73 73 PEG_RXN3 (6) 4 GND GND 25
PEG_TXP3 76 75 PEG_RXP3 5 24 C670 4.7nF/16V_4
(6) PEG_TXP3 76 75 PEG_RXP3 (6) AVDD AGND
C 78 77 6 23 C672 4.7nF/16V_4 C
PEG_TXN2 78 77 PEG_RXN2 SATA_RX2+ VDD VDD eSATA_RX2+_R
(6) PEG_TXN2 80 80 79 79 PEG_RXN2 (6) (14) SATA_RXP5 7 BO+ BI+ 22 1 2eSATA_RX2+
PEG_TXP2 82 81 PEG_RXP2 (14) SATA_RXN5 SATA_RX2- 8 21 eSATA_RX2-_R 1 2eSATA_RX2-
(6) PEG_TXP2 82 81 PEG_RXP2 (6) BO- BI-
84 84 83 83 9 GND GND 20

SEL0_B
SEL1_B
SEL2_B
SEL3_B
PEG_TXN1 PEG_RXN1 C671 4.7nF/16V_4

CLKIN+
86 85 10 19

CLKIN-
(6) PEG_TXN1 86 85 PEG_RXN1 (6) VDD IREF

OUT+
PEG_TXP1 PEG_RXP1

OUT-
(6) PEG_TXP1 88 88 87 87 PEG_RXP1 (6)
90 89 R665 *470_4
PEG_TXN0 90 89 PEG_RXN0
(6) PEG_TXN0 92 92 91 91 PEG_RXN0 (6)
PEG_TXP0 94 93 PEG_RXP0 PI2EQX3201

11
12
13
14
15
16
17
18
(6) PEG_TXP0 94 93 PEG_RXP0 (6)
96 96 95 95
EV_CRT_DDCCLK 98 97 CLK_MXM#
(18) EV_CRT_DDCCLK 98 97 CLK_MXM# (2)
EV_CRT_DDCDAT 100 99 CLK_MXM Option SB to ESATA directly
(18) EV_CRT_DDCDAT 100 99 CLK_MXM (2)
102 102 101 101
EV_HDMI_DDCCLK 104 103 GFXRST#
(21) EV_HDMI_DDCCLK 104 103 GFXRST# (15)
EV_HDMI_DDCDAT 106 105 SYSFANON# R666 *0_4 R667 *0_4
(21) EV_HDMI_DDCDATA 106 105 SYSFANON# (3)
108 107 GFXON SATA_TX2+ 1 2 SATA_TX2+_R 1 2 eSATA_TX2+
108 107 MAINON (29,33,34,35)
EV_LVDS_DDCCLK 110 109 GFXPG R668 *0_4 R669 *0_4
(18) EV_LVDS_DDCCLK 110 109 GFXPG (29)

1
EV_LVDS_DDCDAT 112 111 3ND_MBDATA SATA_TX2- 1 2 SATA_TX2-_R 1 2 eSATA_TX2-
(18) EV_LVDS_DDCDAT 112 111 3ND_MBDATA (21,28,29)

1
114 113 3ND_MBCLK R672 *0_4 R677 *0_4
114 113 3ND_MBCLK (21,28,29)
EV_CRT_R 116 115 EV_LVDS_BLON SATA_RX2+ 1 2 SATA_RX2+_R 1 2 eSATA_RX2+ R670 R673 R671 R674 R676
(18) EV_CRT_R 116 115 EV_LVDS_BLON (18)
118 117 EV_LVDS_BL_BRGHT R678 *0_4 R679 *0_4 1K_4 *1K_4 *1K_4 *1K_4 R675 *0_4
118 117 EV_LVDS_BL_BRGHT (18)
EV_CRT_G 120 119 DVI_HPD SATA_RX2- 1 2 SATA_RX2-_R 1 2 eSATA_RX2- *0_4

2
(18) EV_CRT_G 120 119 DVI_HPD (21)
122 121

2
EV_CRT_B 122 121 EV_CRT_HSYNC
(18) EV_CRT_B 124 124 123 123 EV_CRT_HSYNC (18)
126 125 EV_CRT_VSYNC 03/03 REV_3A Change CN30 Footprint
126 125 EV_CRT_VSYNC (18)
EV_LVDS_LTX#2 128 127
(18) EV_LVDS_LTX#2
EV_LVDS_LTX2 130
128 127
129 EV_LVDS_UTX#2 and P/N update p/n to DFHS11FR021
(18) EV_LVDS_LTX2 130 129 EV_LVDS_UTX#2 (18)
B 132 131 EV_LVDS_UTX2 B
132 131 EV_LVDS_UTX2 (18)
EV_LVDS_LTX#1 134 133 USBPWR0 1 11/01 Modify footprint
(18) EV_LVDS_LTX#1 134 133 USB Vcc
EV_LVDS_LTX1 136 135 EV_LVDS_UTX#1 USBP7-_C 2
(18) EV_LVDS_LTX1 136 135 EV_LVDS_UTX#1 (18) D-
138 137 EV_LVDS_UTX1 C560 + USBP7+_C 3
138 137 EV_LVDS_UTX1 (18) D+
EV_LVDS_LTX#0 140 139 100u/6.3V_3528 4
(18) EV_LVDS_LTX#0 140 139 GND
EV_LVDS_LTX0 142 141 EV_LVDS_UTX#0 CN34
(18) EV_LVDS_LTX0 142 141 EV_LVDS_UTX#0 (18)
144 143 EV_LVDS_UTX0 USBPWR0
144 143 EV_LVDS_UTX0 (18) 1 5
EV_LVDS_LCLK# 146 145 5 USBP9-
(18) EV_LVDS_LCLK# 146 145 GND (15) USBP9- 2 6
EV_LVDS_LCLK 148 147 EV_LVDS_UCLK# eSATA_TX2+ 6 C574 + USBP9+
(18) EV_LVDS_LCLK 148 147 EV_LVDS_UCLK# (18) A+ (15) USBP9+ 3 7
150 149 EV_LVDS_UCLK R682 1 2 0_4 USBP7-_C eSATA_TX2- 7 100u/6.3V_3528
150 149 EV_LVDS_UCLK (18) VIN (15) USBP7- A- 4 8
EV_TV_C/R 152 151 R683 1 2 0_4 USBP7+_C 8
(22) EV_TV_C/R 152 151 (15) USBP7+ GND
154 153 eSATA_RX2- 9 12 USB
EV_TV_Y/G 154 153 eSATA_RX2+ B- Shield
(22) EV_TV_Y/G 156 156 155 155 10 B+ Shield 13
158 158 157 157 02/27 REV_3A Add Add R682,R682 11 GND Shield 14
10/25 Modify T63 EV_TV_COMP 160 159 C516 15 02/12 REV_3A Mount
160 159 Shield
162 162 161 161
EV_HDMICLK- 164 163 EV@*0.1u/50V_6 CN30
(21) EV_HDMICLK- 164 163 +5V
EV_HDMICLK+ 166 165 10/15 Modify 2006107-1 Close CN12
(21) EV_HDMICLK+ 166 165
168 168 167 167
EV_HDMITX2N 170 169 +5V 11/05 Modify footprint to "-H" USBP9- D41 2 1 EGA D37 2 1 EGA USBP0-
(21) EV_HDMITX2N 170 169
EV_HDMITX2P 172 171 02/15 REV_3A Add CN40
(21) EV_HDMITX2P 172 171 D44
174 173 USBP9+ 2 1 EGA D36 2 1 EGA USBP0+
(21) EV_HDMITX1N
(21) EV_HDMITX1P
EV_HDMITX1N
EV_HDMITX1P
176
178
174
176
178
173
175
177
175
177
+3V
C512 C515
USB board connector USBP7- D38 2 1 EGA D35 2 1 EGA USBP1-
180 180 179 179
EV_HDMITX0N 182 181 EV@*0.1u/10V_4 EV@*10u/6.3V_609/20 REV_A1 Modify USBP7+ D39 2 1 EGA D34 2 1 EGA USBP1+
(21) EV_HDMITX0N 182 181
EV_HDMITX0P 184 183 CN12
(21) EV_HDMITX0P 184 183 D40
186 185 USBPWR0 2 1 VPORT D16 2 1 VPORT +5VPCU

12
A 186 185 +5VPCU 1 A
188 187 (15,29) USBOC#1 USBOC#2
VIN_VGA 188 187 VIN_VGA VIN 2
190 190 189 189 3
192 191 R507 EV@*0_8 +3V USBP1+
VIN 192 191 VIN (15) USBP1+ 4
194 193 USBP1-
194 193 (15) USBP1- 5
196 195 USBP0+ 03/04 REV_3A Del CN40
198
196
198
195
197 197
C513 C514
(15)
(15)
USBP0+
USBP0-
USBP0- 6
7
Quanta Computer Inc.
200 200 199 199 8
USB_EN#2
EV@Tyco EV@*0.1u/10V_4 EV@*10u/6.3V_6
(29) USB_EN#1
+5VPCU
9 11 PROJECT : BL5M Montevina
10 Size Document Number Rev
BT@88266-100XX-XXX-10P-R 1A
09/29 REV_A1 Modify VGA CONNECTOR/USB/ESATA
Date: Monday, March 10, 2008 Sheet 19 of 37
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 5 4 3 2 1

Only For UMA

D D

C +3V C

HDMI IC
U9

39 22 IV_HDMITX2P
(6) TMDSB_DATA2 IN_D+ OUT_D1+ IV_HDMITX2P (21)
(6) TMDSB_DATA2# 38 23 IV_HDMITX2N IV_HDMITX2N (21)
IN_D1- OUT_D1-
R274 R273 (6) TMDSB_DATA1 42 19 IV_HDMITX1P IV_HDMITX1P (21)
IN_D2+ OUT_D2+ IV_HDMITX1N
(6) TMDSB_DATA1# 41 20 IV_HDMITX1N (21)
[email protected]_4 [email protected]_4 IN_D2- OUT_D2-
(6) TMDSB_DATA0 45 16 IV_HDMITX0P IV_HDMITX0P (21)
IN_D3+ OUT_D3+ IV_HDMITX0N
(6) TMDSB_DATA0# 44 17 IV_HDMITX0N (21)
SDVO_CTRLCLK IN_D3- OUT_D3-
(6) SDVO_CTRLCLK SDVO_CTRLDATA IV_HDMICLK+
(6,11) SDVO_CTRLDATA (6) TMDSB_CLK 48 13 IV_HDMICLK+ (21)
IN_D4+ OUT_D4+ IV_HDMICLK-
(6) TMDSB_CLK# 47 14 IV_HDMICLK- (21)
IN_D4- OUT_D4-
SDVO_CTRLCLK 9 28 IV_HDMI_DDCCLK
+3V SCL SCL_SINK IV_HDMI_DDCCLK (21)
SDVO_CTRLDATA 8 29 IV_HDMI_DDCDATA IV_HDMI_DDCDATA (21)
SDA SDA_SINK
R270 IHM@*4.7K_4 OC_0 HDMI_LF_HPOUT 7 30 HTPLG
HPD HPD_SINK HTPLG (21)
R271 IHM@*4.7K_4 OC_1 2
VCC[1] +3V
11
R275 IHM@*4.7K_4 OC_3 OE# VCC[2]
25 15
OE# VCC[3]
03/03 REV_3A Add R578,R655,R577 VCC[4]
21
DDC_EN 32 26
R578 IHM@0_4 OC_0 DDC_EN VCC[5]
33
OC_3 VCC[6]
10 40
R655 IHM@0_4 OC_1 OC_3 VCC[7]
46
VCC[8]
R577 IHM@0_4 OC_3 OC_0 3
OC_1 OC_0
03/03 REV_3A DNI R272 4 OC_1 GND[1] 1
5
R272 IHM@*499/F_4 GND[2]
6 12
OC_2(REXT) GND[3]
18
GND[4]
27 GND GND[5] 24
GND[6] 31
+3V
9/11 GND[7]
36
EQ_0 34 37
B
R225 [email protected]_4 EQ_0 FAE recommend OC_3 and OE# EQ_1 EQ_0 GND[8] B
35 43
EQ_1 GND[9]
reverse PU 4.7K GND[10]
49
R224 IHM@*4.7K_4 EQ_1
IHM@PI3VDP411LST
R226 [email protected]_4 DDC_EN

R227 IHM@*4.7K_4 OE#

+3V
EQUALIZATION SETTING
R685 [email protected]_4 EQ_1 EQ_0 EQ_1 EQUALIZATION
R684 IHM@*4.7K_4 OE# 0 0 3dB C244 C229 C243 C221

0 1 6dB [email protected]/10V_4 [email protected]/16V_4 [email protected]/10V_4 [email protected]/16V_4

03/03 REV_3A Add R685 1 0 9dB

1 1 12dB

11/01 Add

+3V

R252

IHM@20K_4

Port-B_HPD#
Port-B_HPD# (6)
A A
3

HDMI_LF_HPOUT R283 IHM@0_4 2 R260

Q20 [email protected]/F_6
IHM@2N7002
1

R284
IHM@100K_4 Quanta Computer Inc.
PROJECT : BL5M Montevina
Size Document Number Rev
1A
PI3VDP411LST(HDMI)
Date: Monday, March 17, 2008 Sheet 20 of 37
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 5 4 3 2 1

U28 *RCIamp0514M
IV_HDMITX2N 4 3 HDMITX2N R182 0_4 R174 0_4 HDMITX2P_C 1 1 HDMITX2P_C
(20) IV_HDMITX2N IV_HDMITX2P HDMITX2P HDMITX2N_C 10 10 HDMITX2N_C
2 1 2 2
(20) IV_HDMITX2P RN1 IV@0X2 L15 *WCM2012-90 L13 *WCM2012-90 9 9
3 VCC GND 8
4 3 HDMITX2N 4 3 HDMITX2N_C HDMITX0N 4 3 HDMITX0N_C HDMITX1P_C 4 4 HDMITX1P_C
(19) EV_HDMITX2P
HDMITX2P HDMITX2P_C HDMITX0P HDMITX0P_C HDMITX1N_C 7 7 HDMITX1N_C
2 1 1 2 1 2 5 5
(19) EV_HDMITX2N RN2 EV@0X2 6 6

IV_HDMITX1N 4 3 HDMITX1N R184 0_4 R175 0_4

(20) IV_HDMITX1N
IV_HDMITX1P 2 1 HDMITX1P HDMITX0P_C 1 10 HDMITX0P_C
(20) IV_HDMITX1P 1 10
RN3 IV@0X2 R177 0_4 R170 0_4 HDMITX0N_C 2 9 HDMITX0N_C
2 9
(19) EV_HDMITX1P 4 3 3 VCC GND 8
2 1 L14 *WCM2012-90 L12 *WCM2012-90 HDMICLK+_C 4 7 HDMICLK+_C
(19) EV_HDMITX1N 4 7
RN4 EV@0X2 HDMITX1N 4 3 HDMITX1N_C HDMICLK- 4 3 HDMICLK-_C HDMICLK-_C 5 6 HDMICLK-_C
HDMITX1P HDMITX1P_C HDMICLK+ HDMICLK+_C 5 6
1 2 1 2
IV_HDMITX0N 4 3 HDMITX0N U26 *RCIamp0514M
(20) IV_HDMITX0N
IV_HDMITX0P 2 1 HDMITX0P
(20) IV_HDMITX0P RN5 IV@0X2
D R179 0_4 R172 0_4 D
(19) EV_HDMITX0P 4 3
(19) EV_HDMITX0N RN6
2 1
EV@0X2
10/19 REV_A1 Change net
+5VPCU U25 *RCIamp0514M
IV_HDMICLK+ RN7 2 1 IV@0X2 HDMICLK+ HDMI_DDCDATA_C 1 1 HDMI_DDCDATA_C
(20) IV_HDMICLK+
IV_HDMICLK- HDMICLK- HDMI_DDCCLK_C 10 10 HDMI_DDCCLK_C
(20) IV_HDMICLK- 4 3 2 2
9 9
D11 RSX101M F2 3 VCC
RN8 DDC5V GND 8 DDC5V
2 1 EV@0X2 2 1 4 4
(19) EV_HDMICLK-
HDMI_HP 7 7 HDMI_HP
4 3 5 5
(19) EV_HDMICLK+
POLY SWITCH 1.1A/6V_1206 6 6

C473 C170

10u/10V_8 0.1u/10V_4 Layout note:

Place close
to HDMI
Conn
02/27 REV_3A Mount C473

10/24 REV_A1 Add Q50,Q51,R156,R168,R606,R608

CN23
+5VPCU +5VPCU
HDMITX2P_C 1
CEC_POWER D2+
2
+3V HDMITX2N_C D2 Shield
3
HDMITX1P_C D2-
4
D1+
5
HDMITX1N_C D1 Shield
6 20
R178 HDMITX0P_C D1- SHELL1
7 21
R168 D0+ SHELL2
CEC@0_4 8
R171 R176 R169 HDMITX0N_C D0 Shield
[email protected]_4 9 22
[email protected]_4 [email protected]_4 [email protected]_4 HDMICLK+_C D0- SHELL3
10 23
CK+ SHELL4
11
HDMICLK-_C CK Shield
C 12 C
Q11 Q13 CEC CK-
13
CE Remote
1

1
CEC@2SK3541 CEC@2SK3541 14
2.2K_4 R163 HDMI_DDCCLK_C NC
15
HDMI_DDCDATA_C HDMI_DDCDATA 2.2K_4 R159 HDMI_DDCDATA_C DDC CLK
3 2 3 2 16
DDC DATA
17
DDC5V GND
18
RP33 2 HDMI_HP +5V
1 IV@0X2 IV_HDMI_DDCDATA (20) 19
R167 CEC@*0_4 R487 CEC@*0_4 HP DET
4 3 IV_HDMI_DDCCLK (20)
To HDMI CONN 10/19 REV_A1 Change net
4 3 EV_HDMI_DDCDATA (19) HDMI-C12816-119A5-L
CEC_POWER 2 1
EV@0X2 EV_HDMI_DDCCLK (19)
Q12 Q14 RP32
1

1
CEC@2SK3541 CEC@2SK3541
02/12 REV_3A Change footprint
HDMI_DDCCLK_C 3 2 HDMI_DDCCLK 3 2 10/19 REV_A1 Change footprint
12/18 REV_2A Change footprint
CEC_POWER
R173 CEC@*0_4 R486 CEC@*0_4
C179 CEC@*0.1u/10V_4 U5
5 1
2
4 3

CEC@*TC7SET14FU
CEC_POWER

CEC_POWER +3VPCU
C508 [email protected]/10V_4 U30
5 1
2 R189
HPDET 4 3 D12
CEC@10K_4 CEC@CH500H-40
CEC@NL17SZ17
CEC_IN
+3VPCU

3
B C509 [email protected]/10V_4 U31 R193 B
To EC 5 1 CEC@27K_4
2 HDMI_HP Q42
4 3 R496 [email protected]/F_4 1 CEC
(29) CEC_EC_HP +3V_S5 +3VPCU
+3V
From HDMI conn Pin 19
CEC@NL17SZ17 R497 CEC@2SK3541
(Hot Plug Det) To HDMI CONN Pin 13
CEC@470K/F_4
To IV/EV VGA C511 [email protected]/10V_4 CEC@*0_4

3
R211 CEC@0_4
Hot Plug Detect R208
5

1
R504 4 CEC_OUT 1
(19) DVI_HPD
EV@1K_4 2 PLTRST# CEC_P R187 CEC@27K_4
PLTRST# (15,24,25,28,29)
3

R506 U32 Q16

(20) HTPLG
2

IV@1K_4 CEC@TC7SH08FU CEC@2N7002 CEC@2SK3541

2
R188 Q43
CEC_SCLK 3 1 CEC@100K_4

R505 *0_6 CEC_POWER

+5VPCU
RP51 CEC@*0_4P2R_S
CEC_POWER
4 3 SCLK (2,16,25,28) To SB
R503 0_6 CEC_P 2 1
+3VPCU SDATA (2,16,25,28)
C507 CEC@*22p_6 XIN_CEC Q15
2

CEC@2N7002
1

Y5 RP52 CEC@0_4P2R_S
CEC_POWER CEC_SDATA 3 1 4 3 3ND_MBCLK (19,28,29) To EC
CEC@*8 MHz 2 1 3ND_MBDATA (19,28,29)
R192 R488
2

C506 CEC@*22p_6 XOUT_CEC [email protected]_4 [email protected]_4

C483
C178 U27
CEC@1u/10V_6 [email protected]/10V_4
7 1 CEC_SCLK
VCC SCL CEC_SDATA
16 VCC SDA 20
CEC_POWER 18 HDMI_DDCDATA
CEC@47K_4 R191 XOUT_CEC 4 DDCSDA HDMI_DDCCLK
CEC_POWER 17
C510 CEC@*0.1u/10V_4 CEC@47K_4 R190 XIN_CEC XOUT DDCSCL
A 6 A
XIN
TEST1 13 4 3
1 2 CEC-RESET# 3 12 2 1
3 4 CEC-MODE 8
RESET TEST0 RP50 [email protected] CEC_POWER
CEC@*G691L308T73UF [email protected] RP53 MODE CEC_OUT
10
CEC OUT CEC_IN
3 5 9
Vcc CEC-RESET# VSS CEC IN
Reset# 1 15 NC
2 14 19 HPDET
GND NC HPDET
11 2
U29 T129 CEC-RESET# NC NC

T130 CEC-MODE CEC@R5F211A4SP Quanta Computer Inc.

PROJECT : BL5M Montevina
03/03 REV_3A Change P/N Size Document Number Rev
1A
HDMI+CEC
Date: Monday, March 10, 2008 Sheet 21 of 37
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 5 4 3 2 1

SATA ODD CN24

GND14 14 +3V +3V

1 R216 EV@0_4 SYS_TV_Y/G

GND1 (19) EV_TV_Y/G

1
RXP 2 SATA_TXP4 (14)
3 R217 EV@0_4 SYS_TV_C/R D8 D9
RXN SATA_TXN4 (14) (19) EV_TV_C/R
4 3 TV-CHROMA 3 TV-LUMA
GND2
TXN 5 SATA_RXN4 (14)
6 SATA_RXP4 (14) *DA204U *DA204U
TXP
7

2
GND3
R204 IV@0_4
(6) INT_TV_Y/G
8 R495 1K_4 Device Present
DP R205 IV@0_4
+5V 9 (6) INT_TV_C/R
10 +5VSATA_ODD R485 0_8
+5V +5V
11
RSVD
D 12 D
GND C496 C497 C489 C484
13
GND
15 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 10u/10V_8
GND15 L6 BLM18PG181SN1D CN20 L10 BLM18PG181SN1D
C18534-11305-L SYS_TV_C/R TV-CHROMA 4 3 TV-LUMA SYS_TV_Y/G
4 3

11/02 Modify footprint 6

6 5
5
R82 C75 C70 C118 C110 R119

150/F_4 6p_4 6p_4 6p_4 6p_4 150/F_4

10/15 Add 2
2 1
1

HOLE37 SUYIN_030018FR004S100FR
H-C236D146P2-8
7 6
8 5
9 4
1
2
3

10/25 Modify
R215 R212 11/01 Modify Footprint
*0_4 *0_4

03/05 REV_3A Reserve R215,R212 fro EMI TVOUT

W-LAN&BT LED

C CPU SINK VGA SINK MB SINK

10/23 REV_A1 Modify footprint LED / WLAN SW 02/12 REV_3A change LED3
Mainstream --> Orange
Low Cost --> Orange
C
10/26 REV_A1 Modify footprint LED4,LED3 footprint 1 2 RF_LED_R R650 390_4
and P/N RF_LED (29)
HOLE38 HOLE39 HOLE41 HOLE10 HOLE31 HOLE33 HOLE3 HOLE14 HOLE29
H-C236D146P2-8 H-C236D146P2-8 *H-C236D146P2-8 *H-C315D118P2-8 *H-C335D118P2-8 *H-C276D118P2-8 H-C236D146P2-8 *H-TC217C131D91P2
*H-TC217C131D91P2 27-21UYOC/S530-A3/TR8
7 6 7 6 7 6 7 6 7 6 7 6 7 6
8 5 8 5 8 5 8 5 8 5 8 5 8 5 WiMAX LED
9 4 9 4 9 4 9 4 9 4 9 4 9 4 HOLE30 HOLE22 HOLE46
*h-sped110p2 *H-SPED118P2 *H-C236D98BN 27-21/BHC-ZL1M2TY/3C
+5V R649 100_4 2 1WiMAX_R 1 3
1
2
3

1
2
3

1
2
3

1
2
3

1
2
3

1
2
3

1
2
3

1
02/12 LED4 Q51
REV_3A

2
HOLE15 HOLE40 HOLE16 HOLE34 HOLE32 HOLE19 HOLE18 HOLE20 10/25 Modify BSS84

1
H-C236D146P2-8 H-C236D146P2-8 H-C236D146P2-8Modify *h-ts315bc295d118p2
*h-tsbc315d118p2*H-C315D118P2-8 *H-TC217C131D91P2
*H-TC217C131D91P2 03/07 REV_3A Mount R649
7 6 7 6 7 6 HOLE32 to 7 6 R420 +3V
(25) WiMAX_LED#
8 5 8 5 8 5 8 5
9 4 9 4 9 4 AGND 9 4 03/10 REV_3A Add 10K_4
09/27 REV_A1
Modify 10/26 REV_A1 Add
1
2
3

1
2
3

1
2
3

1
2
3

1
D47
Footprint
12/18 REV_2A Modify 10/26 REV_A1 Del HOLE34 for EXP
ADOGND RF_LED_R
HOLE12 HOLE11 HOLE9 HOLE2 1
*H-C315D118P2-8 *H-C315D118P2-8 *H-C335D118P2-8 H-C236D146P2-8 HOLE24 HOLE28 10/30 Copy from BL5S
*H-TC217C131D91P2
*H-TC217C131D91P2 3
7 6 7 6 7 6 7 6
MINI-1 SINK MODEM 8
9
5
4
8
9
5
4
8
9
5
4
8
9
5
4
12/18 REV_2A Add WiMAX_R
2
HOLE36 HOLE35 HOLE23 BZ5V6
H-c236d146p2-8 H-c236d146p2-8 H-C236D146P2-8 HOLE13 HOLE45
1
2
3

1
2
3

1
2
3

1
2
3

7 6 7 6 7 6 *H-C91D91N *H-C98D98N D24

1

8 5 8 5 8 5 +5V
9 4 9 4 9 4 11/05 Add LOGO_1
HOLE7 HOLE17 HOLE25 HOLE21 HOLE6 HOLE5 1
*H-C335D118P2-8 *H-C335I248D118P2-8
*H-C335D118P2-8 H-C197D83P2-8 *H-C217D87P2 *H-C217D87P2
1
2
3

1
2
3

1
2
3

R418 3
7 6 7 6 7 6 7 6

1
8 5 8 5 8 5 8 5 LOGO_2
2
B 02/12 REV_3A Change footprint 9 4 9 4 9 4 9 4 10K_4 B
D26 BZ5V6
R417
MINI-2 SINK
1
2
3

1
2
3

1
2
3

1
2
3

2 1 ODD_LED#
(28) IDE_LED# ODD_LED#
BAS316 02/27 REV_3A Mount D24,D47
HOLE44 HOLE27 HOLE42 HOLE43
150_4
H-c236d146p2-8 H-c236d146p2-8 H-c236d146p2-8 H-c236d146p2-8 HOLE8 HOLE1 HOLE4 HOLE26 10/20 REV_A1 Add
7 6 7 6 7 6 7 6 *H-C315D118P2-8 *H-C315D118P2-8 *H-C335D146P2-8 H-C197D83P2-8
8 5 8 5 8 5 8 5 7 6 7 6 7 6 7 6 10/22 REV_A1 Modify +5V
9 4 9 4 9 4 9 4 8 5 8 5 8 5 8 5
9 4 9 4 9 4 9 4 02/12 REV_3A Change R415,R414 value
1
2
3

1
2
3

1
2
3

1
2
3

R419 +5V +5V

1
2
3

1
2
3

1
2
3

1
2
3

D27 10K_4 Q52

2 1 HDDLED# MMBT3906 R415 R414
09/20 REV_A1 Add HOLE32,HOLE33 for ESATA D50 2 1 EGA_4 SATA_TXP1 09/20 REV_A1 Add HOLE30,HOLE31 for ESATA BAS316 330_4 330_4
D51 2 1 EGA_4 SATA_TXN1
D52 2 1 EGA_4 SATA_RXN1

2'nd SATA HDD SATA HDD

2
D53 2 1 EGA_4 SATA_RXP1
D54 2 1 EGA_4 SATA_TXP0
D55 2 1 EGA_4 SATA_TXN0
D56 99-113UNC/V90/TR8 99-113UNC/V90/TR8
CN31 2 1 EGA_4 SATA_RXN0
CN33 SATA_LED# (14)
D57 2 1 EGA_4 SATA_RXP0 LED2 LED1
23 02/12 REV_3A Add for ESD 23

1
GND23 GND23
10/25 Modify Mainstream --> White
1 1 Low Cost --> N/A
GND1 SATA_TXP0 GND1 SATA_TXP1 12/18 REV_2A Change LED type

LOGO_1
2 SATA_TXP0 (14) 2 SATA_TXP1 (14)
RXP SATA_TXN0 RXP SATA_TXN1

LOGO_2
3 SATA_TXN0 (14) 3 SATA_TXN1 (14)
RXN RXN
4 4
GND2 SATA_RXN0 GND2 SATA_RXN1 +3VPCU
5 SATA_RXN0 (14) 5 SATA_RXN1 (14)
TXN SATA_RXP0 TXN SATA_RXP1
6 SATA_RXP0 (14) 6 SATA_RXP1 (14)
TXP TXP
7 7
GND3 GND3

3
R409
10K_4
8 +3.3VSATA_2 R338 *0_8 +3V 8 +3.3VSATA +3V
3.3V 3.3V LED_LOGO LED_LOGO
9 9 2 2
3.3V 3.3V (29) LED_LOGO
A 10 10 A
3.3V 3.3V
GND 11 C329 C325
GND 11 C327 C331 12/18 REV_2A Change P/N SW1 Q28 Q30
12 12 2 2N7002 2N7002
GND GND
13 *4.7u/10V_8 *0.1u/10V_4 13 *4.7u/10V_8 *0.1u/10V_4 03/09 REV_3A Del

1
GND GND *0.1u/10V_4
14 14 (29) KILL_SW 1
5V 5V C393
15 15
5V +5VSATA_2 R320 0_8 5V +5VSATA R547 0_8
5V 16 +5V 5V 16 +5V 3
17 17 +3VPCU D25
GND GND DA204U SW-NSS506-212F-CCCD1T-3P
18 18
RSVD C297 C296 C295 C310 RSVD C322 C561 C562 C531
19 19
GND GND 1
20 20
12V
12V 21 0.1u/10V_4 0.1u/10V_4 10u/10V_8150u/6.3V_7343 12V
12V 21 0.1u/10V_4 0.1u/10V_4 10u/10V_8150u/6.3V_7343
3
Quanta Computer Inc.
22 22
12V 12V
24 24
2 PROJECT : BL5M Montevina
GND24 GND24
02/12 REV_3A Change footprint Size Document Number Rev
SA@127043FR022XX27ZR 02/12 REV_3A Change footprint SA@127043FR022GX51ZR
PATA/ODD/TV/LED 1A

Date: Monday, March 10, 2008 Sheet 22 of 37

5 4 3 2 1

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 A B C D E

VCC_XD
CARDREADER POWER
C317 C548 C549

+3VARUN 0.01u_4 0.01u_4 0.01u_4

C364 C362 C363 09/20 REV_A1 Add U39

4.7u/6.3V_6 0.1u/10V_4 0.1u/10V_4

+3V U33 30mil

RT9711BPF
4 +3V L23 BK1608HS220_6 +1.8V 2 8 VCC_XD 4
IN1 OUT3 VCC_XD
3 7
IN2 OUT2
6
C521 MC_PWR_3V# 4 OUT1
C357 C367 C385 C369 C386 C358 EN#
1
1u/16V_8 GND *10K_4 R537
9 5 +3V
4.7u/6.3V_6 0.1u/10V_4 0.1u/10V_4 4.7u/6.3V_6 0.1u/10V_4 0.1u/10V_4 GND-C OC#

U15 09/20 REV_A1 C569 from 4.7u/6.3V_6 to 1u/16V_8

102
103
122

120
125
OZ129T 10/30 Change Value and need change PN

26
56

67
73
79
81

14
15
91
92
7
AD[31..0]
(15) AD[31..0]
09/20 REV_A1 Del Q43,R489

PCI_VCC
PCI_VCC
3.3VCCD
3.3VCCD
3.3VCCD
3.3VCCD

1.8VCCD
1.8VCCD
1.8VCCD
1.8VCCD
1.8VCCD
1.8VCCD
3.3VCCA
3.3VCCA
3.3VCCA
3.3VCCA
AD31 19
AD30 AD31 C360 15p_4
20
AD29 AD30 R379 5.9K/F_4
21 78
AD29 REF

2
AD28 22 Y4 24.576MHz
AD27
AD26
23
24
AD28
AD27
AD26
XI
XO
83
84
1394_XIN
1394_XOUT 5 IN 1 CARD READER SD/MS_CLK_C

AD25 25

1
AD24 AD25 TPBIAS0 C359 15p_4 C627
REQ0# AD17 AD23
27
AD24 TPBIAS
76
TPA0P
29 75
AD22 AD23 TPA+ TPA0N *22p_4 12/19
GNT0# INTA# 30
AD22 TPA-
74 H=1.2mm Better than 50ppm REV_2A Add
AD21 31 72 TPB0P
AD20 AD21 TPB+ TPB0N
32
AD20 TPB-
71 02/27 REV_3A DNI C627
AD17 R386 100/F_4 OZ129_IDSEL AD19 34
AD18 AD19 CN32
35
AD17 AD18 MC_PWR_3V# XD_CLE R564 0_4 XD_CLE_C
36 4 6 43
AD16 AD17 MC_3V# SD/MS_CLK SD_D2 R560 0_4 SD_D2_C CLE_XD GND
37 113 9 42
AD15 AD16 SD/MS_CLK SD_D3 XD_WPO# R559 0_4 XD_WPO#_C DAT2_SD GND-SDIO SD/MS_CLK_C R552 0_4 SD/MS_CLK
The 100ohm is that reduce the notice form PCI signal AD14
47
AD15 SD_D3
111
SD_D2 XD_CD# R567 0_4 XD_CD#_C
10
-WP_XD CLK_SD
25
MS_BS/XD_D3_C R349 0_4 MS_BS/XD_D3
48 112 2 26
AD13 AD14 SD_D2 SD_D1 XD_R/B# R563 0_4 XD_R/B#_C CD_XD MS-BS
49 107 3 27
3 AD12 AD13 SD_D1 SD_D0 XD_ALE R562 0_4 XD_ALE_C R/-B_XD VSS_SD 3
50 108 7 28
AD11 AD12 SD_D0 SD_CMD XD_RE# R566 0_4 XD_RE#_C ALE_XD MS-VSS MS_D2/XD_D1_C
51 110 4 29
AD10 AD11 SD_CMD SM_WPI#/SD_WP -RE_XD D1_XD SD_D0_C R551 0_4 SD_D0
52 117 1 30
AD9 AD10 SM_WPI#/SD_WP SD_CD# VCC_XD GND_XD DAT0_SD MS_D0/XD_D2_C
53 114 11 31
AD8 AD9 SD_CD# MS-VSS D2_XD SD_D1_C R550 0_4 SD_D1
54 32
AD7 AD8 MS_D1/XD_D7 DAT1_SD MS_BS/XD_D3_C
57 95 13 33
AD6 AD7 MS_D1/XD_D7 XD_D6 MS_CD# R555 0_4 MS_CD#_C MS-VCC D3_XD XD_D4_C R343 0_4 XD_D4
58 93 18 34
AD5 AD6 XD_D6 XD_D5 MS-INS D4_XD XD_D5_C R342 0_4 XD_D5
59 89 19 35
AD4 AD5 XD_D5 XD_D4 VSS_SD D5_XD XD_D6_C R341 0_4 XD_D6
60 87 17 36
AD3 AD4 XD_D4 MS_BS/XD_D3 SD_CMD R557 0_4 SD_CMD_C GND_XD D6_XD MS_D1/XD_D7_C
61 88 15 37
AD2 AD3 MS_BS/XD_D3 MS_D0/XD_D2 SD/MS_CLK_C CMD_SD D7_XD
62 90 14 38 VCC_XD
AD1 AD2 MS_D0/XD_D2 MS_D2/XD_D1 MS_D3/XD_D0 R556 0_4 MS_D3/XD_D0_C MS-SCLK VCC_XD SD_CD#_C R360 0_4 SD_CD#
63 94 16 39
AD0 AD1 MS_D2/XD_D1 MS_D3/XD_D0 MS_D2/XD_D1 R554 0_4 MS_D2/XD_D1_C MS-DATA3 C/D_SD
64 96 20 40
AD0 MS_D3/XD_D0 XD_CE# MS-DATA2 GND_SD SM_WPI#/SD_WP_C R382 0_4 SM_WPI#/SD_WP
119 41
XD_CE# XD_R/B# XD_CE# R565 0_4 XD_CE#_C W/P_SD
(15) CBE3# 28 100 5
C/BE3# XD_R/B# XD_CLE XD_WE# R561 0_4 XD_WE#_C -CE_XD
(15) CBE2# 38 118 8
C/BE2# XD_CLE XD_ALE SD_D3 R558 0_4 SD_D3_C -WE_XD MS_D1/XD_D7_C R553 0_4 MS_D1/XD_D7
(15) CBE1# 46 109 12 24
C/BE1# XD_ALE XD_WE# CD/DAT3_SD MS-DATA1 MS_D0/XD_D2_C R348 0_4 MS_D0/XD_D2
(15) CBE0# 55 105 VCC_XD 21 22
C/BE0# XD_WE# XD_RE# VDD_SD SDIO/MS-DATA0 MS_D3/XD_D0_C
101 23
OZ129_IDSEL XD_RE# XD_WPO# D0_XD
5 98
IDSEL XD_WPO# MS_CD# MXP038-01-A_CARD READER
(2) PCLK_OZ129 45 99
PCI_CLK MS_CD# XD_CD#
(15) DEVSEL# 42 97
DEVSEL# XD_CD#
(15) FRAME# 39
FRAME#
(15) IRDY# 40
IRDY#
(15) TRDY# 41 2
TRDY# NC1
(15) STOP# 43
STOP# NC2
8 03/03 REV_3A Change P/N
(15) PAR 44 9
PAR NC6
(15) REQ0# 17 10
REQ# NC7
(15) GNT0# 18 13
GNT# NC5
(15) PCIRST#
(15) INTA#
INTA#
PCI_PME#
1
11
3
PCI_RST#
INTA#
NC3
NC4
126
127
128
1394
(15) PCI_PME# PME# NC8
CLKRUN# 6
(16,29) CLKRUN# CLKRUN#
2 2
(28) TP_XD_LED 106 85
MEDIA_ACTV TEST0 TPBIAS0 C361 1394@1u/10V_4
86
TEST1
AGND
AGND
AGND
AGND
AGND
AGND

03/07 REV_3A Del RN29,RN30

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

MEDIA_LED: 1=Enable MEDIA_LED activity(Default)

R362 R363
H=1.6mm
12
16
33
66
68
104
115
116
121
123
124

65
69
70
77
80
82

[email protected]/F_4 [email protected]/F_4
L24 0_6

TPA0P TPA0P CN37

As close as TPA0N TPA0N 5
possible to OZ129 TPB0N 1
TPA0N 3
TPA0P 4
TPB0P 2 6
TPB0N TPB0N
TPB0P TPB0P
1394@C13121-100A

PCLK_OZ129 R365 R364

[email protected]/F_4 [email protected]/F_4

R383 1394_COM

*22_4 C345
R366
1394@270P_4
[email protected]/F_4
1 C368 1

*22p_4

Reserve EMI Quanta Computer Inc.

MMC Size Document Number

PROJECT : BL5M Montevina
OZ129T (Card Reader/1394)
Rev
1A

Date: Monday, March 10, 2008 Sheet 23 of 37

A B C D E

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 5 4 3 2 1

LAN_MARVELL_88E8040/88E8055
BOM Option Table AUX3V_S5 +2.5V_1.8V_LAN
+3V_S5
L16
Reference Description C249 10u/6.3V_8
40@ 10/100 : 88E8040 10/100 : 88E8040 P/N : AL008040001 C555 0.1u/16V_4 55_72@BK1608HS220_6_1A C220 C215 C535 C530 C540
+2.5V_1.8V_LAN
55@ GIGA : 88E8055 GIGA : 88E8055 P/N : AJ080550000 C544 0.1u/16V_4 [email protected]/6.3V_6
R235
0.1u/16V_4 0.1u/16V_4 0.1u/16V_4
55_72@ GIGA : 88E8072 GIGA : 88E8072 P/N : AL008072000 C559 0.1u/16V_4 [email protected]/16V_4
[email protected]_4

3
Q17 C551
D U34 C556 0.1u/16V_4 D

E
1 CTRL18 1 [email protected]/6.3V_6
VDDO_TTL +3V_S5 B
40 C527 0.1u/16V_4 4 C546 C541 C536 C539
VDDO_TTL C

C
C532 0.1u/10V_4 PCIE_RXN2_C 50 45 25 mil Trace width
(15) PCIE_RXN2 TX_N VDDO_TTL
C529 0.1u/10V_4 PCIE_RXP2_C 49 61 55_72@BCP69T1 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4
(15) PCIE_RXP2

2
TX_P VDDO_TTL
(15) PCIE_TXN2 53 RX_N
(15) PCIE_TXP2 54 RX_P AVDDH 8

56 23 C223
(2) CLK_PCIE_LAN# REFCLKN AVDD +2.5V_1.8V_LAN
(2) CLK_PCIE_LAN 55 REFCLKP AVDD 19
22 [email protected]/6.3V_6
AVDD
AVDD 28

35 SPI_DI AVDDL 51
34 SPI_DO AVDDL 52
37 SPI_CLK
36 32 +1.2V_LAN
SPI_CS NC
NC 57

VDD25 64
R536 [email protected]_4 PU_VDDO_TTL 43 C246 C237 C558 C554 C542 C557
+3V_S5 PU_VDDO_TTL +1.2V_LAN
42 4 CTRL18 R269
CLKREQn
88E805X CTRL18 [email protected]/6.3V_6
[email protected]_4
[email protected]/16V_4
0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4

VDD 2 +1.2V_LAN

3
VPD_DATA 41 7 Q18 C523
VPD_CLK VPD_DATA VDD
38 13

E
VPD_CLK VDD CTRL12 [email protected]/6.3V_6
VDD 33 1 B
39 4 C526 C528 C524 C525
VDD C

C
R570 0_4 5 44 25 mil Trace width
(15,21,25,28,29) PLTRST# PERSTn/TSTPT VDD
48 55_72@BCP69T1 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4

2
VDD
(16,25,28) PCIE_WAKE# 6 WAKEn VDD 58
C C
R569 4.87K/F_4 LAN_RSET 16 3 CTRL12
RSET CTRL12 C247
46 TESTMODE TSTPT 29
[email protected]/6.3V_6
LAN_RSET +3V 47 VMAIN_AVLBL HSDACN 25
+3V_S5 12 VAUX_AVLBL
HSDACP 24
2K Ohm for 8040 9 SWITCH_VAUX

4.87K Ohm for 8055/72 11 SWITCH_VCC MDIN[3] 31 TX3N

TX3P
MDIP[3] 30
R572 4.7K_4 LOM_DISABLE# 10 27 TX2N
+3V_S5 LOM_DISABLEn MDIN[2]
26 TX2P
D28 LAN_XIN MDIP[2] TX1N
(29) LOM_DISABLE 15 XTALI MDIN[1] 21
20 TX1P
*BAS316 LAN_XOUT MDIP[1] TX0N
14 XTALO MDIN[0] 18
17 TX0P
MDIP[0]
10/24 REV_A1 Add

2
4

2
4

2
4

2
4
12/18 REV_2A Add 74 GND10
C552 65 59 LAN_ACTLED# RN28 RN27 RN26 RN25
27p_4 LAN_XIN GND1 LED_ACTn 100MBPS# R548 *0_4 LAN_LINKLED#
66 GND2 LED_LINK10/100n 60
67 62 1000MBPS# R549 *0_4 [email protected]/F_4P2R [email protected]/F_4P2R [email protected]/F_4P2R [email protected]/F_4P2R

1
3

1
3

1
3

1
3
GND3 LED_LINK1000n 10_1000MBPS# R568 0_4
68 GND4 LED_LINKn 63 12/10 REV_3A DNI RR513,R514,U11
4
3

69 GND5 Mount R508

Y6 70 GND6
25MHz-S
H = 0.8mm 71
72
GND7
LAN_N1 LAN_N2 LAN_N3 LAN_N4
GND8 C547 C550 C545 C543 C537 C538 C534 C533
73
2
1

GND9
C553 88E8040_55 *[email protected]/16V_4 55@1000p_4 [email protected]/16V_4 55@1000p_4 [email protected]/16V_4 55@1000p_4 [email protected]/16V_4 55@1000p_4 +3V_S5
27p_4 LAN_XOUT
B B
10/24 REV_A1 Modify
R513 R514
*4.7K_4 *4.7K_4
U11
DELTA 10/100 : LFE8696-R P/N : DB0MA8LAN00 VPD_DATA
VPD_CLK
5
6
SDA A0 1
2
SCL A1
H = 4mm GIGA : LFE9249-R P/N : DB0ZR1LAN11 7
A2 3

CN26 WP

HWS 10/100 : HPL-4001B P/N : DB0SA1LAN01 LAN_ACTLED# 12

R508
0_4
4 GND VCC 8 +3V_S5
Y-
H = 4mm GIGA : HPL-5001-3 P/N : DBOZB1LAN12 +3V_S5
R219 220_4 LAN_VCC3 11 Y+
*24LC08

BOTHHAND 10/100 : TST1284 LF P/N : DB0KN7LAN24 X-TX3N 8 NC4/3-

H = 4mm GIGA : GST5009 LF P/N : DBKN1NLAN03 X-TX3P 7 NC/3+

X-TX1N 6
U7 C198 470p/50V_4 LAN_ACTLED# RX-/1-
+2.5V_1.8V_LAN 1 24 TERM4 X-TX2N 5
TX3P TCT1 MCT1 X-TX3P C236 470p/50V_4 LAN_LINKLED# NC2/2-
2 TD1+ MX1+ 23
TX3N 3 22 X-TX3N X-TX2P 4
TD1- MX1- C200 470p/50V_4 +3V_S5 NC1/2+
+2.5V_1.8V_LAN 4 21 TERM3 X-TX1P 3
TX2P TCT2 MCT2 X-TX2P RX+/1+
5 TD2+ MX2+ 20
TX2N 6 19 X-TX2N X-TX0N 2
TD2- MX2- TX-/0-
+2.5V_1.8V_LAN 7 18 TERM2 X-TX0P 1
TX1P TCT3 MCT3 X-TX1P TX+/0+
8 TD3+ MX3+ 17 GND 14 0_8 R502
A TX1N 9 16 X-TX1N 13 0_8 R277 A
C245 C218 TD3- MX3- LAN_LINKLED# GND
10 G-
+2.5V_1.8V_LAN 10 15 TERM1 R282 220_4 LAN_VCC4 9
TCT4 MCT4 +3V_S5 G+
0.1u/16V_4 1000p_4 TX0P 11 14 X-TX0P
TX0N TD4+ MX4+ X-TX0N
12 TD4- MX4- 13
RJ45-CONN
TRANSFORMER R223 R231 R249 R276

75/F_4 75/F_4
55_72@75/F_4
55_72@75/F_4 Quanta Computer Inc.
C201 TERM9 02/12 REV_3A Change footprint and P/N PROJECT : BL5M Montevina
1000p/3KV_1808 TERMINATION PLANE Size Document Number Rev
1A
LAN_Marvell_8040/8055
Date: Monday, March 10, 2008 Sheet 24 of 37
5 4 3 2 1

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 5 4 3 2 1

+3V +1.5V +3V

09/28 REV_A1 Modify
Mini PCI-E Card 12/04 REV_2A Change to +3V_S5 C23 C17 C21 C22 C19

4
2
WLAN (16,29) SERIRQ
(14) LDRQ#1
SERIRQ
LDRQ#1
PLTRST#
R28
R538
R620
*0_4
*0_4
*0_4 WIMAX_P +1.5V +3V_S5
0.1u/10V_4 10u/10V_8 0.001u_4 0.1u/10V_4 10u/10V_8 RP4

4.7KX2
(15,21,24,28,29) PLTRST#
PCLK_DEBUGR21 *0_4 Q5

WIMAX_P
(2) PCLK_DEBUG

2
2N7002E

3
1
03/14 REV_3A DNI
CN19 3 1 WL_SMDATA
(2,16,21,28) SDATA
SERIRQ_WLAN 51 52 10/30 Modify Wimax LED net.
T101 NC +3.3Vaux
R27 *0_4 CL_RST#1_MIN 49 50 12/04 REV_2A Mount R24
MINI-Card I (16) CL_RST#1
(16) CL_DATA1
R26
R22
*0_4
*0_4
CL_DATA1_MIN
CL_CLK1_MIN
47
C-Link_RST
C-Link_DAT
GND
+1.5V
48
(16) CL_CLK1 45 46 T1
C-Link_CLK LED_WPAN# +3V
43 44 T98
D
WIMAX_P GND LED_WLAN# WiMAX_LED#_B 0_4 R23 WiMAX_LED#
D
WIMAX_P 41 42 WiMAX_LED# (22)
WIMAX_P +3.3Vaux LED_WWAN#
12/04 REV_2A Change to +3V_S5 WIMAX_P 39
+3.3Vaux GND
40 R24 0_4
R439 0_4 37 38 USBP3+_B 0_4 R19 USBP3+
GND USB_D+ USBP3+ (15)
35 36 USBP3-_B 0_4 R17 USBP3- Q3
GND USB_D- USBP3- (15)

2
PCIE_TXP1 33 34 2N7002E
(15) PCIE_TXP1 PETp0 GND
PCIE_TXN1 31 32 WL_SMDATA
(15) PCIE_TXN1 PETn0 SMB_DATA
29 30 WL_SMCLK 3 1 WL_SMCLK
GND SMB_CLK (2,16,21,28) SCLK
27 28
PCIE_RXP1 GND +1.5V
(15) PCIE_RXP1 25 26
PCIE_RXN1 PERp0 GND
(15) PCIE_RXN1 23 24
PERn0 +3.3Vaux PLTRST#
21 22 PLTRST# (15,21,24,28,29)
GND PERST# RF_EN_WLAN R15 0_4 +3V
T97 19 20 RF_EN (29)
NC W_DISABLE#
T96 17 18
NC GND
15 16 LFRAME#_PCIE *0_4 R14 LFRAME#
CLK_PCIE_MINI GND NC LAD3_PCIE *0_4 R13 LAD3 LFRAME# (14,29)
(2) CLK_PCIE_MINI 13 14
REFCLK+ NC

4
2
CLK_PCIE_MINI# 11 12 LAD2_PCIE *0_4 R11 LAD2 LAD3 (14,29)
(2) CLK_PCIE_MINI# REFCLK- NC
9 10 LAD1_PCIE *0_4 R10 LAD1 LAD2 (14,29) RP3
GND NC LAD0_PCIE *0_4 R9 LAD0 LAD1 (14,29)
T99 7 8
+3V_S5 +3V WCS_CLK R437 BT@0_4 WCS_CLKR CLKREQ# NC LAD0 (14,29) 4.7KX2
(28) WCS_CLK 5 6
WCS_DAT WCS_DATR BT_CHCLK +1.5V
12/13 REV_2A Add (28) WCS_DAT
R436 BT@0_4 3
BT_DATA GND
4 Q4

2
WLAN_WAKE# 1 2 WIMAX_P WIMAX_P 2N7002E

3
1
WAKE# +3.3Vaux
To BT
minipai-c15706-52p-ldv 3 1 MINI2_SMDATA
2N7002E-LF (2,16,21,28) SDATA
Q1
09/28 REV_A1 Modify
0_6 *0_6
(16,24,28) PCIE_WAKE# 3 1 WLAN_WAKE#
12/04 REV_2A Change to +3V_S5
+3V
R626 R651

2
+3V_S5
R16 10K_4

1 3 WIMAX_P +3V_S5 +3V Q2

2
2N7002E

Q57 C641 10u/10V_8 3 1 MINI2_SMCLK

2

(2,16,21,28) SCLK
AO3413
+

C C642 0.1u/10V_4 R543 R540 C

4.7K_4 *4.7K_4
+3V +1.5V +3V_S5
09/20 REV_A1 Modify
3

03/03 REV_3A Add

CN27
2 WMAX_P (29) 51 52
Reserved +3.3V
49 50
Reserved GND
47 48
Q55 Reserved +1.5V
45 46
1

DTC144EU Reserved LED_WPAN#

43 44
GND LED_WLAN#
41 42 T69
+3.3Vaux LED_WWAN# *0_4 R20
39 40
0_4 R18 +3.3Vaux GND
37 38
MINI-Card II PCIE_TXP3
35
GND
GND
USB_D+
USB_D-
36
T72
T73
(15) PCIE_TXP3 33 34
PCIE_TXN3 PETp0 GND MINI2_SMDATA
(15) PCIE_TXN3 31 32
PETn0 SMB_DATA MINI2_SMCLK
29 30
GND SMB_CLK
12/20 REV_2A Add PAD 27
GND +1.5V
28
PCIE_RXP3 25 26
(15) PCIE_RXP3 PERp0 GND
PCIE_RXN3 23 24
(15) PCIE_RXN3 PERn0 +3.3Vaux PLTRST#
PAD1 21 22
GND PERST# PLTRST# (15,21,24,28,29)
EMIPAD 19 20 0_4 R25
Reserved W_DISABLE# RF_EN (29)
17 18
Reserved GND
15 16
1

CLK_PCIE_MINI2 GND UIM_VPP

13 14
EMI (2) CLK_PCIE_MINI2
(2) CLK_PCIE_MINI2#
CLK_PCIE_MINI2# 11
REFCLK+
REFCLK-
UIM_RESET
UIM_CLK
12
9 10
GND UIM_DATA
7 CLKREQ# UIM_PWR 8
12/18 REV_2A Add C620~C626 5
Reserved +1.5V
6
3 4

GND

GND
+1.8VSUS Reserved GND
1 2 +3V
WAKE# +3.3V +3V +1.5V
3G@minipai-c15706-52p-ldv

53

54
C620 C621 C622 C623 C624 C625 C626
B B
C370 C597 C356 C341 C355
33p_4 33p_4 33p_4 33p_4 33p_4 33p_4 33p_4
0.1u/10V_4 10u/10V_8 0.001u_4 0.1u/10V_4 10u/10V_8

+1.5V 12/23 REV_2A Change P/N

C31 C263 C517 C337 C24

0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 MINI-Card III +3V

4
2
+3V +1.5V +3V_S5
RP58
+3VPCU
4.7KX2
CN35 Q48

2
51 52 2N7002E

3
1
C44 C148 C12 C16 C199 C74 C563 NC +3.3V
49 50
C-Link_RST GND MINI3_SMDATA
47 C-Link_DAT +1.5V 48 (2,16,21,28) SDATA 3 1
0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 45 46
C-Link_CLK LED_WPAN#
43 44
GND LED_WLAN#
41 42
NC NC R357 *0_4
39 40
R361 0_4 NC NC +3V
37 38 T151
+5V +3VPCU +5VPCU GND USB_D+
35 36 T152
PCIE_TXP5 GND USB_D-
(15) PCIE_TXP5 33 34
PCIE_TXN5 PETp0 GND MINI3_SMDATA
(15) PCIE_TXN5 31 32
PETn0 SMB_DATA MINI3_SMCLK Q49
29 GND SMB_CLK 30

2
27 28 2N7002E
C15 C418 C13 C2 C618 C619 PCIE_RXP5 GND +1.5V
(15) PCIE_RXP5 25 26
PCIE_RXN5 PERp0 GND MINI3_SMCLK
(15) PCIE_RXN5 23 24 (2,16,21,28) SCLK 3 1
0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 PERn0 +3.3Vaux PLTRST#
21 GND PERST# 22 PLTRST# (15,21,24,28,29)
A 19 20 RF_EN_WLAN A
NC W_DISABLE#
17 18
NC GND
15 16
CLK_PCIE_MINI3 GND NC
(2) CLK_PCIE_MINI3 13 REFCLK+ NC 14
+5VPCU CLK_PCIE_MINI3# 11 12
(2) CLK_PCIE_MINI3# REFCLK- NC
9 10
GND NC
12/18 REV_2A Add C618 7
CLKREQ# NC
8
T153 5 BT_CHCLK +1.5V 6
T154 3 BT_DATA GND 4
C388 C228 C139 C18 1 2

0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4

T155 WAKE#
minipai-c15706-52p-ldv
+3.3V +3V
Quanta Computer Inc.
PROJECT : BL5M Montevina
Size Document Number Rev
1A
H= 8mm MINI PCIE/HOLE
Date: Friday, March 14, 2008 Sheet 25 of 37
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 5 4 3 2 1

+5V *G961-18ADJTEU(SOT89-5)
Codec(CX20561) U39
INT SPK AMP R398 *0_6 4 3
VEN VOUT
5

GND
VIN

ADJ
R644
*36K/F_4

1
C387 +3AVDD
*1u/16V_6

+3V_S5 L41 PBY160808T-301Y-N_6

D D
+3AVDD R646
*12K/F_4 ADOGND
+3VSUS L42 *PBY160808T-301Y-N_6 +AZA_VDD L25 PBY160808T-301Y-N_6 +3V
C583 C592 C582 C608 C599 C372
02/12 REV_3A Change
10u/10V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 10u/10V_8
R384,RR618,R636,R422 R397 0_6 +5V_VDD C586
+5V
footprint
C610 C589 *0.1u/10V_4
ADOGND
SECNTL (27)
R384 0_6 10u/10V_8 0.1u/10V_4

ADOGND
11/29REV_2A Change to +1.5V_S5 C576 C577 C606 C603 02/12 REV_3A Change R391,R634,R639,R633 value ADOGND
R618 0_6

15

14

23
U37

6
8
10u/10V_8 0.1u/10V_4 0.1u/10V_4 10u/10V_8
R625 0_4 SPKR-L C371 2.2u/6.3V_6 SPKR-L-1 R391 5.1K/F_6 SPKR-L-2 1 20

LVDD
RVDD

VDD3

NC
SECNTL
CT
+1.5V_S5 LIN1 VOL
ADOGND
SPKR-R C591 2.2u/6.3V_6 SPKR-R-1 R634 5.1K/F_6 SPKR-R-2 18
R636 0_6 RIN1
ADOGND INSPKL+ R639 16K/F_6 2 13 ADOGND
C600 330p/25V_4 LIN2 IN1/IN2
REV_2A 11/29 Del R626 17
RIN2
Determining HDA use +1.5V/+3V ADOGND INSPKR+ R633 16K/F_6 19 INSPKR+
C595 330p/25V_4 ROUT+ INSPKR-
12
C578 R422 0_6 ROUT- INSPKL+
12/18 REV_2A Mount R618,R636,R422

44

26
40
36
24
LOUT+

9
4
3
U38 ADOGND C590 4.7u/6.3V_6 G1441_RBY 16 7 INSPKL-
0.1u/10V_4 C604 4.7u/6.3V_6 G1441_PBY RBYPASS LOUT-
3

DVDD_1-8
DVDD_3-3
DVDD_44

AVDD_26
AVDD_40
VDD_IO

AVEE
C ADOGND LBYPASS C

THRMPAD
GND/HS
GND/HS
GND/HS
GND/HS
34 G1441_SHDN 5
PORTA_L HPL (27) SHDN
(14) ACZ_RST#_AUDIO 11 35 HPR (27)
RESET# PORTA_R R623 0_4 G1441_SE/BTL 11
ADOGND SE/BTL
(14) BIT_CLK_AUDIO 6 19 MIC1-VREFO_B R392 0_4 MIC1-VREFO
BIT_CLK MICBIASB MIC1-VREFO (27)
(14) ACZ_SYNC_AUDIO 10 14 MIC1-LL C581 2.2u/6.3V_6 MIC1-L G1441

25
22
21
10
9
SYNC PORTB_L MIC1-L (27)
R619 33_4 ACZ_SDIN20561 8 15 MIC1-RR C584 2.2u/6.3V_6 MIC1-R
(14) ACZ_SDIN0 SDATA_IN PORTB_R MIC1-R (27)
(14) ACZ_SDOUT_AUDIO 5
SDATA_OUT MIC1-VREFO_C R385 *0_4 MIC1-VREFO
18
Reserve for EMI MICBIASC FM_linein_L C588 2.2u/6.3V_6 FM_linein_LL R632 10K_4
16 FM_LEFT (27)
R630 0_4 DIB_P_L PORTC_L FM_linein_R C593 2.2u/6.3V_6 FM_linein_RR R631 10K_4
(27) DIB_P
R635 0_4 DIB_N_L
43
42
DIB_P PORTC_R
17 FM_RIGHT (27) INT SPEAKER
(27) DIB_N DIB_N FM_linein_LL R621 *0_4 MIC1-L
27 FM_linein_RR R622 *0_4 MIC1-R ADOGND
C579 0.1u/10V_4 PC_BEEP PORTD_L
(16) SPKR 12 28
PC_BEEP PORTD_R
10/24 REV_A1 Add R611,R612,R609,R610
CN15
(27) SPDIF_OUT R627 0_4 48 20 MIC2_INT_L C375 2.2u/6.3V_6 INT_MIC_R_1 L51 BK1608LL121_6 INT_MIC_R SPEAKER_H1.95
S/PDIF MIC_L MIC2_INT_R C376 2.2u/6.3V_6 INSPKL- L47 BK1608LL121_6 INSPKL-N
21
MIC_R INSPKL+ L45 BK1608LL121_6 INSPKL+N 1
03/04 REV_3A Add L51 25
29 R394 5.1K/F_4 +3AVDD INSPKR- L46 BK1608LL121_6 INSPKR-N
GPIO2 MONO SPKR-L INSPKR+ L48 BK1608LL121_6 INSPKR+N 36
45 30
GPIO1 GPIO2 STEREO_L SPKR-R R390 5.11K/F_4 4
46 31 Port_A# (27)
EAPD# GPIO1 STEREO_R C380 C379 C378 C377
47
EAPD#/GPIO0 R395 10K/F_4
Port_B# (27)
Mount ESD protect parts:BC03220KZ19 *47p_6 *47p_6 *47p_6 *47p_6
13 SENSEA R389 20K/F_4
SENSEA Port_C# (16)
1 24 CX20561_VILT
B DMIC_CLOCK VREF B
2
DMIC_1/2 12/18 REV_2A Mount R389
39 CX20561_FLY_P 10/30 Change to CC0603
CX20561-12Z Not FLY_P CX20561_FLY_N C602 1u/10V_4
37
support digital MIC FLY_N
CX20561-13Z support CX20561_RVD22 C607 C601
PC Beep GAIN CONTROL 22
DVSS_41

AVSS_25
AVSS_38

digital MIC VREF_LO

DVSS_7

23 CX20561_RVD23
VREF_HI 10u/10V_8 0.1u/10V_4 +5V_VDD
GAIN GPIO1 GPIO2 RESERVED_32
32
RESERVED_33 33
C598 C596
0dB 10K 10K CX20561-12Z
7
41

25
38

R629 *10K_4 GPIO1 1u/10V_4 1u/10V_4 ADOGND R617

-6dB omit omit R628 *10K_4 GPIO2 +3AVDD 100K_4

ADOGND G1441_SHDN
-12dB 10K omit R624

3
D45 1 2 MTW355
(29) AMP_MUTE#
10K_4
-18dB omit 10K
EAPD# MUTE#
ADOGND D46 1 2 *MTW355 2 Q47

H : AMP turn on 2N7002E

L : AMP power down
R581
12/18 REV_2A DNI D46

1
+3AVDD R584 4.7K_4 03/04 REV_3A Reserve
C573 ADOGND
1K_4 10u/6.3V_6
INT_MIC_R_1
A
INT_MIC MIC1-LL FM_linein_L MIC2_INT_L A
MUTE# (27)
ADOGND CN36 MIC1-RR FM_linein_R MIC2_INT_R
INT_MIC_R
ADOGND 2
1
INT_MIC C585 C580 C594 C587 C374 C373 C645
*100p_4 *100p_4 *100p_4 *100p_4 0.1u/10V_4 0.1u/10V_4 *100p_4
Quanta Computer Inc.
ADOGND ADOGND ADOGND ADOGND ADOGND ADOGND ADOGND
PROJECT : BL5M Montevina
Size Document Number Rev
03/21 REV_3A Mount C374,C373 1A
Conexant CX205601
Date: Friday, March 21, 2008 Sheet 26 of 37
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 5 4 3 2 1

02/12 REV_3A Change footprint

FM Tuner
VR R416 10K_4
MDC +3V
+3AVDD
C232
R396 10K_4 09/26 REV_A1 Modify
CN29 CN11
10/24 Change footprint 0.1u/10V_4
VR1 1 2
SB_GPIO7 +3V +3V 1 10
DIGVOL_UP R408 0_4 VR_UP 2 1 3 4 (16) SB_GPIO7 SB_GPIO7
(29) DIGVOL_UP A COM SB_GPIO27 GND 2
5 6 (16) SB_GPIO27 SB_GPIO27
FM_INT AGND C266 3
4 4 (26) DIB_P 7 DIB_P FM_L 8 4
9 10 (26) FM_LEFT FM_LEFT
(26) DIB_N DIB_N FM_R 5
DIGVOL_DN R400 0_4 VR_DN 3 5 11 12 0.1u/10V_4 (26) FM_RIGHT FM_RIGHT
(29) DIGVOL_DN B 5 FM_SUSCLK AGND 6

7
D (16) FM_DET 7 D
MDC (16) FM_INT FM_INT
C383 C392 8 9
11/05 Add FM_DET
BL121-08R-8P-L-BL5
0.1u/10V_4 0.1u/10V_4 ADOGND
VR_XRE094_NOBLE

ADOGND ADOGND
SYSTEM MIC
+3AVDD +3AVDD
C617

ADOGND R399 4.7K_4 CN39

(26) MIC1-VREFO
U41 1 7
C609 U17 5 1 MIC1-L L26 BK1608LL121_6 MIC1_L1 2
*0.1u/10V_4 (26) MIC1-L
2 VR_DN 6
*0.1u/10V_4 5 2 4 3 MIC1-R L27 BK1608LL121_6 MIC1_R1 3
Vcc CLK (26) MIC1-R
Port_B# 4
(26) Port_B#
1 VR_UP *NL17SZ17 8
ADOGND D C616 5
DIGVOL_UP 4 3 C644 C643 C398 C397 MIC_JACK
Q GND *0.1u/10V_4 *100p_4 *100p_4
C382 *100p_4 *100p_4 Normal OPEN Jack
*SN74LVC1G79DBVR ADOGND
*0.1u/10V_4 ADOGND ADOGND +3AVDD
ADOGND ADOGND
C D19 CNXT suggestion can not over 100P C
ADOGND 03/04 REV_3A Reserve for GPRS
DIGVOL_DN 1 ADOGND
12/13 REV_2A Add U41,C617,C616 Port_B#
C612 3
12/13 REV_2A Del Q27,R393 2
*0.1u/10V_4
*DA204U
ADOGND
ADOGND

HP Amplifier

12/18 REV_2A Del R637,R643 HPL_SYS

HP HPR_SYS 12/22 REV_2A Add C638,C639 R410 *1412@10K_6 +3AVDD
12/18 REV_2A Add C667,C668
C638 C639 C390 *1412@47p_4
G1412_HPL R640 *1412@0_4 +3V_SPD C389 C384
*100p_4 *100p_4
G1412_HPR R642 *1412@0_4 CN38 *[email protected]/6.3V_6 *[email protected]/10V_4
ADOGND ADOGND HP_JD U18
5 9 ADOGND
4
C667 0_6 HPL_1 L49 BK1608LL121_6 HPL_SYS 10
B (26) HPL B
3 HPL_2 R404 *1412@10K_6 4 - 5 G1412_HPL ADOGND ADOGND
C668 0_6 HPR_1 L50 BK1608LL121_6 HPR_SYS INL OUTL
(26) HPR 2
1 + 9
R641 R638 C611 C605 NC1
+3AVDD 3 11
SVDD NC2
7 LED 15 12
C614 *1412@10u/10V_8 HPL_2 0.1u_4 0.1u_4 0.1u_4 0.1u_4 SPDIF_OUT Drive R401 *1412@100K_4 PVDD NC3
(26) SPDIF_OUT 8 +3AVDD NC4
14
6 IC 6 2
SVSS SGND +NVDD
C613 *1412@10u/10V_8 HPR_2 10 13
+NVDD NVDD PGND
HP_JACK D22 1 2 *1412@MTW355 17
(26) MUTE# TPAD
02/12 REV_3A Change C667,C668 value C395
D21 1 2 *1412@MTW355 1412MUTE# 1
+5V (26) SECNTL SHDNR#
16 ADOGND
ADOGND SHDNL# *[email protected]/6.3V_6
+ 7
Port_A# OUTR
(26) Port_A# +5V
02/12 REV_3A Change HPR_2 R413 *1412@10K_6 8
INR -
Q25 R388
R641,R638,C611,C605,L49,L50 value +3AVDD
ADOGND
3

2N7002 10K_4 D20 *1412@G1412

ADOGND
R387 1
2 HP_JD
Q26 22K_4 3
+3V 1 3 +3V_SPD
3

C391 *1412@47p_4
2N7002 2
Q50 *DA204U R421 *1412@10K_6 G1412_HPR
1

2 HP_JD ADOGND
ME2347
C381 *[email protected]/6.3V_6
1

A A
D58 SPDIF_OUT +3V_SPD +3AVDD +NVDD
1

+3AVDD U16
VPORT_6
1 VOUT C+ 6
2

02/12 REV_3A Add D58 2

VIN /SHDN
5 1412MUTE#
Quanta Computer Inc.
12/19 REV_2A Add C635
3 4
C- GND
0.1u/10V_4 C631 C632 PROJECT : BL5M Montevina
47p_4 47p_4 Size Document Number Rev
*1412@G5930
1A
ADOGND 12/18 REV_2A Add
ADOGND Audio JACK/VR
Date: Monday, March 10, 2008 Sheet 27 of 37
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 5 4 3 2 1

Finger Printer 09/26 REV_A1 Del R156,R168 T/P +5V_TP TPDATA_1

TPCLK_1
02/12 REV_3A DNI CN10
FINGER_POWER C81

6
1 C78 C80 C82
(15) USBP4- 2
(15) USBP4+ 4.7u/10V_8 0.1u/10V_4 *10p_4 *10p_4
CM@0_8 R29 3
4

5
+3V *CM@0_8 R33 CN8
+5V FP@88266-040XX-XXX-4P-R
D59 2 1 EGA_4 USBP4-
D60 16
+3V 1 3 FINGER_POWER 2 1 EGA_4 USBP4+
+5V
L7 1 2 BLM18PG181SN1D +5V_TP
1
1 3 FELICA_POWER D61 2 1 VPORT_6
FINGER_POWER 02/12 REV_3A Add D59,D60,D61
+5V +5VPCU 2
C30 CM@10u/10V_8 R67 0_4 TPDATA_1

+
(29) TPDATA 3
TPCLK_1

+
Q9 R32 C25 CM@*10u/10V_8 10/24 REV_A1 Change footprint R68 0_4
2

(29) TPCLK 4
CM@*AO3413 C28 CM@*1000p_4 CM@*4.7K_4 Q8 R30 GND
Felica

2
CM@*AO3413 C27 CM@*1000p_4 CM@*4.7K_4 5
C29 CM@*0.1u/10V_4 CN9 TP_LED_ON_C 6
D
C26 CM@*0.1u/10V_4 BATLED1# 7 D
(29) BATLED1# 8
BATLED0#
8 (29) BATLED0# 9
FELICA_DE +3VPCU PWRLED#
6 (29) PWRLED# 10
T50 SUSLED_EC
5 (29) SUSLED_EC 11

3
SATA_LED#
4 (22) IDE_LED# 12

3
(15) USBP8+ R157 FP@0_6 USBP8+_C ACIN
3 (29,30) ACIN 13
2 (15) USBP8- R162 FP@0_6 USBP8-_C TP_XD_LED
FP_PWRON (29) 2 (23) TP_XD_LED 14
2 FELICA_POWER R69 R51
FELICA_PWRON (29) 1 15
7 10K_4 330_4
Q6 BL121-14R-TAND-14P-L-BU1

1
CM@*DTC144EU Q7 BL121-06R-6P-L-BL5 Q10

2
CM@*DTC144EU MMBT3904

1 3 TP_LED_ON_C
(29) TP_LED_ON
R78
BLUETOOTH MODULE CONNECTOR
10/30 Add
*0_4
CN14
+3VPCU +3V

12
1
RP2
(15) USBP5+ 2 Power board
(15) USBP5- 3 +5VPCU
10 1 MX7 CN6 WCS_CLK
(25) WCS_CLK 4
MX1 9 2 MX2 CN7 C575
MX6 MX3 36 BT_RESET 5
8 3
MX5 MX4 36 WCS_DAT 6
7 4 (25) WCS_DAT 7
MX0 6 5 K_LED_P +3V [email protected]/10V_4 CN5 C20
1 MY16 K_LED_P USB_DETACH 8
2 MY16 (29) 1 9 +5VPCU 1
10KX8 MY16

11
3 MY17 2 10 (29) NBSWON# 2
10/30 Add *0.1u/10V_4
4 MY17 (29) 3 (29) PWRLED# 3 6
7 8 MX7 MY17 BT@88266-100XX-XXX-10P-R
MX2 5 K_LED_P 4 4 5
5 6
MX3 6 MY2 5 K_LED_P R614 BT@*0_4 BT_RESET
3 4 MY2 (29)
MX4 7 MY1 6 MY2
1 2
8 MY1 (29) 7 (29) BT_EN 12/18 REV_2A Add BL123-04R-4P-R-BL5
MY0 MY1 R615 BT@0_4 USB_DETACH
100px4 9 MY0 (29) 8
MY4 MY0
CP4 10 MY4 (29) 9 USB_DETACH: Low USB connect
MY3 MY4 Wire Cable 1.25mm Pitch
11 MY3 (29) 10
C 7 8 MX0 MY5 MY3 High USB disconnect C
12 MY5 (29) 11
5 6 MX5 MY14 MY5 10/25 Modify
MX6 13 MY6 MY14 (29) 12 MY14
3 4 MY6 (29)
MX1 14 MY7 13 MY6
1 2 MY7 (29)
15 MY13 14 MY7
100px4 16 MY8
MY13 (29) 15 MY13
BUTTONS ON KB COVER
CP5 17 MY8 (29) 16
MY9 MY8
7 8 MY7 18 MY10 MY9 (29) 17 MY9
MMB
19 MY10 (29) 18
5 6 MY13 MY11 MY10
20 MY11 (29) 19
3 4 MY12 MY12 MY11 10/25 Modify
21 MY12 (29) 20
1 2 MY15 MY15 MY12 10/30 1 Modify MX1 to MX5 Main strem
22 MY15 (29) 21
MX7 MY15 Low cost CN3
100px4 23 MX2 MX7 (29) 22 MX7
CP3 24 MX2 (29) 23
MX3 MX2
25 MX3 (29) 24 12 BL123-06R-6P-R-BL5
MX4 MX3 +3VPCU
26 MX4 (29) 25 1
MX0 MX4
27 MX0 (29) 26 (29) MX5 2 7
MX5 MX0 +3VPCU
28 MX6 MX5 (29) 27 MX5 (29) MX2 3 1
29 MX6 (29) 28 (29) MY1 4 +5VPCU 2
MX1 MX6
30 MX1 (29) 29 5 (29) KEY_INT 3
K_LED_P MX1
31 K_LED_P 30 (29) MX3 6 4
CAPSLED K_LED_P
32 CAPSLED (29) 31 (16) LOW_DET 7 (19,21,29) 3ND_MBDATA 5
7 8 MY3 FN_F10 CAPSLED
MY5 33 NUMLED FN_F10 (29) 32 FN_F10 (29) MX4 8 (19,21,29) 3ND_MBCLK 6
5 6 NUMLED (29) (29) FN0#
MY14 34 33 NUMLED 9 8
3 4 (29) FN1#
MY6 34 10
1 2
R12 150_4 K_LED_P 11 CN4
100px4 35 +3V
BL123-10R-TAND-10P-L-BU1
CP2 88171-3400L-34P-R 35
7 8 MY2 *196130-340201-34P-R
5 6 MY1
3 4 MY0 Keyboard Side
1 2 MY4 FFC Cable 1.0mm Pitch FFC Cable 1.0mm Pitch
100px4
CP1

B B

New card (BTO) CN13

NEW CARD'S POWER SWITCH 26

GND1 GND29
29
+NEW_3V 25 30
(15) PCIE_TXP4 PETp0 GND30
24
(15) PCIE_TXN4 PETn0
23
GND2
CPPE# : ( Internal Pull Up , active low when card support PCIE ) (15) PCIE_RXP4 22
PERp0
(15) PCIE_RXN4 21 PERn0
4
2

CPUSB# : ( Internal Pull Up , active low when card support USB ) 20

GND3
RP46 19
+3V_S5 (2) CLK_PCIE_NEW REFCLK+
SHDN# : ( Internal Pull Up ) 03/03 REV_3A Change (2) CLK_PCIE_NEW# 18
REFCLK-
[email protected]_4 CPPE# 17
Q23
U13 P/N R571 *NEW@0_4 NEW_CLKREQ#_RR 16
CPPE#
(2) NEW_CLKREQ# CLKREQ#
2

2
+NEW_3V
H=0.8mm 15
3
1

+3.3V1
09/26 REV_A1 Add 14
+3.3V2
SDATA 3 1 NEW_SMDATA U13 Q24 PERST# 13
(2,16,21,25) SDATA PERST#
2 3 +NEW_3V NEW@*DTC144EU +NEW_3VAUX 12
+3V 3.3VIN 3.3VOUT PCIE_WAKE# 3 +3.3VAUX
NEW@2N7002E 4 5 1 11
3.3VIN 3.3VOUT (16,24,25) PCIE_WAKE# +NEW_1.5V WAKE#
10
+NEW_3VAUX +1.5V1
+3V_S5 17 15 9
+NEW_3V AUXIN AUXOUT NEW_SMDATA +1.5V2
8
+NEW_1.5V R333 NEW_SMCLK SMB_DATA
+1.5V 12 11 7
1.5VIN 1.5VOUT SMB_CLK
14
1.5VIN 1.5VOUT
13 02/12 REV_3A Change 6
RESERVED1
NEW@0_4 5
Q22 PLTRST# 6 1 T89
R313 value,DNI C272 CPUSB# 4
RESERVED2
(15,21,24,25,29) PLTRST# SYSRST# STBY# CPUSB#
2

20 10 CPPE# R298 NEW@0_4 USBP6+_R 3

SHDN# CPPE# (15) USBP6+ USB_D+
T86 9 CPUSB# R299 NEW@0_4 USBP6-_R 2
SCLK NEW_SMCLK RCLKEN CPUSB# (15) USBP6- USB_D-
(2,16,21,25) SCLK 3 1 18
RCLKEN
NEW@0_4 09/26 REV_A1 Add 1
GND4
16 8 PERST#_R R313 PERST#
NEW@2N7002E T79 NC PERST#
7 GND OC# 19
A +3V NEW@NCARD-13180151-T-26P-L A
G577BSR91U C272
+3V_S5 NEW@*3300p_4

5
NEW_CLKREQ#_RR
R303 NEW@47K_4 1 R573 NEW@10K_4 +3V_S512/18 REV_2A Modify footprint
AL000577001 NEW_CLKREQ# 4
2 R574 NEW@10K_4
AL002231000 +3V_S5

3
U36

3
+3V_S5 +3V +1.5V
NEW@NC7SZ32P5X
+NEW_3VAUX +NEW_3V +NEW_1.5V

C267 C305 C303 C262 C260

2 RCLKEN Quanta Computer Inc.
C259 C306 C290 C304 C256 C261
[email protected]/10V_4 [email protected]/10V_4
0.1u/10V_4 [email protected]/10V_4
[email protected]/10V_4 Q45
PROJECT : BL5M Montevina
[email protected]/10V_4 [email protected]/10V_8
[email protected]/10V_4
[email protected]/10V_4 [email protected]/10V_8
[email protected]/10V_4 Size Document Number Rev

1
NEW@2N7002E 1A
New Card/Keyboard/WTB
Date: Monday, March 10, 2008 Sheet 28 of 37
5 4 3 2 1

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 5 4 3 2 1

Page 29 copy from BL5S

+3VPCU
10/26 REV_A1 Add R64,R73,R176
BATLED1# R70 10K_4

SM BUS PU
BATLED0# R64 10K_4
PWRLED# R79 10K_4 +3VPCU

+3VPCU MBCLK R107 4.7K_4

+3V DNBSWON#_uR MBDATA R87 4.7K_4
R40 DIGVOL_UP 2ND_MBCLK R80 4.7K_4
L8 +A3VPCU EC_VDD 0_6 DIGVOL_DN 2ND_MBDATA R85 4.7K_4
BLM18AG601SN1_6 FN0# R86 4.7K_4
C69 C109 C40 C37 FN1# R81 4.7K_4
C99 C65 C98 3ND_MBCLK R50 4.7K_4
0.1u/10V_4 10u/10V_8 0.1u/10V_4 10u/10V_8 3ND_MBDATA R47 4.7K_4
*0.1u/10V_4 *0.1u/10V_4 *0.1u/10V_4

8769AGND

115

102
D D
PCLK_591 C120 C55 C97 C59 C41 C100 +3V

19
46
76
88

4
10u/10V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 U2 USBOC#0 R88 *10K_4

VCC1
VCC2
VCC3
VCC4
VCC5

AVCC

VDD
09/20 REV_A1 Modify CRT_SENSE# R132 4.7K_4
R43 H=1.6mm R108 10K_4
+3VPCU
*22_4

I/O Base Address

3 97 To: Battery Connector (Input)
(14,25) LFRAME# LFRAME AD0/GPI90 TEMP_MBAT (30)
126 98 USBOC#0
(14,25) LAD0 LAD0 AD1/GPI91 USBOC#0 (15,19)
127 99 To: Media Board (Input)
(14,25) LAD1 LAD1 AD2/GPI92 FN0# (28)
128 A/D 100 To: Media Board (Input) I/O Address
(14,25) LAD2 LAD2 AD3/GPI93 FN1# (28)
C39 1 108 To: Volume Wheel (Input)
(14,25) LAD3 LAD3 AD4/GPIO05 DIGVOL_UP (27)
*10p_4 2 96 To: Volume Wheel (Input) BADDR1-0 Index Data
(2) PCLK_591 LCLK AD5/GPIO04 DIGVOL_DN (27)
95 To: HW Power Button (Input)
AD6/GPIO03 NBSWON# (28)
8 94 To: South Bridge (Input) 00 XOR TREE TEST MODE
(16,23) CLKRUN# CLKRUN/GPIO11 AD7/GPIO07 SUSB# (16)

(14) GATEA20 121

GA20 01 CORE DEFINED
101 To: Battery Charger (Output)
DA0/GPI94 CC-SET (30)
122 105 To: FAN Control IC (Output) 10 2Eh 2Fh
(14) RCIN# KBRST DA1/GPI95 VFAN (3)
D/A 106 To: Battery Charger (Output)
SCI#_uR DA2/GPI96 CV-SET (30)
D7 29 LPC 107 To: SUS LED circuit (Output) 11 164Eh 164Fh
(16) SCI# ECSCI/GPIO54 DA3/GPI97 SUSLED_EC (28)
To: Back light control circuit (Output) BAS316 6 SHBM=0: Enable shared memory with host BIOS
(18) EC_FPBACK# LDRQ/GPIO24
80 EC_VBAT
To: HDMI (Input) GPIO41(VBAT)
(21) CEC_EC_HP 124
LPCPD/GPIO10 BADDR0
GPIO GPIO42/TCK
17 RF_LED (22)
To: RF LED (Output) BADDR0 R54 *10K_4
7 20 To: Mute Audio AMP (Output)
(15,21,24,25,28) PLTRST# LRESET GPIO43/TMS AMP_MUTE# (26)
wake-up 21 To: Battery Connector (Input) BADDR1 BT_EN R56 10K_4
GPIO44/TDI ID (30)
To: USB power switch (Output) 123 capability 25 To: Select VIN is from DC or Battery (Output)
(19) USB_EN# PWUREQ/GPIO67 GPIO50/TDO D/C# (30)
27 02/12 REV_3A Add to control MMB LED SHBM RF_EN R113 10K_4
CIRTX2/GPIO52/RDY DISPON (18)
(16,25) SERIRQ 125
SERIRQ
no wake-up GPO82/TRIS
110 LED_LOGO (22)
To: Logo LED (Output) 12/18 REV_2A R54 DNI,R56 mount
09/29 REV_A1 Modify 9 capability GPO84/BADDR0 112 BADDR0 10/22 REV_A1 Modify
(19) USB_EN#1 SMI/GPIO65
Disabled ('1') if using FWH device on LPC.
111 To: Enable BT module (Output)
SOUT_CR/GPO83/BADDR1 BT_EN (28) Enabled ('0') if using SPI flash for both system BIOS and EC firmware
54 113 To: CRT connector and South Bridge (Input)
(28) MX0 KBSIN0 SIN_CR/CIRRX/GPIO87 CRT_SENSE# (15,18)
55 SER 93 To: MR sensor (Input)
(28) MX1 KBSIN1 GPIO06 LID591# (18)
(28) MX2 56
KBSIN2
ID
57 32 To: Control Panel brightness (Output)
C
(28) MX3
58
KBSIN3 A_PWM/GPIO15
118
CONTRAST (18)
To: Enable/Disable WiFi and BT (Input)
H=1.75mm +3VPCU
C

(28) MX4 KBSIN4 B_PWM/GPIO21 KILL_SW (22) U4

59 62 To: Battery LED--Full charge (Output)
(28) MX5 KBSIN5 C_PWM/GPIO13 BATLED0# (28)
SMBUS Table 60 65 To: Battery LED--Charging (Output) 2ND_MBCLK 6 1
(28) MX6 KBSIN6 D_PWM/GPIO32 BATLED1# (28) SCL A0
61 PWM 22 To: Control S3 power (Output) 2ND_MBDATA 5 2
(28) MX7 KBSIN7 E_PWM/GPIO45 SUSON (34,35) SDA A1
16 To: Control S1 power (Output) 3
F_PWM/GPIO40/CLKIN48 MAINON (19,33,34,35) A2
SMBUS Devices 53 81 To: Touch PAD Connector (Output)
(28) MY0 KBSOUT0/JENK G_PWM/GPIO66 TP_LED_ON (28)
52 66 PWRLED# (28) To: Power ON LED (Output) 7 8
(28) MY1 KBSOUT1/TCK H_PWM/GPIO33 WP VCC
1 Battery (28) MY2 51
KBSOUT2/TMS GND
4
(28) MY3 50
KBSOUT3/TDI 10/24 REV_A1 Add C155
2 CPU Thermal Sensor 49 KB 31 T3 To: AMD PWM (Output) 24LC08BT-I
(28) MY4 KBSOUT4/JEN0 TA1/GPIO56
3D Sensor 48 63 To: FAN connector (Input) 0.1u/10V_4
(28) MY5 KBSOUT5/TDO TB1/GPIO14 FANSIG (3)
EC EEPROM 47 117 LOM_DISABLE (24) To: LOM_DISABLE (Output)
(28) MY6 KBSOUT6/RDY TA2/GPIO20
(28) MY7 43
KBSOUT7 TIMER TB2/GPIO01
64 ACIN (28,30)
To: ACIN LED and AC detect circuit (Input) ADDRESS: A0H
3 VGA Board Thermal Sensor 42 26 To: Control S5 power (Output)
(28) MY8 KBSOUT8 TA3/GPIO51 S5_ON (31,35)
Touch Sensor 41 15 To: CPU Vcc core PWM IC (Output)
(28) MY9 KBSOUT9 TB3/GPIO36 VRON (32)
(28) MY10
(28) MY11
40
39
KBSOUT10
KBSOUT11 10/22 REV_A1 Modify SPI FLASH H=2.16mm +3VPCU
(28) MY12 38 84 T29
KBSOUT12/GPIO64 SPI_DI/GPIO77 To: Enable WiFi (Output)
(28) MY13 37
KBSOUT13/GPIO63 SPI SPI_DO/GPO76/SHBM
83 RF_EN (25)
36 82 To: Battery Charger (Output) U3
(28) MY14 KBSOUT14/GPIO62 SPI_SCK/GPIO75 CELL-SET (30)
10/26 REV_A1 Modify (28) MY15 35 91 DNBSWON#_uR D10 BAS316
DNBSWON# (16)
To: South Bridge (Output) SPI_SDI_uR R181 33_4 SPI_SDI 2 8
KBSOUT15/GPIO61/XOR_OUT GPIO81 SO VDD
(28) MY16 34
KBSOUT16/GPIO60 RSMRST#_uR0_4 R118 To: South Bridge (Output) SPI_SDO_uR R153 33_4 SPI_SDO 5 C151
(28) MY17 33 75 RSMRST# (16) 7
KBSOUT17/GPIO57 IRRX1/GPIO72/SIN2 To: South Bridge (Input) SI HOLD
FIR IRRX2_IRSL0/GPIO70
73 SUSC# (16)
To: Battery connector 74 PWROK_EC R117 0_4 To: South Bridge, be careful the timing (Output) SPI_SCK_uR R152 33_4 SPI_SCK 6 3 0.1u/10V_4
IRTX/GPIO71/SOUT2 ECPWROK (16) SCK WP
To: Battery connector 70 23 To: Touch Sensor Board Con. (Input)
(30) MBCLK SCL1/GPIO17 CIRRXM/GPIO46/TRST KEY_INT (28) SPI_CS0#_uR
To: CPU Thermal Sensor, 3D Sensor, EC EEPROM 69 14 To: CIR (Input) 1 4
(30) MBDATA SDA1/GPIO22 GPIO34/CIRRXL CIRRX2 CE VSS
To: CPU Thermal Sensor, 3D Sensor, EC EEPROM 67 SMB CIR 114 To: Internal KB LED (output)
(3) 2ND_MBCLK SCL2/GPIO73 CIRTX1/GPIO16 NUMLED (28)
To: VGA Board Thermal Sensor, Touch Sensor 68 109 To: Internal KB LED (output) +3VPCU R180 10K_4 W25X80VSSIG
(3) 2ND_MBDATA SDA2/GPIO74 CIRTX2/GPIO30 CAPSLED (28)
To: VGA Board Thermal Sensor, Touch Sensor 119
(19,21,28) 3ND_MBCLK SCL3/GPIO23
To: AMD CPU (Output) 120
(19,21,28) 3ND_MBDATA SDA3/GPIO31 SPI_SDI_uR
(25) WMAX_P 24 86
HWPG SCL4/GPO47 F_SDI/F_SDIO1 SPI_SDO_uR +3VPCU
28 87
SDA4/GPIO53 F_SDO/SDIO0 SPI_CS0#_uR
03/03 REV_3A Add WMAX_P net FIU F_CS0 90
10/22 REV_A1 Modify 92 SPI_SCK_uR MY0 R60 10K_4
F_SCK
To: Touch PAD
(28) TPCLK 72
PSCLK1/GPIO37 09/20 REV_A1 Modify
+5V To: Touch PAD 71
B (28) TPDATA PSDAT1/GPIO35 B
(30) CHG-EN 10
PSCLK2/GPIO26
INTERNAL KEYBOARD STRIP SET
R116 10K_4 TPCLK To: Finger Printer Con (output) 11 PS/2 30
(28) FP_PWRON PSDAT2/GPIO27 CLKOUT/GPIO55 USBOC#1 (15,19)
R115 10K_4 TPDATA To: Internal KB LED (output) 12
(28) FN_F10 PSCLK3/GPIO25
To: Felica Con (output) 13 85 VCC_POR# R114 4.7K_4 +3VPCU
(28) FELICA_PWRON PSDAT3/GPIO12 VCC_POR
8768_32KX1 77 104 VREF_uR R62 0_4 +A3VPCU
VCORF

32KX1/32KCLKIN VREF
AGND
GND1
GND2
GND3
GND4
GND5
GND6

R110 20M_6 8768_32KX2 79

32KX2
EC
SUSON R438 100K_4
CIR (Copy from PB2A)
5
18
45
78
89
116

103

44

Only for 8769/775C

S5_ON R515 100K_4
R111 WPC8763LDG: AL008763B00
VCORF_uR

Y1 33K/F_6 WPC8769LDG: AJ087690F08

4 1 L9 11/05 Add +3VPCU +5VPCU

3 2 WPCE775L: AJ007750F00
HZ0603B601R-00_6 WPCE775C: AJ007750F01 R647 0_4 C615 0.1u/10V_4
C114 C115 C54
15p_4 32.768KHZ 15p_4 R645 *0_4
1u/10V_6 For WPC8763 +A3VPCU
+5VPCU
8769AGND 8769AGND C76
EC_VBAT R131 *0_4 U40
*0.1u/10V_4 R648
*10K_4 CIR_VCC 3
R112 0_4 To: CCD Power Switch (Output) VCC
CCD_POWERON (18)
CIRRX2 1
+3V OUT
2
For WPCE775 GND
4
GND
R41
10K_4 IR-FM-9038SM-5CN

A 11/01 Del D12 10/19 REV_A1 Change footprint A

10/21 REV_A1 Change pin define
D14 BAS316
(19) GFXPG
HWPG

D18 BAS316
(31) SYS_HWPG
D6 BAS316
(33) HWPG_1.05V
D5 BAS316
(6,34) HWPG_1.8V
D13 BAS316
Quanta Computer Inc.
(35) HWPG_1.5V
PROJECT : BL5M Montevina
Size Document Number Rev
1A
EC-WPCE775C
Date: Monday, March 10, 2008 Sheet 29 of 37
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 5 4 3 2 1

PF1 VA PD12
PR157
0.02_7520 12/18 REV_3A Change footprint
PCN1 PF1 PL2 PDS1040S-13 PQ26 VIN PQ27
BUS-10A-1206 HI0805R800R-00_8 1 FDD6685 FDD6685
4 1 2 3 1 2 VA2 3 4 3 4
2
3
PC57 PR18
R1

1
PC51 PC53 PC34 PR47 PC96 PC95
33K_6
2 2200p/50V_6 PL1 0.1u/50V_6 0.1u/50V_6 0.1u/50V_6 220K/F_6 0.1u/50V_6 2200p/50V_6

1
HI0805R800R-00_8
1 PD11
D PC55 PC56 P4SMAJ20A D
0.1u/50V_6 0.1u/50V_6
NC PR79,PR80,PR78,PD6 11/05 +3VPCU 1 6 PR19

2
20277-04XX-4P-L PD5 PR37 0_6 10K_6
SW1010CPT PR43 2 5 D/C# (29)
220K/F_6
PR85 PD6 3 4

3
*10K/F_6 PR172
ACIN_1 2 1 4.7K/F_6 Add PR171,172 and PQ39 12/18 PQ2
(28,29) ACIN
IMD2AT108
2
*ZD12V PR171
PR84 PR83 100K/F_6 Del PR5,8 12/18 PQ1

3
*6.8K/F_6 *10K/F_6 DMN601K-7

1
PL8 VIN
2 ACPRN HI0805R800R-00_8
PC4 VA3
PQ39 2.2u/10V_8
DMN601K-7 ISL6251_VDD 1 2
PR28 PR22

1
2.2/F_6 20/F_6
Input sense resistor and Constant power setting table
PR45
CHG-EN (29)
PC14 4.7_6 PC29
0.1u/50V_6 4.7u/10V_8
Add PR168,PR169 10/31 ISL6251_VDDP
UMA Discrete 1 2
PC121 PC118
C PR10 EN PR10,7 12/18 CSIP CSIN 0.1u/50V_6 10u/25V_1206 C

5
6
7
8
PD3 PC120

19

20

15
20m Ohm 20m Ohm 0_6

1
RB500V 2200p/50V_6
R1 PR15
CS+020AGM00 CS+020AGM00

CSIP

VDDP
CSIN

VDD
6251EN 20/F_6 PR35 PC22 4
6251LR CSOP 21 2.7_6 .1u/25V_8 PQ34 Change footprint and P/N 12/18
CSOP 6251B_2 6251B_1 FDS8878
10K Ohm 2.43K Ohm BOOT
16

2
PC6
R2 47n/25V_6 PR151
CS31003F949 CS22433F913 PR7 17 ISL6251_UGATE PL12 0.03_3720

1
100K/F_6 BAT-V CSON 22 UGATE 6R8uH

3
2
1
CSON 6251LR BAT-V
10K Ohm 10K Ohm PR11 ISL6251_PHASE
1 2
R3 PHASE
18

5
6
7
8
20/F_6
CS31003F949 CS31003F949

1
PU1 14 ISL6251_LGATE PR159
ACPRN ISL6251A LGATE PC119
10A 10A PC5
23
ACPRN
4 *2.2_6
.01u/50V_6
PF1 PR6 0.1u/50V_6
DKA00VFU000 DKA00VFU000 13

2
10/F_6 PGND
DCIN 24 12 PQ36
DCIN GND FDS6690AS PC132 PC110
+3VPCU PR132 *2200p/50V_6 6251LR 2200p/50V_6

3
2
1
82.5K/F_6 11 PC112 PC91
6251ACSET 2 VADJ BAT-V 10u/25V_1206 10u/25V_1206
PR1 PR4 ACSET
*100K_4 10K_6 PC89 Modify on 11/05 10
100p/50V_6 PR131 ACLIM VREF
3
EN

VCOMP
TEMP_MBAT 10K/F_6

ICOMP
CELLS

CHLIM
B TEMP_MBAT (29) B

VRFE
CN18

ICM
HI0805R800R-00_8 PR38 PR41
10 1 MBAT+ 1
PF2
2
PL5
BAT-V NC PR9 12/18
R2 10K/F_6 *514K/F_6

6251ICOMP 5

9
2 ID
11 3 ID (29) Float = 4.2V / CELL
B/I BUS-15A-1206 PR9 VADJ
4 TEMP_MBAT PL6 *10K/F_6 CV-SET (29)
5 HI0805R800R-00_8 ISL6251_VDD 6251EN VREF ACLIM PR40 *0_6
6
1

PR2

6251VCOMP1
7 100K/F_6 PR128 CC-SET (29)
12 8 *10K/F_6 PR42 PR39
+3VPCU
R3
2

9 PC92 6251CELLS_1 PC21 *514K/F_6

13 10K/F_6
PC1 PC2 0.1u/50V_6 100p/50V_6
SUYIN BATTERY
6251CELLS_1 PR125
3

*10K/F_6 PC8
ADDRESS: 16H 47p/50V_6 47p/50V_6 .01u/50V_6 PR29
*100_4
PR126 PR129 PR12 6251CELLS_2 2 6251VCOMP2 ICMNT
ICMNT
100_4 100_4 0_6
3

PR137 LIM = (1/R2)*(((0.05/VREF=2.39)VACLM)+0.050)

MBDATA (29) PQ24 3.3K/F_6
*DMN601K-7 CURRNT LIMIT POINT =(90w/19v)*0.85= 4.026A
1

2
(29) CELL-SET 2
MBCLK (29) PR124 4.026A=(1/0.02)((0.05/2.365)Vaclm+0.05)
PQ23 *100K/F_6 PC102

1
PR127 *DMN601K-7 .01u/50V_6 Vaclm=((33//152)/(33//152+19.6//152))*Vref
1

+3VPCU +3VPCU *100K/F_6

1

A PD9 PD10 A
1

ZD3.6V ZD3.6V PR3 PC3 R2=adapter current sense resistnece

1

*100K/F_6 .01u/50V_6 PC13 PC16

PD2 PD1 *100p/50V_6 *3300p/50V_4
2

3 ID 3TEMP_MBAT

*DA204U *DA204U
Quanta Computer Inc.
2

PROJECT : BL5M Montevina

CELL-SET = Hi ----> Cells = VDD ---->4S Size Document Number Rev
CELL-SET = Low ----> Cells = GND ---->3S CHARGER (ISL6251A) 1A

Date: Monday, March 10, 2008 Sheet 30 of 37

5 4 3 2 1

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 5 4 3 2 1

MAIND
MAIND (34,35)

SUSD
SUSD (35)

(3) SYS_SHDN# 1 2

PR115
0_4
D VIN VIN D
VL

+ VL

2
PC77
PR105 4.7u/10V_8

1
390K_4

2
PR110 PR103 PR100
39K/F_4 0_4 PC72 0_4 PC64 PC62
PC90 PC69 PC71 PC82 PC74 1u/10V_6 0.1u/50V_6 10u/25V_1206
100U/25V_6X7.7 0.1u/50V_6 2200p/50V_6 10u/25V_1206 0.1u/50V_6 PC65

1
2

5
6
7
8
PC70 PC73 2200p/50V_4
*10u/25V_1206 *.01u/16V_4 PC67
0.1u/50V_6 PQ10

1
3V5V_EN REF 4 FDS8878
3V_DH

1
8
7
6
5
PR99 *0_6
PR107 OCP : 8A
150K_4

8
7
6
5
4
3
2
1
4 5V_DH +3VPCU
PQ11 PL3

LDO

ONLDO

REF
LDOREFIN

VIN
NC

VCC
TON

3
2
1
FDS8878 2R2uH-5.8mR
OCP: 8A 03/17 REV_3A Change PR108 to 63.4K/F +3VPCU
03/14 REV_3A Add PR108,PR113 PR91 3V_LX

5
6
7
8
+5VPCU +5VPCU
9 32 REFIN2 196K/F_6
BYP REFIN2

1
PL4 10 31 1 2

1
2
3
2R2uH-5.8mR OUT1 PU5 ILIM2 PR89
C 11 FB1 OUT2 30 C
+5VPCU 5V_LX 1 2 12 29 SKIP 4 *2.2_6
PR109 178K/F_6 DDPWRGD_R 13 ILIM1 ISL6237 SKIP# DDPWRGD_R
PGOOD1 PGOOD2 28
2

8
7
6
5
3V5V_EN 14 27 3V5V_EN PR93 +

2
EN1 EN2
1

PR108 15 26 0_6
63.4K/F_4 PR122 DH1 DH2 PC61 PC63
16 LX1 LX2 25
+ 2.2_6 4 5V_DL 37 PC60
PAD *2200p/50V_6
36
1

3
2
1
PAD

PGND
PVCC
PC87 PC85 PC80 PQ9

BST1

BST2
GND
PAD
PAD
PAD
2

DL1

DL2
PC81 PC66 FDS6690AS

NC
2

PQ13 0.1u/50V_6 0.1u/50V_6

PR113 PC86 FDS6690AS PR98

35
34
33

17
18
19
20
21
22
23
24
10K/F_4 2200p/50V_6 PR112 1/F_6
1
2
3

1/F_6 1 2
1 2 3V_DL PR92
1

*0_6 0.1u/50V_6 330u/6.3V_6X5.7

10u/25V_1206 0.1u/50V_6 ADD PR174 12/18 +3VPCU
PR174 VL PR101 SKIP PR94 *0_6 REF
330u/6.3V_6X5.7 PC78 0_6 0_6 PR175
2 0.1u/50V_6 *0_6
PC75 PR95 0_6
3 1u/16V_6 PR96
PD8 *10K_6
OCP:8A 1 1PS302 NC PR175 12/18
PC76 DDPWRGD_R PR97 0_6
L(ripple current) 0.1u/50V_6 OCP:8A SYS_HWPG (29)
PC79
=(19-5)*5/(2.2u*0.4M*19) 0.1u/50V_6 2
L(ripple current)
~4.18A 3 =(19-3.3)*3.3/(2.2u*0.5M*19)
B B
Iocp=8-(4.18/2)=5.91A 1
PD7 ~2.48A
1PS302
Vth=5.91A*15mOhm=88.65mV Iocp=8-(2.48/2)=6.67A
PR102
R(Ilim)=(88.65mV*10)/5uA Vth=6.67A*15mOhm=100.05mV
+15V_ALWP 1 2 REFIN2
~177.3K +15V

1
PR90 *0_6 R(Ilim)=(100.05mV*10)/5uA
PR106 PR104
22_8 PC68 *200K_4 *39K_4
~200.1K +3VPCU
0.1u/50V_6

3
VIN +15V +5VPCU

+5VPCU +3VPCU
+3VPCU SUSD 2
PR168 PR166
1M_6 1M_6 PQ20
3

DMN601K-7

1
5
6
7
8
1
2
5
6

S5D 2 +3VSUS

1
2
5
6
3

PQ14 MAIND 3 PQ12 MAIND 4

DMN601K-7 FDC653N_NL S5D 3 PQ7
2 FDC653N_NL
(29,35) S5_ON
1

2 PQ6
4

PR167 FDS8884
+5V_S5

4
1M_6 PQ37
1

PQ38 DMN601K-7
3
2
1

+5V +3V_S5
DTC144EU
1

A A

+3V

Quanta Computer Inc.

PROJECT : BL5M Montevina
Size Document Number Rev
1A
SYSTEM 5V/3V (ISL6237)
Date: Monday, March 17, 2008 Sheet 31 of 37
5 4 3 2 1

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 5 4 3 2 1

+3VPCU +3VPCU PC101

2200p/50V_6
VIN

1
+

1
PR77 PR76 PR75 PR70 PR65 PR59 PR56
*0_6 *0_6 *0_6 *0_6 *0_6 *0_6 *0_6 PC100

2
1
0.1u/50V_6

2
PR69
DELAY_VR_PWRGOOD (3,6,16)

5
D 2.2_6 D
PC98 PC88
H_VID6 H_VID5 H_VID4 H_VID3 H_VID2 H_VID1 H_VID0 10u/25V_1206 PC97 100U/25V_6X7.7

2
6266A_UG1 4 10u/25V_1206

PC45 VCC_CORE

1
2
3
PR46 4.99K/F_6 VIN +3V PQ35 2200p/50V_6
PWR_MON 2 1 PGD_IN AOL1414
PL10 0.36uH
6266A_PH1 1 2
1

1
PR145

1
PC33 10/F_6 PR55 PR51

4
5
0.1u/50V_6 10_4 1.91K/F_4 PR68 + PC38 + PC30
2

+5V_S5 2.2_6 *560U/2V_7

330u/2V_7343

2
1
6266A_LG1 4

2
(3) PSI# PSI# PC116

1
PR148 0.1u/50V_6

1
2
3
10/F_6 PC39 PQ33 PC43
0.1u/50V_6 AOL1412 2200p/50V_6

2
PR50 PR49

22

20

48
2

1
PR36 0_8 0_6 0_6
PC117

3V3
VCC

VIN

PGOOD
1u/25V_8
1 PR26 3.65K/F_6
VSUM
21 35
GND UGATE1 PR52 2.2_6 PR33 10K/F_6
Close to Phase 1 Inductor 49
GND_T BOOT1
36 1 2

1
Throttling temp. PR20 1/F_6
+3V_S5 PC35
105 degree C 0.22u/25V_8

2
C 34 PR136 *0_6 C
PSI# PR48 0_4 PSI#_1 PHASE1 ISEN2
2
PSI#
32
PR44 VR_ON PR155 *0_4 PGD_IN LGATE1
3 VIN
*10K/F_4 PGD_IN
33
PR150 147K/F_6 PGND1
4
RBIAS

1
24 ISEN1 PC129
ISEN1

1
(3) H_PROCHOT# 5 PR14 2200p/50V_6
VR_TT#

2
PR146 470K_4 NTC PR149 4.02K/F_4 6 PC17 2.2_6

2
NTC
+5V_S5 0.22u/25V_6

2
2 1 PC28 7

1
PC31 1 0.022u/50V_6 SOFT PC32 PC130 PC40 PC128
2

5
.01u/16V_4 31 1 2 10u/25V_1206 10u/25V_1206 0.1u/50V_6
H_VID0 PVCC
Panasonic 37
VID0
(4) H_VID0 4.7u/25V_8
ERT-J0EV474J H_VID1 38 PU2 27 6266A_UG2 4
(4) H_VID1 VID1 UGATE2
ISL6266A PR34 2.2_6
H_VID2 39 26 1 2 PC9
(4) H_VID2

1
2
3
VID2 BOOT2

1
PSI#_1 H_VID3 40 PQ25 2200p/50V_6
(4) H_VID3 VID3 PC26 AOL1414
H_VID4 41 0.22u/25V_8 PL7 0.36uH
(4) H_VID4

2
VID4 6266A_PH2
28 1 2
H_VID5 PHASE2
(4) H_VID5 42
VID5

1
PR156 30 6266A_LG2

4
H_VID6 LGATE2 PR130
*0_6 (4) H_VID6 43
VID6
29 2.2_6
PR60 0_4 VR_ON PGND2 + PC7 + PC58
(29) VRON 44 4
VR_ON ISEN2 *560U/2V_7
23

2
PR61 499/F_4 DPRSLPVR ISEN2 PC94 330u/2V_7343
(6,16) PM_DPRSLPVR 45

1
2
3
DPRSLPVR

1
DPRSLPVR
PR62 0_4 46 PC18 PQ28 2200p/50V_6
(3,6,14) ICH_DPRSTP# DPRSTP# 0.22u/25V_6 AOL1412

2
PR63 0_4 CLKEN# 47 PR17 PR16
(16) VR_PWRGD_CK410# CLK_EN# 0_6
PC27 1000p/50V_4 0_6
B PR23 1K/F_4 25 2 1 B
VR_ON NC

8
OCSET PR143 13.3K/F_4
1 2 13
VDIFF
PR64 PR31 PC15 19 VSUM
100/F_4 2200p/50V_6 VSUM
10K/F_6
PR30 1K/F_4
12
FB2
1

PR135 PR133
11K/F_4 2.7K/F_4
11 PC105
2
1

FB 68n/25V_6 PR13 3.65K/F_6

PR140 97.6K/F_4 PC113 220p/50V_4 VSUM
2 1 PC109
2

Add PR170 10/31 0.22u/10V_6 PR147 PR134 10K/F_6

10 10K _6 NTC
PC24 COMP
2 1 PR21 1/F_6
18
100P/50V_4 PR144 8.25K/F_4 VO
Panasonic
DROOP

9 PR138 *0_6
VW ERT-J1VR103J
VSEN

ISEN1
RTN

DFB

1 2 PR32
1K/F_4 PC12
15

14

16

17

PC115 1000p/50V_6 0.33u/25V_6 Close to Phase 1 Inductor

2

PR27
PC20 2 1 3.9K/F_4
330p/50V_4

PC11 180p/50V_4
2 1 ISL6266_VO
2

A PC106 PC107 A
330p/50V_4 .01u/16V_4
1

Parallel
PR25 0_4
VCCSENSE (4)

VSSSENSE (4)
PR24 0_4

Quanta Computer Inc.

PROJECT : BL5M Montevina
Size Document Number Rev
1A
CPU CORE(ISL6266A)
Date: Monday, March 10, 2008 Sheet 32 of 37
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 1 2 3 4 5

A A

VIN
+5V_S5
PR158

10_6
PD4
RB500V
PC36

5
PR73 PC37
B 1M_6 *0.1u/50V_6 B
4.7u/10V_8

2
PR71 4 PC25 PC23 PC19 PC10 PC103
0_6 2200p/50V_6 2200p/50V_6 0.1u/50V_6 10u/25V_1206 10u/25V_1206
PC41

1
2
3
PR72 47K_6 .1u/25V_8 PQ30
15 13 AOL1414
(19,29,34,35) MAINON EN/DEM BOOT
+3V UGATE-1.05V
OCP: 14A
16 12
PC48 TON UGATE PL11
0.1u/50V_6 1 11 PHASE-1.05V
VOUT PHASE +1.05V

1
2 10 PR57 3.24K/F_6 1R5uH-3.9mR
VDD OC

5
PR58 PU3 PR142

1
*10K_6 3 RT8202 9 *2.2_6
FB VDDP +
4 8 LGATE-1.05V 4 PR67
(29) HWPG_1.05V

2
PGOOD LGATE PC42

2
4.02K/F_6 33p/50V_6
6 7 Rds*OCP=RILIM*20uA

1
2
3
GND PGND PC111
5 17 PQ31 *2200p/50V_6
NC TPAD AOL1412
14
GND

GND

GND

GND

NC
1

PC123 PC50 PC49 PC127 PC134 PR66

1u/16V_6 560u/2.5V_6X5.7 10u/10V_8 10K/F_6
2

18

19

20

21

*1000p/50V_6 .01u/50V_6 VOUT=(1+R2/R3)*0.75

C 1.05V_FB C

TON=3.85p*RTON*Vout/(Vin-0.5) AOL1412 Rds=4.6mOhm

14A OCP --- OC=3.22K
Frequency=Vout/(Vin*TON)

D D

Quanta Computer Inc.

PROJECT : BL5M Montevina
Size Document Number Rev
1A
VTT 1.05V (RT8202)
Date: Monday, March 10, 2008 Sheet 33 of 37
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 5 4 3 2 1

D D

VIN

+1.8VSUS

5
6
7
8
PR139
PC46
4 *2.2/F_6
10u/10V_1206 PQ29
PU4 FDS8878
TPS51116 PC104 PC99 PC93
1 19 PC108 2200p/50V_6 10u/25V_1206 10u/25V_1206
VLDOIN DRVH *2200p/50V_6
2 20 PC124 0.1u/50V_6
OCP: 12.44A
+SMDDR_VTERM

3
2
1
VTT VBST PL9
4 18 +1.8VSUS
PC54 PC52 VTTSNS LL
10u/10V_8 10u/10V_8 5 17 2R2uH-5.8mR
GND DRVL
3 16 +
VTTGND PGND

5
PR141
DIS_MODE 6 11 S3_1.8V PR154
C MODE S3 0_6 MAINON (19,29,33,35) C
*2.2/F_6
7 12 S5_1.8V PR153 4
+SMDDR_VREF VTTREF S5 0_6 SUSON (29,35)
PR161 5VIN 8 14 5VIN

1
2
3
0_6 PC133 COMP V5IN PQ32 PC114 PC131 PC47
0.033u/50V_6 9 13 PR152 +3VPCU +3VPCU AOL1412 *2200p/50V_6 560u/2.5V_6X5.7 10u/10V_8
VDDSNS PGOOD 100K/F_6
GND
GND
GND
GND
GND
GND
5VIN GND
10 15
VDDQSET CS
PR80
(10u*PR35)/Rdson+Delta_I/2=Iocp
21
22
23
24
25
26
27

0_6 PC125
PR53
*1000p/50V_6 5.1K/D_6

PR160 *0_6 DIS_MODE FOR DDR II

5VIN
+5VPCU HWPG_1.8V (6,29)
1

PR54 PC126
0_6
+1.8VSUS PR162 0_6 4.7u/6.3V_6
2

PR79
*110K/F_6
R2
S3_1.8V S5_1.8V

PR78
B R1 *76.8K/F_6 PC44 PC122 B
*0.1u/50V_6 *0.1u/50V_6

R1=(100*Vout-R2)K
if tune Vout PR38 un-mount, PR156 PR165 mount

+1.8VSUS
MAIND
MAIND (31,35)
1
2
5
6

MAIND 3 PQ8
FDC653N_NL
4

A A
+1.8V

Quanta Computer Inc.

PROJECT : BL5M Montevina
Size Document Number Rev
1A
DDR 1.8V(TPS51116)
Date: Monday, March 10, 2008 Sheet 34 of 37
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 5 4 3 2 1

+1.8VSUS
+3V_S5

1
PR88
100K_4

2
PU6
5 7 HWPG_1.5V (29)
VIN POK
D D
9 1
PC141 PC144 VIN1 GND +1.5V
10u/6.3V_8 0.1u/10V_4
APL5913
(19,29,33,34) MAINON 8 3 +1.5V (4,9,17,25,28)
EN VOUT
PR87 +5V_S5
2.8A

1
0_6 6 4
PR86 VCNTL VOUT

FB
2
100K_4

2
PR164

1
PC59
*0.1u/50V_6
88.7K/F_4
PC137
1u/10V_4 PR163 PC140
100K/F_4 1 2 0.1u/10V_4

PC136
47n/50V_4

PC138 PC139
Vout =0.8(1+R1/R2) 10u/6.3V_8 10u/6.3V_8
=1.25V

C C

VIN +SMDDR_VREF +1.8VSUS +15V

PU7 0.15A
PR165
(29,31) S5_ON 2 1 3 5 +1.5V_S5
PR120 PR74 PR81 PR116 SHDN VO
1M_6 22_8 22_8 1M_6 0_6 2
GND
1 4 PC135
SUS_ON_G SUSD VIN NC 1u/16V_6
SUSD (31) +3VPCU
G909
3

PC142
3

2.2u/10V_6
PR117
2 1M_6 2 2 2
(29,34) SUSON PC84
1

PQ3 PQ4 PQ15 *2200p/50V_4 PC143

PR169 PQ16 DMN601K-7 DMN601K-7 DMN601K-7 *0.1u/50V_6
1

*100K_4 DTC144EU
1

1
2

B B

NC PR169 12/18

VIN +3V +5V +SMDDR_VTERM +1.8V +15V

PR121 PR119 PR123 PR82 PR114 PR111

1M_6 22_8 22_8 22_8 22_8 1M_6

MAINON_ON_G MAIND
MAIND (31,34)
3

3
3

A PR118 A

2 1M_6 2 2 2 2 2
(19,29,33,34) MAINON PC83
PQ21 PQ22 PQ5 PQ19 PQ18 *2200p/50V_4
PQ17 DMN601K-7 DMN601K-7 DMN601K-7 DMN601K-7 DMN601K-7
1

DTC144EU
1

Quanta Computer Inc.

PROJECT : BL5M Montevina
Size Document Number Rev
1A
Discharge (1.25V/1.5V)
Date: Monday, March 10, 2008 Sheet 35 of 37
5 4 3 2 1

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 5 4 3 2 1

Model REV DATE CHANGE LIST NOTE

00 20070824 FIRST RELEASED : 20070824
20070914 FIRST RELEASED : E200709-2519
BL5S 1A

D D

C C

B B

A A

Quanta Computer Inc.

PROJECT : BL5M Montevina
Size Document Number Rev
1A
Change List
Date: Tuesday, March 04, 2008 Sheet 36 of 37
5 4 3 2 1

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 5 4 3 2 1

ISL6262A
P.33 VCC_CORE
VRON enable
AC DMN601K RT9025-25PSP
System +5V_S5 +1.25V
P.31 P.35
Charger S5_ON enable MAINON enable
D D
DC +5VPCU
AC/DC Insert enable FDC653N_NL APL5913
+5V +1.5V
P.31 P.35
ISL6237 MAINON enable MAINON enable
P.31
FDS8884
+3VPCU +3V
P.31
AC/DC Insert enable MAINON enable

FDC653N_NL
RT8202 +3V_S5
+1.05V P.31
P.33 MAINON enable S5_ON enable

DMN601K
+3VSUS
C P.31 C
+SMDDR_VTERM SUSON enable
TPS51116 SUSON enable
P.34 +SMDDR_VREF
SUSON enable FDC653N_NL
+1.8VSUS P.34 +1.8V
SUSON enable MAINON enable

Power Distribution List

Power Distribution
VCC_CORE CPU
+5VPCU ICH8M, RJ45/USB /B, USB/eSATA, Satellite LED, CIR
+3VPCU RTC, HALL SENSOR, KB, TP/FP/LED /B, Power /B, Kill SW, EC, ID, SPI Flash, CIR
+1.5V CPU, GMCH, ICH9M, Mini Card, New Card
B B

+1.8VSUS GMCH, DDR

+SMDDR_VREF GMCH, DDR
+SMDDR_VTERM DDR
+1.05V CPU, CLK, Thermal Trip, GMCH, ICH8M
+5V_S5 ICH8M, G-SENSOR, Felica, USB/eSATA
+5V CPU, ICH8M, VGA, Camera, CRT, HDMI, SATA HDD, PATA ODD, PCMCIA, TP/FP/LED /B, EC, Speaker, Headphone
CLK, CPU Thermal Monitor, FAN, GMCH, DDR, ICH8M, VGA, LCD/LED Panel, HALL SENSOR, CRT, HDMI, SATA HDD, PATA ODD, PCMCIA, Cardreader (OZ129T)
+3V
Mini Card, KB, TP/FP/LED /B, RJ45/USB /B, Bluetooth, MMB, New Card, PC BEEP, EC, Codec (CX20561), VR, Headphone, MDC
+3V_S5 ICH8M, Mini Card, RJ45/USB /B, New Card
+3VSUS ICH8M, FP
+1.8V HDMI, Cardreader (OZ129T)
+1.25V CLK, GMCH, ICH8M
A A

Quanta Computer Inc.

PROJECT : BL5M Montevina
Size Document Number Rev
1A
Change List
Date: Tuesday, March 04, 2008 Sheet 37 of 37
5 4 3 2 1

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