EEE 304
Experiment No. 04
Name Of The Experiment: Design of Decoder/Encoder/Multiplexer
circuit
Important: Submit your Prelab at the beginning of the lab.
Objectives:
(i) Implementation of simple decoding technique
(ii) Introduction of priority concept in encoding/decoding
(iii) Study different aspects of MUX(Data Selector)
Apparatus:
(i) OR gate (IC 7432, 1 piece)
(ii) AND gate (IC 7408, 2 piece)
(iii) NOT gate (IC 7404, 1 piece)
(iv) IC 74150 (16X1 MUX)(1 piece)
(v) IC 74153 (dual 4X1 MUX)(1 piece)
(vi) IC 74154 (4 line to 16 line decoder)(1 piece)
(vii) Wires, trainer board, etc.
Introduction to decoder logic:
The basic function of a decoder circuit is to detect the presence of a specified combination of
bits(code) on its inputs and to indicate the presence of that code by a specified output level. In its
general form, a decoder has n input lines to handle n bits and from one to 2n output lines to
indicate the presence of one or more nbit combinations.
Example:
Suppose we need to construct a decoder system which has A and B(i.e 2 bits) as its input and we
have to determine the presence of each combination of these inputs (22=4 combination)by
observing the output lines(one for each combination). The presence of AB=11 can be determined
by observing the output of an AND gate whose output is AB. Similarly logic equation for other 3
combinations can be found. Then , if we find out which output line is active ,we can determine
input. The complete circuit diagram is shown below:
Prepared by :Dr. A.B.M.H. Rashid, Md Abu Jafar Siddiq Date:16/12/06
Prelab 1:Develop the logic required to detect the binary code 10010 and produce an active
LOW output.
Exercise 1: Construct a decoder circuit which can detect the presence of 8 and 15 at the
input.
Exercise 2: Construct a 5 bit(i.e 5 line to 32 line)decoder circuit by cascading two 4
line to 16 line decoder(IC 74154).
The priority encoder circuit:
An encoder essentially performs a “reverse” decoder function. It accepts an active level on one
of its inputs representing a digit, such as a decimal or octal digit, and converts it to a coded
output, such as BCD or binary.
Example: The decimal to binary encoder
This type of encoder has ten inputsone for each decimal digitand four outputs corresponding to
the BCD code. The BCD code is listed in the following table:
Decimal Digit BCD code
A3 A2 A1 A0
00 0 0 0
10 0 0 1
20 0 1 0
30 0 1 1
40 1 0 0
50 1 0 1
60 1 1 0
70 1 1 1
81 0 0 0
91 0 0 1
Note that A0 output should be high when any of 1,3,5,7,9 input lines is present at the input.
Hence the expression for A0 will be:
A0 =1+3+5+7+9
Similarly A1=2+3+6+7
A2=4+5+6+7
A3= 8+9
The input lines do not always exhibits same priority. There may be cases where some inputs
have higher priorities than others. In such cases ,when two input lines are active simultaneously,
the output choose to respond to the input line with highest priority. The encoder described above
can be modified to function as a priority encoder. In that case , the encoder will produce BCD
output corresponding to the highest order decimal digit input that is active and will ignore any
other active inputs.For instance, if the 6 and 3 inputs are both active, the BCD output is
0110(which represents decimal 6).
Prepared by :Dr. A.B.M.H. Rashid, Md Abu Jafar Siddiq Date:16/12/06
Now lets look at the requirements for the priority detection logic.This logic circuitry prevents a
lower order digit input from disrupting the encoding of a higher order digit. We want to examine
the output A0. Note that A0 is HIGH when 1,3,5,7 or 9 is high. Note that Digit 1 should activate
the A0 output only if no higher order digits other than those that also activate A0 are HIGH. The
requirements can be stated as follows:
1.A0 is HIGH if 1 is HIGH and 2,4,6 and 8 are LOW
2.A0 is HIGH if 3 is HIGH and 4,6 and 8 are LOW
3.A0 is HIGH if 5 is HIGH and 6 and 8 are LOW
4.A0 is HIGH if 7 is HIGH and 8 are LOW
5.A0 is HIGH if 9 is HIGH
A0 output is HIGH if any of the above 5 conditions occur. Hence,
A0= 12 4 68 34 68 568 78 9
Prelab 2: For the above example of priority encoder, find the logic equations for A1,A2
and A3
Exercise 3: Construct a priority encoder which implement the encoding of 0,3,1,2 with
descending priority(i.e 0 has the highest priority and 2 has the lowest)
Multiplexer or Data Selector:
A multiplexer is a device that allows digital information from several sources to be routed onto a
single line for transmission over that line to a common destination. The basic multiplexer has
several data input lines and a single output line. It also has data selector inputs, which permit
digital data on any one of the inputs to be switched to the output line. Multiplexers are also
known as data selector.
*** C here stands for selector switch
Note from the table that when C is 1, output is connected to the input B and in that case the state
of input at A does not have any effect on the output Y. Similarly when C is 0, output is
connected to the input A.
Prepared by :Dr. A.B.M.H. Rashid, Md Abu Jafar Siddiq Date:16/12/06
Following is the top view of IC 74LS153 which is a dual 4 line to 1 line Multiplexer(i.e it
contains two 4 line to 1 line MUX). Its internal circuit diagram is also given.
Exercise 4: Implement the Multiplexing function using IC 74LS153
Combinational logic implementation using MUX:
A useful application of the data selector is in the generation of combinational logic functions in sum of
products form. When used in this way, the device can replace discrete gates, can often greatly reduce the
number of ICs and can make the design changes much easier. A good example is given below.
Prepared by :Dr. A.B.M.H. Rashid, Md Abu Jafar Siddiq Date:16/12/06
Exercise 5: Implement the following logic using IC 74150
F (A,B,C,D)=∑(1,3,5,7,9,11,13,15)
C
Cascading of MUX to increase the number of input line:
We can cascade several MUXs to construct a single MUX with higher number of input lines.
In the following example we have constructed a 4 line to 1 line MUX using 3 two line to one line
MUX
S1 S0 Input connected
to the output
0 0 I0
0 1 I1
1 0 I2
1 1 I3
Exercise 6: Implement a 8 line to 1 line MUX using two 4 line to 1 line MUX(found in IC
74153) and an OR gate.
Home work:
1.Design the same circuit as described in Exercise 6 using three 4 line to 1 line MUX
2.Implement a 10 line to 1 line MUX using two 4 line to 1 line MUX, one 2 line to 1 line MUX
and a 3 input or gate. Can you suggest any alternative design solution?
3. Explain Fan – in and Fan – out. Explain these effects for a n to 2n decoder.
Reviewed By: Md. Imran Momtaz
Prepared by :Dr. A.B.M.H. Rashid, Md Abu Jafar Siddiq Date:16/12/06
