COURSE OUTCOME 2

1. What are the three kinds of processor modes or CPU modes.

a. Real, Protected and Privileged mode
b. Real, Privileged and Plain mode
c. Real, Plain and Protected mode
d. Real, Protected and Flat mode
2. This specifies the percentage of hits to total cache accesses.
a. Efficiency
b. Accuracy
c. Precision
d. Hit ratio
3. Choosing to make the instruction set smaller using fewer instructions and simpler
addressing codes was the decision of designers.
a. Computer
b. RISC
c. CISC
d. System
4. When two instructions are to be pair, it must .
a. Lack dependencies
b. Basic
c. Contain no displacement
d. All of the above
5. Which is not a feature of the Pentium II?
a. MMX
b. Reservation station
c. SSE
d. 242-pin SECC
6. This is an implementation technique where multiple instructions are overlapped
in execution?
a. Super scale
b. Pipelining
c. RISC
d. CISC
7. Which processor is influenced by the EPIC philosophy?
a. Pentium 4
b. Xeon
c. Itanium
d. Celeron
8. It provides a way for other processors in a multiprocessor system to instantly
take over the Pentium’s buses.
a. BOFF
b. HALT
c. Bus HALT
d. Shutdown
9. The state in which data requested for processing by a component or application
is found in the cache memory?
a. Cache fluff
b. Cache miss
c. Cache drop
d. Cache hit
10.This cycle is used to transfer up to 8 bytes of non-cacheable data between the
processor and memory
a. Single-transfer
b. Burst
c. LOCK
d. BOFF
11.This data dependency exists if the second instruction reads an operand written to
it by the first instruction.
a. Write after read
b. Execute
c. Execute after read
d. Read after write
12.These are all component of NetBurst Architecture EXCEPT:
a. Hyper Piped Line Technology
b. Rapid Execution Engine
c. Execution Trace Cache
d. Executive Engine Line
13.Which is not goal of RISC?
a. Pipelining everything
b. Utilize the compiler extensively
c. Reduce accesses to main memory
d. Make instructions to multi-task
14.In the Branch Prediction, which states predict a jump?
a. State 0, State 1
b. State 1, State 2
c. State 2, State 3
d. State 0, State 3
15.It is a special type of high speed RAM where data and the address of the data
are stored.
a. Stack
b. Pipeline
c. Cache
d. Register
16.If an internal parity error is detected by the Pentium, a cycle is run.
a. Shutdown
b. Halt
c. Bus hold
d. Inquire
17.It is a technique used to enable one instruction to complete with each clock cycle.
a. RISC
b. Burst
c. Pipelining
d. Micro-op
18.This signal causes the Pentium to writeback all modified data lines in its internal
code and data cache
a. PWT
b. WB/WT
c. RESET
d. FLUSH
19.It allows a new 8-byte chunk to transfer every clock cycle
a. Bus operation
b. Pipelining
c. Burst operation
d. Branch operation
20.Branch prediction is assisted by the use of:
a. History bits
b. Branch priority
c. Prediction arrays
21.Which is not Dynamic Execution Technology?
a. Multiple-Branch Prediction
b. Data Flow Analysis
c. Speculative Execution
d. Bus Snooping
22.Which is examined first when processor need to read data from main memory?
a. Cache
b. Memory
c. Stack
d. Register
23.Also known as an external cache
a. Second Level cache
b. Third Level cache
c. Data cache
d. None of the above
24.Bus input provides a second way for a different bus master to take control
of the Pentium’s buses.
a. BOFF
b. HOLD
c. INTR
d. FLUSH
25.Processors capable of parallel execution of multiple instructions are called
machines.
a. Dual-load
b. Parallelized
c. Superscalar
d. Multi-core
26.Pentium Pro’s IFDU contains how many separate instruction decoders for
simultaneous decoding.
a. 5
b. 4
c. 3
d. 2
27.Which has no L2 cache?
a. Pentium
b. Pentium MMX
c. Celeron
d. All of the choices
28.MMX instructions can process
a. Integer data only
b. Floating point number
c. Both a and b
29.It controls the access to the system buses by generating memory address and
control signals, and passes and fetches data or instructions to either a level 1
data cache or a level 1 instruction cache
a. BIU
b. IFU
c. DU
d. FPU
30.Separation of I- and D-caches is first implemented in
a. 80486
b. Pentium
c. Pentium Pro
d. Pentium MMX
31.Which instruction is NOT new Pentium instructions?
a. CMPXCHG
b. CPUID
c. WRMSR
d. RSM
32.Indicates that a new valid bus cycle is currently being driven by the Pentium
processor
a. ADS#
b. BRDY#
c. EADS#
d. PRDY#
33.Which is NOT a version of Pentium Pro?
a. With 256kB L2 cache
b. With 512kB L2 cache
c. No L2 cache
d. None of the choices
34.The following are new flags bits made available in Pentiums except for
a. ID
b. VM
c. AC
d. VIP
35.Which CPU supports RAMBUS memory technology
a. Pentium
b. Pentium II
c. Pentium III
d. Pentium 4
36.The Pentium II differs from earlier microprocessors because
a. It is offered as an integrated circuit
b. It is available on a plug-in cartridge
c. The internal cache of Pentium Pro architecture has been moved out
d. both b and c are true
37.The following microprocessors are all 3-way superscalar except
a. Pentium
b. Pentium 2
c. Pentium 3
d. Celeron
38.Which has 36-bit address bus and therefore can access 64GB of memory
a. 80486
b. Pentium
c. Pentium Pro
d. Both b and c
39.All of the following Pentiums has 64-bit data bus except
a. Pentium
b. Pentium Overdrive
c. Pentium Pro
d. Pentium II
40.All of the following belongs to P6 microarchitecture family except
a. Pentium Pro
b. Celeron
c. Pentium 3
d. Pentium 4
41.Which microprocessor has integrated (on-die) L2 cache?
a. Pentium
b. Pentium Pro
c. Pentium 2
d. Celeron
42.Indicates to the Pentium whether or not the system can support a cache line fill
for the current cycle
a. CACHE#
b. HIT#
c. HITM#
d. KEN#
43.Pentium can run instructions concurrently.
a. 2
b. 3
c. 4
d. 5
44.SSE2 is first introduced in
a. Pentium Pro
b. Pentium 2
c. Pentium 3
d. Pentium 4
45.Which is/are an improvement(s) of Pentium Pro over Pentium?
a. CPU3
b. L2 cache
c. Double-sized L1 cache
d. Both a and b
 46.Which of the following is a special bus cycle?
a. Code read, 256 bits burst Line Fill
b. I/O write, 32-bits or less, Non-cacheable
c. Interrupt Acknowledge (2 locked cycles)
d. Halt
47.This Pentium signal provides even parity for the memory address on all Pentium
initiated memory and I/O transfers.
a. BUSCHK
b. FERR
c. BRDY
d. APCHK
48.Which of the following is an invalid Pentium Bus Address?
a. 0000 0005H
b. 0000 0008H
c. 0000 0010H
d. 0000 0020H
49.Which is included in the IFDU?
a. Branch prediction logic
b. Error detection logic
c. Out-of-order execution
d. None of the choices
50.Not included in Pentium’s Special Cycle.
256 bit burst write back
51.Pentium’s superscalar architecture means
It can execute more than one instruction at a time
51.When two instructions are to be paired ____.
All of the above
52.___ can correct any __ bit error and detect any ___ bit error.
Pentium Pro, 1, 2
51.In Intel’s Tick Tock Model, Tick refers to
Shrinking of Process Technology

T At any time, an instruction pipeline may have multiple instructions in different stages of processing.
T Pentium PRO is Intel’s first sixth generation processor.
T The Pentium’s data bus is 64 bits wide.
T After a cache miss, there could be no another miss for the same data read from main memory.
F A Burst Cyle transfers a maximum of 64 bits for a minimum of 2 clocks.
T The reduced set of operations in RISC is easier to implement on silicon, resulting faster performance.
T Instructions are executed out of order in speculative execution.
F Pentium’s standard Single Transfer Cycle can read or write up to 32 bytes at a time.
F Pentium’s U-pipeline executes only simple instructions while V-pipeline can execute any processor instruction.
F Pentium 4’s pipelines has 14 stages.
T Pentium is a 32-bit microprocessor.
F Pentium’s address lines are named A31:A0.
F The Pentium is a pure RISC machine.
T For the Pentium, all cache operations are burst cycles.
T Cache is used to reduce accesses to main memory.