L6563

L6563A

Advanced transition-mode PFC controller

Features
■ Very precise adjustable output overvoltage
protection
■ Tracking boost function SO-14

■ Protection against feedback loop failure

(Latched shutdown) Applications
■ Interface for cascaded converter's PWM
PFC pre-regulators for:
controller
■ HI-END AC-DC adapter/charger
■ Input voltage feedforward (1/V2)
■ Desktop PC, server, WEB server
■ Inductor saturation detection (L6563 only)
■ IEC61000-3-2 OR JEIDA-MITI compliant
■ Remote ON/OFF control
SMPS, in excess of 350W
■ Low (≤ 90µA) start-up current
■ 5mA max. quiescent current Table 1. Device summary
Part number Package Packaging
■ 1.5% (@ TJ = 25°C) internal reference voltage
■ -600/+800 mA totem pole gate driver with L6563 SO-14 Tube
active pull-down during UVLO L6563TR SO-14 Tape & Reel
■ SO14 package L6563A SO-14 Tube
L6563ATR SO-14 Tape & Reel
Figure 1. Block diagram
INV COMP MULT VFF

1 2 3 5
1/V2
TRACKING
Ideal diode
BOOST LINE VOLTAGE
6 - FEEDFORWARD
TBO 1:1 MULTIPLIER
CURRENT +
MIRROR 2.5V 4
LEADING-EDGE CS
1.7V BLANKING
1:1 Voltage
VOLTAGE references
BUFFER from REGULATOR - + - +
3V VFF Vbias Q
INDUCTOR
(INTERNAL SUPPLY BUS) VCC
SATURATION
DETECTION
14 ( not in L6563A ) SAT
VCC
15 V
R Q
UVLO
R1 COMPARATOR S 13
12 GD
GND + Driver
- UVLO
R2 VREF2
Starter
11 OFF
ZERO CURRENT
- DETECTOR
ZCD 1.4V STARTER 0.2V
+
0.7V 0.26V
+

10
- - PFC_OK
RUN DISABLE SAT 7
LATCH
+

0.52V
+

0.6V Vbias FEEDBACK -

ON/OFF CONTROL
FAILURE 2.5V
(BROWNOUT DETECTION) 9 8 PROTECTION

PWM_STOP PWM_LATCH

March 2007 Rev 4 1/39

www.st.com 39
Contents L6563 - L6563A

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5 Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2 Feedback Failure Protection (FFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3 Voltage Feedforward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4 THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.5 Tracking Boost function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.6 Inductor saturation detection (L6563 only) . . . . . . . . . . . . . . . . . . . . . . . . 27
6.7 Power management/housekeeping functions . . . . . . . . . . . . . . . . . . . . . . 28
6.8 Summary of L6563/A idle states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7 Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

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L6563 - L6563A Description

1 Description

The device is a current-mode PFC controller operating in Transition Mode (TM). Based on
the core of a standard TM PFC controller, it offers improved performance and additional
functions.
The highly linear multiplier, along with a special correction circuit that reduces crossover
distortion of the mains current, allows wide-range-mains operation with an extremely low
THD even over a large load range.
The output voltage is controlled by means of a voltage-mode error amplifier and a precise
(1.5% @TJ = 25°C) internal voltage reference. The stability of the loop and the transient
response to sudden mains voltage changes are improved by the voltage feedforward
function (1/V2 correction).
Additionally, the IC provides the option for tracking boost operation (where the output
voltage is changed tracking the mains voltage). The device features extremely low
consumption (≤ 90 µA before start-up and ≤ 5 mA running).
In addition to an effective two-step OVP that handles normal operation overvoltages, the IC
provides also a protection against feedback loop failures or erroneous output voltage
setting.
In the L6563 a protection is added to stop the PFC stage in case the boost inductor
saturates. This function is not included in the L6563A. This is the only difference between
the two part numbers.
An interface with the PWM controller of the DC-DC converter supplied by the PFC pre-
regulator is provided: the purpose is to stop the operation of the converter in case of
anomalous conditions for the PFC stage (feedback loop failure, boost inductor's core
saturation) in the L6563 only and to disable the PFC stage in case of light load for the DC-
DC converter, so as to make it easier to comply with energy saving norms (Blue Angel,
EnergyStar, Energy2000, etc.). The device includes disable functions suitable for remote
ON/OFF control both in systems where the PFC pre-regulator works as a master and in
those where it works as a slave.
The totem-pole output stage, capable of 600 mA source and 800 mA sink current, is suitable
to drive high current MOSFETs or IGBTs. This, combined with the other features and the
possibility to operate with the proprietary Fixed-Off-Time control, makes the device an
excellent low-cost solution for EN61000-3-2 compliant SMPS in excess of 350W.

Figure 2. Typical system block diagram

PFC PRE-REGULATOR DC-DC CONVERTER

Vinac Voutdc

PWM is turned off in case of PFC’s

anomalous operation for safety

L6563 PWM or
Resonant
L6563A CONTROLLER

PFC can be turned off at light

load to ease compliance with
energy saving regulations.

3/39
Description L6563 - L6563A

1.1 Pin connection

Figure 3. Pin connection (top view)

INV 1 14 Vcc
COMP 2 13 GD
MULT 3 12 GND
CS 4 11 ZCD
VFF 5 10 RUN
TBO 6 9 PWM_STOP
PFC_OK 7 8 PWM_LATCH

1.2 Pin description

Table 2. Pin description

Pin N° Name Description
Inverting input of the error amplifier. The information on the output voltage of the PFC pre-
regulator is fed into the pin through a resistor divider.
1 INV The pin normally features high impedance but, if the tracking boost function is used, an
internal current generator programmed by TBO (pin 6) is activated. It sinks current from the
pin to change the output voltage so that it tracks the mains voltage.
Output of the error amplifier. A compensation network is placed between this pin and INV
2 COMP (pin 1) to achieve stability of the voltage control loop and ensure high power factor and low
THD.
Main input to the multiplier. This pin is connected to the rectified mains voltage via a
3 MULT resistor divider and provides the sinusoidal reference to the current loop. The voltage on
this pin is used also to derive the information on the RMS mains voltage.
Input to the PWM comparator. The current flowing in the MOSFET is sensed through a
resistor, the resulting voltage is applied to this pin and compared with an internal reference
to determine MOSFET’s turn-off.
4 CS A second comparison level at 1.7V detects abnormal currents (e.g. due to boost inductor
saturation) and, on this occurrence, shuts down the IC, reduces its consumption almost to
the start-up level and asserts PWM_LATCH (pin 8) high. This function is not present in the
L6563A.

Second input to the multiplier for 1/V2 function. A capacitor and a parallel resistor must be
connected from the pin to GND. They complete the internal peak-holding circuit that
5 VFF derives the information on the RMS mains voltage. The voltage at this pin, a DC level equal
to the peak voltage at pin MULT (pin 3), compensates the control loop gain dependence on
the mains voltage. Never connect the pin directly to GND.

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L6563 - L6563A Description

Table 2. Pin description (continued)

Pin N° Name Description
Tracking Boost function. This pin provides a buffered VFF voltage. A resistor connected
between this pin and GND defines a current that is sunk from pin INV (pin 1). In this way,
6 TBO
the output voltage is changed proportionally to the mains voltage (tracking boost). If this
function is not used leave this pin open.
PFC pre-regulator output voltage monitoring/disable function. This pin senses the output
voltage of the PFC pre-regulator through a resistor divider and is used for protection
purposes. If the voltage at the pin exceeds 2.5V the IC is shut down, its consumption goes
almost to the start-up level and this condition is latched. PWM_LATCH pin is asserted high.
7 PFC_OK Normal operation can be resumed only by cycling the Vcc. This function is used for
protection in case the feedback loop fails.
If the voltage on this pin is brought below 0.2V the IC is shut down and its consumption is
considerably reduced. To restart the IC the voltage on the pin must go above 0.26V. If these
functions are not needed, tie the pin to a voltage between 0.26 and 2.5 V.
Output pin for fault signaling. During normal operation this pin features high impedance. If
either a voltage above 2.5V at PFC_OK (pin 7) or a voltage above 1.7V on CS (pin 4) of
8 PWM_LATCH L6563 is detected the pin is asserted high. Normally, this pin is used to stop the operation
of the DC-DC converter supplied by the PFC pre-regulator by invoking a latched disable of
its PWM controller. If not used, the pin will be left floating.
Output pin for fault signaling. During normal operation this pin features high impedance. If
the IC is disabled by a voltage below 0.5V on RUN (pin 10) the voltage at the pin is pulled
9 PWM_STOP to ground. Normally, this pin is used to temporarily stop the operation of the DC-DC
converter supplied by the PFC pre-regulator by disabling its PWM controller. If not used,
the pin will be left floating.
Remote ON/OFF control. A voltage below 0.52V shuts down (not latched) the IC and
brings its consumption to a considerably lower level. PWM_STOP is asserted low. The IC
10 RUN restarts as the voltage at the pin goes above 0.6V. Connect this pin to VFF (pin 5) either
directly or through a resistor divider to use this function as brownout (AC mains
undervoltage) protection, tie to INV (pin 1) if the function is not used.
Boost inductor’s demagnetization sensing input for transition-mode operation. A negative-
11 ZCD
going edge triggers MOSFET’s turn-on.
12 GND Ground. Current return for both the signal part of the IC and the gate driver.
Gate driver output. The totem pole output stage is able to drive power MOSFET’s and
13 GD IGBT’s with a peak current of 600 mA source and 800 mA sink. The high-level voltage of
this pin is clamped at about 12V to avoid excessive gate voltages.
14 VCC Supply Voltage of both the signal part of the IC and the gate driver.

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Absolute maximum ratings L6563 - L6563A

2 Absolute maximum ratings

Table 3. Absolute maximum ratings

Symbol Pin Parameter Value Unit
VCC 14 IC supply voltage (Icc = 20mA) self-limited V
2, 4 to 6, 8
--- Analog inputs & outputs -0.3 to 8 V
to 10
--- 1, 3, 7 Max. pin voltage (Ipin = 1 mA) Self-limited V
IPWM_STOP 10 Max. sink current 3 mA
-10 (source)
IZCD 9 Zero current detector max. current mA
10 (sink)
PTOT Power dissipation @TA = 50°C 0.75 W
TJ Junction temperature operating range -25 to 150 °C
TSTG Storage temperature -55 to 150 °C

3 Thermal data

Table 4. Thermal data

Symbol Parameter Value Unit
RthJA Maximum thermal resistance junction-ambient 120 °C/W

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L6563 - L6563A Electrical characteristics

4 Electrical characteristics

Table 5. Electrical characteristics

( -25°C < TJ < +125°C, VCC = 12V, Co = 1nF between pin GD and GND, CFF =1µF between pin VFF
and GND; unless otherwise specified)
Symbol Parameter Test condition Min Typ Max Unit

Supply voltage

Vcc Operating range After turn-on 10.3 22 V

VccOn Turn-on threshold (1) 11 12 13 V
VccOff Turn-off threshold (1) 8.7 9.5 10.3 V
Hys Hysteresis 2.3 2.7 V
VZ Zener Voltage Icc = 20 mA 22 25 28 V

Supply current

Istart-up Start-up current Before turn-on, Vcc = 10V 50 90 µA

Iq Quiescent current After turn-on 3 5 mA
ICC Operating supply current @ 70kHz 3.8 5.5 mA
Latched by PFC_OK > Vthl or
180 250 µA
Vcs > VCSdis
Idle state quiescent
Iqdis
Current Disabled by PFC_OK < Vth or
1.5 2.2 mA
RUN < VDIS

Iq Quiescent current During static/dynamic OVP 2 3 mA

Multiplier input

IMULT Input bias current VMULT = 0 to 3 V -0.2 -1 µA

VMULT Linear operation range 0 to 3 V
VCLAMP Internal clamp level IMULT = 1 mA 9 9.5 V

∆V cs VMULT=0 to 0.5V, VFF=0.8V

--------------------
- Output max. slope 2.2 2.34 V/V
∆V MULT VCOMP = Upper clamp

VMULT = 1 V, VCOMP= 4 V,
KM Gain (3) VVFF = VMULT
0.375 0.45 0.525 V

Error amplifier

TJ = 25 °C 2.465 2.5 2.535

Voltage feedback input
VINV V
threshold
10.3 V < Vcc < 22 V (2) 2.44 2.56

Line regulation Vcc = 10.3 V to 22V 2 5 mV

IINV Input bias current TBO open, VINV = 0 to 4 V -0.2 -1 µA

7/39
Electrical characteristics L6563 - L6563A

Table 5. Electrical characteristics (continued)

( -25°C < TJ < +125°C, VCC = 12V, Co = 1nF between pin GD and GND, CFF =1µF between pin VFF
and GND; unless otherwise specified)
Symbol Parameter Test condition Min Typ Max Unit
VINVCLAMP Internal clamp level IINV = 1 mA 9 9.5 V
Gv Voltage gain Open loop 60 80 dB
GB Gain-bandwidth product 1 MHz
Source current VCOMP = 4V, VINV = 2.4 V -2 -3.5 -5 mA
ICOMP
Sink current VCOMP = 4V, VINV = 2.6 V 2.5 4.5 mA

Upper clamp voltage ISOURCE = 0.5 mA 5.7 6.2 6.7 V

VCOMP
Lower clamp voltage ISINK = 0.5 mA (2) 2.1 2.25 2.4 V

Current sense comparator

ICS Input bias current VCS = 0 -1 µA

tLEB Leading edge blanking 100 200 300 ns
td(H-L) Delay to output 120 ns

Current sense reference VCOMP = Upper clamp,

VCSclamp 1.0 1.08 1.16 V
clamp VVFF = VMULT =0.5V

VMULT = 0, VVFF = 3V 25
Vcsoffset Current sense offset mV
VMULT = 3V, VVFF = 3V 5
Ic latch-off level (L6563
VCSdis (2) 1.6 1.7 1.8 V
only)

Output overvoltage

Dynamic OVP triggering

IOVP 17 20 23 µA
current
Hys Hysteresis (4) 15 µA
Static OVP threshold (2) 2 2.15 2.3 V

Voltage feedforward

VVFF Linear operation range RFF = 47 kΩ to GND 0.5 3 V

Dropout
∆V 20 mV
VMULTpk-VVFF

8/39
L6563 - L6563A Electrical characteristics

Table 5. Electrical characteristics (continued)

( -25°C < TJ < +125°C, VCC = 12V, Co = 1nF between pin GD and GND, CFF =1µF between pin VFF
and GND; unless otherwise specified)
Symbol Parameter Test condition Min Typ Max Unit

Zero current detector

VZCDH Upper clamp voltage IZCD = 2.5 mA 5.0 5.7 V

VZCDL Lower clamp voltage IZCD = - 2.5 mA -0.3 0 0.3 V
Arming voltage
VZCDA (4) 1.4 V
(positive-going edge)
Triggering voltage
VZCDT (4) 0.7 V
(negative-going edge)
IZCDb Input bias current VZCD = 1 to 4.5 V 1 µA
IZCDsrc Source current capability -2.5 mA
IZCDsnk Sink current capability 2.5 mA

Tracking boost function

Dropout voltage
∆V ITBO = 0.25 mA 20 mV
VVFF - VTBO

ITBO Linear operation 0 0.25 mA

IINV - ITBO current
ITBO = 25 µA to 0.25 mA -3.5 3.5 %
mismatch

VTBOclamp Clamp voltage VVFF = 4V (2) 2.9 3 3.1 V

PFC_OK

Vthl Latch-off threshold Voltage rising (2) 2.4 2.5 2.6 V

Vth Disable threshold Voltage falling (2) 0.2 V

VEN Enable threshold Voltage rising (2) 0.26 V

IPFC_OK Input bias current VPFC_OK = 0 to 2.5V -0.1 -1 µA

Vclamp Clamp voltage IPFC_OK = 1 mA 9 9.5 V

PWM_LATCH

Low level leakage

Ileak VPWM_LATCH=0 -1 µA
current
VH High level IPWM_LATCH = -0.5 mA 3.7 V

PWM_STOP

High level leakage

Ileak VPWM_STOP = 6V 1 µA
current
VL Low level IPWM_STOP = 0.5 mA 1 V
Vclamp Clamp voltage IPFC_OK = 2 mA 9 9.5 V

9/39
Electrical characteristics L6563 - L6563A

Table 5. Electrical characteristics (continued)

( -25°C < TJ < +125°C, VCC = 12V, Co = 1nF between pin GD and GND, CFF =1µF between pin VFF
and GND; unless otherwise specified)
Symbol Parameter Test condition Min Typ Max Unit

Run function

IRUN Input bias current VRUN = 0 to 3 V -1 µA

VDIS Disable threshold Voltage falling (2) 0.5 0.52 0.54 V

VEN Enable threshold Voltage rising (2) 0.56 0.6 0.64 V

Start timer

tSTART Start timer period 75 150 300 µs

Gate driver

IGDsource = 20 mA 2 2.6 V
VOHdrop Dropout voltage
IGDsource = 200 mA 2.5 3 V
VOLdrop IGDsink = 200 mA 1 2 V
tf Current fall time 30 70 ns
tr Current rise time 40 80 ns
VOclamp Output clamp voltage IGDsource = 5mA; Vcc = 20V 10 12 15 V

UVLO saturation Vcc=0 to VccOn, Isink=10mA 1.1 V

(1), (2) Parameters tracking each other

V MULT ⋅ ( V COMP – 2.5 )
(3) The multiplier output is given by: V CS = K M ⋅ ------------------------------------------------------------
2
-
V VFF
(4) Parameters guaranteed by design, functionality tested in production.

10/39
L6563 - L6563A Typical electrical performance

5 Typical electrical performance

Figure 4. Supply current vs supply voltage Figure 5. VCC Zener voltage vs TJ

Icc Vccz (pin 14)
(mA) (V) 28

10 27
5
26
1
0.5
25
0.1
0.05 24
Co = 1nF
0.01 f = 70 kHz
23
0.005 Tj = 25°C

0 22
0 5 10 15 20 25 -50 0 50 100 150
Vcc(V) Tj (°C)

Figure 6. IC consumption vs TJ Figure 7. Feedback reference vs TJ

Icc VREF (pin 1)
10
(mA) (V) 2.6
5 Operating
Quiescent Vcc = 12 V
2
2.55
1
Vcc = 12 V Disabled or
0.5 Co = 1 nF during OVP
2.5
f = 70 kHz
0.2 Latched off

0.1 2.45
0.05 Before start-up

0.02 2.4
-50 0 50 100 150 -50 0 50 100 150
Tj (°C) Tj (°C)

Figure 8. Start-up & UVLO vs TJ Figure 9. E/A output clamp levels vs TJ

VCOMP (pin 2)
12.5
VCC-ON 7
(V)
(V) 12
6 Upper clamp
11.5 Vcc = 12 V
5
11
4
10.5

10 3

VCC-OFF 9.5
2 Lower clamp
(V)
9 1
-50 0 50 100 150 -50 0 50 100 150
Tj (°C) Tj (°C)

11/39
Typical electrical performance L6563 - L6563A

Figure 10. Static OVP level vs TJ Figure 11. Vcs clamp vs TJ

VCOMP (pin 2) VCSx (pin 4)
2.5 (V) 1.5
(V)

2.4 Vcc = 12 V Vcc = 12 V

1.4 VCOMP = Upper clamp

2.3 1.3

2.2 1.2

2.1 1.1

2 1
-50 0 50 100 150 -50 0 50 100 150
Tj (°C) Tj (°C)

Figure 12. Dynamic OVP current vs TJ Figure 13. Current-sense offset vs

(normalized value) mains voltage phase angle
IOVP VCSoffset (pin 4)
120%
30
Vcc = 12 V (mV) Vcc = 12 V
Tj = 25 °
25
110%
VMULT = 0 to 3V
20 VFF = 3V

100% 15 VMULT = 0 to 0.7V

VFF = 0.7V

10
90%
5

80% 0
-50 0 50 100 150 0 0.628 1.256 1.884 2.512 3.14
Tj (°C) θ (°)

Figure 14. Delay-to-output vs TJ Figure 15. Ic latch-off level on current sense vs

TJ (L6563 only)
tD(H-L) Vpin4
300
(ns) 2.0
(V)
Vcc = 12 V Vcc = 12 V
250
1.8

200 1.6

150 1.4

100 1.2

50 1.0
-50 0 50 100 150 -50 0 50 100 150
Tj (°C) Tj (°C)

12/39
L6563 - L6563A Typical electrical performance

Figure 16. Multiplier characteristics @ VFF = 1V Figure 17. ZCD clamp levels vs TJ
VCS (pin 4) VCOMP (pin 2) VZCD (pin 11)
(V) (V) 7
upper voltage (V)
Vcc = 12 V Upper clamp
clamp 5.5 6
1 Tj = 25 °C
5.0
4.5 5 Vcc = 12 V
0.8 IZCD = ±2.5 mA
4
4.0
0.6 3

3.5 2
0.4
1
3.0
0.2 Lower clamp
0
2.6
0 -1
0 0.2 0.4 0.6 0.8 1 1.2 -50 0 50 100 150
VMULT (pin 3) (V) Tj (°C)

Figure 18. Multiplier characteristics @ VFF = 3V Figure 19. ZCD source capability vs TJ
V CS (pin 4) VCOMP (pin 2) I
ZCDsrc
(V)
upper voltage
(V) (mA) 0
Vcc = 12 V clamp Vcc = 12 V
0.5 Tj = 25 °C VZCD = lower clamp
5.5
-2
0.4 5.0

4.5
0.3 -4
4.0
0.2
3.5
-6
0.1 3.0

2.6
0 -8
0 0.5 1 1.5 2 2.5 3 3.5 -50 0 50 100 150
VMULT (pin 3) (V) Tj (°C)

Figure 20. Multiplier gain vs TJ Figure 21. VFF & TBO dropouts vs TJ
KM (mV) 6
1
Vcc = 12 V Vpin6 - Vpin5
0.8 VCOMP =4 V
VMULT = V FF =1V 4

0.6
Vcc = 12 V
2 Vpin3 = 2.9 V

0.4 Vpin5 - Vpin3

0
0.2

0 -2
-50 0 50 100 150 -50 0 50 100 150
Tj (°C) Tj (°C)

13/39
Typical electrical performance L6563 - L6563A

Figure 22. TBO current mismatch vs TJ Figure 23. RUN thresholds vs TJ

I(INV)-I(TBO) Vpin10
100·
I(INV) 1.0
-0.8 (V)
Vcc = 12 V
-1.0 0.8 Vcc = 12 V

-1.2
ON
-1.4 0.6
ITBO = 250 µA
-1.6 OFF
0.4
-1.8

-2.0 0.2
ITBO = 25 µA
-2.2
0.0
-2.4 -50 0 50 100 150
-50 0 50 100 150
Tj (°C) Tj (°C)

Figure 24. TBO-INV current mismatch vs Figure 25. PWM_LATCH high saturation vs TJ
TBO currents
I(INV)-I(TBO) Vpin8
100·
I(INV) 5.3
(V)
-1.6 Vcc = 12 V
5.2
-1.7 Vcc = 12 V
Tj = 25 °C 5.1
Isource = 50 µA
-1.8
5.0
-1.9 4.9

-2.0 4.8

-2.1 4.7

4.6 Isource = 500 µA

-2.2
4.5
-2.3 -50 0 50 100 150
0 100 200 300 400 500 600
I(TBO) Tj (°C)

Figure 26. TBO clamp vs TJ Figure 27. PWM_STOP low saturation vs TJ

Vpin6 Vpin9
5.0
0.50
3.5 (V)
(V)
Vcc = 12 V
0.40
4.0 Isink = 0.5 mA
3.25

3.0
0.30
3
2.0
0.20

Vcc = 12 V
2.75
Vpin3= 4 V 1.0
0.10

2.5 0
0.0
-50 0 50 100 150 -50 0 50 100 150
Tj (°C) Tj (°C)

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L6563 - L6563A Typical electrical performance

Figure 28. PFC_OK thresholds vs TJ Figure 29. UVLO saturation vs TJ

Vpin7 Vpin15
(V) 3.0 (V) 1.1
2.0 Latch-off Vcc = 0 V
Vcc = 12 V 1

1.0 0.9

0.5 0.8

0.3 0.7
ON
0.2
OFF 0.6

0.1 0.5
-50 0 50 100 150 -50 0 50 100 150
Tj (°C) Tj (°C)

Figure 30. Start-up timer vs TJ Figure 31. Gate-drive output low saturation
Tstart 150 Vpin15 (V)
(µs) 4
Vcc = 12 V
Tj = 25 °C
140 Vcc = 11 V
SINK
3
130

2
120

1
110

100 0
-50 0 50 100 150 0 200 400 600 800 1,000
Tj (°C) IGD(mA)

Figure 32. Gate-drive clamp vs TJ Figure 33. Gate-drive output high saturation
Vpin15clamp
(V) 12 Vpin15 (V)
-1.5
Tj = 25 °C
Vcc = 20 V
-2
Vcc - 2.0 Vcc = 11 V
SOURCE
11.5
Vcc --2.5
2.5

-3
Vcc - 3.0
11

Vcc --3.5
3.5

10.5 -4
Vcc - 4.0

-4.5
0 100 200 300 400 500 600 700
10
-50 0 50 100 150 IGD (mA)
Tj (°C)

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Application information L6563 - L6563A

6 Application information

6.1 Overvoltage protection

Normally, the voltage control loop keeps the output voltage VO of the PFC pre-regulator
close to its nominal value, set by the ratio of the resistors R1 and R2 of the output divider.
Neglecting the ripple components, under steady state conditions the current through R1
equals that through R2. Considering that the non-inverting input of the error amplifier is
internally biased at 2.5V, the voltage at pin INV will be 2.5V as well, then:

Equation 1

V O – 2.5
I R2 = I R1 = 2.5
-------- = ---------------------
-
R2 R1

If the output voltage experiences an abrupt change ∆Vo the voltage at pin INV is kept at 2.5V
by the local feedback of the error amplifier, a network connected between pins INV and
COMP that introduces a long time constant. Then the current through R2 remains equal to
2.5/R2 but that through R1 becomes:

Equation 2

V O – 2.5 + ∆V O
I' R1 = ---------------------------------------
-
R1

The difference current ∆IR1 = I’R1 - I’R1 = ∆VO/R1 will flow through the compensation network
and enter the error amplifier (pin COMP). This current is monitored inside the IC and when it
reaches about 18 µA the output voltage of the multiplier is forced to decrease, thus reducing
the energy drawn from the mains. If the current exceeds 20 µA, the OVP is triggered
(Dynamic OVP), and the external power transistor is switched off until the current falls
approximately below 5 µA. However, if the overvoltage persists (e.g. in case the load is
completely disconnected), the error amplifier will eventually saturate low hence triggering an
internal comparator (Static OVP) that will keep the external power switch turned off until the
output voltage comes back close to the regulated value. The output overvoltage that is able
to trigger the OVP function is then:

Equation 3
∆VO = R1 · 20 · 10-6

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L6563 - L6563A Application information

An important advantage of this technique is that the overvoltage level can be set
independently of the regulated output voltage: the latter depends on the ratio of R1 to R2,
the former on the individual value of R1. Another advantage is the precision: the tolerance of
the detection current is 15%, which means 15% tolerance on the ∆VO. Since it is usually
much smaller than Vo, the tolerance on the absolute value will be proportionally reduced.
Example: VO = 400V, ∆VO = 40V.
Then: R1 = 40V/20µA = 2MΩ ; R2 = 2.5·2MΩ·/(400-2.5) = 12.58kΩ.
The tolerance on the OVP level due to the L6563/A will be 40·0.15 = 6 V, that is ± 1.36%.
When either OVP is activated the quiescent consumption is reduced to minimize the
discharge of the Vcc capacitor.

Figure 34. Output voltage setting, OVP and FFP functions: internal block diagram

Vout

{ {
R3a R1a
0.26V + FAULT (not latched)
R3 R1
R3b R1b -
PFC_OK 7
+ FAULT (latched)
9.5V
-
2.25V Static OVP
+
INV 1 2.5V E/A
- -
9.5V Dynamic OVP
ITBO +
TBO
FUNCTION 20 µA L6563
2 L6563A
COMP
Frequency
Compensation
R4 R2

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Application information L6563 - L6563A

6.2 Feedback Failure Protection (FFP)

The OVP function above described is able to handle "normal" overvoltage conditions, i.e.
those resulting from an abrupt load/line change or occurring at start-up. It cannot handle the
overvoltage generated, for instance, when the upper resistor of the output divider (R1) fails
open: the voltage loop can no longer read the information on the output voltage and will
force the PFC pre-regulator to work at maximum ON-time, causing the output voltage to rise
with no control.
A pin of the device (PFC_OK) has been dedicated to provide an additional monitoring of the
output voltage with a separate resistor divider (R3 high, R4 low, see Figure 34). This divider
is selected so that the voltage at the pin reaches 2.5V if the output voltage exceeds a preset
value, usually larger than the maximum Vo that can be expected, also including worst-case
load/line transients.
Example: VO = 400 V, Vox = 475V. Select: R3 = 3MΩ;
then: R4 = 3MΩ ·2.5/(475-2.5) = 15.87kΩ.
When this function is triggered, the gate drive activity is immediately stopped, the device is
shut down, its quiescent consumption is reduced below 250 µA and the condition is latched
as long as the supply voltage of the IC is above the UVLO threshold. At the same time the
pin PWM_LATCH is asserted high. PWM_LATCH is an open source output able to deliver
3.7V min. with 0.5 mA load, intended for tripping a latched shutdown function of the PWM
controller IC in the cascaded DC-DC converter, so that the entire unit is latched off. To
restart the system it is necessary to recycle the input power, so that the Vcc voltages of both
the L6563/A and the PWM controller go below their respective UVLO thresholds.
The PFC_OK pin doubles its function as a not-latched IC disable: a voltage below 0.2V will
shut down the IC, reducing its consumption below 1 mA. In this case both PWM_STOP and
PWM_LATCH keep their high impedance status. To restart the IC simply let the voltage at
the pin go above 0.26 V.
Note that this function offers a complete protection against not only feedback loop failures or
erroneous settings, but also against a failure of the protection itself. Either resistor of the
PFC_OK divider failing short or open or a PFC_OK pin floating will result in shutting down
the IC and stopping the pre-regulator.

6.3 Voltage Feedforward

The power stage gain of PFC pre-regulators varies with the square of the RMS input
voltage. So does the crossover frequency fc of the overall open-loop gain because the gain
has a single pole characteristic. This leads to large trade-offs in the design.
For example, setting the gain of the error amplifier to get fc = 20 Hz @ 264 Vac means
having fc ≅ 4 Hz @ 88 Vac, resulting in a sluggish control dynamics. Additionally, the slow
control loop causes large transient current flow during rapid line or load changes that are
limited by the dynamics of the multiplier output. This limit is considered when selecting the
sense resistor to let the full load power pass under minimum line voltage conditions, with
some margin. But a fixed current limit allows excessive power input at high line, whereas a
fixed power limit requires the current limit to vary inversely with the line voltage.
Voltage Feedforward can compensate for the gain variation with the line voltage and allow
overcoming all of the above-mentioned issues. It consists of deriving a voltage proportional
to the input RMS voltage, feeding this voltage into a squarer/divider circuit (1/V2 corrector)
and providing the resulting signal to the multiplier that generates the current reference for
the inner current control loop (see Figure 35).

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L6563 - L6563A Application information

Figure 35. Voltage feedforward: squarer-divider (1/V2) block diagram and transfer
characteristic

Rectified mains Vcsx

E/A output
2
current (VCOMP)
reference
(Vcsx)
MULTIPLIER
R5 1.5 VCOMP=4V
"ideal" diode
Actual
- Ideal
2 3
1/V
+
1
MULT
9.5V
L6563 R6
L6563A 0.5
5
VFF
CFF
RFF 0
0 0.5 1 2 3 4
VFF=VMULT

In this way a change of the line voltage will cause an inversely proportional change of the
half sine amplitude at the output of the multiplier (if the line voltage doubles the amplitude of
the multiplier output will be halved and vice versa) so that the current reference is adapted to
the new operating conditions with (ideally) no need for invoking the slow dynamics of the
error amplifier. Additionally, the loop gain will be constant throughout the input voltage
range, which improves significantly dynamic behavior at low line and simplifies loop design.
Actually, deriving a voltage proportional to the RMS line voltage implies a form of integration,
which has its own time constant. If it is too small the voltage generated will be affected by a
considerable amount of ripple at twice the mains frequency that will cause distortion of the
current reference (resulting in high THD and poor PF); if it is too large there will be a
considerable delay in setting the right amount of feedforward, resulting in excessive
overshoot and undershoot of the pre-regulator's output voltage in response to large line
voltage changes. Clearly a trade-off is required.
The device realizes Voltage Feedforward with a technique that makes use of just two
external parts and that limits the feedforward time constant trade-off issue to only one
direction. A capacitor CFF and a resistor RFF , both connected from the VFF (pin 5) pin to
ground, complete an internal peak-holding circuit that provides a DC voltage equal to the
peak of the rectified sine wave applied on pin MULT (pin 3). RFF provides a means to
discharge CFF when the line voltage decreases (see Figure 35). In this way, in case of
sudden line voltage rise, CFF will be rapidly charged through the low impedance of the
internal diode and no appreciable overshoot will be visible at the pre-regulator's output; in
case of line voltage drop CFF will be discharged with the time constant RFF·CFF, which can
be in the hundred ms to achieve an acceptably low steady-state ripple and have low current
distortion; consequently the output voltage can experience a considerable undershoot, like
in systems with no feedforward compensation.

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Application information L6563 - L6563A

The twice-mains-frequency (2·fL) ripple appearing across CFF is triangular with a peak-to-
peak amplitude that, with good approximation, is given by:

Equation 4

2V MULTpk
∆V FF = ---------------------------------------
1 + 4f L R FF C FF

where fL is the line frequency. The amount of 3rd harmonic distortion introduced by this
ripple, related to the amplitude of its 2·fL component, will be:

Equation 5

100
D 3 % = ---------------------------------
2πf L R FF C FF

Figure 36 shows a diagram that helps choose the time constant RFF·CFF based on the
amount of maximum desired 3rd harmonic distortion. Always connect RFF and CFF to the
pin, the IC will not work properly if the pin is either left floating or connected directly to
ground.

Figure 36. RFF·CFF as a function of 3rd harmonic distortion introduced in the input
current

10

1
f L = 50 Hz
R FF· C FF [s]

0.1
f L= 60 Hz

0.01
0.1 1 10
D3 %

The dynamics of the voltage feedforward input is limited downwards at 0.5V (see Figure 35),
that is the output of the multiplier will not increase any more if the voltage on the VFF pin is
below 0.5V. This helps to prevent excessive power flow when the line voltage is lower than
the minimum specified value (brownout conditions).

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L6563 - L6563A Application information

6.4 THD optimizer circuit

The L6563/A is provided with a special circuit that reduces the conduction dead-angle
occurring to the AC input current near the zero-crossings of the line voltage (crossover
distortion). In this way the THD (Total Harmonic Distortion) of the current is considerably
reduced.
A major cause of this distortion is the inability of the system to transfer energy effectively
when the instantaneous line voltage is very low. This effect is magnified by the high-
frequency filter capacitor placed after the bridge rectifier, which retains some residual
voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input
current flow to temporarily stop.
To overcome this issue the device forces the PFC pre-regulator to process more energy
near the line voltage zero-crossings as compared to that commanded by the control loop.
This will result in both minimizing the time interval where energy transfer is lacking and fully
discharging the high-frequency filter capacitor after the bridge.
Figure 37 shows the internal block diagram of the THD optimizer circuit.

Figure 37. THD optimizer circuit

t t t

2
1/V
COMP
VFF

+ to PWM
MULTIPLIER
comparator
MULT +

t
OFFSET t

GENERATOR

@ Vac1
@ Vac2 > Vac1 t

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Application information L6563 - L6563A

Figure 38. THD optimization: standard TM PFC controller (left side) and L6563/A
(right side)

Input current Input current

Rectified mains voltage Rectified mains voltage

Imains
Input current Imains
Input current

MOSFET's drainVdrain
voltage MOSFET's drainVdrain
voltage

Essentially, the circuit artificially increases the ON-time of the power switch with a positive
offset added to the output of the multiplier in the proximity of the line voltage zero-crossings.
This offset is reduced as the instantaneous line voltage increases, so that it becomes
negligible as the line voltage moves toward the top of the sinusoid. Furthermore the offset is
modulated by the voltage on the VFF pin (see Section 6.3 on page 18 section) so as to have
little offset at low line, where energy transfer at zero crossings is typically quite good, and a
larger offset at high line where the energy transfer gets worse.
The effect of the circuit is shown in Figure 38, where the key waveforms of a standard TM
PFC controller are compared to those of this chip.
To take maximum benefit from the THD optimizer circuit, the high-frequency filter capacitor
after the bridge rectifier should be minimized, compatibly with EMI filtering needs. A large
capacitance, in fact, introduces a conduction dead-angle of the AC input current in itself -
even with an ideal energy transfer by the PFC pre-regulator - thus reducing the effectiveness
of the optimizer circuit.

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L6563 - L6563A Application information

6.5 Tracking Boost function

In some applications it may be advantageous to regulate the output voltage of the PFC pre-
regulator so that it tracks the RMS input voltage rather than at a fixed value like in
conventional boost pre-regulators. This is commonly referred to as "tracking boost" or
"follower boost" approach.
With this IC the function can be realized by connecting a resistor (RT) between the TBO pin
and ground. The TBO pin presents a DC level equal to the peak of the MULT pin voltage and
is then representative of the mains RMS voltage. The resistor defines a current, equal to
V(TBO)/RT, that is internally 1:1 mirrored and sunk from pin INV (pin 1) input of the error
amplifier. In this way, when the mains voltage increases the voltage at TBO pin will increase
as well and so will do the current flowing through the resistor connected between TBO and
GND. Then a larger current will be sunk by INV pin and the output voltage of the PFC pre-
regulator will be forced to get higher. Obviously, the output voltage will move in the opposite
direction if the input voltage decreases.
To avoid undesired output voltage rise should the mains voltage exceed the maximum
specified value, the voltage at the TBO pin is clamped at 3V. By properly selecting the
multiplier bias it is possible to set the maximum input voltage above which input-to-output
tracking ends and the output voltage becomes constant. If this function is not used, leave
the pin open: the device will regulate a fixed output voltage.
Starting from the following data:
● Vin1 = minimum specified input RMS voltage;
● Vin2 = maximum specified input RMS voltage;
● Vo1 = regulated output voltage @ Vin = Vin1;
● Vo2 = regulated output voltage @ Vin = Vin2;
● Vox = absolute maximum limit for the regulated output voltage;
● ∆Vo = OVP threshold,

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Application information L6563 - L6563A

to set the output voltage at the desired values use the following design procedure:
1. Determine the input RMS voltage Vinclamp that produces Vo = Vox:

Equation 6

Vox – Vo 1 Vox – Vo 2
Vin clamp = --------------------------- ⋅ Vin 2 – --------------------------- ⋅ Vin 1
Vo 2 – Vo 1 Vo 2 – Vo 1

and choose a value Vinx such that Vin2 = Vinx < Vinclamp. This will result in a limitation of the
output voltage range below Vox (it will equal Vox if one chooses Vinx = Vinclamp)
2. Determine the divider ratio of the MULT pin (pin 3) bias:

Equation 7

3
k = -----------------------
2 ⋅ Vin x

and check that at minimum mains voltage Vin1 the peak voltage on pin 3 is greater than
0.65V.
3. Determine R1, the upper resistor of the output divider:

Equation 8

∆Vo 6
R1 = ----------- ⋅ 10
20

4. Calculate the lower resistor R2 of the output divider and the adjustment resistor RT:

Equation 9
Vin 2 – Vin 1
R2 = 2.5 ⋅ R1 ⋅ --------------------------------------------------------------------------------------------------
( Vo 1 – 2.5 ) ⋅ Vin 2 – ( Vo 2 – 2.5 ) ⋅ Vin 1
Vin 2 – Vin 1
RT = 2 ⋅ k ⋅ R1 ⋅ ------------------------------
Vo 2 – Vo 1

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L6563 - L6563A Application information

5. Check that the maximum current sourced by the TBO pin (pin 6) does not exceed the
maximum specified (0.25mA):

Equation 10

3 –3
I TBOmax = ------- ≤ 0.25 ⋅ 10
RT

In the following Mathcad® sheet, as an example, the calculation is shown for the circuit
illustrated in Figure 40. Figure 41 shows the internal block diagram of the tracking boost
function.

Design data
Vin1 := 88V Vo1:= 200V
Vin2 := 264V Vo2:= 385V
Vox ;= 400V
∆Vo ;= 40V

Step 1

Vox – Vo 1 Vox – Vo 2
Vin clamp : = --------------------------- ⋅ Vin 2 – --------------------------- ⋅ Vin 1 Vinclamp = 278.27V
Vo 2 – Vo 1 Vo 2 – Vo 1

choose: Vinx: = 270V

Step 2

3
k: = ----------------------- k = 7.857 x 10-3
2 ⋅ Vin x

Step 3

∆Vo 6
R1: = ----------- ⋅ 10 R1 = 2 x 106 Ω
20

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Application information L6563 - L6563A

Step 4

Vin 2 – Vin 1
R2: = 2.5 ⋅ R1 ⋅ -------------------------------------------------------------------------------------------------- R2 = 4.762 x 104 Ω
( Vo 1 – 2.5 ) ⋅ Vin 2 – ( Vo 2 – 2.5 ) ⋅ Vin 1

Vin 2 – Vin 1
R T : = k ⋅ 2 ⋅ R1 ⋅ ------------------------------
RT = 2.114 x 104 Ω
Vo 2 – Vo 1

Step 5

3 3 ITBOmax = 0.142 mA
I TBOmax : = ------- ⋅ 10
RT

Vo(Vi): = V MULTpk ← k ⋅ 2 ⋅ Vi Vo(Vin1) = 200V

V TBO ← if ( V MULTpk < 3,V MULTpk ,3 ) Vo(Vin2) = 385V

2.5 ⋅ ⎛ 1 + R1
--------⎞ + V TBO ⋅ --------
R1
⎝ Vo(VinX) = 391.307V
R2⎠ RT

Figure 39. Output voltage vs. input voltage characteristic with TBO

400 Vo 2
Vin 2Vin x

350

Vo ( Vin ) 300

250

200
100 150 200 250 300
Vin

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L6563 - L6563A Application information

Figure 40. 80W, wide-range-mains PFC pre-regulator with tracking boost function active

D1 Vo=200 to 385 V
STTH1L06 NTC Po=80W

T
R8a R10a
C5
Supply Voltage R5 1 MΩ 3.3 MΩ
1 µF
10.3 to 22V 62 kΩ
R8b R10b
R1a R3 1 MΩ 3.3 MΩ
68 kΩ C6 100 nF
BRIDGE C1 3.3 MΩ
4 x 1N4007 0.22 µF
FUSE +
400V MOS
4A/250V R1b 8 9 11 2 1 R6
STP8NM50
3.3 MΩ 10 Ω
14 13 C6
- 3 L6563 56 µF
Vac 400V
(88V to 264V) 4
12 5 10 6 7

C3
R2 C2 C7
22m F C4 R10 R4 R7a,b
51.1 kΩ 2.2nF 10 nF R9 R11
25V 470 nF 390 kΩ 21 kΩ 0.68 Ω
47.5 kΩ 34.8 kΩ
1/4 W

Figure 41. Tracking boost and voltage feedforward blocks

Vout COMP Rectified mains

2 current
IR1 reference
R1
2.5V

INV 1 + MULTIPLIER
E/A 1/V 2 R5
-
9.5V
"ideal"
1:1 CURRENT -
ITBO diode 3
MIRROR +
IR2 R2 3V MULT
9.5V
L6563 R6
L6563A 6 5
TBO VFF
ITBO RT CFF
RFF

6.6 Inductor saturation detection (L6563 only)

Boost inductor's hard saturation may be a fatal event for a PFC pre-regulator: the current
upslope becomes so large (50-100 times steeper, see Figure 42) that during the current
sense propagation delay the current may reach abnormally high values. The voltage drop
caused by this abnormal current on the sense resistor reduces the gate-to-source voltage,
so that the MOSFET may work in the active region and dissipate a huge amount of power,
which leads to a catastrophic failure after few switching cycles.
However, in some applications such as ac-dc adapters, where the PFC pre-regulator is
turned off at light load for energy saving reasons, even a well-designed boost inductor may
occasionally slightly saturate when the PFC stage is restarted because of a larger load
demand. This happens when the restart occurs at an unfavorable line voltage phase, so that
the output voltage may drop significantly below the rectified peak voltage. As a result, in the

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Application information L6563 - L6563A

boost inductor the inrush current coming from the bridge rectifier adds up to the switched
current and, furthermore, there is little or no voltage available for demagnetization.
To cope with a saturated inductor, the L6563 is provided with a second comparator on the
current sense pin (CS, pin 4) that stops and latches off the IC if the voltage, normally limited
within 1.1V, exceeds 1.7V. Also the cascaded DC-DC converter can be stopped via the
PWM_LATCH pin that is asserted high. In this way the entire system is stopped and enabled
to restart only after recycling the input power, that is when the Vcc voltages of the L6563
and the PWM controller go below their respective UVLO thresholds. System safety will be
considerably increased.
To better suit the applications where a certain level of saturation of the boost inductor needs
to be tolerated, the L6563A does not support this protection function.

Figure 42. Effect of boost inductor saturation on the MOSFET current and detection method

6.7 Power management/housekeeping functions

A special feature of this IC is that it facilitates the implementation of the "housekeeping"
circuitry needed to coordinate the operation of the PFC stage to that of the cascaded DC-
DC converter. The functions realized by the housekeeping circuitry ensure that transient
conditions like power-up or power down sequencing or failures of either power stage be
properly handled.
This device provides some pins to do that. As already mentioned, one communication line
between the IC and the PWM controller of the cascaded DC-DC converter is the
PWM_LATCH pin, which is normally open when the PFC works properly and goes high if it
loses control of the output voltage (because of a failure of the control loop) or if the boost
inductor saturates, with the aim of latching off the PWM controller of the cascaded DC-DC
converter as well (Section 6.2: Feedback Failure Protection (FFP) on page 18 for more
details).
A second communication line can be established via the disable function included in the
PFC_OK pin (Section 6.2 on page 18 for more details ). Typically this line is used to allow
the PWM controller of the cascaded DC-DC converter to shut down the L6563/A in case of
light load, to minimize the no-load input consumption. Should the residual consumption of
the chip be an issue, it is also possible to cut down the supply voltage. Interface circuits like
those shown in Figure 43, where the L6563/A works along with the L5991, PWM controller
with standby function, can be used. Needless to say, this operation assumes that the
cascaded DC-DC converter stage works as the master and the PFC stage as the slave or, in
other words, that the DC-DC stage starts first, it powers both controllers and
enables/disables the operation of the PFC stage.

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L6563 - L6563A Application information

Figure 43. Interface circuits that let DC-DC converter’s controller IC disable the L6563/A at light
load

16 ST-BY 16 ST-BY
L6563 L6563
L5991/A L5991/A
7 14
4 Vref 4 Vref
PFC_OK Vcc
BC557 Supply_Bus
27 27
kΩ kΩ
100 nF 47 100 nF
BC557 kΩ BC557 100 nF
15
kΩ
100 150 100 150
kΩ BC547 kΩ
kΩ kΩ
BC547 BC547
150 150
kΩ kΩ

BC557
100 kΩ

VREF
10 kΩ L6563
Vcc 8.2 V Vcc 8 PFC_OK 7
L6563A
(RUN) (10)
16 14
2.2 kΩ 2.2 kΩ
L6668
L6563
L6668 14 PFC_STOP BC547
L6563A 14 PFC_STOP

14 PFC_STOP PFC_OK 7
(RUN) (10) L6563
L6599
L6563A

The third communication line is the PWM_STOP pin (pin 9), which works in conjunction with
the RUN pin (pin 10). The purpose of the PWM_STOP pin is to inhibit the PWM activity of
both the PFC stage and the cascaded DC-DC converter. The pin is an open collector,
normally open, that goes low if the device is disabled by a voltage lower than 0.52V on the
RUN pin. It is important to point out that this function works correctly in systems where the
PFC stage is the master and the cascaded DC-DC converter is the slave or, in other words,
where the PFC stage starts first, powers both controllers and enables/disables the operation
of the DC-DC stage.
This function is quite flexible and can be used in different ways. In systems comprising an
auxiliary converter and a main converter (e.g. desktop PC's silver box or hi-end LCD-TV),
where the auxiliary converter also powers the controllers of the main converter, the pin RUN
can be used to start and stop the main converter. In the simplest case, to enable/disable the
PWM controller the PWM_STOP pin can be connected to either the output of the error
amplifier (Figure 44 a) or, if the chip is provided with it, to its soft-start pin (Figure 44 b). The
use of the soft-start pin allows the designer to delay the start-up of the DC-DC stage with
respect to that of the PFC stage, which is often desired. An underlying assumption in order
for that to work properly is that the UVLO thresholds of the PWM controller are certainly
higher than those of the L6563/A.

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Application information L6563 - L6563A

Figure 44. Interface circuits that let the L6563/A switch on or off a PWM controller

If this is not the case or it is not possible to achieve a start-up delay long enough (because
this prevents the DC-DC stage from starting up correctly) or, simply, the PWM controller is
devoid of soft start, the arrangement of Figure 45 lets the DC-DC converter start-up when
the voltage generated by the PFC stage reaches a preset value. The technique relies on the
UVLO thresholds of the PWM controller.

Figure 45. Interface circuits for actual power-up sequencing (master PFC)

Another possible use of the RUN and PWM_STOP pins (again, in systems where the PFC
stage is the master) is brownout protection, thanks to the hysteresis provided.
Brownout protection is basically a not-latched device shutdown function that must be
activated when a condition of mains undervoltage is detected. This condition may cause
overheating of the primary power section due to an excess of RMS current. Brownout can
also cause the PFC pre-regulator to work open loop and this could be dangerous to the PFC
stage itself and the downstream converter, should the input voltage return abruptly to its
rated value. Another problem is the spurious restarts that may occur during converter power
down and that cause the output voltage of the converter not to decay to zero monotonically.
For these reasons it is usually preferable to shutdown the unit in case of brownout.

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L6563 - L6563A Application information

IC shutdown upon brownout can be easily realized as shown in Figure 46 The scheme on
the left is of general use, the one on the right can be used if the bias levels of the multiplier
and the RFF·CFF time constant are compatible with the specified brownout level and with the
specified holdup time respectively.
In Table 6 it is possible to find a summary of all of the above mentioned working conditions
that cause the device to stop operating.

Figure 46. Brownout protection (master PFC)

AC mains

L6563
L6563A
5 10
RUN VFF RUN
10
L6563
L6563A RFF CFF

6.8 Summary of L6563/A idle states

.
Table 6. Summary of L6563/A idle states
Caused or PWM_LATCH PWM_STOP Typical IC
Condition IC behavior
revealed by (pin 8) (pin 9) consumption
UVLO Vcc < 8.7 V Open Open 50 µA Auto-restart
Feedback PFC_OK > 2.5 V Active (high) Open 180 µA Latched
disconnected
Saturated Vcs > 1.7 V Active (high) Open 180 µA Latched
Boost Inductor (L6563 only) (L6563 only) (L6563 only) (L6563 only)
AC Brownout RUN < 0.52 V Open Active (low) 1.5 mA Auto-restart
Standby PFC_OK < 0.2 V Open Open 1.5 mA Auto-restart

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Application examples and ideas L6563 - L6563A

7 Application examples and ideas

Figure 47. Demo board (EVAL6563-80W) 80W, Wide-range, Tracking Boost: Electrical schematic

D1 NTC
Daux Vo=220 to 390 V
STTH2L06 2.5 Ω
1N4007 Po = 80 W

T
D3 R9A
C6
R3A R3B 1N4148 R2 1 MΩ
C8
1 µF R4
120 kΩ 120 kΩ 33 Ω 39 kΩ R12A
D2 15 nF R9B 1 MΩ
20 V 1 MΩ
TP1 R1
P1 C1 R11A 47 kΩ
+ 1W08G 0.47 µF 1 MΩ C12 220 nF
FUSE 400V R18
4A/250V 47 kΩ Q1
R11B 8 9 11 2 1 R12A
STP8NM50
1 MΩ 1 MΩ
14 13 C5
-
L6563 R6 56 µF
Vac 3 22 Ω 400 V
(88V to 264V) 7
12 6 5 10 4
C7
4.7 nF R15
C4 0Ω C11
100 nF TP2 C9 4.7 nF
470 nF
R10 R20
15.8 kΩ 47 kΩ R7A R7B R8
R14 R13
C2 37.4 kΩ
33 µF 22.1 kΩ
R17 C10 0.68 Ω 0.68 Ω 10.5 kΩ
390 kΩ N.A. 1/2 W 1/2 W
25V

Boost inductor spec:

E25x13x7 core, 3C85 ferrite or equivalent
1.6 mm gap for 0.43 mH primary inductance
Primary: 80 turns 20 x 0.1 mm
Secondary: 9 turns 0.1 mm

Figure 48. EVAL6563-80W: PCB and component layout (Top view, real size: 64 x 94 mm)

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L6563 - L6563A Application examples and ideas

Figure 49. EVAL6563-80W: PCB layout, soldering side (Top view)

Table 7. EVAL6563-80W: Evaluation results at full load

∆Vo
Vin (VAC) Pin (W) Vo (VDC) Po (W) η (%) PF THD (%)
(Vpk-pk)

90 85.3 219.4 16.6 79.64 93.4 0.999 3.7

115 84.9 244.1 15.0 80.80 95.2 0.998 4.3
135 83.7 263.7 13.9 80.16 95.8 0.997 4.8
180 83.5 307.6 14.5 80.28 96.1 0.993 6.0
230 85.2 356.7 13.0 81.33 95.5 0.984 7.7
265 85.0 390.6 12.1 80.85 95.1 0.974 9.5

Note: Measurements done with the line filter shown in Figure 51.

Table 8. EVAL6563-80W: Evaluation results at half load

∆Vo
Vin (VAC) Pin (W) Vo (VDC) Po (W) η (%) PF THD (%)
(Vpk-pk)

90 43.4 219.9 8.6 40.90 94.2 0.997 4.8

115 42.6 244.5 7.7 40.10 94.1 0.994 5.7
135 43.1 264.0 7.3 40.39 93.7 0.989 6.5
180 43.8 307.7 7.7 40.31 92.0 0.978 8.4
230 45.6 356.8 6.8 41.03 90.0 0.951 9.6
265 46.0 390.7 6.7 40.63 88.3 0.920 14.2

Note: Measurements done with the line filter shown in Figure 51.

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Application examples and ideas L6563 - L6563A

Figure 50. EVAL6563-80W: Vout vs. Vin relationship (tracking boost)

Figure 51. Line filter (not tested for EMI compliance) used for EVAL6563-80W
evaluation

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L6563 - L6563A Application examples and ideas

Figure 52. 250W, wide-range-mains PFC pre-regulator with fixed output voltage

D1 NTC1
L1 D2 2.5 Vout = 400V
1N5406 STTH5L06 Pout = 250 W

R9A
R4 1M
1M R11A
R3 R9B 1.87 M
Vcc 47 k R5 C4 1M
R1A 10.3 to 22 V 6.8 k 1 µF R11B
820 k 1.87 M

R1B
B1 C1 820 k 11 2 1 7
KBU8M + 1 µF 14
FUSE C2 D3 1N4148
400V
8A/250V 1 µF 6 C8
3 L6563 R6 33 150 µF
13 C6 450 V
Vac - 470 nF
88V 5 10 8 9 12 4 M1 630 V
to STP12NM50
R7
264V 390 k

C7
10 nF

R8A,B R10 R12

R2 C3 C5
0.22 12.7 k 20 k
10 k 10nF 470nF
1W

Boost Inductor (L1) Spec

ETD29x16x10 core, 3C85 ferrite or equivalent
1.5 mm gap for 150 µH primary inductance
Primary: 74 turns 20xAWG30 ( 0.3 mm)
Secondary: 8 turns 0.1 mm

Figure 53. 350W, wide-range-mains PFC pre-regulator with fixed output voltage and FOT control

D1 NTC1
D2 2.5 Vout = 400V
L1 1N5406 STTH806DTI Pout = 350W

R4 R13A
1M 1M
R15A
R13B 1.87 M
Vcc R5 C5 1M
R1A 10.3 to 22 V 6.8 k 1 µF
R15B
620 k 1.87 M

R1B
B1 C1 620 k 14 8 9 2 1 7
KBU8M + 1 µF D3 1N4148
FUSE C2
400V
8A/250V 1 µF 6 M1A C11
3 L6563 R9 6.8
STP12NM50 220 µF
13 C9 450 V
10 470 nF
Vac -
88V 5 11 12 4 D4 630 V
to 1N4148
R3 M1B
264V 390 k R6 R8 STP12NM50
1.5 k 1.5 k D5 R10 6.8
C10
1N4148 10 nF
TR1 C6 330 pF R11 330
BC557
R12A,B,C R14 R16
R2 C3 C4 R7 C7 12.7 k 20 k
10 k 470nF 12 k 560 pF C8 0.33
10nF
330 pF 1W

L1: core E42*21*15, B2 material

1.9 mm air gap on centre leg, main winding
inductance 0.55 mH
58 T of 20 x AWG32 ( 0.2 mm)

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Application examples and ideas L6563 - L6563A

Figure 54. Demagnetization sensing without auxiliary winding

RZCD CZCD

ZCD
Vinac Vout
9 Rload
L6563
L6563A

Figure 55. Enhanced turn-off for big MOSFET driving

Vcc

14

13 GD
DRIVER Q

BC327
L6563
L6563A 12 Rs

GND

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L6563 - L6563A Package mechanical data

8 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK®

packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com

Table 9. SO-14 Mechanical data

mm. inch
Dim.
Min Typ Max Min Typ Max
A 1.35 1.75 0.053 0.069

A1 0.10 0.30 0.004 0.012

A2 1.10 1.65 0.043 0.065
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.01
D (1) 8.55 8.75 0.337 0.344
E 3.80 4.0 0.150 0.157
e 1.27 0.050
H 5.8 6.20 0.228 0.244
h 0.25 0.50 0.01 0.02
L 0.40 1.27 0.016 0.050
k 0° (min.), 8° (max.)
ddd 0.10 0.004

Figure 56. Package dimensions

0016019D

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Revision history L6563 - L6563A

9 Revision history

Table 10. Revision history

Date Revision Changes
13-Nov-2004 1 First issue
24-Sep-2005 2 Changed the maturity from “Preliminary data” to “Datasheet”
Added new part number L6563A (Table 2)
17-Nov-2006 3 Updated the Section 4 on page 7 & Section 7 on page 32 the
document has been reformatted
Replaced block diagram, added Figure 37 on page 21 and minor
12-Mar-2007 4
editor changes.

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L6563 - L6563A

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