11/9/2017 Effect of Wire Length On the Slew: Static Timing Analysis (STA) Basic (Part-7a) |VLSI Concepts
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Effect of Wire Length On the Slew: Static Timing Analysis (STA) Basic 3Ps (Passion, Pati
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Static Timing analysis is divided into several parts:
Part1 -> Timing Paths
Part2 -> Time Borrowing
Part3a -> Basic Concept Of Setup and Hold
Part3b -> Basic Concept of Setup and Hold Violation
Part3c -> Practical Examples for Setup and Hold Time / Violation
Part4a -> Delay - Timing Path Delay
VLSI EXPERT (v
Part4b -> Delay - Interconnect Delay Models google.com/+Vlsi-e
Part4c -> Delay - Wire Load Model Bridging Gap Betw
Acdamia and Indu
Part5a -> Maximum Clock Frequency
Part5b -> Examples to calculate the “Maximum Clock Frequency” for different circuits. Follow
Part 6a -> How to solve Setup and Hold Violation (basic example) 303 followers
Part 6b -> Continue of How to solve Setup and Hold Violation (Advance examples)
Part 6c -> Continue of How to solve Setup and Hold Violation (more advance examples)
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Part 7a -> Methods for Increase/Decrease the Delay of Circuit (Effect of Wire Length On the Slew)
Part 7b -> Methods for Increase/Decrease the Delay of Circuit (Effect of Size of the Transistor On the Slew) 5,366,382
Part 7c -> Methods for Increase/Decrease the Delay of Circuit (Effect of Threshold voltage On the Slew)
Part 8 -> 10 ways to fix Setup and Hold Violation.
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11/9/2017 Effect of Wire Length On the Slew: Static Timing Analysis (STA) Basic (Part-7a) |VLSI Concepts
Till now we have discussed the Ideal scenario for few of the cases. Like No Clock-to-Q delay, No Net Delay. But now we will
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discuss about those parameter also.
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First understand/revise what are the different types or forms of Delay into a circuit.
In FFs: Comments
Clock to Q delay
Propagation delay of sequential flip flop
Time taken to charge and discharge the output load (capacitance) at Pin Q.
Rise time and Fall time delay
Combinational Circuit:
Cell delay
Delay contributed by Gate itself.
Edusaksham
Typically defined as 50% input pin voltage to 50% output voltage. VLSI - Self...
Usually a function of Both Output Loading and Input Transition time. INR 5,750.00
Can be divide into propagation delay and transition delay.
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Propagation delay is the time from input transition to completion of a specific % (e.g 10%) of the output
transition.
Propagation delay is function of output loading and input transition time.
Transition Delay is the time for an output pin to change the stage.
Transition delay is function of capacitance at the output pin and can also be a function of input
transition time.
Time taken to charge and discharge the output load (capacitance) of the Cell output.
Net Delay: Edusaksham
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RC delay.
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Now we will discuss different techniques to increase or decrease the delay in the design. We will also discuss the basics of different
techniques, which will help us to understand why we are using any particular technique. "Timing Paths" : Sta
Timing Analysis (ST
basic (Part 1)
Now we have to see what best we can do to remove these violations or as explained earlier – How can we increase or decrease the Basic of Timing
delay of the clock or data path in the design. If I will ask you, then might be you can tell me 10 ways to do so. But I don’t want to Analysis in Physical
explain in that way. Let’s start one by one with basics and then in the last I will brief all those points. Design
"Setup and Hold Tim
Let’s talk about the Transition delay first. There are 2 types of transition delays. Rise Delay and Fall delay. In terms of definition : Static Timing Analy
(STA) basic (Part 3a
Delay - "Wire Load
Model" : Static Timin
Analysis (STA) basic
Rise Time Delay (tr): The time required for a signal to transition from 10% of its maximum value to 90% of its (Part 4c)
maximum value.
Fall Time Delay (tf): The time required for a signal to transition from 90% of its maximum value to 10% of its "Setup and Hold Tim
Violation" : Static
maximum value. Timing Analysis (ST
basic (Part 3b)
"Examples Of Setup
Basically these times (rise time and fall time) are related to the Capacitance Charging and Discharging time. and Hold time" : Sta
So when capacitance is charging just because of any change in the input voltage then time taken by capacitance to reach from 10% Timing Analysis (ST
to 90% of maximum value is known as rise time. Since this time (rise time) is going to introduce the delay in the circuit in basic (Part 3c)
comparison to the Ideal scenario (Capacitance charging time is Zero – It can charge instantly), it’s known as Rise Time Delay also. Delay - "Interconnec
Similarly, during the discharging of the capacitance from 90% to 10% of its maximum value, it’s going to add one more delay – Delay Models" : Sta
known as Fall Time Delay. Timing Analysis (ST
basic (Part 4b)
Following figure is just an example of rise time and fall time.
Note: Transition time is also known as Slew. "Time Borrowing" :
Static Timing Analys
(STA) basic (Part 2)
5 Steps to Crack VL
Interview
10 Ways to fix SETU
and HOLD violation
Static Timing Analys
(STA) Basic (Part-8)
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Effect of Wire length on the Slew (transition time): "DIGITAL BASIC
Sequential Circuit
In the below figure you can observe, how the step waveform (consider this as ideal one) degrades from the start to the end of the A visitor from Sant
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wire (color coding can help you to understand) and this is resulting a considerable amount of delay for long wires. That means if Maria, California a
wire length is less, then degradation of waveform be less, means less effective delay and Vice-versa. We can conclude from this- from vlsi-expert.co
“If we want to increase the delay- we can increase the wire length and vice versa” viewed "Fixing Set
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I am sure you can cross question me that why this degradation is happing. Simple Ans is - you can model a wire into a series of
Resistance and Capacitance network. For more detail please refer following post Interconnect Delay Models.
Note: This delay is also known as Net delay/Wire Delay/Interconnect Delay.
In the next post we will discuss about the effect of Size of the Transistor on the "Transition Delay" and "Propagation Delay".
Examples: Solve Setup and Hold Violation (c) (Previous) Index Effect of Size of the Transistor On the Slew (Next)
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usps tracking October 30, 2017 at 8:13 AM
Yes, the article I was looking for. Your article gives me another approach on the subject. I hope to read more articles from you.
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