A B C D E

1 1

Compal Confidential 2

A4WAS MB Schematic Document

LA-C611P
3 3

Rev: 1.0
2015.07.17

4 4

DAX
Part Number Description

DAZ1DR00100 PCB A4W AS LA-C611P LS-C341P

Security Classification Compal Secret Data Compal Electronics, Inc.
A4WAS_PCB_REV10 2014/11/10 2016/11/10 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Friday, July 17, 2015 Sheet 1 of 60
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 A B C D E

VGA HDMI Conn. eDP

Fan Control
page 41

Interleaved Memory
page 32
page 29
Memory BUS 204pin DDR3L-SO-DIMM X1
BANK 0, 1, 2, 3 page 18
1
Dual Channel 1

DP to VGA HDMI
Realtek RTD2168 PS8407A eDP
Intel Skylake U 1.35V DDR3L 1333/1600
page 31 page 30 204pin DDR3L-SO-DIMM X1
BANK 4, 5, 6, 7 page 19
DDI1 DDI2
DP x 2 lanes HDMI x 4 lanes DDI
Skylake U
Skylake PCH-LP(MCP) USB 3.0 USB 2.0 CMOS
(SKL-U_2+2) conn x2 conn x1 Camera
USB port 1,2 USB/B (port 3) USB port 7
Nvidia N16x
with DDR3 x4
page 35 page 20~28 Processor
NGFF
WLAN PCIe 1.0 PCIe 3.0 x4
USB port 5 2.5GT/s 8GT/s Dual Core + GT2
2 2
port 6 port 1-4 Flexible IO
page 37 page 37 page 29

SATA3.0 SATA3.0 USBx8 48MHz

PCIe 1.0 6.0 Gb/s 6.0 Gb/s
2.5GT/s port 7 port 8
port 5 (SATA0) (SATA1) 3.3V 24MHz
HD Audio
Touch
SATA HDD SATA CDROM Screen
LAN(GbE)/ Card Reader 15W
Conn. Conn. HDA Codec I2C (PORT1)
Realtek 8411B 1356pin BGA USB port 6
page 33 ALC255
page 06~17 SPI page 40 page 29

Card Reader RJ45 conn. LPC/eSPI BUS

3
2 in 1 (SD) SPI ROM x2 3
page 36 page 36
CLK=24MHz Int. Speaker Int. MIC UAJ
page 8
on Sub/B
page 34
ENE page 40 page 40 page 37

page 34 KB9022 TPM

page 38 page 39

RTC CKT. Sub Board

page 14
LS-C341 Int.KBD Touch Pad
PS2 (from EC) / I2C (from SOC)
USB+Audio/B
Power On/Off CKT. page 37
page 39
page 39 page
39

4 DC/DC Interface CKT. 4

page 42

Security Classification Compal Secret Data Compal Electronics, Inc.

2014/11/10 2016/11/10 Title
Power Circuit DC/DC Issued Date Deciphered Date Block Diagrams
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
page 43~55 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 2 of 60

A B C D E
 A B C D E

Board ID Table for AD channel

Vcc 3.3V +/- 5% BOARD ID Table
Ra 100K +/- 5% Power State
Board ID SIGNAL
Board ID PCB Revision
Rb V BID min V BID typ V BID max EC AD3 STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock 0 0.1
0 0 0 V 0 V 0.300 V 0x00 - 0x0B
1 0.2
1 12K +/- 1% 0.347 V 0.345 V 0.360 V 0x0C - 0x1C S0 (Full ON) HIGH HIGH HIGH ON ON ON ON
2 0.3
2 15K +/- 1% 0.423 V 0.430 V 0.438 V 0x1D - 0x26 S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF 3 1.0
3 20K +/- 1% 0.541 V 0.550 V 0.559 V 0x27 - 0x30
1
S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
4 1

4 27K +/- 1% 0.691 V 0.702 V 0.713 V 0x31 - 0x3B

5
5 33K +/- 1% 0.807 V 0.819 V 0.831 V 0x3C - 0x46 S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF 6
6 43K +/- 1% 0.978 V 0.992 V 1.006 V 0x47 - 0x54
7
7 56K +/- 1% 1.169 V 1.185 V 1.200 V 0x55 - 0x64

BOM Structure Table

BOM Option Table BOM Option Table Voltage Rails
Power Plane Description S0 S3 S4/S5
Item BOM Structure Item BOM Structure Adapter power supply N/A N/A N/A
+19V_VIN
Unpop @ dGPU VGA@ +17.4V_BATT Battery power supply N/A N/A N/A
Connector CONN@ N16S-GT SGT@ +19VB AC or battery power rail for power circuit. N/A N/A N/A
EMC requirement EMC@ N16V-GM SKU VGM@ +VCC_CORE Processor IA Cores Power Rail ON OFF OFF
EMC requirement depop @EMC@ GPU CG6 / Non GC6 NGC6@ / GC6@ +VCC_GT Processor Graphics Power Rails ON OFF OFF
CODEC(ALC255) 255@ VRAM BOM Select X76@/X7601@ ~ +VCC_SA System Agent power rail ON OFF OFF
CODEC(ALC283) 283@ X7614@
+0.675VS_VTT DDR +0.675VS power rail for DDR terminator . ON OFF OFF
SPI ROM 8M*2 8M_DUAL@ Single/Dual Rank SR@/DR@ +1.0VALW_PRIM +1.0V Always power rail ON ON ON*1
SPI ROM 8M*1 8M_SINGLE@ Memory Door/
2 No Memory Door MDY@/ MDN@ +1.0V_VCCSTU Sustain voltage for processor in Standby modes ON ON OFF 2
UMA only UMA@ +VCCIO CPU IO power rail ON OFF OFF
TPM TPM@ DMIC*1 1DMIC@ +1.0VS_VCCSTG +1.0VALW_PRIM Gated version of VCCST ON OFF OFF
For Intel CMC CMC@ DMIC*2 2DMIC@ +1.35V_VDDQ DDRIIIL +1.35V Power Rail ON ON OFF
For ES Sampel Only ES@ For Acer IOAC IOAC@ +1.8VALW_PRIM +1.8V Always power rail ON ON ON*1
Keyboard backlight KB@ No Acer IOAC NIOAC@ +1.8VS System +1.8V power rail ON OFF OFF
LPC MODE for EC LPC@ CPU Code PreES:QH7Y@ +3VLP +19VB to +3VLP power rail for suspend power ON ON ON
ESPI MODE for EC ESPI@ ES:QHMF@, QHMG@ +3VALW System +3VALW always on power rail ON ON ON*1
BA Serial BA@ QS:QJFC@, QJ8N@, +3VS System +3V power rail ON OFF OFF
EA Serial HDD@ QJ8L@
+5VALW +5V Always power rail ON ON ON
MP:SR2EU@, +5VS System +5V power rail ON OFF OFF
SR2EY@, SR2EZ@
I2C Address Table +RTCVCC RTC Battery Power ON ON ON
+1.05VSDGPU +1.05VS power rail for GPU ON OFF OFF
Address(8bit)
BUS Device Address(7 bit) +1.5VSDGPU +1.5VS power rail for GPU ON OFF OFF
Write Read
+3VSDGPU_AON +3VS power rail for GPU(AON rails) ON OFF OFF
I2C_0 (+3VS) Reserved (Touch Panel) +3VSDGPU_MAIN +3VS power rail for GPU GC62.0 ON OFF OFF
I2C_1 (+3VS) TM-P2969-001 (TP) 0x2C +VGA_CORE Core power for descrete GPU ON OFF OFF
SB8787-1200 (TP-ELAN) 0x15
3
DIMM1 0xA0 3

SOC_SMBCLK +3VS DIMM2 0xA4

LIS3DHTR(G-Sensor) 0x30
SOC_SML1CLK +3VS N16S-GT (VGA) 0x9E
PCH-LP (SOC) 0x90 Note : ON*1 means power plane is ON only when WOL enable and RTC wake at BIOS setting, otherwise it is OFF.

BQ24780 (Charger IC) 0x12

EC_SMB_CK1 +3VLP
BATTERY PACK 0x16

4 4

Compal Secret Data

Security Classification
2014/11/10 2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Thursday, July 16, 2015 Sheet 3 of 60
A B C D E
 5 4 3 2 1

D D

C C

B B

A A

Compal Secret Data

Security Classification
2014/11/10 2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Map
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Thursday, July 16, 2015 Sheet 4 of 60
5 4 3 2 1
 A B C D E

PWR Sequence_SKL-U2+2_DDR3L_NON CS
+RTCVCC
tPCH01_Min : 9 ms
SOC_RTCRST#

+19VB

+3VLP
1 1

EC_ON
tPCH04_Min : 9 ms
+5VALW/+3VALW(+3VALW_DSW...)
tPCH34_Max : 20 ms
SPOK tPCH06_Min : 200 us (+3VALW stable (@95% of full value) to +1.0VALW_PRIM starting to ramp)

+1.8VALW_PRIM

+1.8VALW_PG

+VCCPRIM_CORE/+1.0VALW_PRIM
tPCH03_Min : 10 ms
EC_RSMRST#

ON/OFF

PBTN_OUT# tPCH43_Min : 95 ms
Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#
2 PM_SLP_S5# 2
tPCH18_Min : 90 us
ESPI_RST#

PM_SLP_S4#

SYSON

+1.0V_VCCSTU

+1.35V_VDDQ

PM_SLP_S3#

SUSP#
tCPU04 Min : 100 ns
+1.0VS_VCCSTG
tCPU10 Min : 1 ms
+VCCIO
3 3
+5VS/+3VS/+1.8VS/+1.5VS
tCPU00 Min : 1 ms
EC_VCCST_PG

VR_ON
tCPU19 Max : 100 ns
SM_PG_CTRL
tCPU18 Max : 35 us
+0.675VS_VTT
tCPU09 Min : 1 ms
+VCC_SA

VR_PWRGD
tCPU16 Min : 0 ns
PCH_PWROK (SYS_PWROK) tPLT05 Min : Platform dependent

H_CPUPWRGD

PLT_RST#
4 4

+VCC_CORE / +VCC_GT

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Sequence
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Thursday, July 16, 2015 Sheet 5 of 60
A B C D E
 A B C D E

UC1A SKL-U
Functional Strap Definitions Rev_0.53
E55 C47
31 SOC_DP1_N0 DDI1_TXN[0] EDP_TXN[0] EDP_TXN0 29
F55 C46
31 SOC_DP1_P0 DDI1_TXP[0] EDP_TXP[0] EDP_TXP0 29
#543016 PDG0.9 P.775 E58 D46
31 SOC_DP1_N1 DDI1_TXN[1] EDP_TXN[1] EDP_TXN1 29
F58 C45
31 SOC_DP1_P1 DDI1_TXP[1] EDP_TXP[1] EDP_TXP1 29
<DP to VGA> F53 A45 <eDP>
DDPB_CTRLDATA/ GPP_E19 (Internal Pull Down): G53 DDI1_TXN[2] EDP_TXN[2] B45
EDP_TXN2 29
DDPC_CTRLDATA/ GPP_E21 (Internal Pull Down): F56 DDI1_TXP[2] EDP_TXP[2] A47
EDP_TXP2 29
DDI1_TXN[3] EDP_TXN[3] EDP_TXN3 29
DDPD_CTRLDATA/ GPP_E23 (Internal Pull Down): G56
DDI1_TXP[3] EDP_TXP[3]
B47
EDP_TXP3 29
(Sampled:Rising edge of PCH_PWROK) C50 E45
30 SOC_DP2_N0 EDP_AUXN 29
Display Port B/C/D Detected D50 DDI2_TXN[0] DDI EDP EDP_AUXN F45 EDP_AUXP 29
30 SOC_DP2_P0 DDI2_TXP[0] EDP_AUXP
0 =Port is not detected. 30 SOC_DP2_N1
C52
DDI2_TXN[1]
1 D52 B52 1
1 =Port is detected. 30 SOC_DP2_P1 DDI2_TXP[1] EDP_DISP_UTIL
<HDMI> 30 SOC_DP2_N2
A50
DDI2_TXN[2] SOC_DP1_AUXN
B50 G50
30 SOC_DP2_P2 DDI2_TXP[2] DDI1_AUXN SOC_DP1_AUXP SOC_DP1_AUXN 31
D51 F50 DP Aux (Port B for VGA)
30 SOC_DP2_N3 DDI2_TXN[3] DDI1_AUXP SOC_DP1_AUXP 31
C51 E48
30 SOC_DP2_P3 DDI2_TXP[3] DDI2_AUXN +3VS
F48
+3VS DDI2_AUXP G46 RC212
COMPENSATION PU FOR eDP DISPLAY SIDEBANDS DDI3_AUXN F46 10K_0402_5%
+VCCIO L13 DDI3_AUXP EC_SCI# 1 @ 2
R4955 2 1 2.2K_0402_5% SOC_DP1_CTRL_DATA L12 GPP_E18/DDPB_CTRLCLK L9 SOC_DP1_HPD
GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 SOC_DP2_HPD SOC_DP1_HPD 31 From VGA Trans.
L7 SOC_DP2_HPD 30 EC_SCI# SOC internal PU
EDP_COMP SOC_DP2_CTRL_CLK GPP_E14/DDPC_HPD1 From HDMI
RC1 1 2 N7 L6
HDMI DDC (Port C) 30 SOC_DP2_CTRL_CLK SOC_DP2_CTRL_DATA GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 EC_SCI#
24.9_0402_1% N8 N9
30 SOC_DP2_CTRL_DATA GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 CPU_EDP_HPD EC_SCI# 38
L10 CPU_EDP_HPD 29
GPP_E17/EDP_HPD From eDP
#543016 PDG0.9 P.186 N11
N12 GPP_E22/DDPD_CTRLCLK R12
Trace width=20 mils,Spacing=25mil,Max length=100mils SPI touch RST follow CRB #544669 P.8 GPP_E23/DDPD_CTRLDATA EDP_BKLTEN
ENBKL
ENBKL 38
R11 SOC_BKL_PWM
EDP_COMP EDP_BKLTCTL SOC_ENVDD SOC_BKL_PWM 29
#543016 PDG0.9 P.753 E52 1 OF 20 U13
+1.0V_VCCST EDP_RCOMP EDP_VDDEN SOC_ENVDD 29
PH 1K to VCCST
CPU over 130 degree will output low force S0->S5 SKL-U_BGA1356
+1.0VS_VCCSTG @

1 2 H_THERMTRIP#

1
RC2 1K_0402_5% Reserved CATERR# for #545659 PCH EDS 0.7 P.108
RC3 sightings issue check UC1D SKL-U SCI capability is available on all GPIOs,
1K_0402_5% Rev_0.53 while NMI and SMI capability is available on
H_CATERR# D63
@ T166 H_PECI CATERR# selected GPIOs only.
38 H_PECI A54 Below are the PCH GPIOs that can be routed to

2
+3VS 1 2 H_PROCHOT#_R C65 PECI
38,45 H_PROCHOT# H_THERMTRIP# PROCHOT# JTAG generate SMI# or NMI:
RC4 499_0402_1% C63
A65 THERMTRIP# B61 CPU_XDP_TCK0 ‧ GPP_B14, GPP_B20, GPP_B23
RC157 1 2 100K_0402_5% TP_INT# SKTOCC# PROC_TCK D60 SOC_XDP_TDI ‧ GPP_C[23:22]
CPU MISC PROC_TDI ‧ GPP_D[4:0]
XDP_BPM#0 C55 A61 SOC_XDP_TDO
@ T160 XDP_BPM#1 BPM#[0] PROC_TDO SOC_XDP_TMS ‧ GPP_E[8:0], GPP_E[16:13]
@ T161 D55 C60
B54 BPM#[1] PROC_TMS B59 SOC_XDP_TRST#
2
R615 1 2 100K_0402_5% I2C_TS_INT# C56 BPM#[2] PROC_TRST# 2
+3VS BPM#[3] PCH_JTAG_TCK1
B56
I2C_TS_INT# A6 PCH_JTAG_TCK D59 SOC_XDP_TDI
SPI touch INT follow CRB 29 I2C_TS_INT# GPP_E3/CPU_GP0 PCH_JTAG_TDI
D22 A7 A56 SOC_XDP_TDO
CC52 @EMC@ RB751V-40_SOD323-2 1 2 TP_INT# BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDO C59 SOC_XDP_TMS
38,39 EC_TP_INT# GPP_B3/CPU_GP2 PCH_JTAG_TMS SOC_XDP_TRST#
.1U_0402_16V7K AY5 C61
2 1 H_PECI RC137 2 @ 1 0_0402_5% GPP_B4/CPU_GP3 PCH_TRST# A59 CPU_XDP_TCK0
2 1 49.9_0402_1% CPU_POPIRCOMP AT16 JTAGX
PDG0.9 P.771 RC5
PROC_POPIRCOMP
CC53 @EMC@ RC6 2 1 49.9_0402_1% PCH_OPIRCOMP AU16
PROC_POPIRCOMP/PCH_OPIRCOMP EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
.1U_0402_16V7K PD 50ohm RC7 2 1 49.9_0402_1%
2 1 H_PROCHOT#_R RC8 2 1 49.9_0402_1% EOPIO_RCOMP H65 OPCE_RCOMP
OPC_RCOMP
#544669 CRB RVP7 1.0
Reserved for ESD 2014/9/17 EDRAM_OPIO_RCOMP/EOPIO_RCOMP 4 OF 20
PD50ohm SKL-U_BGA1356
@

+1.0VS_VCCSTG

RC11 2 CMC@ 1 51_0402_5% SOC_XDP_TMS CMC@

RPC2

Place to CPU side

RC13 2 CMC@ 1 51_0402_5% SOC_XDP_TDI SOC_XDP_TMS
SOC_XDP_TDI
1
2
8
7
XDP_TMS
XDP_TDI XDP CONN
RC15 2 CMC@ 1 51_0402_5% SOC_XDP_TDO SOC_XDP_TRST# 3 6 XDP_TRST# +1.0VALW_PRIM +1.0V_XDP
SOC_XDP_TDO 4 5 XDP_TDO
RC17 2 CMC@ 1 51_0402_5% SOC_XDP_TDO
3 0_0804_8P4R_5% RC12 1 @ 2 0_0603_5% 3

APS CONN 17 XDP_ITP_PMODE

CFG3
XDP_ITP_PMODE
RC55
RC56
1 CMC@ 2 0_0402_5% XDP_PRSENT_CPU
1 CMC@ 2 0_0402_5% XDP_HOOK6 JPCMC1 CMC_DEBUG_36P
+1.0V_XDP +1.0V_XDP
+3VALW +3VALW_PRIM OBS DATA JTAG/RC/HOOKS

JAPS1 RC31 1 CMC@ 2 1K_0402_5% XDP_ITP_PMODE CFG0 1 22

17 CFG0 DATA_0 VCCOBS_AB
1 CFG1 3
1 17 CFG1 DATA_1
10,38,42 PM_SLP_S3# 2 CMC@ CFG2 5
2 XDP_PRSENT_CPU 17 CFG2 DATA_2
3 RC43 2 @ 1 0_0402_5% RPC15 CFG3 7
3 XDP_SPI_SI XDP_HOOK3 17 CFG3 DATA_3 XDP_TRST#
10 PM_SLP_S5# 4 8 XDP_SPI_SI 1 8 CFG4 9 28
4 XDP_PRSENT_PCH PCH_JTAG_TCK1 XDP_TCK1 17 CFG4 DATA_4 XDP_TRST* XDP_TDI
10,38,42 PM_SLP_S4# 5 RC46 2 @ 1 0_0402_5% 2 7 CFG5 11 29
5 CPU_XDP_TCK0 XDP_TCK0 17 CFG5 DATA_5 XDP_TDI XDP_TMS
10 PM_SLP_A# 6 3 6 CFG6 13 30
6 XDP_SPI_IO2 XDP_PRSENT_PCH 17 CFG6 DATA_6 XDP_TMS XDP_TCK0
7 8 XDP_SPI_IO2 4 5 CFG7 15 32
7 CPU_XDP_TCK0 17 CFG7 DATA_7 XDP_TCK0 XDP_TCK1
8 RC35 2 CMC@ 1 51_0402_1% 31
9 8 17 XDP_TCK1 35 XDP_TDO
10 SOC_RTCRST# 9
Place to CPU side PCH_JTAG_TCK1
0_0804_8P4R_5%
17 CFG17
CFG17
DATA_CLK_1P XDP_TDO
10 RC37 2 @ 1 51_0402_5% CFG16 21
PBTN_OUT#_R2 10 17 CFG16 DATA_CLK_1N XDP_PREQ#
11 33 XDP_PREQ# 12
12 11 CFG8 2 XDP_PREQ* 34 XDP_PRDY#
12 EC_RSMRST# XDP_HOOK0 17 CFG8 DATA_8 XDP_PRDY* XDP_PRDY# 12
10 SYS_RESET# 13 RC151 2 @ 1 1K_0402_5% CFG0 10,38 EC_RSMRST# RC23 1 CMC@ 2 1K_0402_5% CFG9 4
13 17 CFG9 DATA_9 XDP_HOOK0
14 CFG10 6 27
14 17 CFG10 DATA_10 HOOK_0 XDP_HOOK3
10,38 PM_SLP_S0# 15 CFG11 8 25
15 17 CFG11 DATA_11 HOOK_3 XDP_HOOK6
16 CFG12 10 26
16 17 CFG12 DATA_12 HOOK_6
17 Follow 544924_Skylake_EDS_Vol_1_Rev_0.93 CFG13 12
17 17 CFG13 DATA_13 XDP_PRSENT_PCH
18 CFG14 14 24
18 17 CFG14 DATA_14 XDP_PRSNT_PCH* XDP_PRSENT_CPU
19 CFG15 16 23
GND 17 CFG15 DATA_15 XDP_PRSNT_CPU*
20
GND +3VALW_PRIM CFG19 18 19
17 CFG19 DATA_CLK_2P GND
ACES_50506-01841-P01 CFG18 20 36
17 CFG18 DATA_CLK_2N <MT> GND
CONN@
RC9 1 CMC@ 2 1K_0402_5% XDP_SPI_SI
ACES_50506-01841-P01_18P-NPM
4 4

INTEL_CMC_PRIMARY
CONN@

Compal Secret Data

10,38 PBTN_OUT#
RC53 2 @ 1 0_0402_5% PBTN_OUT#_R2 Security Classification
2014/11/10 2016/11/10 Title
Compal Electronics, Inc.
RC54 2 @ 1 0_0402_5%
Issued Date Deciphered Date
38,39 ON/OFFBTN#
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
SKL-U(1/12)DDI,MSIC,XDP,EDP
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A4WAS M/B LA-C611P
Monday, June 22, 2015
Sheet 6 of 60
A B C D E
 A B C D E

Interleaved Memory

1 1

SKL-U
UC1B SKL-U UC1C
Rev_0.53 Rev_0.53
AU53 DDR_A_CLK#0
18 DDR_A_D[0..15] DDR_A_D0 DDR0_CKN[0] DDR_A_CLK0 DDR_A_CLK#0 18 19 DDR_B_D[0..15] DDR_B_D0 DDR_B_CLK#0
AL71 AT53 DDR_A_CLK0 18 AF65 AN45 DDR_B_CLK#0 19
DDR_A_D1 AL68 DDR0_DQ[0] DDR0_CKP[0] AU55 DDR_A_CLK#1 DDR_B_D1 AF64 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] AN46 DDR_B_CLK#1
DDR_A_D2 DDR0_DQ[1] DDR0_CKN[1] DDR_A_CLK1 DDR_A_CLK#1 18 DDR_B_D2 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] DDR_B_CLK0 DDR_B_CLK#1 19
AN68 AT55 DDR_A_CLK1 18 AK65 AP45 DDR_B_CLK0 19
DDR_A_D3 AN69 DDR0_DQ[2] DDR0_CKP[1] DDR_B_D3 AK64 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] AP46 DDR_B_CLK1
DDR_A_D4 DDR0_DQ[3] DDR_A_CKE0 DDR_B_D4 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDR_B_CLK1 19
AL70 BA56 DDR_A_CKE0 18 AF66
DDR_A_D5 AL69 DDR0_DQ[4] DDR0_CKE[0] BB56 DDR_A_CKE1 DDR_B_D5 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56 DDR_B_CKE0
DDR_A_D6 DDR0_DQ[5] DDR0_CKE[1] DDR_A_CKE1 18 DDR_B_D6 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] DDR_B_CKE1 DDR_B_CKE0 19
AN70 AW56 @ T14 AK67 AP55 DDR_B_CKE1 19
DDR_A_D7 AN71 DDR0_DQ[6] DDR0_CKE[2] AY56 DDR_B_D7 AK66 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] AN55
DDR_A_D8 DDR0_DQ[7] DDR0_CKE[3] @ T15 DDR_B_D8 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] @ T17
AR70 AF70 AP53 @ T18
DDR_A_D9 AR68 DDR0_DQ[8] AU45 DDR_A_CS#0 DDR_B_D9 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3]
DDR_A_D10 DDR0_DQ[9] DDR0_CS#[0] DDR_A_CS#1 DDR_A_CS#0 18 DDR_B_D10 DDR1_DQ[9]/DDR0_DQ[25] DDR_B_CS#0
AU71 AU43 DDR_A_CS#1 18 AH71 BB42 DDR_B_CS#0 19
DDR_A_D11 AU68 DDR0_DQ[10] DDR0_CS#[1] AT45 DDR_A_ODT0 DDR_B_D11 AH68 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] AY42 DDR_B_CS#1
DDR_A_D12 DDR0_DQ[11] DDR0_ODT[0] DDR_A_ODT1 DDR_A_ODT0 18 DDR_B_D12 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] DDR_B_ODT0 DDR_B_CS#1 19
AR71 AT43 DDR_A_ODT1 18 AF71 BA42 DDR_B_ODT0 19
DDR_A_D13 AR69 DDR0_DQ[12] DDR0_ODT[1] DDR_B_D13 AF69 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] AW42 DDR_B_ODT1
DDR_A_D14 DDR0_DQ[13] DDR_A_MA5 DDR_B_D14 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1] DDR_B_ODT1 19
AU70 BA51 DDR_A_MA5 18 AH70
DDR_A_D15 AU69 DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] BB54 DDR_A_MA9 DDR_B_D15 AH69 DDR1_DQ[14]/DDR0_DQ[30] AY48 DDR_B_MA5
18 DDR_A_D[16..31] DDR_A_D16 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR_A_MA6 DDR_A_MA9 18 19 DDR_B_D[16..31] DDR_B_D16 DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR_B_MA9 DDR_B_MA5 19
BB65 BA52 DDR_A_MA6 18 AT66 AP50 DDR_B_MA9 19
DDR_A_D17 AW65 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AY52 DDR_A_MA8 DDR_B_D17 AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48 DDR_B_MA6
DDR_A_D18 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR_A_MA7 DDR_A_MA8 18 DDR_B_D18 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR_B_MA8 DDR_B_MA6 19
AW63 AW52 DDR_A_MA7 18 AP65 BB48 DDR_B_MA8 19
DDR_A_D19 AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 DDR_A_BS2 DDR_B_D19 AN65 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AP48 DDR_B_MA7
DDR_A_D20 DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR_A_MA12 DDR_A_BS2 18 DDR_B_D20 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDR_B_BS2 DDR_B_MA7 19
BA65 AW54 DDR_A_MA12 18 AN66 AP52 DDR_B_BS2 19
DDR_A_D21 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54 DDR_A_MA11 DDR_B_D21 AP66 DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50 DDR_B_MA12
DDR_A_D22 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR_A_MA15 DDR_A_MA11 18 DDR_B_D22 DDR1_DQ[21]/DDR0_DQ[53] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR_B_MA11 DDR_B_MA12 19
BA63 BA55 DDR_A_MA15 18 AT65 AN48 DDR_B_MA11 19
DDR_A_D23 BB63 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 DDR_A_MA14 DDR_B_D23 AU65 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN53 DDR_B_MA15
DDR_A_D24 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR_A_MA14 18 DDR_B_D24 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR_B_MA14 DDR_B_MA15 19
BA61 AT61 AN52 DDR_B_MA14 19
2 DDR_A_D25 AW61 DDR0_DQ[24]/DDR0_DQ[40] AU46 DDR_A_MA13 DDR_B_D25 AU61 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] 2
DDR_A_D26 DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDR_A_CAS# DDR_A_MA13 18 DDR_B_D26 DDR1_DQ[25]/DDR0_DQ[57] DDR_B_MA13
BB59 AU48 DDR_A_CAS# 18 AP60 BA43 DDR_B_MA13 19
DDR_A_D27 AW59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT46 DDR_A_WE# DDR_B_D27 AN60 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AY43 DDR_B_CAS#
DDR_A_D28 DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDR_A_RAS# DDR_A_WE# 18 DDR_B_D28 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] DDR_B_WE# DDR_B_CAS# 19
BB61 AU50 DDR_A_RAS# 18 AN61 AY44 DDR_B_WE# 19
DDR_A_D29 AY61 DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AU52 DDR_A_BS0 DDR_B_D29 AP61 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] AW44 DDR_B_RAS#
DDR_A_D30 DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR_A_MA2 DDR_A_BS0 18 DDR_B_D30 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDR_B_BS0 DDR_B_RAS# 19
BA59 AY51 DDR_A_MA2 18 AT60 BB44 DDR_B_BS0 19
DDR_A_D31 AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AT48 DDR_A_BS1 DDR_B_D31 AU60 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AY47 DDR_B_MA2
18 DDR_A_D[32..47] DDR_A_D32 DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR_A_MA10 DDR_A_BS1 18 19 DDR_B_D[32..47] DDR_B_D32 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] DDR_B_BS1 DDR_B_MA2 19
AY39 AT50 DDR_A_MA10 18 AU40 BA44 DDR_B_BS1 19
DDR_A_D33 AW39 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] BB50 DDR_A_MA1 DDR_B_D33 AT40 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AW46 DDR_B_MA10
DDR_A_D34 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR_A_MA0 DDR_A_MA1 18 DDR_B_D34 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDR_B_MA1 DDR_B_MA10 19
AY37 AY50 DDR_A_MA0 18 AT37 AY46 DDR_B_MA1 19
DDR_A_D35 AW37 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] BA50 DDR_A_MA3 DDR_B_D35 AU37 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA46 DDR_B_MA0
DDR_A_D36 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] DDR_A_MA4 DDR_A_MA3 18 DDR_B_D36 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] DDR_B_MA3 DDR_B_MA0 19
BB39 BB52 DDR_A_MA4 18 AR40 BB46 DDR_B_MA3 19
DDR_A_D37 BA39 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] DDR_B_D37 AP40 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] BA47 DDR_B_MA4
DDR_A_D38 DDR0_DQ[37]/DDR1_DQ[5] DDR_A_DQS#0 DDR_B_D38 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4] DDR_B_MA4 19
BA37 AM70 DDR_A_DQS#0 18 AP37
DDR_A_D39 BB37 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] AM69 DDR_A_DQS0 DDR_B_D39 AR37 DDR1_DQ[38]/DDR1_DQ[22] AH66 DDR_B_DQS#0
DDR_A_D40 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] DDR_A_DQS#1 DDR_A_DQS0 18 DDR_B_D40 DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] DDR_B_DQS0 DDR_B_DQS#0 19
AY35 AT69 DDR_A_DQS#1 18 AT33 AH65 DDR_B_DQS0 19
DDR_A_D41 AW35 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] AT70 DDR_A_DQS1 DDR_B_D41 AU33 DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] AG69 DDR_B_DQS#1
DDR_A_D42 DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] DDR_A_DQS#2 DDR_A_DQS1 18 DDR_B_D42 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3] DDR_B_DQS1 DDR_B_DQS#1 19
AY33 BA64 DDR_A_DQS#2 18 AU30 AG70 DDR_B_DQS1 19
DDR_A_D43 AW33 DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDR_A_DQS2 DDR_B_D43 AT30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3] AR66 DDR_B_DQS#2
DDR_A_D44 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4] DDR_A_DQS#3 DDR_A_DQS2 18 DDR_B_D44 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6] DDR_B_DQS2 DDR_B_DQS#2 19
BB35 AY60 DDR_A_DQS#3 18 AR33 AR65 DDR_B_DQS2 19
DDR_A_D45 BA35 DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDR_A_DQS3 DDR_B_D45 AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[2]/DDR0_DQSP[6] AR61 DDR_B_DQS#3
DDR_A_D46 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] DDR_A_DQS#4 DDR_A_DQS3 18 DDR_B_D46 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[3]/DDR0_DQSN[7] DDR_B_DQS3 DDR_B_DQS#3 19
BA33 BA38 DDR_A_DQS#4 18 AR30 AR60 DDR_B_DQS3 19
DDR_A_D47 BB33 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 DDR_A_DQS4 DDR_B_D47 AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[3]/DDR0_DQSP[7] AT38 DDR_B_DQS#4
18 DDR_A_D[48..63] DDR_A_D48 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] DDR_A_DQS#5 DDR_A_DQS4 18 19 DDR_B_D[48..63] DDR_B_D48 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2] DDR_B_DQS4 DDR_B_DQS#4 19
AY31 AY34 DDR_A_DQS#5 18 AU27 AR38 DDR_B_DQS4 19
DDR_A_D49 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] BA34 DDR_A_DQS5 DDR_B_D49 AT27 DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] AT32 DDR_B_DQS#5
DDR_A_D50 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] DDR_A_DQS#6 DDR_A_DQS5 18 DDR_B_D50 DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3] DDR_B_DQS5 DDR_B_DQS#5 19
AY29 BA30 DDR_A_DQS#6 18 AT25 AR32 DDR_B_DQS5 19
DDR_A_D51 AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4] AY30 DDR_A_DQS6 DDR_B_D51 AU25 DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] AR25 DDR_B_DQS#6
DDR_A_D52 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] DDR_A_DQS#7 DDR_A_DQS6 18 DDR_B_D52 DDR1_DQ[51] DDR1_DQSN[6] DDR_B_DQS6 DDR_B_DQS#6 19
BB31 AY26 DDR_A_DQS#7 18 AP27 AR27 DDR_B_DQS6 19
DDR_A_D53 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 DDR_A_DQS7 DDR_B_D53 AN27 DDR1_DQ[52] DDR1_DQSP[6] AR22 DDR_B_DQS#7
DDR_A_D54 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5] DDR_A_DQS7 18 DDR_B_D54 DDR1_DQ[53] DDR1_DQSN[7] DDR_B_DQS7 DDR_B_DQS#7 19
BA29 AN25 AR21 DDR_B_DQS7 19
DDR_A_D55 BB29 DDR0_DQ[54]/DDR1_DQ[38] AW50 DDR_B_D55 AP25 DDR1_DQ[54] DDR1_DQSP[7]
DDR_A_D56 AY27 DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# AT52 DDR_B_D56 AT22 DDR1_DQ[55] AN43
DDR_A_D57 DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR @ T22 DDR_B_D57 DDR1_DQ[56] DDR1_ALERT#
AW27 AU22 AP43 @ T23
DDR_A_D58 AY25 DDR0_DQ[57]/DDR1_DQ[41] AY67 +0.675V_VREFCA Trace width/Spacing >= 20mils DDR_B_D58 AU21 DDR1_DQ[57] DDR1_PAR AT13 DDR_DRAMRST#
DDR_A_D59 DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA +0.675V_A_VREFDQ +0.675V_VREFCA Place componment near SODIMM DDR_B_D59 DDR1_DQ[58] DRAM_RESET# DDR_DRAMRST# 18,19
3 AW25 AY68 +0.675V_A_VREFDQ AT21 AR18 3
DDR_A_D60 BB27 DDR0_DQ[59]/DDR1_DQ[43] DDR CH - A
DDR0_VREF_DQ BA67 +0.675V_B_VREFDQ DDR_B_D60 AN22 DDR1_DQ[59] DDR_RCOMP[0] AT18
DDR_A_D61 DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ +0.675V_B_VREFDQ DDR_B_D61 DDR1_DQ[60] DDR_RCOMP[1] SM_RCOMP0
BA27 #543016 PDG0.9 P.163 RC place near SODIMM AP22 DDR CH - B AU18 RC38 1 2 121_0402_1%
DDR_A_D62 BA25 DDR0_DQ[61]/DDR1_DQ[45] AW67 DDR_PG_CTRL DDR_B_D62 AP21 DDR1_DQ[61] DDR_RCOMP[2] SM_RCOMP1 RC39 1 2 80.6_0402_1%
DDR_A_D63 BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL DDR_B_D63 AN21 DDR1_DQ[62] SM_RCOMP2 RC40 1 2 100_0402_1%
DDR0_DQ[63]/DDR1_DQ[47] 2 OF 20 DDR1_DQ[63] 3 OF 20
#543016 PDG0.9 P.117
SKL-U_BGA1356 SKL-U_BGA1356 W=12-15 Space= 20/25 L=500mil
@ @
Pre_ES Sample
UC1 DDR_VTT_CNTL to DDR
VTT supplied ramped +1.35V_VDDQ
<35uS
+3VS
MP Sample Add on 7/14
(tCPU18)
UC1 UC1 UC1

CPU_QH7Y_A2_1.6G .1U_0402_16V7K 2 1 CC57

1

QH7Y@
SA00008A400 UC7
1 5 RC10
NC VCC 220K_0402_5% CPU_ i3-6100U_D1_2.3G CPU_i5-6200U_D1_2.3G CPU_i7-6500U_D1_2.5G
DDR_PG_CTRL
ES Sample 2 SR2EU@ SR2EY@ SR2EZ@
2

A 4
Y SM_PG_CTRL 47 SA000092NB0 SA000092OB0 SA000092P90
UC1 UC1 3
GND
2

74AUP1G07GW_TSSOP5
RC16
@ 2M_0402_5%

CPU_QHMF_C0_2.3G CPU_QHMG_C0_1.6G +1.35V_VDDQ

1

QHMF@ QHMG@
SA00008M420 SA00008M320
2
G

4 4
3 1
QS Sample
S

UC1 UC1 UC1

Reserve for cost test. @ Q2009
MESS138W-G_SOT323-3

Compal Secret Data

CPU_ i3-6100U_D0_2.3G
QJFC@
CPU_i5-6200U_D0_2.3G
QJ8N@
CPU_i7-6500U_D0_2.5G
QJ8L@
Security Classification
2014/11/10 2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
SA000092N30 SA000092O30 SA000092P20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(2/12)DDRIII
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, July 14, 2015 Sheet 7 of 60
A B C D E
 A B C D E

6 XDP_SPI_SI RC44 1 CMC@ 2 1K_0402_1% SOC_SPI_SI

SKL-U
6 XDP_SPI_IO2 RC21 1 CMC@ 2 1K_0402_1% SOC_SPI_IO2 UC1E
Rev_0.53
SPI - FLASH
RC21/44 place to within 1100 mil of SPIO_MOSI/SPI0_IO2 pin for XDP SMBUS, SMLINK
SOC_SPI_CLK AV2
SOC_SPI_SO AW3 SPI0_CLK R7 SOC_SMBCLK_1
SOC_SPI_SI AV3 SPI0_MISO GPP_C0/SMBCLK R8 SOC_SMBDATA_1 SMB
SOC_SPI_IO2 AW2 SPI0_MOSI GPP_C1/SMBDATA R10 SOC_SMBALERT# (Link to XDP, DDR)
SPI ROM SOC_SPI_IO3 AU4 SPI0_IO2 GPP_C2/SMBALERT# @ T239
SOC_SPI_CS#0 AU3 SPI0_IO3 R9 SOC_SML0CLK +3VALW _PRIM
SOC_SPI_CS#1 AU2 SPI0_CS0# GPP_C3/SML0CLK W2 SOC_SML0DATA
1 AU1 SPI0_CS1#
SPI0_CS2#
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
W1 SOC_SML0ALERT# 4.7K_0402_5% 2 ESPI@ 1 RC202 Strap Pin 1

W3 SOC_SML1CLK
SPI - TOUCH GPP_C6/SML1CLK V3 SOC_SML1DATA SOC_SML1CLK 20,31,38 SML1
GPP_C7/SML1DATA SOC_SML1ALERT# SOC_SML1DATA 20,31,38
M2 AM7 (Link to EC,DGPU)
GPP_D1/SPI1_CLK GPP_B23/SML1ALERT#/PCHHOT# @ T234
M3
J4 GPP_D2/SPI1_MISO
V1 GPP_D3/SPI1_MOSI
SPI Touch V2 GPP_D21/SPI1_IO2
M1 GPP_D22/SPI1_IO3 ESPI / LPC Bus
LPC
GPP_D0/SPI1_CS# LPC_AD0
GPP_A1/LAD0/ESPI_IO0
AY13 RC144 1 @ 2 0_0402_5%
LPC_AD0_R 38,39 ESPI : +1.8V
BA13 LPC_AD1 RC145 1 @ 2 0_0402_5%
C LINK GPP_A2/LAD1/ESPI_IO1 LPC_AD2 LPC_AD1_R 38,39 LPC : +3.3V
BB13 RC146 1 @ 2 0_0402_5%
GPP_A3/LAD2/ESPI_IO2 LPC_AD3 LPC_AD2_R 38,39
G3 AY12 RC147 1 @ 2 0_0402_5%
CL_CLK GPP_A4/LAD3/ESPI_IO3 LPC_FRAME# LPC_AD3_R 38,39
G2 BA12
LPC_FRAME# 38,39
Change RC144~RC147, RC45 to
G1 CL_DATA GPP_A5/LFRAME#/ESPI_CS# BA11 ESPI_RST#
CL_RST# GPP_A14/SUS_STAT#/ESPI_RESET# ESPI_RST# 38 15ohm when use ESPI

EC_KBRST#_R AW13 AW9 ESPI_CLK RC45 2 LPC@ 1 22_0402_5%

38 EC_KBRST#_R GPP_A0/RCIN# GPP_A9/CLKOUT_LPC0/ESPI_CLK CK_LPC_TPM_R R395 2 TPM@ 1 22_0402_5% ESPI_CLK_R 38 To EC
AY9
TPM_SERIRQ GPP_A10/CLKOUT_LPC1 PM_CLKRUN# CK_LPC_TPM 39
38,39 TPM_SERIRQ AY11 AW11
To TPM GPP_A6/SERIRQ GPP_A8/CLKRUN# PM_CLKRUN# 39
5 OF 20 For TPM
LPC Mode
SKL-U_BGA1356
@
+3VALW _PRIM
+1.8VS_3VS_PGPPA
SOC_SML0CLK RC49 1 2 499_0402_1%
PM_CLKRUN# 1 2 SOC_SML0DATA RC50 1 2 499_0402_1%
2 2
RC107 10K_0402_5% +3VS
RPC7
TPM_SERIRQ 1 2 SOC_SMBCLK_1 1 8 SOC_SMBCLK RC222 1 2 2.2K_0402_5%
RC112 10K_0402_5% SOC_SMBDATA_1 2 7 SOC_SMBDATA RC223 1 2 2.2K_0402_5%
SOC_SML1CLK 3 6
SOC_SML1DATA 4 5

2.2K_0804_8P4R_5%

+3VS

5
2015MOW06 no need PU1K on SPI_IO2/IO3 Q2017B
DMN66D0LDW -7_SOT363-6
RPC5 RC52 UC2 +3VALW _SPI SOC_SMBCLK_1 3 4 SOC_SMBCLK
SOC_SMBCLK 18,19,41

SOC_SPI_IO2 RC47 1 @ 2 1K_0402_1%

SOC_SMBDATA_1 6 1 SOC_SMBDATA
SOC_SMBDATA 18,19,41
33_0804_8P4R_5% 33_0402_5% W 25Q64FVSSIQ_SO8
8M_DUAL@ 8M_DUAL@ 8M_DUAL@ Q2017A
SD309330A80 SD028330A80 SA000039A30 SOC_SPI_IO3 RC48 1 @ 2 1K_0402_1% DMN66D0LDW -7_SOT363-6

2
+3VS
RC51 1 ES@ 2 1K_0402_1%

MOW36 add PD 1K depop PH 1K

only for SKL U ES sample
3 3
Single SPI ROM_CS0#
RPC5 and RC52 are close UC2
RPC5 RPC23 and RC59 are close UC9
SOC_SPI_IO3_0_R 1 8 SOC_SPI_IO3
SOC_SPI_SI_0_R 2 7 SOC_SPI_SI Dual SPI ROM_CS1# RPC23
SOC_SPI_CLK_0_R 3 6 SOC_SPI_CLK SOC_SPI_IO3_1_R 1 8 SOC_SPI_IO3
To SPI ROM SOC_SPI_SO_0_R 4 5 SOC_SPI_SO SOC_SPI_CLK_1_R 2 7 SOC_SPI_CLK
SOC_SPI_SI_1_R 3 6 SOC_SPI_SI
15_0804_8P4R_5% SOC_SPI_SO_1_R 4 5 SOC_SPI_SO
8M_SINGLE@ To SPI ROM
33_0804_8P4R_5%
SOC_SPI_IO2_0_R 1 2 SOC_SPI_IO2 8M_DUAL@
RC52 15_0402_5%
8M_SINGLE@ 8M_DUAL@
SOC_SPI_IO2_1_R 2 1 SOC_SPI_IO2
RC59 33_0402_5%
+3VALW _SPI CC8
SPI ROM ( 8MByte ) .1U_0402_16V7K
UC2 1 2
SOC_SPI_CS#0 1 8
SPI ROM ( 2/4/8/16MByte ) +3VALW _SPI CC101
SOC_SPI_SO_0_R 2 /CS VCC 7 SOC_SPI_IO3_0_R .1U_0402_16V7K
SOC_SPI_IO2_0_R 3 DO(IO1) /HOLD(IO3) 6 SOC_SPI_CLK_0_R UC9 1 2 8M_DUAL@
4 /WP(IO2) CLK 5 SOC_SPI_SI_0_R SOC_SPI_CS#1 1 8
GND DI(IO0) SOC_SPI_SO_1_R 2 /CS VCC 7 SOC_SPI_IO3_1_R
W 25Q64FVSSIQ_SO8 SOC_SPI_IO2_1_R 3 DO(IO1) /HOLD(IO3) 6 SOC_SPI_CLK_1_R
8M_SINGLE@ 4 /WP(IO2) CLK 5 SOC_SPI_SI_1_R
GND DI(IO0)
+3VALW _SPI W 25Q16DVSSIQ_SO8
ROM Socket 8M_DUAL@
4 4
JC1 RC26
SOC_SPI_CS#0 1 8 SOC_SPI_CLK_1_R 1 @EMC@2 0_0402_5% 1 2
SOC_SPI_IO2_0_R 3 CS# VCC 6 SOC_SPI_CLK_0_R CC70 @EMC@
SOC_SPI_IO3_0_R 7 WP# SCLK 5 SOC_SPI_SI_0_R 10P_0402_50V8J
4 HOLD# SI/SIO0 2 SOC_SPI_SO_0_R
GND SO/SIO1
ACES_91960-0084N_MX25L3206EM2I
Security Classification Compal Secret Data Compal Electronics, Inc.
CONN@ RC24 2014/11/10 2016/11/10 Title
SOC_SPI_CLK_0_R 1 @EMC@2 0_0402_5% 1 2
Issued Date Deciphered Date
CC9
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(3/12)SPI,ESPI,SMB,LPC
10P_0402_50V8J AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
@EMC@ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 8 of 60
A B C D E
 A B C D E

#545659 SKL_PCH_EDS_R0.7 P.84

UC1G SKL-U
Rev_0.53
AUDIO
#543016 PDG0.9 P.321
HDA_SYNC BA22 Terminating Unused SDIO/SDXC Signals
HDA_BIT_CLK AY22 HDA_SYNC/I2S0_SFRM
HDA_SDOUT HDA_BLK/I2S0_SCLK SDIO signals are multiplexed with GPIOs and
BB22 SDIO/SDXC default to GPIO functionality (as input). If
HDA_SDIN0 BA21 HDA_SDO/I2S0_TXD
AY21 HDA_SDI0/I2S0_RXD AB11
SDIO interface is not used, the signals
HDA_RST# AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13
can be used as GPIOs instead. If the GPIO
1 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 functionality is also not used, the signals can 1
J5 AB12
AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12 be left as no-connect.
AW20 I2S1_SFRM GPP_G3/SD_DATA2 W11
Functional Strap Definitions I2S1_TXD GPP_G4/SD_DATA3
GPP_G5/SD_CD#
W10
AK7 W8
AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W7
AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
AK10 GPP_F2/I2S2_TXD BA9
SPKR / GPP_B14 (Internal Pull Down): GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9
(Sampled:Rising edge of PCH_PWROK) GPP_A16/SD_1P8_SEL
PCH_DMIC_CLK H5 AB7 SD_RCOMP RC76 2 1 200_0402_1%
40 PCH_DMIC_CLK PCH_DMIC_DATA GPP_D19/DMIC_CLK0 SD_RCOMP
TOP Swap Override 40 PCH_DMIC_DATA D7
GPP_D20/DMIC_DATA0
0 = Disable TOP Swap mode.---> AAX05 Use D8 AF13
1 = Enable TOP Swap Mode. C8 GPP_D17/DMIC_CLK1 GPP_F23
GPP_D18/DMIC_DATA1

40 SPKR SPKR AW5

GPP_B14/SPKR
7 OF 20

SKL-U_BGA1356
@

HDA for AUDIO

2 RPC9 2
1 8 HDA_SYNC
40 HDA_SYNC_R HDA_SDOUT
40 HDA_SDOUT_R 2 7
3 6 HDA_BIT_CLK
40 HDA_BIT_CLK_R HDA_RST#
40 HDA_RST#_R 4 5

33_0804_8P4R_5%

1 @ 2 HDA_SDOUT
38 ME_EN
RC77 0_0402_5%
HDA_SDIN0
40 HDA_SDIN0

SKL_ULT
UC1I
Rev_0.53
CSI-2

A36 C37 +3VALW _1.8VALW _PGPPD

B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
CSI2_DN1 CSI2_CLKN1

1
D38 D32
C36 CSI2_DP1 CSI2_CLKP1 C29 RC133
D36 CSI2_DN2 CSI2_CLKN2 D29 UMA@
CSI2_DP2 CSI2_CLKP2 10K_0402_5%
A38 B26
B38 CSI2_DN3 CSI2_CLKN3 A26

2
CSI2_DP3 CSI2_CLKP3
3 C31 E13 CSI2_COMP RC80 2 1 100_0402_1% DGPU_PRSNT#
3
D31 CSI2_DN4 CSI2_COMP B7 DGPU_PRSNT#
C33 CSI2_DP4 GPP_D4/FLASHTRIG
D33 CSI2_DN5
CSI2_DP5

1
EMMC
A31
B31 CSI2_DN6 AP2 RC134
A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1 VGA@
CSI2_DN7 GPP_F14/EMMC_DATA1 10K_0402_5%
B33 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3

2
A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7 GPIO67
B27 CSI2_DN10 AM2
CSI2_DP10 GPP_F21/EMMC_RCLK DGPU_PRSNT#
C27 AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD DIS,Optimus 0
9 OF 20 AT1 EMMC_RCOMP 2 1
EMMC_RCOMP RC89 200_0402_1%
UMA 1
SKL-U_BGA1356
@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(4/12)HDA,EMMC,SDIO,CSI2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 9 of 60
A B C D E
 A B C D E

UC1J SKL_ULT
+RTCVCC Rev_0.53
CLOCK SIGNALS

RC91 1 2 20K_0402_5% SOC_SRTCRST# CLK_PCIE_N0 D42

20 CLK_PCIE_N0 CLK_PCIE_P0 CLKOUT_PCIE_N0
DGPU 20 CLK_PCIE_P0
C42
CLKREQ_PCIE#0 AR10 CLKOUT_PCIE_P0
CC10 1 2 1U_0402_6.3V6K
GPP_B5/SRCCLKREQ0#
PH at DGPU side
CLK_PCIE_N1 B42
33 CLK_PCIE_N1 CLK_PCIE_P1 CLKOUT_PCIE_N1 CLK_CPU_ITP#
GLAN 33 CLK_PCIE_P1 CLKREQ_PCIE#1
A42
CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N
F43
CLK_CPU_ITP
T164 @
33 CLKREQ_PCIE#1 AT7
GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P
E43 T165 @ Follow 2014MOW48
RC93 1 2 20K_0402_5% SOC_RTCRST# Skylake U PU 2.7k ohm to 1V
CLK_PCIE_N2 D41 BA17 SUSCLK
1 35 CLK_PCIE_N2 CLK_PCIE_P2 CLKOUT_PCIE_N2 GPD8/SUSCLK T3807@ Cannonlake U PD 60.4 ohm 1
CC11 1 2 1U_0402_6.3V6K NGFF WL+BT(KEY E) 35 CLK_PCIE_P2 CLKREQ_PCIE#2
C41
CLKOUT_PCIE_P2 SOC_XTAL24_IN
35 CLKREQ_PCIE#2 AT8
GPP_B7/SRCCLKREQ2# XTAL24_IN
E37 XCLK_BIASREF
JCMOS1 1 @ 2 0_0603_5% CLR CMOS E35 SOC_XTAL24_OUT T:50ohm S:12/15 L:1000 Via:2
D40 XTAL24_OUT
CLKOUT_PCIE_N3 XCLK_BIASREF
Place at RAM DOOR CLKREQ_PCIE#3
C40
CLKOUT_PCIE_P3 XCLK_BIASREF
E42 RC96 1 2 2.7K_0402_1% +1.0VALW _CLK5_F24NS
AT10 1 @ 2
GPP_B8/SRCCLKREQ3# AM18 SOC_RTCX1 RC136 60.4_0402_1%
B40 RTCX1 AM20 SOC_RTCX2
RC94 1 2 1M_0402_5% SM_INTRUDER# A40 CLKOUT_PCIE_N4 RTCX2
CLKREQ_PCIE#4 AU8 CLKOUT_PCIE_P4 AN18 SOC_SRTCRST#
GPP_B9/SRCCLKREQ4# SRTCRST# AM16 SOC_RTCRST#
+3VS RTCRST# SOC_RTCRST# 6
E40
E38 CLKOUT_PCIE_N5
CLKREQ_PCIE#5 AU7 CLKOUT_PCIE_P5
1 2 CLKREQ_PCIE#4 GPP_B10/SRCCLKREQ5#
RC165 10K_0402_5%
1 2 CLKREQ_PCIE#5 10 OF 20
RC105 10K_0402_5% 2014MOW48:
SKL-U_BGA1356 Skylake U use 24M 50 ohm ESR
@ Cannonlake U use 38.4M 30 ohm ESR
1 2 CLKREQ_PCIE#1
RC121 10K_0402_5% +3VS
1 2 CLKREQ_PCIE#2 SOC_XTAL24_IN
RC123 10K_0402_5%
20,42,54,55 DGPU_PW ROK PCH PLTRST Buffer

1
1 2 CLKREQ_PCIE#3 +3VS
RC124 10K_0402_5% R115
VGA@ 10K_0402_5% SOC_XTAL24_OUT 1 2

5
G
L2N7002LT1G_SOT23-3 Q2 RC92 1M_0402_5%
Pull high @ VGA side PLT_RST# 2

P
2 2

2
3 1 CLKREQ_PCIE#0 B 4 PLT_RST_BUF#
+3VALW _PRIM 20 PEG_CLKREQ# Y PLT_RST_BUF# 33,35
1 YC1

D
A

G
1

1
24MHZ_12PF_7V24000020
+3VALW _DSW RPC11
R107 R112 UC3 R157

3
8 1 PCH_PW ROK 2.2K_0402_5% 2.2K_0402_5% MC74VHC1G08DFT2G_SC70-5 100K_0402_5% 3 1
7 2 EC_RSMRST# @ @ 3 1
GND GND

1
SYS_RESET#

15P_0402_50V8J
CC12

15P_0402_50V8J
CC13
6 3
2

2
5 4 LAN_W AKE# 2 @ 1
RC125 0_0402_5% 4 2

2
10K_0804_8P4R_5%

Follow 543016_SKL_U_Y_PDG_0_9 Note for PCH_PWROK

PDG1.0 Figure43-4 note20: PCH_PWROK UC1K SKL-U
Rev_0.53
@ T84
does not glitch when RSMRST# is @ T85
+3VALW _DSW SYSTEM POWER MANAGEMENT
de-asserted PM_SLP_S0#
AT11
GPP_B12/SLP_S0# PM_SLP_S3# PM_SLP_S0# 6,38
AP15
PM_BATLOW # PLT_RST# GPD4/SLP_S3# PM_SLP_S4# PM_SLP_S3# 6,38,42
1 2 AN10 BA16
20,38,39 PLT_RST# SYS_RESET# GPP_B13/PLTRST# GPD5/SLP_S4# PM_SLP_S5# PM_SLP_S4# 6,38,42
RC103 10K_0402_5% 6 SYS_RESET# B5 AY16
EC_RSMRST# SYS_RESET# GPD10/SLP_S5# PM_SLP_S5# 6
1 2 W AKE# 6,38 EC_RSMRST# AY17 @ T86
RC104 1K_0402_5% RSMRST# AN15 SLP_SUS#
AC_PRESENT #543016 PDG0.9 P.526 H_CPUPW RGD SLP_SUS# SLP_LAN# @ T90
1 @ 2 T95 @ A68 AW15 @ T87
RC106 10K_0402_5% PROCPWRGD is used only for power sequence EC_VCCST_PG B65 PROCPWRGD SLP_LAN# BB17 SLP_W LAN#
debug and is not required to be connected to VCCST_PWRGD GPD9/SLP_WLAN# PM_SLP_A# @ T88
anything on the platform. T89 @ AN16 PM_SLP_A# 6
SYS_PW ROK B6 GPD6/SLP_A#
+3VALW _PRIM 38,42 SYS_PW ROK PCH_PW ROK SYS_PWROK PBTN_OUT#_R
38,42 PCH_PW ROK BA20 BA15
PCH_DPW ROK BB20 PCH_PWROK GPD3/PWRBTN# AY15 AC_PRESENT
DSW_PWROK GPD1/ACPRESENT PM_BATLOW # AC_PRESENT 38
3 AU13 3
SUSPW RDNACK AR13 GPD0/BATLOW#
38 RDNACK SUSPW GPP_A13/SUSWARN#/SUSPWRDNACK
RC115 1 @ 2 10K_0402_5% SOC_VRALERT# WAKE# (DSX wake event) @ SUSACK# AP11
GPP_A15/SUSACK# AU11
10 KΩ pull-up to VccDSW3_3. T92
GPP_A11/PME# @ T91
W AKE# BB15 AP16 SM_INTRUDER#
The pull-up is required even LAN_W AKE# WAKE# INTRUDER#
if PCIe* interface is not AM15
+3VALW _DSW AW17 GPD2/LAN_WAKE# AM10 EXT_PW R_GATE#
used on the platform. GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# SOC_VRALERT# @ T93
AT15 AM11
LAN WAKE: LAN Wake Indicator from the GbE PHY. GPD7/RSVD GPP_B2/VRALERT#
11 OF 20
SOC_RTCX2
SKL-U_BGA1356
RC111 2 @ 1 100K_0402_5% PBTN_OUT#_R @

SOC_RTCX1

Note for VCCST_PWRGD 1 2

+1.0V_VCCST 1. 1.0V tolerance RC98 10M_0402_5%
2 @ 1 PBTN_OUT#_R
2. PDG1.0 Figure43-4 note17: when failure events, 6,38 PBTN_OUT#
VCCST_PWRGD and PCH_PWROK de-assert at the same time RC109 0_0402_5%
1

RC113 EC_RSMRST# 2 @ 1 PCH_DPW ROK YC2

From EC(open-drain) 1K_0402_5% RC114 0_0402_5% 1 2

32.768KHZ_9PF_CM7V-T1A9.0PF20PPM
2

RC116 1 2 60.4_0402_1% EC_VCCST_PG Change PN to SJ10000L000

38,42 EC_VCCST_PG_R
1 1
SYS_PW ROK 2 @ 1 PCH_PW ROK CC15 CC16
RC122 0_0402_5% 8.2P_0402_50V8D 8.2P_0402_50V8D

CC51 @EMC@ 2 2
4 4
.1U_0402_16V7K
2 1 SYS_RESET# SYS_PW ROK RC110 1 2 10K_0402_5%

CC50 @EMC@
.1U_0402_16V7K
2 1 H_CPUPW RGD
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(5/12)CLK,GPIO
Reserved for ESD 2014/9/17 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 10 of 60
A B C D E
 A B C D E

# 543016 SKY PDG 0.9 P.401

+3VS

DGPU_PWR_EN RC214 1 VGA@ 2 10K_0402_5%

UC1F SKL-U
Rev_0.53
LPSS ISH
DGPU_HOLD_RST# RC219 1 VGA@ 2 10K_0402_5%
TS_EN AN8 +3VS
29,38 TS_EN AP7 GPP_B15/GSPI0_CS# P2 VGA_ID
GC6_FB_EN_R AP8 GPP_B16/GSPI0_CLK GPP_D9 P3 RANK_ID +1.8VS_3VS_PGPPA +1.8VS
GSPI0_MOSI AR7 GPP_B17/GSPI0_MISO GPP_D10 P4 PROJECT_ID0
@ T111 GPP_B18/GSPI0_MOSI GPP_D11 PROJECT_ID1
P1 RC177
1
AM5 GPP_D12 ALS_INT# RC205 1 @ 2 10K_0402_5% 0_0402_5% 2 ESPI@ 1
1
AN7 GPP_B19/GSPI1_CS# M4 ISH_I2C0_SDA
EC_LID_OUT# AP5 GPP_B20/GSPI1_CLK GPP_D5/ISH_I2C0_SDA N3 ISH_I2C0_SCL RPC12 RC178
38 EC_LID_OUT# GSPI1_MOSI AN5 GPP_B21/GSPI1_MISO GPP_D6/ISH_I2C0_SCL ISH sensor HUB GYRO_INT1# 1 8
@ T112 0_0402_5% 2 @ 1
GPP_B22/GSPI1_MOSI N1 ISH_I2C1_SDA (Reserve for Verify) M_INT# 2 7
RC189 2 @ 1 SOC_AC_DET AB1 GPP_D7/ISH_I2C1_SDA N2 ISH_I2C1_SCL GYRO_INT2# 3 6
20,38 DGPU_AC_DETECT AB2 GPP_C8/UART0_RXD GPP_D8/ISH_I2C1_SCL G_INT# 4 5
0_0402_5%
GPU_EVENT_R# W4 GPP_C9/UART0_TXD AD11 I2C_5_SDA @
GPP_C10/UART0_RTS# GPP_F10/I2C5_SDA/ISH_I2C2_SDA I2C_5_SCL T105 @
AB3 AD12 T106 @ no use 10K_0804_8P4R_5%
GPP_C11/UART0_CTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL RC117 2 @ 1
UART_2_CRXD_DTXD AD1 100K_0402_5%
35 UART_2_CRXD_DTXD UART_2_CTXD_DRXD AD2 GPP_C20/UART2_RXD U1 SOC_GPIOD13
35 UART_2_CTXD_DRXD UART_2_CRTS_DCTS GPP_C21/UART2_TXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA SOC_GPIOD14 T107 @
AD3 U2 T108 @ no use
UART_2_CCTS_DRTS AD4 GPP_C22/UART2_RTS# GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U3 SOC_GPIOD15
GPP_C23/UART2_CTS# GPP_D15/ISH_UART0_RTS# SOC_GPIOD16 T113 @
U4 T110 @
GPP_D16/ISH_UART0_CTS#/SML0BALERT#
I2C_0_SDA U7 AC1 DGPU_PWR_EN
<Reserved for Touch PNL> 29 I2C_0_SDA I2C_0_SCL U6 GPP_C16/I2C0_SDA GPP_C12/UART1_RXD/ISH_UART1_RXD AC2 DGPU_HOLD_RST# DGPU_PWR_EN 42 +3VALW_PGPPC
29 I2C_0_SCL GPP_C17/I2C0_SCL GPP_C13/UART1_TXD/ISH_UART1_TXD DGPU_HOLD_RST# 20
AC3
I2C_1_SDA U8 GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4
39 I2C_1_SDA GPP_C18/I2C1_SDA GPP_C15/UART1_CTS#/ISH_UART1_CTS#
<Touch PAD/PNL> 39 I2C_1_SCL
I2C_1_SCL U9 +3VS
GPP_C19/I2C1_SCL AY8 GYRO_INT1#
I2C_2_SDA AH9 GPP_A18/ISH_GP0 BA8 M_INT# I2C_0_SDA RC126 1 2 1K_0402_5%
no use T135 @ I2C_2_SCL AH10 GPP_F4/I2C2_SDA GPP_A19/ISH_GP1 BB7 G_INT# I2C_0_SCL 1 2 1K_0402_5%
T134 @ G_INT# 41 RC127
GPP_F5/I2C2_SCL GPP_A20/ISH_GP2 BA7 GYRO_INT2#
I2C_3_SDA AH11 GPP_A21/ISH_GP3 AY7 ALS_INT# I2C_1_SDA RC128 1 2 2.2K_0402_5%
no use T131 @ I2C_3_SCL AH12 GPP_F6/I2C3_SDA GPP_A22/ISH_GP4 AW 7 I2C_1_SCL 1 2 2.2K_0402_5%
T130 @ RC129
GPP_F7/I2C3_SCL GPP_A23/ISH_GP5 AP13
I2C_4_SDA AF11 GPP_A12/BM_BUSY#/ISH_GP6
no use T128 @ I2C_4_SCL AF12 GPP_F8/I2C4_SDA
T129 @ GPP_F9/I2C4_SCL +3VALW_1.8VALW_PGPPD
6 OF 20
2 RPC19 2
SKL-U_BGA1356 ISH_I2C1_SCL 1 8
@ ISH_I2C1_SDA 2 7
Functional Strap Definitions ISH_I2C0_SCL
ISH_I2C0_SDA
3 6
4 5
@
GPU_EVENT_R# 1 GC6@ 2 GPU_EVENT# 1K_0804_8P4R_5% +3VS
GPU_EVENT# 20
SPKR / GPP_B14 (Internal Pull Down): RC204 0_0402_5%
(Sampled:Rising edge of PCH_PWROK) GC6_FB_EN_R 1 GC6@ 2 GC6_FB_EN TO DGPU UART_2_CRXD_DTXD 1 2
GC6_FB_EN 20
RC195 0_0402_5% RC62 49.9K_0402_1%
UART_2_CTXD_DRXD 1 2
TOP Swap Override
RC63 49.9K_0402_1%
0 = Disable TOP Swap mode.---> AAX05 Use UART_2_CRTS_DCTS 1 @ 2
*
1 = Enable TOP Swap Mode. RC64 49.9K_0402_1%
UART_2_CCTS_DRTS 1 @ 2
RC65 49.9K_0402_1%
+3VALW_1.8VALW_PGPPD +3VALW_1.8VALW_PGPPD

GSPI0_MOSI /GPP_B18 (Internal Pull Down): VGA_ID 1 2 10K_0402_5% PROJECT_ID0 2 1 10K_0402_5%

RC215 @ RC207 @
(Rising edge of PCH_PWROK) RC216 1 2 10K_0402_5% RC210 1 2 10K_0402_5%
No Reboot
RANK_ID RC217 1 SR@ 2 10K_0402_5% PROJECT_ID1 RC211 2 @ 1 10K_0402_5%
0 = Disable No Reboot mode. --> AAX05 Use RC218 1 DR@ 2 10K_0402_5% RC213 1 2 10K_0402_5%
* 1 = Enable No Reboot Mode. (PCH will disable the TCO I2C/ISH Port(From PDG 0.9)
Timer system reboot feature). This function is useful
when running ITP/XDP.

3 3

GSPI1_MOSI / GPP_B22 (Internal Pull Down):

VGA_ID GPP_D9 Project_ID1 Project_ID0
Project ID
(Rising edge of PCH_PWROK) GL 0 GPP_D12 GPP_D11
GM 1 *A4WAS 0 0
Boot BIOS Strap Bit
0 = SPI Mode --> AAX05 Use
* 1 = LPC Mode
Reserved 0 1
RANK_ID GPP_D10 Reserved 1 0
DR 0 Reserved 1 1
SML0ALERT# / GPP_C5 (Internal Pull Down):
SR 1
(Sampled: Rising edge of RSMRST# )

eSPI or LPC
0 = LPC is selected for EC --> For KB9022/9032 Use
* 1 = eSPI is selected for EC --> For KB9032 Only.

SMBALERT# / GPP_C2 (Internal Pull Down): HDA_SDO/I2S_TXD0 (Internal Pull Down):

(Sampled: Rising edge of RSMRST# ) (Sampled: Rising edge of PCH_PWROK ) DDPB_CTRLDATA/ GPP_E19 (Internal Pull Down):
Flash Descriptor Security Override DDPC_CTRLDATA/ GPP_E21 (Internal Pull Down):
TLS Confidentiality 0 = Enable security measures defined in the Flash DDPD_CTRLDATA/ GPP_E23 (Internal Pull Down):
0 = Disable Intel ME Crypto Transport Layer Security Descriptor. (Sampled:Rising edge of PCH_PWROK)
4 * Display Port B/C/D Detected 4
(TLS) cipher suite (no confidentiality). 1 = Disable Flash Descriptor Security (override). This
1 = Enable Intel ME Crypto (TLS) (with confidentiality). strap should only be asserted high using external 0 =Port D is not detected.
Must be pulled up to support Intel AMT with TLS and Intelpull-up in manufacturing/debug environments ONLY. 1 =Port D is detected.
SBA (Small Business Advantage) with TLS.

Compal Secret Data

Security Classification
2014/11/10 2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(6/12)GPIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 11 of 60
A B C D E
 A B C D E

UC1H SKL-U
Rev_0.53

SSIC / USB3
PCIE/USB3/SATA
H8 USB3_CRX_DTX_N1 37
USB3_1_RXN G8
PCIE_CRX_GTX_N1 USB3_1_RXP USB3_CRX_DTX_P1 37
20 PCIE_CRX_GTX_N1 H13 C13 USB3 MB
PCIE_CRX_GTX_P1 PCIE1_RXN/USB3_5_RXN USB3_1_TXN USB3_CTX_DRX_N1 37
20 PCIE_CRX_GTX_P1 G13 D13
PCIE_CTX_GRX_N1 PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB3_CTX_DRX_P1 37
20 PCIE_CTX_C_GRX_N1 CC17 VGA@ 1 2 0.22U_0402_16V7K B17
CC21 VGA@ 1 2 0.22U_0402_16V7K PCIE_CTX_GRX_P1 A17 PCIE1_TXN/USB3_5_TXN J6
20 PCIE_CTX_C_GRX_P1 PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN USB3_CRX_DTX_N2 37
H6 USB3_CRX_DTX_P2 37
PCIE_CRX_GTX_N2 G11 USB3_2_RXP/SSIC_1_RXP B13
20 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P2 F11 PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN A13
USB3_CTX_DRX_N2 37 USB3 MB
1 20 PCIE_CRX_GTX_P2 PCIE_CTX_GRX_N2 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP USB3_CTX_DRX_P2 37 1
20 PCIE_CTX_C_GRX_N2 CC18 VGA@ 1 2 0.22U_0402_16V7K D16
CC19 VGA@ 1 2 0.22U_0402_16V7K PCIE_CTX_GRX_P2 C16 PCIE2_TXN/USB3_6_TXN J10
20 PCIE_CTX_C_GRX_P2 PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN
DGPU PCIE_CRX_GTX_N3 USB3_3_RXP/SSIC_2_RXP
H10
20 PCIE_CRX_GTX_N3 H16 B15
PCIE_CRX_GTX_P3 G16 PCIE3_RXN USB3_3_TXN/SSIC_2_TXN A15
20 PCIE_CRX_GTX_P3 PCIE_CTX_GRX_N3 PCIE3_RXP USB3_3_TXP/SSIC_2_TXP
CC20 VGA@ 1 2 0.22U_0402_16V7K D17
20 PCIE_CTX_C_GRX_N3 PCIE_CTX_GRX_P3 PCIE3_TXN
CC22 VGA@ 1 2 0.22U_0402_16V7K C17 E10
20 PCIE_CTX_C_GRX_P3 PCIE3_TXP USB3_4_RXN F10
PCIE_CRX_GTX_N4 G15 USB3_4_RXP C15
20 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_P4 PCIE4_RXN USB3_4_TXN
20 PCIE_CRX_GTX_P4 F15 D15
CC23 VGA@ 1 2 0.22U_0402_16V7K PCIE_CTX_GRX_N4 B19 PCIE4_RXP USB3_4_TXP
20 PCIE_CTX_C_GRX_N4 PCIE_CTX_GRX_P4 PCIE4_TXN USB20_N1
CC24 VGA@ 1 2 0.22U_0402_16V7K A19 AB9
20 PCIE_CTX_C_GRX_P4 PCIE4_TXP USB2N_1 USB20_P1 USB20_N1 37
AB10 USB3 MB
PCIE_CRX_DTX_N5 USB2P_1 USB20_P1 37
F16
33 PCIE_CRX_DTX_N5 PCIE_CRX_DTX_P5 PCIE5_RXN USB20_N2
E16 AD6
33 PCIE_CRX_DTX_P5 PCIE_CTX_DRX_N5 PCIE5_RXP USB2N_2 USB20_P2 USB20_N2 37
GLAN+CR 33 PCIE_CTX_C_DRX_N5
CC25 2 1 .1U_0402_16V7K
PCIE_CTX_DRX_P5
C19
PCIE5_TXN USB2P_2
AD7
USB20_P2 37 USB3 MB
CC26 2 1 .1U_0402_16V7K D19
33 PCIE_CTX_C_DRX_P5 PCIE5_TXP AH3 USB20_N3
PCIE_CRX_DTX_N6 USB2N_3 USB20_P3 USB20_N3 37
G18 AJ3 USB2/B
35 PCIE_CRX_DTX_N6 PCIE_CRX_DTX_P6 PCIE6_RXN USB2P_3 USB20_P3 37
F18
35 PCIE_CRX_DTX_P6 PCIE_CTX_DRX_N6 PCIE6_RXP
NGFF WLAN+BT(Key E) 35 PCIE_CTX_C_DRX_N6
C3803 1 2 .1U_0402_16V7K
PCIE_CTX_DRX_P6
D20
PCIE6_TXN USB2N_4
AD9
C3804 1 2 .1U_0402_16V7K C20 AD10
35 PCIE_CTX_C_DRX_P6 PCIE6_TXP USB2P_4
F20 AJ1 USB20_N5
36 SATA_CRX_DTX_N0 PCIE7_RXN/SATA0_RXN USB2N_5 USB20_P5 USB20_N5 35
E20 AJ2 BT
36 SATA_CRX_DTX_P0 PCIE7_RXP/SATA0_RXP USB2P_5 USB20_P5 35
HDD 36 SATA_CTX_DRX_N0
B21
PCIE7_TXN/SATA0_TXN USB2
USB20_N6
A21 AF6
36 SATA_CTX_DRX_P0 PCIE7_TXP/SATA0_TXP USB2N_6 USB20_P6 USB20_N6 29
AF7 TS
USB2P_6 USB20_P6 29
2 G21 2
36 SATA_CRX_DTX_N1 F21 PCIE8_RXN/SATA1A_RXN AH1 USB20_N7
36 SATA_CRX_DTX_P1 PCIE8_RXP/SATA1A_RXP USB2N_7 USB20_P7 USB20_N7 29
ODD 36 SATA_CTX_DRX_N1
D21
PCIE8_TXN/SATA1A_TXN USB2P_7
AH2
USB20_P7 29 Camera
C21
36 SATA_CTX_DRX_P1 PCIE8_TXP/SATA1A_TXP AF8
E22 USB2N_8 AF9
+3VALW _PRIM E23 PCIE9_RXN USB2P_8
PCIE9_RXP
When PCIE8/SATA1A is used B23
PCIE9_TXN USB2N_9
AG1
A23 AG2
as SATA Port 1 (ODD), then 10K_0402_5% 2 @ 1 RC135 PIRQA# PCIE9_TXP USB2P_9 AG3,AG4 PD1K for DCI warm boot fail issue (follow PCH EDS1.2)
PCIE11/SATA1B (M.2 SSD) F25 AH7 2015MOW10, USB2_ID Connected to GND Directly
PCIE10_RXN USB2N_10
cannot be used as SATA E25
PCIE10_RXP USB2P_10
AH8
Port 1. #543016 P.239 PCIE_RCOMPN/PCIE_RCOMPP D23
PCIE10_TXN USB2_COMP
C23 AB6 RC119 1 2 113_0402_1%
BO=4 W=12 S=12 R=100ohm PCIE10_TXP USB2_COMP AG3 USB2_ID RC130 1 2 0_0402_5%
RC120 1 2 100_0402_1% PCIE_RCOMPN F5 USB2_ID AG4 USB2_VBUSSENSE RC131 1 2 0_0402_5%
PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE
PCIE_RCOMPP A9 USB_OC0#
XDP_PRDY# GPP_E9/USB2_OC0# USB_OC1# USB_OC0# 37
D56 C9 USB_OC1# 37
6 XDP_PRDY# XDP_PREQ# D61 PROC_PRDY# GPP_E10/USB2_OC1# D9
6 XDP_PREQ# PROC_PREQ# GPP_E11/USB2_OC2#
PIRQA# BB11 B9
GPP_A7/PIRQA# GPP_E12/USB2_OC3#
E28 J1
E27 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 J2
D24 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 J3
C24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2
E30 PCIE11_TXP/SATA1B_TXP H2
F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3
A25 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 G4
B25 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2
3 PCIE12_TXP/SATA2_TXP 3
H1
GPP_E8/SATALED#
8 OF 20
SKL-U_BGA1356
Acer HSIO def i ne @

+3VALW _PRIM
GPIO DEVICE CONTROL
USB_OC0# USB2 Port 1 USB_OC0# RC132 1 2 10K_0402_5%

USB_OC1# USB2 Port 2 USB_OC1# RC200 1 2 10K_0402_5%

USB_OC2# NA
USB_OC3# NA
DEVSLP[2:0] Implementation
DEVSLP0 NA DEVSLP is a host-controlled hardware signal which enables a SATA host and device to
enter an ultra-low interface power state, including the possibility to completely power
DEVSLP1 NA down host and device PHYs.
The processor provides three SATA DEVSLP signals, DEVSLP[2:0] for SKL U.
‧When high, DEVSLP requests the SATA device to enter into the DEVSLP power state.
‧When low, DEVSLP requests the SATA device to exit from the DEVSLP power state
DEVSLP2 NA and transition to active state.

SATA_GP0 NA

SATA_GP1 NA SATA General Purpose (SATAGP[2:0]) Signals

‧The processor provides three SATA general purpose input signals,SATAGP[2:0] for SKL U.
4 These signals can be configured as interlock switch inputs corresponding to a given SATA port. 4
SATA_GP2 NA ‧When used as an interlock switch status indication, this signal should be driven to 0
to indicate that the switch is closed and to a 1 to indicate that the switch is open.
‧If mechanical presence switches will not be used on the platform, SATAGP[2:0]
signals can be configured as GPP_E[2:0] GPIOs signals.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(7/12)PCIE,USB,SATA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Thursday, July 16, 2015 Sheet 12 of 60
A B C D E
 A B C D E

+1.0VALW_PRIM TO +1.0V_VCCSTU / +1.0VCCST

+5VALW +1.0VALW _PRIM +1.0V_VCCSTU
+1.35V_VDDQ +1.35V_VDDQ_CPU +VCCIO
For Power consumption UC1N SKL-U
Measurement Rev_0.53
CPU POWER 3 OF 4

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 JPC1

CC98

CC97
1 1 2 AU23 AK28
@ AU28 VDDQ_AU23 VCCIO AK30
@ CC96 JUMP_43X118 AU35 VDDQ_AU28 2.73A VCCIO AL30
2 2
.1U_0402_16V7K AU42 VDDQ_AU35 VCCIO AL42
2 JPC2 BB23 VDDQ_AU42 6.35A VCCIO AM28
1 1 2 BB32 VDDQ_BB23 VCCIO AM30 1
UC5 @ BB41 VDDQ_BB32 VCCIO AM42
CC105 2 1 .1U_0402_16V7K 1 14 JUMP_43X118 BB47 VDDQ_BB41 VCCIO
2 VIN1 VOUT1 13 BB51 VDDQ_BB47 AK23
VIN1 VOUT1 VDDQ_BB51 VCCSA +VCC_SA
AK25
RC142 1 2 20K_0402_5% EN_1.0V_VCCSTU 3 12 1 2 VCCSA G23
38,42,47 SYSON ON1 CT1 VCCSA
CC95 +1.35V_VDDQC AM40
VDDQC
0.09A VCCSA
G25
4 11 1000P_0402_50V7K G27
VBIAS GND VCCSA
+1.0V_VCCST A18
VCCST
0.04A VCCSA
G28
RC168 1 @ 2 0_0402_5% EN_1.8VS 5 10 1 2 6A J22
38,42,45,47,49 SUSP# ON2 CT2 VCCSA
CC94 +1.0VS_VCCSTG A22
VCCSTG_A22
0.04A VCCSA
J23
2 1 CC104 6 9 1000P_0402_50V7K J27
+1.8VALW _VS VIN2 VOUT2 VCCSA
@ 1U_0402_6.3V6K 7
VIN2 VOUT2
8 +1.35V_VCCSFR_OC AL23
VCCPLL_OC
0.26A VCCSA
K23
+1.8VS K25
VCCSA
GPAD
15 +1.0V_VCCSFR K20
VCCPLL_K20
0.12A VCCSA
K27
+1.8VALW _PRIM 1 2 K21 K28
1 2 EM5209VF_DFN14_2X3 VCCPLL_K21 VCCSA K30
VCCSA

1U_0402_6.3V6K
JPC8 1 1
VCCIO_SENSE

CC99
JUMP_43X39 AM23 T124 @
@ CC100 VCCIO_SENSE AM22 VSSIO_SENSE
VSSIO_SENSE T125 @
@
2 +1.8VALW_PRIM TO +1.8VS 2
.1U_0402_16V7K
VSSSA_SENSE
H21
H20
VSSSA_SENSE
VCCSA_SENSE VSSSA_SENSE 50
VCCSA_SENSE 50
14 OF 20 VCCSA_SENSE

SKL-U_BGA1356
@

2
+1.0VALW_PRIM TO +1.0VS_VCCSTG 2

+1.0VALW _PRIM
+1.0VALW _PRIM_JP
JPC4 VCCSTG and VCCIO SLEW RATE <=65us +1.35V_VDDQC
1 2 +1.35V_VDDQ_CPU
1 2 +1.0VS_VCCSTG PSC Side 543016_SKL_PDG_1_0
1U_0402_6.3V6K

Imax : 2.77 AJUMP_43X79 1 +1.35V_VDDQC : 1x 1uF 0201 (Placeholder)

CC117

@ RC188 1 @ 2 0_0402_5% RC208 1 @ 2 0_0402_5% CC47 1 2 10U_0603_6.3V6M

For Power consumption UC6 1x 10uF 0402
Measurement 1
2 2 VIN1 +VCCIO
+5VALW VIN2 @ J16 +1.0V_VCCSTU +1.0V_VCCST
CC107 7 6 +1.0VS_VCCSTG_IO 1 2 PSC Side
VIN thermal VOUT 1 2
.1U_0402_16V7K 543016_SKL_PDG_1_0
2 1 3 JUMP_43X79 Imax : 2.73 A RC140 1 @ 2 0_0402_5% CC48 1 2 1U_0402_6.3V6K
@ VBIAS +1.0V_VCCST : 1x 1uF 0402
SUSP# 1 @ 2 SUSP#_R1 4 5
ON GND
RC186 +1.0V_VCCSFR PSC Side
1U_0402_6.3V6K

0_0402_5% 1
CC106

TPS22961DNYR_W SON8 543016_SKL_PDG_1_0

RC143 1 @ 2 0_0402_5% CC55 1 2 1U_0402_6.3V6K
@
+1.0V_VCCSFR : 1x 1uF 0402
2

+1.35V_VDDQ_CPU +1.35V_VCCSFR_OC BSC Side

543016_SKL_PDG_1_0
RC141 1 @ 2 0_0402_5% CC49 1 2 1U_0402_6.3V6K
+1.35V_VCCSFR_OC : 1x 1uF 0201
3 3

+1.0VALW _PRIM_JP BSC Side

U4902 543016_SKL_PDG_1_0
CC56 1 2 1U_0402_6.3V6K
1 7 +1.0VS_VCCSTG_IO +1.0VS_VCCSTG
@
+1.0VS_VCCSTG : 1x 1uF 0402 (Placeholder)
2 VIN VOUT 8
VIN VOUT
SUSP#_R1 3 6 1 2 C977
ON CT 1000P_0402_50V7K +1.35V_VDDQ_CPU
@ PSC Side BSC Side
+5VALW 4
VBIAS 5
GND 9
GND

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
AOZ1336_DFN8_2X2 1 1 1 1 1 1 1 1 1 1 1

CC37

CC41

CC54
@

CC38

CC39

CC40

CC42

CC43

CC44

CC45

CC46
@ @ @ @
+VCCIO 2 2 2 2 2 2 2 2 2 2 2
BSC Side PSC Side
22U_0603_6.3V6M

22U_0603_6.3V6M

543016_SKL_PDG_1_0
10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 1 1 1 1 1 1 1 1 1 +1.35V_VDDQ_CPU : 2x 10uF 0402 (Placeholder)

CC58

CC59

4 4
4x 1uF 0201 (Placeholder)
CC27

CC28

CC29

CC30

CC31

CC32

CC33

CC34

CC35

CC36

@
2
@
2
@
2
@
2
@
2
@
2
@
2
@
2 2 2 2 2
4x 10uF 0402
3x 22uF 0603

Security Classification Compal Secret Data Compal Electronics, Inc.

543016_SKL_PDG_1_0 Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title
+VCCIO : 2x10uF 0402 (Placeholder)
4x 1uF 0201 (Placeholder) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(8/12)Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
4x 1uF 0402 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 13 of 60
A B C D E
 A B C D E

+3VALW _PRIM

+3VALW _1.8VALW _PGPPA +1.8VALW _PRIM

+1.0VALW _PRIM UC1O SKL-U EC LPC/ESPI

CC91 Rev_0.53 0_0402_5% 2 ESPI@ 1 RC196
CPU POWER 4 OF 4
2 1 1U_0402_6.3V6K 0_0402_5% 2 @ 1 RC197
@ AB19
VCCPRIM_1P0 +3VALW _PRIM
Near AB19 (<10 mm) AB20 0.89A AK15 +3VALW _1.8VALW _PGPPA +3VALW _PGPPB
P18 VCCPRIM_1P0 VCCPGPPA AG15
VCCPRIM_1P0 VCCPGPPB +3VALW _PGPPB
+1.0VALW _PRIM Y16 +3VALW _PGPPC
AF18 VCCPGPPC Y15 SPI Touch CC102 2 1 0_0402_5% 2 @ 1 RC161
VCCPRIM_CORE VCCPGPPD +3VALW _1.8VALW _PGPPD
2 1 CC76 AF19
VCCPRIM_CORE
2.57A VCCPGPPE
T16 +3VALW _PGPPE 1U_0402_6.3V6K @
1 +1.0VALW _MPHYAON @ 1U_0402_6.3V6K V20
VCCPRIM_CORE VCCPGPPF
AF16 +1.8VALW _PRIM CC102 near AG15 (<3 mm) 1
+1.0VALW _PRIM near AF18 (<10 mm) V21 AD15
VCCPRIM_CORE VCCPGPPG +3VALW _PGPPG No use
+3VALW _PRIM
+3VALW _PGPPC
RC175 1 @ 2 0_0402_5% 1 2 CC87 CC85 2 1 DCPDSW _1P0 AL1 V19
DCPDSW_1P0 VCCPRIM_3P3_V19 +3VALW _PRIM
1U_0402_6.3V6K 1U_0402_6.3V6K
CC87 near K17 (<3 mm) +1.0VALW _MPHYAON K17
VCCMPHYAON_1P0 VCCPRIM_1P0_T1
T1 +1.0VALW _DTS CC73 2 1 0_0402_5% 2 @ 1 RC163
L1 1U_0402_6.3V6K @
VCCMPHYAON_1P0
VCCATS_1P8
AA1 +1.8VALW _PRIM CC73 near Y16 (<10 mm)
+1.0VALW _PRIM +1.0VALW _APLL N15
+1.0VALW _MPHYGT VCCMPHYGT_1P0_N15 +3VALW _PRIM
N16 AK17 +3VALW _RTC +3VALW _1.8VALW _PGPPD
N17 VCCMPHYGT_1P0_N16 HSIO VCCRTCPRIM_3P3 +1.8VALW _PRIM
VCCMPHYGT_1P0_N17
RC148 1 @ 2 0_0603_5% 1 2 CC123 P15
VCCMPHYGT_1P0_P15
2.1A VCCRTC_AK19
AK19 +RTCVCC
@ 22U_0603_6.3V6M P16 BB14 0_0402_5% 1 @ 2 RC206
VCCMPHYGT_1P0_P16 VCCRTC_BB14 CC103 2 1 0_0402_5% 2 @ 1 RC172
+1.0VALW _AMPHYPLL K15 BB10 CC71 1 2 .1U_0402_16V7K 1U_0402_6.3V6K
L15 VCCAMPHYPLL_1P0 HSIO DCPRTC
+3VALW +3VALW _DSW VCCAMPHYPLL_1P0 A14 +3VALW _PGPPE +3VALW _PRIM
VCCCLK1 +1.0VALW _CLK6_24TBT
+1.0VALW _APLL V15
VCCAPLL_1P0 K19
VCCCLK2 +1.0VALW _VCCCLK2
RC173 1 @ 2 0_0402_5% +1.0VALW _PRIM AB17 CC74 2 1 0_0402_5% 2 @ 1 RC167
Y18 VCCPRIM_1P0_AB17 L21 1U_0402_6.3V6K @
VCCPRIM_1P0_Y18 VCCCLK3 +1.0VALW _APLL
CC74 near T16 (<10 mm)
+3VALW _DSW AD17 N20 +1.0VALW _CLK4_F100OC
+3VALW _PRIM +3VALW _HDA AD18 VCCDSW_3P3_AD17 VCCCLK4 +3VALW _PRIM
AJ17 VCCDSW_3P3_AD18 L19 +3VALW _PGPPG
VCCDSW_3P3_AJ17 VCCCLK5 +1.0VALW _CLK5_F24NS
RC198 1 @ 2 0_0402_5% 1 2 CC63
@ 1U_0402_6.3V6K +3VALW _HDA AJ19 A10 +1.0VALW _CLK6_24TBT CC83 2 1 0_0402_5% 2 @ 1 RC187
VCCHDA VCCCLK6
CC63 near AJ19 (<10 mm) 1U_0402_6.3V6K @
AJ16 AN11 PRIMCORE_VID0
+3VALW _SPI VCCSPI GPP_B0/CORE_VID0 T136 @
+3VALW _SPI AN13 PRIMCORE_VID1
2 GPP_B1/CORE_VID1 T138 @ 2
+1.0VALW _SRAM AF20 CC67 2 1 +3VALW _PRIM
RC154 1 @ 2 0_0402_5% AF21 VCCSRAM_1P0 HSIO 1U_0402_6.3V6K @
VCCSRAM_1P0
T19
VCCSRAM_1P0
CC67 near V19 (<3 mm)
T20
VCCSRAM_1P0
AJ21 +1.0VALW _DTS +1.0VALW _PRIM
+3VALW _PRIM VCCPRIM_3P3_AJ21
+3VALW +3VALW _PRIM AK20 0_0402_5% 2 @ 1 RC162
+1.0VALW _PRIM VCCPRIM_1P0_AK20
JPC7
1 2 +1.0VALW _APLLEBB N18
1 2 +1.0V_MPHYPLL VCCAPLLEBB HSIO 15 OF 20 CC72 2 1 +1.8VALW _PRIM
JUMP_43X39 1U_0402_6.3V6K
@ SKL-U_BGA1356 CC72 near AA1 (<10 mm)
@
+3VALW _RTC +3VALW _PRIM
+1.0VALW _MPHYPLL
+1.0VALW _PRIM HSIO +1.0VALW _MPHYGT CC78 2 1 0_0402_5% 2 @ 1 RC171
Imax : 3.5 A .1U_0402_16V7K
JPC9 VCCMPHYGT CC77 2 1
1 2 RC209 1 @ 2 0_0603_5% CC82 1 2 22U_0603_6.3V6M 1U_0402_6.3V6K
1 2 @ CC77,CC78 near AK17 (<3 mm)
JUMP_43X79 CC81 1 2 22U_0603_6.3V6M
@ @ Per 543016_SKL_U_Y_PDG_0_9
CC80 1 2 1U_0402_6.3V6K +1.0VALW _CLK6_24TBT +1.0VALW _PRIM
CC80 near N15 (<3mm)
CC81,CC82 near N15 (<10mm)
VCCRTC does not exceed 3.2 V From PDG
RTC Battery CC86 2 1 0_0402_5% 2 @ 1 RC169
1U_0402_6.3V6K @
Power Rail Voltage +RTCBATT +CHGRTC W=20mils CC86 near A10 (<3 mm)
3 +1.0VALW _AMPHYPLL DC1 3
2 +RTCVCC
+CHGRTC 3.383V(MAX) W=10mil +1.0VALW _VCCCLK2 +1.0VALW _PRIM
CC61 near K15 (<3 mm) 1
RC149 1 @ 2 0_0603_5% CC61 1 2 1U_0402_6.3V6K W=20mils CC75 2 1 0_0603_5% 2 @ 1 RC164
@ BAT54C(VF) 240 mV 3 1U_0402_6.3V6K @
+1.0VALW _SRAM 1 CC124 2 1
BAS40-04_SOT23-3 22U_0603_6.3V6M @
CC122 near AF20 (<10mm) +3VL_RTC 3.143V C151
RC176 1 @ 2 0_0603_5% CC122 1 2 1U_0402_6.3V6K cap Place close AK19. .1U_0402_16V7K
@ 2 +1.0VALW _CLK4_F100OC +1.0VALW _PRIM
Result : Pass
CC125 2 1 0_0603_5% 2 @ 1 RC190
+1.0VALW _APLLEBB 22U_0603_6.3V6M @
CC68 near N18 (<3mm)
RC156 1 @ 2 0_0402_5% CC68 1 2 1U_0402_6.3V6K +1.0VALW _CLK5_F24NS +1.0VALW _PRIM

0_0603_5% 2 @ 1 RC152

Follow 543016_SKL_U_Y_PDG_0_9
+1.0VALW _PRIM +3VALW _PRIM +1.8VALW _PRIM
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

1 1 1 1 1 1
CC111

CC112

CC113

CC114

CC116

CC115

4 4

@ @ @ @ @ @
2 2 2 2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(9/12)Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 14 of 60
A B C D E
 A B C D E

VCC 27A (U 15W Dual Core GT2) VCCGT / VCCGTX(2+3e only) 40A(need confirm)

+VCC_CORE +VCC_CORE +VCC_GT +VCC_GT

UC1M SKL-U
UC1L SKL-U Rev_0.53
#544924 Skylake EDS P.120 #544924 Skylake EDS P.121
#544924 Skylake EDS P.125 Rev_0.53 CPU POWER 2 OF 4
CPU POWER 1 OF 4 VCC U(15W)-dual core GT2 27A(Typ)-33A(MAX) VCCGT U(15W)-dual core GT2 40A(MAX)
0.55-1.15V 0.55-1.15V N70
A30 G32 A48 VCCGT N71
A34 VCC_A30 VCC_G32 G33 A53 VCCGT VCCGT R63
A39 VCC_A34 VCC_G33 G35 A58 VCCGT VCCGT R64
1 VCC_A39 VCC_G35 VCCGT VCCGT 1
A44 G37 A62 R65
AK33 VCC_A44 VCC_G37 G38 A66 VCCGT VCCGT R66
AK35 VCC_AK33 VCC_G38 G40 AA63 VCCGT VCCGT R67
AK37 VCC_AK35 VCC_G40 G42 AA64 VCCGT VCCGT R68
AK38 VCC_AK37 VCC_G42 J30 AA66 VCCGT VCCGT R69
AK40 VCC_AK38 VCC_J30 J33 AA67 VCCGT VCCGT R70
AL33 VCC_AK40 VCC_J33 J37 AA69 VCCGT VCCGT R71
AL37 VCC_AL33 VCC_J37 J40 AA70 VCCGT VCCGT T62
AL40 VCC_AL37 VCC_J40 K33 AA71 VCCGT VCCGT U65
AM32 VCC_AL40 VCC_K33 K35 AC64 VCCGT VCCGT U68
AM33 VCC_AM32 VCC_K35 K37 AC65 VCCGT VCCGT U71
AM35 VCC_AM33 VCC_K37 K38 AC66 VCCGT VCCGT W63
AM37 VCC_AM35 VCC_K38 K40 AC67 VCCGT VCCGT W64
AM38 VCC_AM37 VCC_K40 K42 AC68 VCCGT VCCGT W65
VCC_AM38 VCC_K42 VCCGT VCCGT
G30
VCC_G30 VCC_K43
K43 Trace Length < 25 mils AC69
VCCGT VCCGT
W66
AC70 W67
K32 E32 AC71 VCCGT VCCGT W68
RSVD_K32 VCC_SENSE VCCSENSE 50 VCCGT VCCGT
E33 J43 W69
VSS_SENSE VSSSENSE 50 VCCGT VCCGT
#544924 Skylake EDS P.125 AK32 J45 W70
RSVD_AK32 B63 SOC_SVID_ALERT# J46 VCCGT VCCGT W71
VCCOPC 1V 2.8A VIDALERT# SOC_SVID_CLK VCCGT VCCGT
VCC_OPC_1P8 1.8V 50mA AB62 A63 J48 Y62
VCCOPC_AB62 VIDSCK SOC_SVID_DAT SOC_SVID_CLK 50 VCCGT VCCGT
P62 D64 J50
VCCEOPIO 0V,0.8V,1V 2.9A V62 VCCOPC_P62 VIDSOUT J52 VCCGT
VCCOPC_V62 G20 +1.0VS_VCCSTG J53 VCCGT AK42
VCCSTG_G20 VCCGT VCCGTX_AK42
H63
VCC_OPC_1P8_H63
+1.0VS(SUSP#) J55
VCCGT VCCGTX_AK43
AK43
J56 AK45
G61 J58 VCCGT VCCGTX_AK45 AK46
VCC_OPC_1P8_G61 VCCGT VCCGTX_AK46
For CPU2+3e SKU J60
VCCGT VCCGTX_AK48
AK48
VCCOPC_SENSE AC63 K48 AK50
2 T132 @ VSSOPC_SENSE VCCOPC_SENSE VCCGT VCCGTX_AK50 2
T133 @ AE63 K50 AK52
VSSOPC_SENSE K52 VCCGT VCCGTX_AK52 AK53
AE62 K53 VCCGT VCCGTX_AK53 AK55
AG62 VCCEOPIO K55 VCCGT VCCGTX_AK55 AK56
VCCEOPIO K56 VCCGT VCCGTX_AK56 AK58
VCCEOPIO_SENSE AL63 K58 VCCGT VCCGTX_AK58 AK60
T137 @ VSSEOPIO_SENSE AJ62 VCCEOPIO_SENSE VCCGT VCCGTX_AK60
T139 @ K60 AK70
VSSEOPIO_SENSE VCCGT VCCGTX_AK70
12 OF 20 L62
VCCGT VCCGTX_AL43
AL43 For CPU2+3e SKU
L63 AL46
SKL-U_BGA1356 L64 VCCGT VCCGTX_AL46 AL50
@ L65 VCCGT VCCGTX_AL50 AL53
L66 VCCGT VCCGTX_AL53 AL56
L67 VCCGT VCCGTX_AL56 AL60
L68 VCCGT VCCGTX_AL60 AM48
L69 VCCGT VCCGTX_AM48 AM50
L70 VCCGT VCCGTX_AM50 AM52
L71 VCCGT VCCGTX_AM52 AM53
M62 VCCGT VCCGTX_AM53 AM56
N63 VCCGT VCCGTX_AM56 AM58
N64 VCCGT VCCGTX_AM58 AU58
N66 VCCGT VCCGTX_AU58 AU63
N67 VCCGT VCCGTX_AU63 BB57
N69 VCCGT VCCGTX_BB57 BB66
SVID ALERT VCCGT VCCGTX_BB66
+1.0V_VCCST VCCGT_SENSE AK62 VCCGTX_SENSE
Place the PU 50 VCCGT_SENSE VSSGT_SENSE
J70
VCCGT_SENSE VCCGTX_SENSE T155 @
J69 AL61 VSSGTX_SENSE
resistors close to CPU 50 VSSGT_SENSE VSSGT_SENSE VSSGTX_SENSE T219 @
13 OF 20
1

3 Trace Length < 25 mils SKL-U_BGA1356 3

RC179 @
56_0402_5%
2

543016 PDG0.9 P.189 Need check

SOC_SVID_ALERT# 1 2 (To VR)
SOC_SVID_ALERT#_R 50
RC180 220_0402_5%

+1.0V_VCCST

SVID DATA Place the PU

resistors close to CPU
1

RC181
100_0402_1%
2

SOC_SVID_DAT
SOC_SVID_DAT 50 (To VR)
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(10/12)Power,SVID
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 15 of 60
A B C D E
 A B C D E

1 1
UC1P SKL-U UC1Q SKL-U
Rev_0.53 Rev_0.53 UC1R SKL-U
GND 1 OF 3 GND 2 OF 3
GND 3 OF 3 Rev_0.53
A5 AL65 AT63 BA49 F8 L18
A67 VSS VSS AL66 AT68 VSS VSS BA53 G10 VSS VSS L2
A70 VSS VSS AM13 AT71 VSS VSS BA57 G22 VSS VSS L20
AA2 VSS VSS AM21 AU10 VSS VSS BA6 G43 VSS VSS L4
AA4 VSS VSS AM25 AU15 VSS VSS BA62 G45 VSS VSS L8
AA65 VSS VSS AM27 AU20 VSS VSS BA66 G48 VSS VSS N10
AA68 VSS VSS AM43 AU32 VSS VSS BA71 G5 VSS VSS N13
AB15 VSS VSS AM45 AU38 VSS VSS BB18 G52 VSS VSS N19
AB16 VSS VSS AM46 AV1 VSS VSS BB26 G55 VSS VSS N21
AB18 VSS VSS AM55 AV68 VSS VSS BB30 G58 VSS VSS N6
AB21 VSS VSS AM60 AV69 VSS VSS BB34 G6 VSS VSS N65
AB8 VSS VSS AM61 AV70 VSS VSS BB38 G60 VSS VSS N68
AD13 VSS VSS AM68 AV71 VSS VSS BB43 G63 VSS VSS P17
AD16 VSS VSS AM71 AW10 VSS VSS BB55 G66 VSS VSS P19
AD19 VSS VSS AM8 AW12 VSS VSS BB6 H15 VSS VSS P20
AD20 VSS VSS AN20 AW14 VSS VSS BB60 H18 VSS VSS P21
AD21 VSS VSS AN23 AW16 VSS VSS BB64 H71 VSS VSS R13
AD62 VSS VSS AN28 AW18 VSS VSS BB67 J11 VSS VSS R6
AD8 VSS VSS AN30 AW21 VSS VSS BB70 J13 VSS VSS T15
AE64 VSS VSS AN32 AW23 VSS VSS C1 J25 VSS VSS T17
AE65 VSS VSS AN33 AW26 VSS VSS C25 J28 VSS VSS T18
AE66 VSS VSS AN35 AW28 VSS VSS C5 J32 VSS VSS T2
AE67 VSS VSS AN37 AW30 VSS VSS D10 J35 VSS VSS T21
AE68 VSS VSS AN38 AW32 VSS VSS D11 J38 VSS VSS T4
AE69 VSS VSS AN40 AW34 VSS VSS D14 J42 VSS VSS U10
2 VSS VSS VSS VSS VSS VSS 2
AF1 AN42 AW36 D18 J8 U63
AF10 VSS VSS AN58 AW38 VSS VSS D22 K16 VSS VSS U64
AF15 VSS VSS AN63 AW41 VSS VSS D25 K18 VSS VSS U66
AF17 VSS VSS AP10 AW43 VSS VSS D26 K22 VSS VSS U67
AF2 VSS VSS AP18 AW45 VSS VSS D30 K61 VSS VSS U69
AF4 VSS VSS AP20 AW47 VSS VSS D34 K63 VSS VSS U70
AF63 VSS VSS AP23 AW49 VSS VSS D39 K64 VSS VSS V16
AG16 VSS VSS AP28 AW51 VSS VSS D44 K65 VSS VSS V17
AG17 VSS VSS AP32 AW53 VSS VSS D45 K66 VSS VSS V18
AG18 VSS VSS AP35 AW55 VSS VSS D47 K67 VSS VSS W13
AG19 VSS VSS AP38 AW57 VSS VSS D48 K68 VSS VSS W6
AG20 VSS VSS AP42 AW6 VSS VSS D53 K70 VSS VSS W9
AG21 VSS VSS AP58 AW60 VSS VSS D58 K71 VSS VSS Y17
AG71 VSS VSS AP63 AW62 VSS VSS D6 L11 VSS VSS Y19
AH13 VSS VSS AP68 AW64 VSS VSS D62 L16 VSS VSS Y20
AH6 VSS VSS AP70 AW66 VSS VSS D66 L17 VSS VSS Y21
AH63 VSS VSS AR11 AW8 VSS VSS D69 VSS VSS
AH64 VSS VSS AR15 AY66 VSS VSS E11
AH67 VSS VSS AR16 B10 VSS VSS E15 18 OF 20
AJ15 VSS VSS AR20 B14 VSS VSS E18
AJ18 VSS VSS AR23 B18 VSS VSS E21 SKL-U_BGA1356
AJ20 VSS VSS AR28 B22 VSS VSS E46 @
AJ4 VSS VSS AR35 B30 VSS VSS E50
AK11 VSS VSS AR42 B34 VSS VSS E53
AK16 VSS VSS AR43 B39 VSS VSS E56
AK18 VSS VSS AR45 B44 VSS VSS E6
AK21 VSS VSS AR46 B48 VSS VSS E65
AK22 VSS VSS AR48 B53 VSS VSS E71
AK27 VSS VSS AR5 B58 VSS VSS F1
3 VSS VSS VSS VSS 3
AK63 AR50 B62 F13
AK68 VSS VSS AR52 B66 VSS VSS F2
AK69 VSS VSS AR53 B71 VSS VSS F22
AK8 VSS VSS AR55 BA1 VSS VSS F23
AL2 VSS VSS AR58 BA10 VSS VSS F27
AL28 VSS VSS AR63 BA14 VSS VSS F28
AL32 VSS VSS AR8 BA18 VSS VSS F32
AL35 VSS VSS AT2 BA2 VSS VSS F33
AL38 VSS VSS AT20 BA23 VSS VSS F35
AL4 VSS VSS AT23 BA28 VSS VSS F37
AL45 VSS VSS AT28 BA32 VSS VSS F38
AL48 VSS VSS AT35 BA36 VSS VSS F4
AL52 VSS VSS AT4 F68 VSS VSS F40
AL55 VSS VSS AT42 BA45 VSS VSS F42
AL58 VSS VSS AT56 VSS VSS BA41
AL64 VSS VSS AT58 VSS
VSS VSS
16 OF 20 17 OF 20
SKL-U_BGA1356 SKL-U_BGA1356
@ @

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(11/12)GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 16 of 60
A B C D E
 A B C D E

1 1

UC1S SKL-U

Rev_0.53
RESERVED SIGNALS-1

6 CFG0 CFG0 E68 BB68 T156 @

CFG1 B67 CFG[0] RSVD_TP_BB68 BB69
6 CFG1 CFG[1] RSVD_TP_BB69 T157 @
6 CFG2 CFG2 D65
CFG3 D67 CFG[2] AK13
6 CFG3 CFG[3] RSVD_TP_AK13 T158 @
6 CFG4 CFG4 E70 AK12 T159 @
CFG5 C68 CFG[4] RSVD_TP_AK12
6 CFG5 CFG[5]
6 CFG6 CFG6 D68 BB2
CFG7 C67 CFG[6] RSVD_BB2 BA3
6 CFG7 CFG[7] RSVD_BA3
6 CFG8 CFG8 F71
CFG9 G69 CFG[8]
6 CFG9 CFG[9]
CFG Signals 6 CFG10 CFG10 F70
CFG[10] TP5
AU5 T162 @
6 CFG11 CFG11 G68 AT5 T163 @
(For Strap & XDP) CFG12 H70 CFG[11] TP6
6 CFG12 CFG[12]
6 CFG13 CFG13 G71
CFG14 H69 CFG[13] D5
6 CFG14 CFG[14] RSVD_D5
6 CFG15 CFG15 G70 D4
CFG[15] RSVD_D4 B2 UC1T SKL-U
CFG16 E63 RSVD_B2 C2
6 CFG16 CFG[16] RSVD_C2 Rev_0.53
6 CFG17 CFG17 F63 SPARE
CFG[17] B3
CFG18 E66 RSVD_B3 A3 AW69 F6
6 CFG18 CFG[18] RSVD_A3 RSVD_AW69 RSVD_F6
6 CFG19 CFG19 F66 AW68 E3
CFG[19] AW1 +1.8VALW _PRIM AU56 RSVD_AW68 RSVD_E3 C11
2 RSVD_AW1 RSVD_AU56 RSVD_C11 2
CFG_RCOMP E60 AW48 B11
CFG_RCOMP E1 C7 RSVD_AW48 RSVD_B11 A11
XDP_ITP_PMODE E8 RSVD_E1 E2 RC57 2 @ 1 +1.8VALW _PRIM_U11 U12 RSVD_C7 RSVD_A11 D12
6 XDP_ITP_PMODE ITP_PMODE RSVD_E2 RSVD_U12 RSVD_D12
0_0402_5% U11 C12
AY2 BA4 H11 RSVD_U11 RSVD_C12 F52
AY1 RSVD_AY2 RSVD_BA4 BB4 RSVD_H11 RSVD_F52
RSVD_AY1 RSVD_BB4 20 OF 20
1
D1 A4
D3 RSVD_D1 RSVD_A4 C4 CC79 SKL-U_BGA1356
RSVD_D3 RSVD_C4 @
1U_0402_6.3V6K
K46 BB5 2
RSVD_K46 TP4 T199 @ @
#544924 SKylake EDS 0.75 P.117 K45
RSVD_K45 CC79 near U11,U12 (<10 mm)
‧RSVD - these signals should not be connected RSVD_A69
A69
‧RSVD_TP - these signals should be routed to a test point AL25
RSVD_AL25 RSVD_B69
B69 14MOW52, Connect U11, U12 to
‧RSVD_NCTF - these signals are non-critical to function AL27 1.8V for Cannonlake-U PCH
RSVD_AL27 AY3 RC182 1 @ 2 0_0402_5%
and may be left un-connected RSVD_AY3 compatibility
C71
B70 RSVD_C71 D71
RSVD_B70 RSVD_D71 C70
F60 RSVD_C70
RSVD_F60 C54
A52 RSVD_C54 D54
RSVD_A52 RSVD_D54

T213 @ BA70
RSVD_TP_BA70 TP1
AY4 T214 @ For 2+3e Solution
T215 @ BA68 BB3 T216 @
RSVD_TP_BA68 TP2
PM_ZVM#
J71 AY71 RC183 1 @ 2 0_0402_5% Zero Voltage Mode: Control Signal to OPC
J68 RSVD_J71 VSS_AY71 AR56 PM_ZVM#
RSVD_J68 ZVM# T225 @ VR, when low OPC VR output is 0V.
3 3
T220 @ F65 AW71 T221 @
G65 VSS_F65 RSVD_TP_AW71 AW70 PM_MSM#
T222 @ VSS_G65 RSVD_TP_AW70 T223 @ Minimum Speed Mode: Control signal to
F61 AP56 PM_MSM# T230 @ +1.0V_VCCST VccEOPIO VR (connected only in 2 VR
E61 RSVD_F61 MSM# C64 solution for OPC).
RSVD_E61 PROC_SELECT#
19 OF 20 SKL_CNL# 1 @ 2
RC184 100K_0402_5%
SKL-U_BGA1356 PROC_SELECT#
@ Processor Select: This pin is for
compatibility with future platforms. It should
Follow 544669_SKL_U_DDR3L_RVP7_schematic_rev1.0 NC with Skylake

CFG_RCOMP 1 2
RC185 49.9_0402_1%

CFG4 1 2
RC193 1K_0402_1%

4 4
Display Port Presence Strap

1 : Disabled; No Physical Display Port

CFG4 attached to Embedded Display Port
Security Classification Compal Secret Data Compal Electronics, Inc.
0 : Enabled; An external Display Port device is Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title
connected to the Embedded Display Port
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SKL-U(12/12)RSVD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 17 of 60
A B C D E
 A B C D E

+1.35V_VDDQ

7 DDR_A_DQS#[0..7]
+0.675V_A_VREFDQ +0.675V_DDRA_VREFDQ
Reverse Type

1
10mils

1.8K_0402_1%
JDIMM1
1 2

RD9
7 DDR_A_D[0..63]
3 VREF_DQ VSS DDR_A_D1
4
DDR_A_D0 5 VSS DQ4 6 DDR_A_D5 2-3A to 1 DIMMs/channel
7 DDR_A_DQS[0..7] DDR_A_D4 DQ0 DQ5
RD10 1 7 8

2
2_0402_1% 9 DQ1 VSS 10 DDR_A_DQS#0 +1.35V_VDDQ
2 1 CD1 11 VSS DQS0# 12 DDR_A_DQS0
7 DDR_A_MA[0..15] DM0 DQS0
1 .1U_0402_16V7K 13 14
DDR_A_BS0 2 DDR_A_D6 15 VSS VSS 16 DDR_A_D3
7 DDR_A_BS0 DQ2 DQ6

1
DDR_A_BS1 CD21 DDR_A_D7 17 18 DDR_A_D2
7 DDR_A_BS1 DQ3 DQ7

1
DDR_A_BS2 19 20

1.8K_0402_1%
0.022U_0402_16V7K RD1
7 DDR_A_BS2 DDR_A_WE# 2 DDR_A_D9 21 VSS VSS 22 DDR_A_D13

RD11
470_0402_5%
1 7 DDR_A_WE# DDR_A_CAS# DDR_A_D8 DQ8 DQ12 DDR_A_D12 1
23 24
7 DDR_A_CAS# DQ9 DQ13

1
DDR_A_RAS# 25 26
7 DDR_A_RAS# VSS VSS

2
RD12 DDR_A_DQS#1 27 28 From CPU to CHB

2
DDR_A_DQS1 29 DQS1# DM1 30 DDR_DRAMRST#
24.9_0402_1% DQS1 RESET# DDR_DRAMRST# 7,19
DDR_A_CLK0 31 32
7 DDR_A_CLK0 DDR_A_CLK#0 DDR_A_D11 VSS VSS DDR_A_D10
33 34 1
7 DDR_A_CLK#0

2
DDR_A_CLK1 DDR_A_D15 35 DQ10 DQ14 36 DDR_A_D14
7 DDR_A_CLK1 DDR_A_CLK#1 37 DQ11 DQ15 38 CD3
7 DDR_A_CLK#1 DDR_A_D20 VSS VSS DDR_A_D21
39 40 .1U_0402_16V7K
DDR_A_D17 41 DQ16 DQ20 42 DDR_A_D19 2
DDR_A_CKE0 Place near to SO-DIMM connector. 43 DQ17 DQ21 44
@
7 DDR_A_CKE0 DDR_A_CKE1 DDR_A_DQS#2 45 VSS VSS 46
7 DDR_A_CKE1 DDR_A_CS#0 DDR_A_DQS2 47 DQS2# DM2 48
7 DDR_A_CS#0 DDR_A_CS#1 DQS2 VSS DDR_A_D16
7 DDR_A_CS#1
49
VSS DQ22
50 CAD NOTE
DDR_A_D23 51 52 DDR_A_D22
DDR_A_D18 DQ18 DQ23 PLACE THE CAP NEAR TO
53 54 DIMM RESET PIN
SOC_SMBDATA 55 DQ19 VSS 56 DDR_A_D24
8,19,41 SOC_SMBDATA SOC_SMBCLK DDR_A_D29 VSS DQ28 DDR_A_D25
8,19,41 SOC_SMBCLK
57
DQ24 DQ29
58 2015MOW02, Can't install Cap on DRAMRST
DDR_A_D28 59 60
61 DQ25 VSS 62 DDR_A_DQS#3
DDR_A_ODT0 63 VSS DQS3# 64 DDR_A_DQS3
7 DDR_A_ODT0 DDR_A_ODT1 65 DM3 DQS3 66
7 DDR_A_ODT1 DDR_A_D30 VSS VSS DDR_A_D26
67 68
DDR_A_D31 69 DQ26 DQ30 70 DDR_A_D27
71 DQ27 DQ31 72
+1.35V_VDDQ VSS VSS +1.35V_VDDQ
Note:
Layout Note: Check voltage tolerance of DDR_A_CKE0 DDR_A_CKE1
73 74
Place near JDIMM1 VREF_DQ at the DIMM socket 75 CKE0 CKE1 76
77 VDD VDD 78 DDR_A_MA15
DDR_A_BS2 79 NC A15 80 DDR_A_MA14
2 81 BA2 A14 82 2
DDR_A_MA12 83 VDD VDD 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
+1.35V_VDDQ 87 A9 A7 88
DDR_A_MA8 89 VDD VDD 90 DDR_A_MA6
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA3 VDD VDD DDR_A_MA2
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

95 96
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
1 1 1 1 1 1 A1 A0
@ @ @ @ 99 100
DDR_A_CLK0 VDD VDD DDR_A_CLK1
CD4

CD5

CD6

CD7

CD8

CD9

101 102
DDR_A_CLK#0 103 CK0 CK1 104 DDR_A_CLK#1
2 2 2 2 2 2 105 CK0# CK1# 106
DDR_A_MA10 107 VDD VDD 108 DDR_A_BS1
DDR_A_BS0 109 A10/AP BA1 110 DDR_A_RAS#
111 BA0 RAS# 112
DDR_A_WE# 113 VDD VDD 114 DDR_A_CS#0
DDR_A_CAS# 115 W E# S0# 116 DDR_A_ODT0
117 CAS# ODT0 118
DDR_A_MA13 119 VDD VDD 120 DDR_A_ODT1 +0.675V_DDRA_VREFCA +0.675V_DDR_VREFCA
+1.35V_VDDQ DDR_A_CS#1 121 A13 ODT1 122
123 S1# NC 124
Follow MA51 VDD VDD 10mils
125 126 RD8 1 @ 2
TEST VREF_CA
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

127 128 0_0402_5%

DDR_A_D37 129 VSS VSS 130 DDR_A_D33
1 DDR_A_D32 DQ32 DQ36 DDR_A_D36
@ @ 131 132 1
+ CD16 133 DQ33 DQ37 134
1 1 1 1 1 1 1 1 DDR_A_DQS#4 VSS VSS
CD10

CD11

CD12

CD13

CD14

CD19

CD15

CD20

330U_D2_2V_Y 135 136 CD17

@ DDR_A_DQS4 137 DQS4# DM4 138
DQS4 VSS .1U_0402_16V7K
2 139 140 DDR_A_D35 2
2 2 2 2 2 2 2 2 SGA00009S00 DDR_A_D39 141 VSS DQ38 142 DDR_A_D34
330U 2V H1.9 DDR_A_D38 143 DQ34 DQ39 144
3
9mohm POLY 145 DQ35 VSS 146 DDR_A_D41 3
DDR_A_D45 147 VSS DQ44 148 DDR_A_D40
DDR_A_D44 149 DQ40 DQ45 150
151 DQ41 VSS 152 DDR_A_DQS#5
153 VSS DQS5# 154 DDR_A_DQS5
155 DM5 DQS5 156
DDR_A_D46 157 VSS VSS 158 DDR_A_D42
DDR_A_D47 DQ42 DQ46 DDR_A_D43
Layout Note: Layout Note: 159
DQ43 DQ47
160
161 162
Place near JDIMM1.203,204 Place near JDIMM1.199 DDR_A_D48 163 VSS VSS 164 DDR_A_D52
DDR_A_D53 165 DQ48 DQ52 166 DDR_A_D49
167 DQ49 DQ53 168
DDR_A_DQS#6 169 VSS VSS 170
DDR_A_DQS6 171 DQS6# DM6 172
173 DQS6 VSS 174 DDR_A_D51
+0.675VS_VTT +3VS DDR_A_D54 175 VSS DQ54 176 DDR_A_D50
DDR_A_D55 177 DQ50 DQ55 178
179 DQ51 VSS 180 DDR_A_D56
DDR_A_D58 181 VSS DQ60 182 DDR_A_D57
DDR_A_D59 DQ56 DQ61
1U_0402_6.3V6K

1U_0402_6.3V6K

183 184
185 DQ57 VSS 186 DDR_A_DQS#7
1 1 1 VSS DQS7# DDR_A_DQS7
187 188
DM7 DQS7
CD24

CD25

CD27 189 190

DDR_A_D60 191 VSS VSS 192 DDR_A_D62
.1U_0402_16V7K DQ58 DQ62
2 2 2 DDR_A_D61 193 194 DDR_A_D63
+0.675VS_VTT +3VS 195 DQ59 DQ63 196 +0.675VS_VTT
197 VSS VSS 198
199 SA0 EVENT# 200 SOC_SMBDATA
201 VDDSPD SDA 202 SOC_SMBCLK
203 SA1 SCL 204 +0.675VS_VTT
VTT VTT
4 205 206 4
207 GND1 GND2 208
BOSS1 BOSS2

BELLW_80001-1021
SP07000P700
Interleaved Memory
CONN@
Compal Secret Data
Security Classification
2014/11/10 2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR3L_DIMMA
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 18 of 60
A B C D E
 A B C D E

7 DDR_B_DQS#[0..7]
+1.35V_VDDQ
+0.675V_DDRB_VREFDQ Standard Type
10mils

1.8K_0402_1%
JDIMM2

1
1 2
7 DDR_B_D[0..63] +0.675V_B_VREFDQ 3 VREF_DQ VSS1 4 DDR_B_D12 2-3A to 1 DIMMs/channel

RD13
DDR_B_D11 5 VSS2 DQ4 6 DDR_B_D8
7 DDR_B_DQS[0..7] DDR_B_D13 DQ0 DQ5
1 7 8
RD14 9 DQ1 VSS3 10 DDR_B_DQS#1

2
2_0402_1% CD28 11 VSS4 DQS#0 12 DDR_B_DQS1
7 DDR_B_MA[0..15] 2 1 DM0 DQS0
.1U_0402_16V7K 13 14
DDR_B_BS0 2 DDR_B_D15 15 VSS5 VSS6 16 DDR_B_D9
7 DDR_B_BS0 DDR_B_BS1
1 DDR_B_D14 DQ2 DQ6 DDR_B_D10
17 18
7 DDR_B_BS1 DDR_B_BS2 DQ3 DQ7
19 20

1.8K_0402_1%
CD31
7 DDR_B_BS2 VSS7 VSS8

1
DDR_B_WE# 0.022U_0402_16V7K DDR_B_D5 21 22 DDR_B_D4
1 7 DDR_B_WE# DDR_B_CAS# 2 DDR_B_D1 DQ8 DQ12 DDR_B_D0 1
23 24

RD15
7 DDR_B_CAS# DQ9 DQ13

1
DDR_B_RAS# 25 26
7 DDR_B_RAS# DDR_B_DQS#0 VSS9 VSS10
RD16 27 28
DDR_B_DQS0 29 DQS#1 DM1 30 DDR_DRAMRST#
24.9_0402_1% DDR_DRAMRST# 7,18 From CPU

2
DDR_B_CLK0 31 DQS1 RESET# 32
7 DDR_B_CLK0 DDR_B_CLK#0 DDR_B_D3 VSS11 VSS12 DDR_B_D6
33 34 1
7 DDR_B_CLK#0

2
DDR_B_CLK1 DDR_B_D2 35 DQ10 DQ14 36 DDR_B_D7 CD30
7 DDR_B_CLK1 DDR_B_CLK#1 DQ11 DQ15
37 38 .1U_0402_16V7K
7 DDR_B_CLK#1 DDR_B_D16 39 VSS13 VSS14 40 DDR_B_D21 @
DDR_B_D17 41 DQ16 DQ20 42 DDR_B_D20 2
DDR_B_CKE0 DQ17 DQ21
7 DDR_B_CKE0 DDR_B_CKE1 Place near to SO-DIMM connector. DDR_B_DQS#2
43
45 VSS15 VSS16
44
46
7 DDR_B_CKE1 DDR_B_CS#0 DDR_B_DQS2 47 DQS#2 DM2 48
7 DDR_B_CS#0 DDR_B_CS#1 DQS2 VSS17 DDR_B_D19
49 50
7 DDR_B_CS#1 DDR_B_D18 VSS18 DQ22 DDR_B_D23
51
DQ18 DQ23
52 CAD NOTE
DDR_B_D22 53 54
SOC_SMBDATA DQ19 VSS19 DDR_B_D29
PLACE THE CAP NEAR TO
55 56 DIMM RESET PIN
8,18,41 SOC_SMBDATA SOC_SMBCLK DDR_B_D24 57 VSS20 DQ28 58 DDR_B_D28
8,18,41 SOC_SMBCLK DDR_B_D25 DQ24 DQ29
59
DQ25 VSS21
60 2015MOW02, Can't install Cap on DRAMRST
61 62 DDR_B_DQS#3
DDR_B_ODT0 63 VSS22 DQS#3 64 DDR_B_DQS3
7 DDR_B_ODT0 DDR_B_ODT1 65 DM3 DQS3 66
7 DDR_B_ODT1 DDR_B_D27 VSS23 VSS24 DDR_B_D30
67 68
DDR_B_D26 69 DQ26 DQ30 70 DDR_B_D31
71 DQ27 DQ31 72
VSS25 VSS26
Layout Note: +1.35V_VDDQ +1.35V_VDDQ
Place near JDIMM2
DDR_B_CKE0 73 74 DDR_B_CKE1
75 CKE0 CKE1 76
77 VDD1 VDD2 78 DDR_B_MA15
2 DDR_B_BS2 79 NC1 A15 80 DDR_B_MA14 2
81 BA2 A14 82
+1.35V_VDDQ DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA8 VDD5 VDD6 DDR_B_MA6
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

89 90
@1 @1 @1 @1 DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
1 1 A5 A4
93 94
DDR_B_MA3 VDD7 VDD8 DDR_B_MA2
CD32

CD33

CD34

CD35

CD36

CD37

95 96
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
2 2 2 2 2 2 99 A1 A0 100
DDR_B_CLK0 101 VDD9 VDD10 102 DDR_B_CLK1
DDR_B_CLK#0 103 CK0 CK1 104 DDR_B_CLK#1
105 CK0# CK1# 106
DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1 +1.35V_VDDQ
DDR_B_BS0 109 A10/AP BA1 110 DDR_B_RAS#
111 BA0 RAS# 112
VDD13 VDD14

1
DDR_B_WE# DDR_B_CS#0

1.8K_0402_1%
113 114
+1.35V_VDDQ DDR_B_CAS# W E# S0# DDR_B_ODT0

RD18
115 116
117 CAS# ODT0 118 +0.675V_DDR_VREFCA
DDR_B_MA13 119 VDD15 VDD16 120 DDR_B_ODT1 +0.675V_VREFCA
DDR_B_CS#1 A13 ODT1 +0.675V_DDRB_VREFCA RD17
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

121 122

2
123 S1# NC2 124
VDD17 VDD18 10mils 0_0402_5%
125 126 1 @ 2 RD19 1 2
@1 @1 127 NCTEST VREF_CA 128 2_0402_1%
1 1 1 1 1 1 DDR_B_D36 VSS27 VSS28 DDR_B_D32
1
CD38

CD39

CD40

CD41

CD42

CD43

CD44

CD45

129 130
DDR_B_D37 131 DQ32 DQ36 132 DDR_B_D33 CD49
DQ33 DQ37

1
1.8K_0402_1%
133 134 1 0.022U_0402_16V7K
2 2 2 2 2 2 2 2 DDR_B_DQS#4 VSS29 VSS30 2

RD20
135 136
DDR_B_DQS4 137 DQS#4 DM4 138 CD47
DQS4 VSS31

1
139 140 DDR_B_D39
VSS32 DQ38 .1U_0402_16V7K
DDR_B_D35 141 142 DDR_B_D38 2 RD21

2
3 DDR_B_D34 143 DQ34 DQ39 144 3
DQ35 VSS33 24.9_0402_1%
145 146 DDR_B_D41
DDR_B_D45 147 VSS34 DQ44 148 DDR_B_D40

2
DDR_B_D44 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#5
153 VSS36 DQS#5 154 DDR_B_DQS5
155 DM5 DQS5 156
Layout Note: Layout Note: DDR_B_D43 VSS37 VSS38 DDR_B_D47 Place near to SO-DIMM connector.
157 158
Place near JDIMM2.203,204 Place near JDIMM2.199 DDR_B_D42 159 DQ42 DQ46 160 DDR_B_D46
161 DQ43 DQ47 162
DDR_B_D49 163 VSS39 VSS40 164 DDR_B_D52
DDR_B_D48 165 DQ48 DQ52 166 DDR_B_D53
167 DQ49 DQ53 168
DDR_B_DQS#6 169 VSS41 VSS42 170
+0.675VS_VTT +3VS DDR_B_DQS6 171 DQS#6 DM6 172
173 DQS6 VSS43 174 DDR_B_D54
DDR_B_D50 175 VSS44 DQ54 176 DDR_B_D51
DDR_B_D55 177 DQ50 DQ55 178
DQ51 VSS45 DDR_B_D61
1U_0402_6.3V6K

1U_0402_6.3V6K

179 180
2.2U_0402_6.3V6M

DDR_B_D56 181 VSS46 DQ60 182 DDR_B_D60

1 1 DQ56 DQ61
1

DDR_B_D57 183 184

DQ57 VSS47 DDR_B_DQS#7
CD52

CD53

185 186
CD55

@ 187 VSS48 DQS#7 188 DDR_B_DQS7

2

2 2 189 DM7 DQS7 190

DDR_B_D59 191 VSS49 VSS50 192 DDR_B_D62
DDR_B_D58 193 DQ58 DQ62 194 DDR_B_D63
+3VS +3VS 195 DQ59 DQ63 196 +0.675VS_VTT
197 VSS51 VSS52 198
199 SA0 EVENT# 200 SOC_SMBDATA
R229 2 1 10K_0402_5% DDR_B_SA1 201 VDDSPD SDA 202 SOC_SMBCLK
203 SA1 SCL 204 +0.675VS_VTT
+0.675VS_VTT VTT1 VTT2
4 4
205 206
G1 G2
LCN_DAN06-K4406-0100
CONN@
SP07000N300
Interleaved Memory
Compal Secret Data
Security Classification
2014/11/10 2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
DDR3L_DIMMB Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 19 of 60
A B C D E
 A B C D E

Note: NGC6 3VSDGPU_MAIN_EN is no function GPIO I/O USAGE

UGPU1A

Part 1 of 6 +3VSDGPU_AON
GC6_FB_EN GC6_FB_EN 11 GPIO0 I GC6_FB_EN
12 PCIE_CTX_C_GRX_P1 AG6 C6 RP2000
AG7 PEX_RX0 GPIO0 B2 10K_0804_8P4R_5%
12 PCIE_CTX_C_GRX_N1 PEX_RX0_N GPIO1 GPIO8_OVERT
12 PCIE_CTX_C_GRX_P2 AF7 D6 8 1 GPIO1 O MEM_VDD_CTL
AE7 PEX_RX1 GPIO2 C7 GPIO9_ALERT 7 2
12 PCIE_CTX_C_GRX_N2 PEX_RX1_N GPIO3
AE9 F9 6 3
12 PCIE_CTX_C_GRX_P3 PEX_RX2 GPIO4 3VSDGPU_MAIN_EN 3VSDGPU_MAIN_EN 42,55 ACIN_BUF
AF9 A3 5 4 GPIO2 O LCD_BL_PWM
12 PCIE_CTX_C_GRX_N3 PEX_RX2_N GPIO5 GPU_EVENT#_1 GPU_EVENT#_1
AG9 A4 2 1
12 PCIE_CTX_C_GRX_P4 PEX_RX3 GPIO6 GPU_EVENT# 11
AG10 B6 D2011 VGA@
12 PCIE_CTX_C_GRX_N4 PEX_RX3_N GPIO7 GPIO8_OVERT
AF10 A6 RB751V-40_SOD323-2 GPIO3 O LCD_VCC
AE10 NC OVERT F8 GPIO9_ALERT GC6@
AE12 NC GPIO9 C5 +3VSDGPU_AON
1 NC GPIO10 DGPU_VID 1
AF12 E7 RP2001 GPIO4 O LCD_BL_EN
AG12 NC GPIO11 D7 ACIN_BUF DGPU_VID 55 10K_0804_8P4R_5%
AG13 NC GPIO12 B4 PSI ACIN_BUF 2 1 GPU_EVENT#_1 8 1

GPIO
AF13 NC GPIO13 B3 PSI 55 D2000 DGPU_AC_DETECT 11,38 3VSDGPU_MAIN_EN 7 2
AE13 NC GPIO14 C3 RB751V-40_SOD323-2 GPU_PEX_RST_HOLD# 6 3
GPIO5 O 3V3_MAIN_EN
AE15 NC GPIO15 D5 VGA@ GC6_FB_EN 5 4
AF15 NC GPIO16 D4
AG15 NC GPIO17 C2 GC6@
GPIO6 I GPU_EVENT#
AG16 NC GPIO18 F7
AF16 NC GPIO19 E6
AE16 NC GPIO20 C4 GPU_PEX_RST_HOLD# GPIO7 O 3D Vision
AE18 NC GPIO21 +3VSDGPU_AON
AF18 NC AB6
AG18 NC PEX_WAKE_NC GPIO8 I SYS_PEX_RST_MON#
AG19 NC SYS_PEX_RST_MON# R2056 2 @ 1 10K_0402_5%
AF19 NC
AE19 NC I2CS_SDA R2000 1 VGA@ 2 1.8K_0402_1%
GPIO9 I/O ALERT
AE21 NC AG3
AF21 NC NC AF4 I2CS_SCL R2001 1 VGA@ 2 1.8K_0402_1%
AG21 NC NC AF3
GPIO10 O MEM_VREF_CTL
AG22 NC NC
NC PSI R2052 2 VGA@ 1 10K_0402_5%
PCIE_CRX_C_GTX_P1 GPIO11 O PWM_VID
12 PCIE_CRX_GTX_P1 CV11 VGA@ 1 2 0.22U_0402_16V7K AC9 AE3
PEX_TX0 NC

DACs
CV12 VGA@ 1 2 0.22U_0402_16V7K PCIE_CRX_C_GTX_N1 AB9 AE4
12 PCIE_CRX_GTX_N1 PCIE_CRX_C_GTX_P2 PEX_TX0_N NC
12 PCIE_CRX_GTX_P2 CV13 VGA@ 1 2 0.22U_0402_16V7K AB10
CV14 VGA@ 1 2 0.22U_0402_16V7K PCIE_CRX_C_GTX_N2 AC10 PEX_TX1
12 PCIE_CRX_GTX_N2
VGA@ 1 2 PCIE_CRX_C_GTX_P3 AD11 PEX_TX1_N GPIO12 I PWR_LEVEL

PCI EXPRESS
12 PCIE_CRX_GTX_P3 CV15 0.22U_0402_16V7K
CV16 VGA@ 1 2 0.22U_0402_16V7K PCIE_CRX_C_GTX_N3 AC11 PEX_TX2 W5 PLTRST_VGA#
12 PCIE_CRX_GTX_N3 PCIE_CRX_C_GTX_P4 PEX_TX2_N NC
12 PCIE_CRX_GTX_P4 CV17 VGA@ 1 2 0.22U_0402_16V7K AC12 AE2 GPIO13 O PSI
CV18 VGA@ 1 2 0.22U_0402_16V7K PCIE_CRX_C_GTX_N4 AB12 PEX_TX3 TSEN_VREF AF2
12 PCIE_CRX_GTX_N4 PEX_TX3_N NC
AB13
NC

2
AC13 GPIO14 I HPD_A
2 AD14 NC 2
AC14 NC GPIO8_OVERT 1 6
NC GPU_OVERT 38
AC15 VGA@ GPIO15 I HPD_C
AB15 NC DMN66D0LDW-7_SOT363-6
AB16 NC B7 R2003 1 VGA@ 2 1.8K_0402_1% Q2000A
AC16 NC I2CA_SCL A7 R2004 1 VGA@ 2 1.8K_0402_1% GPIO16 RESERVED
AD17 NC I2CA_SDA
AC17 NC C9 R2005 1 VGA@ 2 1.8K_0402_1% PLTRST_VGA#
AC18 NC I2CB_SCL C8 R2006 1 VGA@ 2 1.8K_0402_1%
NC I2CB_SDA GPIO17 I HPD_D
I2C
AB18
NC

5
AB19 A9 R2007 1 VGA@ 2 1.8K_0402_1%
AC19 NC I2CC_SCL B9 R2008 1 VGA@ 2 1.8K_0402_1%
AD20 NC I2CC_SDA GPIO9_ALERT 4 3
GPIO18 I HPD_E
NC I2CS_SCL GPU_ALERT 38
AC20 D9 VGA@
AC21 NC I2CS_SCL D8 I2CS_SDA DMN66D0LDW-7_SOT363-6
AB21 NC I2CS_SDA GPIO19 I HPD_F or HPD_B
Q2000B
AD23 NC
AE23 NC Place Under L6 R2023
AF24 NC C2000 0_0402_5%
GPIO20 Reserved
AE24 NC L6 +PLLVDD 1 2 .1U_0402_16V7K PLTRST_VGA# 1 @ 2 PLTRST_VGA#_R
AG24 NC PLLVDD M6 VGA@
AG25 NC SP_PLLVDD 1 2 0_0402_5%
GPIO21 O GPU_PEX_RST_HOLD#
+3VSDGPU_MAIN R2024 @
NC N6 C2001
NC +GPU_PLLVDD 1 2 .1U_0402_16V7K GPIO22

2
VGA@
+3VSDGPU_AON 1 VGA@ 2 AE8
10 CLK_PCIE_P0 PEX_REFCLK I2CS_SCL
R2009 10K_0402_5% AD8 1 6 GPIO23
PEG_CLKREQ# 10 CLK_PCIE_N0 PEX_REFCLK_N SOC_SML1CLK 8,31,38
AC6 Place Under M6 VGA@
10 PEG_CLKREQ# PEX_CLKREQ_N DMN66D0LDW-7_SOT363-6
PEX_TSTCLK_OUT+ AF22
CLK

2 @ 1 PEX_TSTCLK_OUT- AE22 PEX_TSTCLK_OUT C11 XTALIN

Q2001A GPIO24
R2010 200_0402_1% PEX_TSTCLK_OUT_N XTAL_IN B10 XTALOUT
XTAL_OUT
3 PLTRST_VGA# AC7 A10 XTAL_SSIN R2012 1 VGA@ 2 10K_0402_5% 3
2 VGA@ 1 PEX_TREMP AF25 PEX_RST_N XTAL_SSIN C10 XTAL_OUTBUFF R2013 1 VGA@ 2 10K_0402_5% PLTRST_VGA#_R
R2011 2.49K_0402_1% PEX_TERMP XTAL_OUTBUFF

5
GM108-ES-S-A1_FCBGA595
@ I2CS_SDA 4 3
SOC_SML1DATA 8,31,38
VGA@
DMN66D0LDW-7_SOT363-6
Q2001B

SM010019400 3000ma 33ohm@100mhz DCR 0.05

38mA +1.05VSDGPU
D2001 VGA@
GC6_FB_EN 2 +PLLVDD 1 2 27MHZ_10PF_7V27000023
GC6 2.0 function 1 1.5VS_DGPU_PWR_EN
1.5VS_DGPU_PWR_EN 42,53 L2000 CHILISIN PBY160808T-330Y-N
3 GC6@ 1 XTALOUT 3 1 XTALIN
C2003 3 1
PLL_VDD
1

BAV70W_SOT323-3 VGA@ GND GND

10P_0402_50V8J

10P_0402_50V8J
0.1Ux1, 22Ux1 1 1
R2014 30ohm(ESR0.05)x1 22U_0603_6.3V6M VGA@ VGA@ X2000 VGA@
R2016 200K_0402_1% 2 4 2
0_0402_5% GC6@ Near GPU C2004 C2005
1 NGC6@ 2 2 2
10,42,54,55 DGPU_PWROK
2

SM01000AG00 2A 300ohm@100mhz DCR 0.1

17mA
Crystals must have a max ESR of 80 ohm
+3VSDGPU_AON VGA@
U2001 +GPU_PLLVDD 1 2
5

VGA@ L2001 HCB1608KF-301T20_2P

PLT_RST# 2 1
P

10,38,39 PLT_RST# B
1

4SYS_PEX_RST_MON# C2007
DGPU_HOLD_RST# Y SYS_PEX_RST_MON# 22
1 C2006 VGA@
11 DGPU_HOLD_RST# A
2

1
G

4 10U_0603_6.3V6M 47U_0805_6.3V6M 4
2

MC74VHC1G08DFT2G_SC70-5 R2019 R2017 VGA@ 2

3

0_0402_5% 10K_0402_5% SP_PLLVDD+VID_PLLVDD Near GPU

NGC6@ VGA@ 0.1Ux2, 10Ux1,47Ux1
+3VSDGPU_AON
300ohm(ESR0.2)x1
1

U2002
5

GC6@
SYS_PEX_RST_MON# 2
Compal Secret Data Compal Electronics, Inc.
P

B 4 PLTRST_VGA# Security Classification

GPU_PEX_RST_HOLD# 1 Y
A Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title
G

R2018
MC74VHC1G08DFT2G_SC70-5 10K_0402_5% N16X PEG 1/9
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1 GC6@ 2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 20 of 60
A B C D E
 A B C D E

VRAM Interface
+1.5VSDGPU

RP33
CMDA23 1 8
A5MUB exchange 2 7
CMDA21 3 6 +1.5VSDGPU +1.5VSDGPU
4 5
UGPU1B VGA@ 2 2
100_0804_8P4R_5%
1 1
C2084 C2083
MDA[15..0] RP42 .1U_0402_16V7K .1U_0402_16V7K
25,26 MDA[15..0] 1 1
UGPU1 Part 2 of 6 CMDA24 1 8 @ @
MDA[31..16] CMDA[31..0] 25,26,27,28 A5MUB exchange 2 7
25,26 MDA[31..16]
MDA0 E18 C27 CMDA0 CMDA26 3 6
MDA[47..32] MDA1 F18 FBA_D00 FBA_CMD0 C26 CMDA1 4 5 +1.5VSDGPU +1.5VSDGPU
27,28 MDA[47..32] FBA_D01 FBA_CMD1
MDA2 E16 E24 CMDA2 VGA@
MDA[63..48] MDA3 F17 FBA_D02 FBA_CMD2 F24 CMDA3 100_0804_8P4R_5%
27,28 MDA[63..48] FBA_D03 FBA_CMD3 2 2
N16S-GT MDA4 D20 D27 CMDA4
SGT@ MDA5 D21 FBA_D04 FBA_CMD4 D26 CMDA5 RP43 C2086 C2085
F20 FBA_D05 FBA_CMD5 F25 1 8
SA000087F10 MDA6
FBA_D06 FBA_CMD6
CMDA6 CMDA10 .1U_0402_16V7K .1U_0402_16V7K
MDA7 E21 F26 CMDA7 A5MUB exchange 2 7 1 1
FBA_D07 FBA_CMD7 @ @
MDA8 E15 F23 CMDA8 CMDA22 3 6
UGPU1 MDA9 D15 FBA_D08 FBA_CMD8 G22 CMDA9 4 5
MDA10 F15 FBA_D09 FBA_CMD9 G23 CMDA10 VGA@ +1.5VSDGPU +1.5VSDGPU
MDA11 F13 FBA_D10 FBA_CMD10 G24 CMDA11 100_0804_8P4R_5%
MDA12 C13 FBA_D11 FBA_CMD11 F27 CMDA12
FBA_D12 FBA_CMD12 2 2
MDA13 B13 G25 CMDA13 RP44
MDA14 E13 FBA_D13 FBA_CMD13 G27 CMDA14 CMDA4 1 8 C2088 C2087
N16V-GM MDA15 D13 FBA_D14 FBA_CMD14 G26 CMDA15 A5MUB exchange 2 7
FBA_D15 FBA_CMD15 .1U_0402_16V7K .1U_0402_16V7K
VGM@ MDA16 B15 M24 CMDA16 CMDA12 3 6 1 1
FBA_D16 FBA_CMD16 @ @
SA000088R20 MDA17 C16 M23 CMDA17 4 5
MDA18 A13 FBA_D17 FBA_CMD17 K24 CMDA18 VGA@
MDA19 A15 FBA_D18 FBA_CMD18 K23 CMDA19 100_0804_8P4R_5%
MDA20 B18 FBA_D19 FBA_CMD19 M27 CMDA20
MDA21 A18 FBA_D20 FBA_CMD20 M26 CMDA21 RP45
MDA22 A19 FBA_D21 FBA_CMD21 M25 CMDA22 CMDA8 1 8
MDA23 C19 FBA_D22 FBA_CMD22 K26 CMDA23 A5MUB exchange 2 7
MDA24 B24 FBA_D23 FBA_CMD23 K22 CMDA24 CMDA14 3 6
MDA25 C23 FBA_D24 FBA_CMD24 J23 CMDA25 4 5
MDA26 A25 FBA_D25 FBA_CMD25 J25 CMDA26 VGA@
MDA27 A24 FBA_D26 FBA_CMD26 J24 CMDA27 100_0804_8P4R_5%
MDA28 A21 FBA_D27 FBA_CMD27 K27 CMDA28 PVT modify 01/13
2 MDA29 B21 FBA_D28 FBA_CMD28 K25 CMDA29 DQSA, DQSA# reverse RP46 2
MDA30 C20 FBA_D29 FBA_CMD29 J27 CMDA30 CMDA9 1 8
MDA31 C21 FBA_D30 FBA_CMD30 J26 CMDA31 2 7
MDA32 R22 FBA_D31 FBA_CMD31 A5MUB exchange CMDA29 3 6 +1.5VSDGPU +1.5VSDGPU
FBA_D32 DQMA[3..0] 25,26
MDA33 R24 D19 DQMA0 4 5
FBA_D33 FBA_DQM0

INTERFACE A
MDA34 T22 D14 DQMA1 VGA@ 2 2
MDA35 R23 FBA_D34 FBA_DQM1 C17 DQMA2 100_0804_8P4R_5%
MDA36 N25 FBA_D35 FBA_DQM2 C22 DQMA3 C2090 C2089
FBA_D36 FBA_DQM3 DQMA[7..4] 27,28
MDA37 N26 P24 DQMA4 RP47 .1U_0402_16V7K .1U_0402_16V7K

MEMORY
MDA38 N23 FBA_D37 FBA_DQM4 W24 DQMA5 CMDA5 1 8 1 1
FBA_D38 FBA_DQM5 @ @
MDA39 N24 AA25 DQMA6 A5MUB exchange 2 7
MDA40 V23 FBA_D39 FBA_DQM6 U25 DQMA7 CMDA13 3 6
NV 15x DG-06803-V03 MDA41
MDA42
V22
T23
FBA_D40
FBA_D41
FBA_DQM7
F19 DQSA#0
DQSA#[3..0] 25,26
4 5
VGA@
+1.5VSDGPU +1.5VSDGPU

MDA43 U22 FBA_D42 FBA_DQS_RN0 C14 DQSA#1 100_0804_8P4R_5%

FBA_D43 FBA_DQS_RN1 2 2
MDA44 Y24 A16 DQSA#2
MDA45 AA24 FBA_D44 FBA_DQS_RN2 A22 DQSA#3 RP48 C2091 C2092
FBA_D45 FBA_DQS_RN3 DQSA#[7..4] 27,28
MDA46 Y22 P25 DQSA#4 CMDA6 1 8 .1U_0402_16V7K .1U_0402_16V7K
MDA47 AA23 FBA_D46 FBA_DQS_RN4 W22 DQSA#5 A5MUB exchange 2 7 1 1
FBA_D47 FBA_DQS_RN5 @ @
MDA48 AD27 AB27 DQSA#6 CMDA7 3 6
MDA49 AB25 FBA_D48 FBA_DQS_RN6 T27 DQSA#7 4 5
MDA50 AD26 FBA_D49 FBA_DQS_RN7 VGA@ +1.5VSDGPU
FBA_D50 DQSA[3..0] 25,26
MDA51 AC25 E19 DQSA0 100_0804_8P4R_5%
MDA52 AA27 FBA_D51 FBA_DQS_WP0 C15 DQSA1
FBA_D52 FBA_DQS_WP1 2
MDA53 AA26 B16 DQSA2 RP49
MDA54 W26 FBA_D53 FBA_DQS_WP2 B22 DQSA3 CMDA27 1 8 C2093
FBA_D54 FBA_DQS_WP3 DQSA[7..4] 27,28
SM010019400 3000ma 33ohm@100mhz DCR 0.05 MDA55 Y25 R25 DQSA4 2 7 .1U_0402_16V7K
MDA56 R26 FBA_D55 FBA_DQS_WP4 W23 DQSA5 CMDA30 3 6 1
FBA_D56 FBA_DQS_WP5 @
MDA57 T25 AB26 DQSA6 4 5
MDA58 N27 FBA_D57 FBA_DQS_WP6 T26 DQSA7 VGA@
+1.05VSDGPU MDA59 R27 FBA_D58 FBA_DQS_WP7 100_0804_8P4R_5%
MDA60 V26 FBA_D59
VGA@
15+55mA MDA61 V27 FBA_D60 RP50
3 2 1 L2002 +FB_PLLAVDD MDA62 W27 FBA_D61 CMDA28 1 8 3
CHILISIN PBY160808T-330Y-N MDA63 W25 FBA_D62 A5MUB exchange 2 7
22U_0603_6.3V6M

VGA@ VGA@ VGA@ FBA_D63 D24 CMDA25 3 6

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

FBA_CLK0 CLKA0 25,26

1 1 1 1 F16 D25 4 5
FB_PLLAVDD_1 FBA_CLK0_N CLKA0# 25,26
P22 VGA@
C2008 FB_PLLAVDD_2 N22 100_0804_8P4R_5%
FBA_CLK1 CLKA1 27,28
VGA@ T97 @ D23 M22
C2011

C2010

C2009

2 2 2 2 FB_VREF_PROBE FBA_CLK1_N CLKA1# 27,28

RP51
D18 CMDA15 1 8
H22 FBA_WCK01 C18 A5MUB exchange 2 7
FB_DLLAVDD FBA_WCK01_N D17 CMDA11 3 6
Place Near GPU Place Under F16 P22 H22 1 VGA@ 2 FB_CLAMP F3 FBA_WCK23 D16 4 5
10K_0402_5% R2028 FB_CLAMP FBA_WCK23_N T24 VGA@
FBA_WCK45 U24 100_0804_8P4R_5%
60.4_0402_1% 1 @ 2 R2020FBA_CMD34 F22 FBA_WCK45_N V24
60.4_0402_1% 1 @ 2 R2022FBA_CMD35 J22 FBA_CMD34 FBA_WCK67 V25
change to 1.35VSDGPU +1.5VSDGPU FBA_CMD35 FBA_WCK67_N

GM108-ES-S-A1_FCBGA595
@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N16X VRAM 2/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 21 of 60
A B C D E
 A B C D E

UGPU1C MULTI LEVEL STRAPS

Part 3 of 6 F11
AC3 NC AD10 +3VSDGPU_AON +3VSDGPU_MAIN
AC4 NC NC AD7
Y4 NC NC B19 strap0 strap1 strap2 strap3 strap4
Y3 NC FBA_CMD32 V5
NC NC

1
AA3 V6
AA2 NC NC G1 R2029 R2030 R2031 R2032 R2033 R2035 R2036 R2037
AB1 NC NC G2 SGT@ @ @ @ @ @ @ @
NC NC

NC
AA1 G3 49.9K_0402_1% 4.99K_0402_1% 20K_0402_1% 4.99K_0402_1% 10K_0402_1% 30K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
AA4 NC NC G4

2
AA5 NC NC G5
1 NC NC 1
G6
NC G7 STRAP0
AB5 NC V1 STRAP1 ROM_SI
AB4 NC NC V2 STRAP2 ROM_SO
AB3 NC NC W1 STRAP3 ROM_SCLK
AB2 NC NC W2 STRAP4
AD3 NC NC W3
AD2 NC NC W4
NC NC

1
AE1
AD1 NC R2038 R2039 R2040 R2041 R2042 R2044 R2045 R2046
AD4 NC @ @ @ @ @ X76@ SGT@ SGT@
NC For GC62.0 use
AD5 D11 R2050 1 @ 2 10K_0402_5% N14x for CEC ,NC 4.99K_0402_1% 34.8K_0402_1% 15K_0402_1% 4.99K_0402_1% 10K_0402_1% 4.99K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
NC BUFRST_N
N15x for GPIO8

2
D10
T2 NC
T3 NC E9 SYS_PEX_RST_MON#
NC GPIO8 SYS_PEX_RST_MON# 20
T1
R1 NC E10
NC NC
GENERAL
R2
LVDS/TMDS

R3 NC F10
N2 NC NC
NC N16VGM Option Component N16SGT Option Component
N3
NC D1 STRAP0
STRAP0 D2 STRAP1 STRAP0 ---> R2029 2 VGM@1 45.3K_0402_1% SD034453280
V3 STRAP1 E4 STRAP2 STRAP1 ---> R2039 2 VGM@1 45.3K_0402_1% SD034453280
V4 NC STRAP2 E3 STRAP3 STRAP2 ---> R2031 2 VGM@1 10K_0402_1% SD034100280
U3 NC STRAP3 D3 STRAP4 STRAP3 ---> R2041 2 VGM@1 4.99K_0402_1% SD034499180
U4 NC STRAP4 C1 STRAP4 ---> R2042 2 VGM@1 45.3K_0402_1% SD034453280
T4 NC NC ROM_SO ---> R2036 2 VGM@1 4.99K_0402_1% SD034499180
T5 NC ROM_SCLK---> R2037 2 VGM@1 4.99K_0402_1% SD034499180
R4 NC F6 MULTI_STRAP_REF0_GND 1 VGA@ 2
R5 NC MULTI_STRAP_REF0_GND F4 R2051 40.2K_0402_1% ROM_SI pull down 15kohm to GND for DDR3 Hynix 256mx16 VRAM, strap 0x2 ROM_SI pull down 4.99kohm to GND for DDR3 Hynix 256mx16 VRAM, strap 0x0
NC NC F5 ROM_SI pull down 10kohm to GND for DDR3 Micron 256mx16 VRAM, strap 0x1 ROM_SI pull down 10kohm to GND for DDR3 Micron 256mx16 VRAM, strap 0x1
2 NC ROM_SI pull down 25kohm to GND for DDR3 Samsung 256mx16 VRAM, strap 0x4 ROM_SI pull down 15kohm to GND for DDR3 Samsung 256mx16 VRAM, strap 0x2 2
ROM_SI pull up 35kohm to GND for DDR3 Hynix 256mx16 VRAM, strap 0xE ROM_SI pull down 20kohm to GND for DDR3 Hynix 256mx16 VRAM, strap 0x3
N1 ROM_SI pull up 30kohm to GND for DDR3 Micron 256mx16 VRAM, strap 0xD ROM_SI pull down 25kohm to GND for DDR3 Micron 256mx16 VRAM, strap 0x4
M1 NC ROM_SI pull down 30kohm to GND for DDR3 Samsung 256mx16 VRAM, strap 0x5 ROM_SI pull down 30kohm to GND for DDR3 Samsung 256mx16 VRAM, strap 0x5
M2 NC F12 ROM_SI pull up 25kohm to GND for DDR3 Samsung 256mx16 VRAM, strap 0xC
M3 NC THERMDP
K2 NC E12
K3 NC THERMDN
K1 NC
J1 NC
NC
For N16S-GT Multi strap table Decive ID : 0x1347
M4 F2 VCCSENSE_VGA
M5 NC VDD_SENSE VCCSENSE_VGA 55 GPU VRAM RANK X76 Freq Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK
L3 NC Vottage
NC
L4
NC X76629BOL07 0x5 (SA00008DN10) Hynix H5TC4G63CFR-N0C PD 30K
K4
NC Singal Rank X76629BOL08 1GHz 256Mx16x4 0x1 (SA000077K20) Micron MT41J256M16HA-093G:E PD 10K
K5 2GB
NC VSSSENSE_VGA
J4
NC GND_SENSE
F1
VSSSENSE_VGA 55 +1.5V X76629BOL09 0x2 (SA000076P20) Samsung K4W4G1646D-BC1A PD 15K

X76629BOL14 0x4 (SA000076PB0) Samsung K4W4G1646E-BC1A PD 24.9K

J5
NC X76629BOL10 0xC (SA00008DN10) Hynix H5TC4G63CFR-N0C PU 24.9K
N4
N5 NC TEST Dual Rank X76629BOL11 1GHz 256Mx16x8 0x1 (SA000077K20) Micron MT41J256M16HA-093G:E PD 10K
NC 4GB
P3
NC TESTMODE
AD9 TESTMODE R2054 1 VGA@ 2 10K_0402_5%
JTAG_TCK_VGA N16S-GT X76629BOL12 0x2 (SA000076P20) Samsung K4W4G1646D-BC1A PD 15K
P4 AE5 PAD @ T24 PD 4.99K PD 4.99K
NC JTAG_TCK AE6 JTAG_TDI PAD @ T1 PU 50K NC NC NC NC PD 15K
JTAG_TDI JTAG_TDO 0x2 (SA00008DN10) Hynix H5TC4G63CFR-N0C
AF6 PAD @ T186
J2 JTAG_TDO AD6 JTAG_TMS PAD @ T3 900MHz 256Mx16x4 PD 24.9K
J3 NC JTAG_TMS AG4 JTAG_RST R2053 1 VGA@ 210K_0402_5% Singal Rank 2GB 0x4 (SA000077K20) Micron MT41J256M16HA-093G:E
NC JTAG_TRST_N
+1.35V 0x5 (SA000076P20) Samsung K4W4G1646D-BC1A PD 30K
3 3
H3 PU 35K
NC 0xE (SA00008DN10) Hynix H5TC4G63CFR-N0C
H4
NC SERIAL 256Mx16x8
D12 900MHz 4GB 0x4 (SA000077K20) Micron MT41J256M16HA-093G:E PD 24.9K
ROM_CS_N B12 ROM_SI Dual Rank
ROM_SI 0x5 (SA000076P20) Samsung K4W4G1646D-BC1A PD 30K
A12 ROM_SO
ROM_SO C12 ROM_SCLK
ROM_SCLK

GM108-ES-S-A1_FCBGA595
@
For N16V-GM Multi strap table Decive ID : 0x1299
GPU VRAM RANK X76 Freq Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK
Vottage
X76629BOL01 0x9 (SA00008DN10) Hynix H5TC4G63CFR-N0C PU 10K

X76629BOL02 1GHz 256Mx16x4 0x1 (SA000077K20) Micron MT41J256M16HA-093G:E PD 10K

+1.5V Singal Rank
2GB
X76629BOL03 0x4 (SA000076P20) Samsung K4W4G1646D-BC1A PD 24.9K

X76629BOL13 0xA (SA000076PB0) Samsung K4W4G1646E-BC1A PU 15K

PD 5K
0x0 (SA00008DN10) Hynix H5TC4G63CFR-N0C

900MHz 256Mx16x4 0xD (SA000077K20) Micron MT41J256M16HA-093G:E

Singal Rank 2GB PU 30K
N16V-GM PU 45.3K PD45.3K PU 10K PD 4.99K PD 45.3K PU 4.99K PU 4.99K
+1.35V 0x5 (SA000076P20) Samsung K4W4G1646D-BC1A PD 30K

4 X76629BOL04 0xA (SA00008DN10) Hynix H5TC4G63CFR-N0C PU 15K 4

900MHz 256Mx16x8
Dual Rank X76629BOL05 4GB 0xD (SA000077K20) Micron MT41J256M16HA-093G:E PU 30K

X76629BOL06
0xC (SA000076P20) Samsung K4W4G1646D-BC1A PU 24.9K

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N16X STRAPS 3/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 22 of 60
A B C D E
 A B C D E

NV 15x DG-06803-V03

1 1

change to 1.35VSDGPU +1.05VSDGPU

UGPU1D
+1.5VSDGPU 3.24A 1.275A
Part 4 of 6
B26 AA10

.1U_0402_16V7K

.1U_0402_16V7K

4.7U_0603_6.3V6K
C25 FBVDDQ_01 PEX_IOVDDQ_1 AA12

10U_0603_6.3V6M

22U_0603_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
C2039 E23 FBVDDQ_02 PEX_IOVDDQ_2 AA13

C2040

C2032

C2033

C2021

C2022

C2013

C2014

C2016

C2017
1 1 1 1 2 2 FBVDDQ_03 PEX_IOVDDQ_3 1 1 1 1
E26 AA16
F14 FBVDDQ_04 PEX_IOVDDQ_4 AA18
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ F21 FBVDDQ_05 PEX_IOVDDQ_5 AA19 VGA@ VGA@ VGA@ VGA@
2 2 2 2 1 1 G13 FBVDDQ_06 PEX_IOVDDQ_6 AA20 2 2 2 2
G14 FBVDDQ_07 PEX_IOVDDQ_7 AA21
G15 FBVDDQ_08 PEX_IOVDDQ_8 AB22
Under GPU G16 FBVDDQ_09 PEX_IOVDDQ_9 AC23
G18 FBVDDQ_10 PEX_IOVDDQ_10 AD24
G19 FBVDDQ_11 PEX_IOVDDQ_11 AE25 Under GPU Near GPU

10U_0603_6.3V6M
G20 FBVDDQ_12 PEX_IOVDDQ_12 AF26

C2045

C2047
22U_0603_6.3V6M
1 1 FBVDDQ_13 PEX_IOVDDQ_13 Midway GPU & Power supply
G21 AF27
H24 FBVDDQ_14 PEX_IOVDDQ_14
VGA@ VGA@ H26 FBVDDQ_AON
2 2 J21 FBVDDQ_AON AA22
K21 FBVDDQ_AON PEX_IOVDD_1 AB23
L22 FBVDDQ_AON PEX_IOVDD_2 AC24
L24 FBVDDQ_19 PEX_IOVDD_3 AD25
Near GPU

POWER
L26 FBVDDQ_20 PEX_IOVDD_4 AE26
M21 FBVDDQ_21 PEX_IOVDD_5 AE27
2 N21 FBVDDQ_22 PEX_IOVDD_6 2
R21 FBVDDQ_23
T21 FBVDDQ_24
V21 FBVDDQ_25 +3VSDGPU_AON
W21 FBVDDQ_26
FBVDDQ_27 G10
3V3_AON G12 56mA

.1U_0402_16V7K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
3V3_AON G8

C2048

C2049

C2050
VDD33_3 2 1 1
G9
VDD33_4
VGA@ VGA@ VGA@
V7 1 2 2
W7 NC +1.5VSDGPU
AA6 NC
W6 NC D22 FB_CAL_PD_VDDQ 1 VGA@ 2
NC FB_CAL_PD_VDDQ Under GPU Near GPU
Y6 40.2_0402_1% R2078 +3VSDGPU_MAIN
NC
C24 FB_CAL_PU_GND 1 VGA@ 2
FB_CAL_PU_GND 42.2_0402_1% R2079

.1U_0402_16V7K

.1U_0402_16V7K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
M7 B25 FB_CAL_TERM_GND1 VGA@ 2

C2051

C2052

C2053

C2054
NC FB_CAL_TERM_GND 2 2 1 1
N7 51.1_0402_1% R2080
T6 NC
P6 NC VGA@ VGA@ VGA@ VGA@
NC 1 1 2 2

change to 1.35VSDGPU
T7 Under GPU Near GPU
R7 IFPD_PLLVDD_2 +3VSDGPU_AON
U6 NC
R6 IFPD_RSET AA8
286mA
NC PEX_PLL_HVDD_1 AA9
PEX_PLL_HVDD_2

.1U_0402_16V7K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
AB8

C2034

C2035

C2036
3 3
PEX_SVDD_3V3 2 1 1

J7 VGA@ VGA@ VGA@

K7 NC 1 2 2
K6 NC AA14
H6 NC PEX_PLLVDD_1 AA15
J6 NC PEX_PLLVDD_2
NC Near GPU +1.05VSDGPU
130mA +PEX_PLLVDD 0_0603_5% 2 @ 1 R2075

C2041

C2042

C2043
.1U_0402_16V7K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
2 1 1
GM108-ES-S-A1_FCBGA595
@
VGA@ VGA@ VGA@
1 2 2

Under GPU Near GPU

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N16X POWER & GND 4/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 23 of 60
A B C D E
 A B C D E

UGPU1F
UGPU1E +VGA_CORE +VGA_CORE
Part 6 of 6
A2
A26 GND_001
Part 5 of 6
GND_057
K11
K13 K10 V18
NV 15x DG-06803-V03
AB11 GND_002 GND_058 K15 K12 VDD_001 VDD_041 V16
1 GND_003 GND_059 VDD_002 VDD_040 1
AB14 K17 K14 V14
AB17 GND_004 GND_060 L10 K16 VDD_003 VDD_039 V12
AB20 GND_005 GND_061 L12 K18 VDD_004 VDD_038 V10
AB24 GND_006 GND_062 L14 L11 VDD_005 VDD_037 U17

POWER
AC2 GND_007 GND_063 L16 L13 VDD_006 VDD_036 U15
AC22 GND_008 GND_064 L18 L15 VDD_007 VDD_035 U13
AC26 GND_009 GND_065 L2 L17 VDD_008 VDD_034 U11
AC5 GND_010 GND_066 L23 M10 VDD_009 VDD_033 T18
AC8 GND_011 GND_067 L25 M12 VDD_010 VDD_032 T16
AD12 GND_012 GND_068 L5 M14 VDD_011 VDD_031 T14
AD13 GND_013 GND_069 M11 M16 VDD_012 VDD_030 T12
AD15 GND_014 GND_070 M13 M18 VDD_013 VDD_029 T10
AD16 GND_015 GND_071 M15 N11 VDD_014 VDD_028 R17
AD18 GND_016 GND_072 M17 N13 VDD_015 VDD_027 R15
AD19 GND_017 GND_073 N10 N15 VDD_016 VDD_026 R13
AD21 GND_018 GND_074 N12 N17 VDD_017 VDD_025 R11
AD22
AE11
GND_019
GND_020
GND_075
GND_076
N14
N16
P10
P12
VDD_018
VDD_019
VDD_024
VDD_023
P18
P16
DA-06840-V03
AE14 GND_021 GND_077 N18 VDD_020 VDD_022 P14
AE17 GND_022 GND_078 P11 VDD_021
AE20 GND_023 GND_079 P13
AF1 GND_024 GND_080 P15
AF11 GND_025 GND_081 P17
GND
AF14 GND_026 GND_082 P2
AF17 GND_027 GND_083 P23
AF20 GND_028 GND_084 P26
AF23 GND_029 GND_085 P5
AF5 GND_030 GND_086 R10
AF8 GND_031 GND_087 R12 GM108-ES-S-A1_FCBGA595
AG2 GND_032 GND_088 R14 @
AG26 GND_033 GND_089 R16
B1 GND_034 GND_090 R18
B11 GND_035 GND_091 T11
2 B14 GND_036 GND_092 T13 2
B17 GND_037 GND_093 T15
B20 GND_038 GND_094 T17
B23 GND_039 GND_095 U10
B27 GND_040 GND_096 U12
B5
B8
GND_041
GND_042
GND_097
GND_098
U14
U16
DA-06925-V05
E11 GND_043 GND_099 U18
E14 GND_044 GND_100 U2
E17 GND_045 GND_101 U23
E2 GND_046 GND_102 U26
E20 GND_047 GND_103 U5
E22 GND_048 GND_104 V11
E25 GND_049 GND_105 V13
E5 GND_050 GND_106 V15
E8 GND_051 GND_107 V17
H2 GND_052 GND_108 Y2
H23 GND_053 GND_109 Y23
H25 GND_054 GND_110 Y26
H5 GND_055 GND_111 Y5
GND_056 GND_112

AA7
GND AB7
GND

GM108-ES-S-A1_FCBGA595
@
DA07075-V01
3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N16X POWER & GND 5/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 24 of 60
A B C D E
 A B C D E

VRAM DDR3 chips 21,26,27,28 DQSA[7..0]

DQSA[7..0]

DQSA#[7..0]
21,26,27,28 DQSA#[7..0]
DQMA[7..0]
21,26,27,28 DQMA[7..0]
MDA[63..0]
21,26,27,28 MDA[63..0]
CMDA[30..0]
21,26,27,28 CMDA[30..0]

Lower Rank 0 BOT SIDE Rank0 Rank1

Mode E
X76 for VGM X76 for SGT Address 0..31 32..63 0..31 32..63
1 1
ZZZ ZZZ
CMD0 ODT ODT
X7601@ X7607@ U2004 X76@ U2005 X76@ CMD1 CS1*
+MEM_VREFCA0 +MEM_VREFCA0 M8
+MEM_VREFDQ0
M8
VREFCA DQL0
E3 MDA20
+MEM_VREFDQ0 H1 VREFCA DQL0
E3 MDA25 CMD2 CS0*
X76629BOL01 X76629BOL07 H1 F7 MDA16 F7 MDA30
VREFDQ DQL1 VREFDQ DQL1
2Gb Hynix 256Mx16x4 2Gb Hynix 256Mx16x4 DQL2
F2 MDA21
DQL2
F2 MDA24 CMD3 CKE CKE
CMDA7 N3 F8 MDA19 CMDA7 N3 F8 MDA28
A0 DQL3 A0 DQL3
CMDA10 P7
A1 DQL4
H3 MDA23 Group2 CMDA10 P7
A1 DQL4
H3 MDA27 Group3 CMD4 A9 A9 A11 A11
ZZZ ZZZ CMDA24 P3 H8 MDA18 CMDA24 P3 H8 MDA31
A2 DQL5 A2 DQL5
CMDA6 N2
A3 DQL6
G2 MDA22 CMDA6 N2
A3 DQL6
G2 MDA26 CMD5 A6 A6 A7 A7
CMDA22 P8 H7 MDA17 CMDA22 P8 H7 MDA29
A4 DQL7 A4 DQL7
X7602@ X7608@ CMDA26 P2
A5
CMDA26 P2
A5 CMD6 A3 A3 BA1 BA1
CMDA5 R8 CMDA5 R8
A6 A6
CMDA21 R2
A7 DQU0
D7 MDA12 CMDA21 R2
A7 DQU0
D7 MDA6 CMD7 A0 A0 A12 A12
X76629BOL02 X76629BOL08 CMDA8 T8 C3 MDA9 CMDA8 T8 C3 MDA1
A8 DQU1 A8 DQU1
2Gb Micron 256Mx16x4 2Gb Micron 256Mx16x4 CMDA4 R3
A9 DQU2
C8 MDA14 CMDA4 R3
A9 DQU2
C8 MDA4 CMD8 A8 A8 A8 A8
CMDA25 L7 C2 MDA11 CMDA25 L7 C2 MDA2
A10/AP DQU3 A10/AP DQU3
CMDA23 R7
A11 DQU4
A7 MDA13 Group1 CMDA23 R7
A11 DQU4
A7 MDA5 Group0 CMD9 A12 A12 A0 A0
ZZZ ZZZ CMDA9 N7 A2 MDA10 CMDA9 N7 A2 MDA0
A12 DQU5 A12 DQU5
CMDA12 T3
A13 DQU6
B8 MDA15 CMDA12 T3
A13 DQU6
B8 MDA7 CMD10 A1 A1 A2 A2
CMDA14 T7 A3 MDA8 CMDA14 T7 A3 MDA3
A14 DQU7 A14 DQU7
X7603@ X7609@ M7
A15/BA3 +1.5VSDGPU
M7
A15/BA3 +1.5VSDGPU
CMD11 RAS* RAS* RAS* RAS*
CMD12 A13 A13 A14 A14
X76629BOL03 X76629BOL09 CMDA29 M2 B2 CMDA29 M2 B2
BA0 VDD BA0 VDD
2Gb Samsung-D 256Mx16x4 2Gb Samsung-D 256Mx16x4 CMDA13 N8
BA1 VDD
D9 CMDA13 N8
BA1 VDD
D9 CMD13 BA1 BA1 A3 A3
CMDA27 M3 G7 CMDA27 M3 G7
BA2 VDD BA2 VDD
VDD
K2
VDD
K2 CMD14 A14 A14 A13 A13
ZZZ ZZZ K8 K8
VDD VDD
VDD
N1
VDD
N1 CMD15 CAS* CAS* CAS* CAS*
CLKA0 J7 N9 CLKA0 J7 N9
2 CK VDD CK VDD 2
X7604@ X7610@ CLKA0# K7
CK VDD
R1 CLKA0# K7
CK VDD
R1 CMD16 ODT ODT
CMDA3 K9 R9 CMDA3 K9 R9
CKE/CKE0 VDD +1.5VSDGPU CKE/CKE0 VDD +1.5VSDGPU CMD17 CS1*
X76629BOL04 X76629BOL10
4Gb Hynix 256Mx16x8 4Gb Hynix 256Mx16x8 CMDA0 K1
ODT/ODT0 VDDQ
A1 CMDA0 K1
ODT/ODT0 VDDQ
A1 CMD18 CS0*
CMDA2 L2 A8 CMDA2 L2 A8
CS/CS0 VDDQ CS/CS0 VDDQ
CMDA11 J3
RAS VDDQ
C1 CMDA11 J3
RAS VDDQ
C1 CMD19 CKE CKE
ZZZ ZZZ CMDA15 K3 C9 CMDA15 K3 C9
CAS VDDQ CAS VDDQ
CMDA28 L3
WE VDDQ
D2 CMDA28 L3
WE VDDQ
D2 CMD20 RST RST RST RST
310mAVDDQ E9 E9
VDDQ
X7605@ X7611@
VDDQ
F1 310mAVDDQ F1 CMD21 A7 A7 A6 A6
DQSA2 F3 H2 DQSA3 F3 H2
DQSL VDDQ DQSL VDDQ
DQSA1 C7
DQSU VDDQ
H9 DQSA0 C7
DQSU VDDQ
H9 CMD22 A4 A4 A5 A5
X76629BOL05 X76629BOL11
4Gb Micron 256Mx16x8 4Gb Micron 256Mx16x8 CMD23 A11 A11 A9 A9
DQMA2 E7 A9 DQMA3 E7 A9
DML VSS DML VSS
DQMA1 D3
DMU VSS
B3 DQMA0 D3
DMU VSS
B3 CMD24 A2 A2 A1 A1
ZZZ ZZZ E1 E1
VSS VSS
VSS
G8
VSS
G8 CMD25 A10 A10 WE* WE*
DQSA#2 G3 J2 DQSA#3 G3 J2
DQSL VSS DQSL VSS
X7606@ X7612@ DQSA#1 B7
DQSU VSS
J8 DQSA#0 B7
DQSU VSS
J8 CMD26 A5 A5 A4 A4
M1 M1
VSS VSS
VSS
M9
VSS
M9 CMD27 BA2 BA2
X76629BOL06 X76629BOL12 P1 P1
VSS VSS
4Gb Samsung-D 256Mx16x8 4Gb Samsung-D 256Mx16x8 CMDA20 T2
RESET VSS
P9 CMDA20 T2
RESET VSS
P9 CMD28 WE* WE* A10 A10
T1 T1
VSS VSS
ZQ0 L8
ZQ/ZQ0 VSS
T9 ZQ1 L8
ZQ/ZQ0 VSS
T9 CMD29 BA0 BA0 BA0 BA0
ZZZ ZZZ
1

1
CMD30 BA2 BA2
J1 B1 J1 B1
X7613@ X7614@ R2081 VGA@ L1 NC/ODT1 VSSQ B9 R2082 VGA@ L1 NC/ODT1 VSSQ B9
NC/CS1 VSSQ NC/CS1 VSSQ Not Available
243_0402_1% J9 D1 243_0402_1% J9 D1
L9 NC/CE1 VSSQ D8 L9 NC/CE1 VSSQ D8
2

2
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
3 X76629BOL13 X76629BOL14 VSSQ VSSQ
3
2Gb Samsung-E 256Mx16x4 2Gb Samsung-E 256Mx16x4 E8 E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ VSSQ Command Bit Default Pull-down
G9 G9
VSSQ VSSQ ODTx 10k
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 DDR3 CKEx 10k
H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96 RST 10k
CS* No Termination

CLKA0
21,26 CLKA0

1
VGA@
R2087
162_0402_1% +1.5VSDGPU +1.5VSDGPU
2

CLKA0#
21,26 CLKA0#
R2085 R2086
VGA@ VGA@
1.33K_0402_1% 1.33K_0402_1%

+MEM_VREFCA0 +MEM_VREFDQ0
+MEM_VREFCA0 26 +MEM_VREFDQ0 26

1 1
CMDA0 R2093 1 VGA@ 2 10K_0402_5% R2091 R2092
CMDA3 R2094 1 VGA@ 2 10K_0402_5% VGA@ C2055 VGA@ C2056
+1.5VSDGPU CMDA16 R2095 1 VGA@ 2 10K_0402_5% 1.33K_0402_1% .1U_0402_16V7K 1.33K_0402_1% .1U_0402_16V7K
CMDA19 R2098 1 VGA@ 2 10K_0402_5% 2 2
VGA@ VGA@
4 CMDA20 R2099 1 VGA@ 2 10K_0402_5% 4
C2079

C2080

C2081

C2082
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K
C2071

C2072

C2073

C2074

C2075

C2076

C2077

C2078

1 1 1 1 1 1 1 1 1 1 1 1

VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
2 2 2 2 2 2 2 2 2 2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N16X Upper Rank0 6/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 25 of 60
A B C D E
 A B C D E

VRAM DDR3 chips 21,25,27,28 DQSA[7..0]

DQSA[7..0]

DQSA#[7..0]
21,25,27,28 DQSA#[7..0]
DQMA[7..0]
21,25,27,28 DQMA[7..0]
MDA[63..0]
21,25,27,28 MDA[63..0]
CMDA[30..0]
21,25,27,28 CMDA[30..0]
Lower Rank 1 TOP SIDE
1 1

Rank0 Rank1
Mode E
Address 0..31 32..63 0..31 32..63
U2007 X76@ CMD0 ODT ODT
U2006 X76@
+MEM_VREFCA0 M8
+MEM_VREFCA0 M8 +MEM_VREFDQ0 H1 VREFCA DQL0
E3 MDA30 CMD1 CS1*
E3 MDA16 F7 MDA25
25 +MEM_VREFCA0 +MEM_VREFDQ0 H1 VREFCA DQL0 VREFDQ DQL1
25 +MEM_VREFDQ0 VREFDQ DQL1
F7 MDA20
DQL2
F2 MDA28 CMD2 CS0*
F2 MDA19 CMDA9 N3 F8 MDA24
DQL2 A0 DQL3
CMDA9 N3
A0 DQL3
F8 MDA21 CMDA24 P7
A1 DQL4
H3 MDA29 Group3 CMD3 CKE CKE
CMDA24 P7 H3 MDA17 Group2 CMDA10 P3 H8 MDA26
A1 DQL4 A2 DQL5
CMDA10 P3
A2 DQL5
H8 MDA22 CMDA13 N2
A3 DQL6
G2 MDA31 CMD4 A9 A9 A11 A11
CMDA13 N2 G2 MDA18 CMDA26 P8 H7 MDA27
A3 DQL6 A4 DQL7
CMDA26 P8
A4 DQL7
H7 MDA23 CMDA22 P2
A5 CMD5 A6 A6 A7 A7
CMDA22 P2 CMDA21 R8
A5 A6
CMDA21 R8
A6
CMDA5 R2
A7 DQU0
D7 MDA1 CMD6 A3 A3 BA1 BA1
CMDA5 R2 D7 MDA9 CMDA8 T8 C3 MDA6
A7 DQU0 A8 DQU1
CMDA8 T8
A8 DQU1
C3 MDA12 CMDA23 R3
A9 DQU2
C8 MDA2 CMD7 A0 A0 A12 A12
CMDA23 R3 C8 MDA11 CMDA28 L7 C2 MDA4
A9 DQU2 A10/AP DQU3
CMDA28 L7
A10/AP DQU3
C2 MDA14 CMDA4 R7
A11 DQU4
A7 MDA3 Group0 CMD8 A8 A8 A8 A8
CMDA4 R7 A7 MDA8 Group1 CMDA7 N7 A2 MDA7
A11 DQU4 A12 DQU5
CMDA7 N7
A12 DQU5
A2 MDA15 CMDA14 T3
A13 DQU6
B8 MDA0 CMD9 A12 A12 A0 A0
CMDA14 T3 B8 MDA10 CMDA12 T7 A3 MDA5
A13 DQU6 A14 DQU7
CMDA12 T7
A14 DQU7
A3 MDA13 M7
A15/BA3 +1.5VSDGPU
CMD10 A1 A1 A2 A2
M7
A15/BA3 +1.5VSDGPU CMD11 RAS* RAS* RAS* RAS*
CMDA29 M2 B2
BA0 VDD
CMDA29 M2
BA0 VDD
B2 CMDA6 N8
BA1 VDD
D9 CMD12 A13 A13 A14 A14
CMDA6 N8 D9 CMDA30 M3 G7
BA1 VDD BA2 VDD
CMDA30 M3
BA2 VDD
G7
VDD
K2 CMD13 BA1 BA1 A3 A3
K2 K8
2 VDD VDD 2
VDD
K8
VDD
N1 CMD14 A14 A14 A13 A13
N1 CLKA0 J7 N9
VDD CK VDD
21,25 CLKA0
CLKA0 J7
CK VDD
N9 CLKA0# K7
CK VDD
R1 CMD15 CAS* CAS* CAS* CAS*
CLKA0# K7 R1 CMDA3 K9 R9
21,25 CLKA0# CK VDD CKE/CKE0 VDD +1.5VSDGPU
CMDA3 K9
CKE/CKE0 VDD
R9
+1.5VSDGPU
CMD16 ODT ODT
CMDA0 K1
ODT/ODT0 VDDQ
A1 CMD17 CS1*
CMDA0 K1 A1 CMDA1 L2 A8
ODT/ODT0 VDDQ CS/CS0 VDDQ
CMDA1 L2
CS/CS0 VDDQ
A8 CMDA11 J3
RAS VDDQ
C1 CMD18 CS0*
CMDA11 J3 C1 CMDA15 K3 C9
RAS VDDQ CAS VDDQ
CMDA15 K3
CAS VDDQ
C9 CMDA25 L3
WE VDDQ
D2 CMD19 CKE CKE
CMDA25 L3 D2 310mAVDDQ E9
WE VDDQ
310mAVDDQ E9
VDDQ
F1 CMD20 RST RST RST RST
F1 DQSA3 F3 H2
VDDQ DQSL VDDQ
DQSA2 F3
DQSL VDDQ
H2 DQSA0 C7
DQSU VDDQ
H9 CMD21 A7 A7 A6 A6
DQSA1 C7 H9
DQSU VDDQ
CMD22 A4 A4 A5 A5
DQMA3 E7 A9
DML VSS
DQMA2 E7
DML VSS
A9 DQMA0 D3
DMU VSS
B3 CMD23 A11 A11 A9 A9
DQMA1 D3 B3 E1
DMU VSS VSS
VSS
E1
VSS
G8 CMD24 A2 A2 A1 A1
G8 DQSA#3 G3 J2
VSS DQSL VSS
DQSA#2 G3
DQSL VSS
J2 DQSA#0 B7
DQSU VSS
J8 CMD25 A10 A10 WE* WE*
DQSA#1 B7 J8 M1
DQSU VSS VSS
VSS
M1
VSS
M9 CMD26 A5 A5 A4 A4
M9 P1
VSS VSS
VSS
P1 CMDA20 T2
RESET VSS
P9 CMD27 BA2 BA2
CMDA20 T2 P9 T1
RESET VSS VSS
VSS
T1 ZQ3 L8
ZQ/ZQ0 VSS
T9 CMD28 WE* WE* A10 A10
ZQ2 L8 T9
ZQ/ZQ0 VSS

1
VGA@ CMD29 BA0 BA0 BA0 BA0
1

R2101 J1 B1
NC/ODT1 VSSQ
VGA@ J1
NC/ODT1 VSSQ
B1 243_0402_1% L1
NC/CS1 VSSQ
B9 CMD30 BA2 BA2
3 R2100 L1 B9 J9 D1 3
243_0402_1% J9 NC/CS1 VSSQ D1 L9 NC/CE1 VSSQ D8 Not Available

2
L9 NC/CE1 VSSQ D8 NCZQ1 VSSQ E2
2

NCZQ1 VSSQ E2 VSSQ E8

VSSQ E8 VSSQ F9
VSSQ F9 VSSQ G1
VSSQ G1 VSSQ G9
VSSQ G9 VSSQ
VSSQ Command Bit Default Pull-down
96-BALL
96-BALL SDRAM DDR3 ODTx 10k
SDRAM DDR3 H5TQ2G63BFR-11C_FBGA96
H5TQ2G63BFR-11C_FBGA96 DDR3 CKEx 10k
RST 10k
CS* No Termination

+1.5VSDGPU
C2067

C2068

C2069

C2070
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K
C2059

C2060

C2061

C2062

C2063

C2064

C2065

C2066

1 1 1 1 1 1 1 1 1 1 1 1

4
2 2 2 2 2 2 2 2 2 2 2 2 4

VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N16X Upper Rank1 7/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 26 of 60
A B C D E
 A B C D E

VRAM DDR3 chips 21,25,26,28 DQSA[7..0]

DQSA[7..0]

DQSA#[7..0]
21,25,26,28 DQSA#[7..0]
DQMA[7..0]
21,25,26,28 DQMA[7..0]

21,25,26,28 MDA[63..0]
MDA[63..0]

CMDA[30..0]
Upper Rank 0 BOT SIDE
21,25,26,28 CMDA[30..0]

1 Rank0 Rank1 1
Mode E
Address 0..31 32..63 0..31 32..63
U2008 X76@ U2009 X76@

+MEM_VREFCA1 M8 +MEM_VREFCA1
CMD0 ODT ODT
E3 MDA33 M8 E3 MDA50
+MEM_VREFDQ1 H1 VREFCA DQL0 +MEM_VREFDQ1 VREFCA DQL0
VREFDQ DQL1
F7 MDA39 H1
VREFDQ DQL1
F7 MDA52 CMD1 CS1*
F2 MDA32 F2 MDA49
DQL2 DQL2
CMDA7 N3
A0 DQL3
F8 MDA36 CMDA7 N3
A0 DQL3
F8 MDA53 CMD2 CS0*
CMDA10 P7 H3 MDA35 Group4 CMDA10 P7 H3 MDA48 Group6
A1 DQL4 A1 DQL4
CMDA24 P3
A2 DQL5
H8 MDA37 CMDA24 P3
A2 DQL5
H8 MDA55 CMD3 CKE CKE
CMDA6 N2 G2 MDA34 CMDA6 N2 G2 MDA51
A3 DQL6 A3 DQL6
CMDA22 P8
A4 DQL7
H7 MDA38 CMDA22 P8
A4 DQL7
H7 MDA54 CMD4 A9 A9 A11 A11
CMDA26 P2 CMDA26 P2
A5 A5
CMDA5 R8
A6
CMDA5 R8
A6 CMD5 A6 A6 A7 A7
CMDA21 R2 D7 MDA56 CMDA21 R2 D7 MDA41
A7 DQU0 A7 DQU0
CMDA8 T8
A8 DQU1
C3 MDA59 CMDA8 T8
A8 DQU1
C3 MDA44 CMD6 A3 A3 BA1 BA1
CMDA4 R3 C8 MDA58 CMDA4 R3 C8 MDA40
A9 DQU2 A9 DQU2
CMDA25 L7
A10/AP DQU3
C2 MDA62 CMDA25 L7
A10/AP DQU3
C2 MDA46 CMD7 A0 A0 A12 A12
CMDA23 R7 A7 MDA57 Group7 CMDA23 R7 A7 MDA43 Group5 A5MUB SWAP
A11 DQU4 A11 DQU4
CMDA9 N7
A12 DQU5
A2 MDA61 CMDA9 N7
A12 DQU5
A2 MDA47 CMD8 A8 A8 A8 A8
CMDA12 T3 B8 MDA60 CMDA12 T3 B8 MDA42
A13 DQU6 A13 DQU6
CMDA14 T7
A14 DQU7
A3 MDA63 CMDA14 T7
A14 DQU7
A3 MDA45 CMD9 A12 A12 A0 A0
M7 M7
A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU CMD10 A1 A1 A2 A2
CMDA29 M2
BA0 VDD
B2 CMDA29 M2
BA0 VDD
B2 CMD11 RAS* RAS* RAS* RAS*
CMDA13 N8 D9 CMDA13 N8 D9
BA1 VDD BA1 VDD
CMDA27 M3
BA2 VDD
G7 CMDA27 M3
BA2 VDD
G7 CMD12 A13 A13 A14 A14
K2 K2
VDD VDD
VDD
K8
VDD
K8 CMD13 BA1 BA1 A3 A3
N1 N1
VDD VDD
CLKA1 J7
CK VDD
N9 CLKA1 J7
CK VDD
N9 CMD14 A14 A14 A13 A13
CLKA1# K7 R1 CLKA1# K7 R1
2 CK VDD CK VDD 2
CMDA19 K9
CKE/CKE0 VDD
R9
+1.5VSDGPU
CMDA19 K9
CKE/CKE0 VDD
R9
+1.5VSDGPU
CMD15 CAS* CAS* CAS* CAS*
CMD16 ODT ODT
CMDA16 K1 A1 CMDA16 K1 A1
ODT/ODT0 VDDQ ODT/ODT0 VDDQ
CMDA18 L2
CS/CS0 VDDQ
A8 CMDA18 L2
CS/CS0 VDDQ
A8 CMD17 CS1*
CMDA11 J3 C1 CMDA11 J3 C1
RAS VDDQ RAS VDDQ
CMDA15 K3
CAS VDDQ
C9 CMDA15 K3
CAS VDDQ
C9 CMD18 CS0*
CMDA28 L3 D2 CMDA28 L3 D2
WE VDDQ WE VDDQ
VDDQ
E9 310mAVDDQ E9 CMD19 CKE CKE
310mAVDDQ F1 F1
VDDQ
DQSA4 F3
DQSL VDDQ
H2 DQSA6 F3
DQSL VDDQ
H2 CMD20 RST RST RST RST
DQSA7 C7 H9 DQSA5 C7 H9
DQSU VDDQ DQSU VDDQ
CMD21 A7 A7 A6 A6
DQMA4 E7
DML VSS
A9 DQMA6 E7
DML VSS
A9 CMD22 A4 A4 A5 A5
DQMA7 D3 B3 DQMA5 D3 B3
DMU VSS DMU VSS
VSS
E1
VSS
E1 CMD23 A11 A11 A9 A9
G8 G8
VSS VSS
DQSA#4 G3
DQSL VSS
J2 DQSA#6 G3
DQSL VSS
J2 CMD24 A2 A2 A1 A1
DQSA#7 B7 J8 DQSA#5 B7 J8
DQSU VSS DQSU VSS
VSS
M1
VSS
M1 CMD25 A10 A10 WE* WE*
M9 M9
VSS VSS
VSS
P1
VSS
P1 CMD26 A5 A5 A4 A4
CMDA20 T2 P9 CMDA20 T2 P9
RESET VSS RESET VSS
VSS
T1
VSS
T1 CMD27 BA2 BA2
ZQ5 L8 T9 ZQ4 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
CMD28 WE* WE* A10 A10
1

1
J1
NC/ODT1 VSSQ
B1 J1
NC/ODT1 VSSQ
B1 CMD29 BA0 BA0 BA0 BA0
R2083 VGA@ L1 B9 R2084 VGA@ L1 B9
NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9
NC/CE1 VSSQ
D1 243_0402_1% J9
NC/CE1 VSSQ
D1 CMD30 BA2 BA2
L9 D8 L9 D8
2

2
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
VSSQ VSSQ Not Available
3 E8 E8 3
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
VSSQ VSSQ
96-BALL 96-BALL Command Bit Default Pull-down
SDRAM DDR3 SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96 ODTx 10k

DDR3 CKEx 10k

RST 10k
CS* No Termination

+1.5VSDGPU +1.5VSDGPU

+1.5VSDGPU
R2088 R2089
VGA@ VGA@
1.33K_0402_1% 1.33K_0402_1%
C2102

C2101

C2099

C2105
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K
C2098

C2104

C2094

C2103

C2095

C2097

C2100

C2096

1 1 1 1 1 1 1 1 1 1 1 1 CLKA1
+MEM_VREFCA1 +MEM_VREFDQ1 21,28 CLKA1
+MEM_VREFCA1 28 +MEM_VREFDQ1 28

1
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ 1 1 VGA@
2 2 2 2 2 2 2 2 2 2 2 2 R2096 R2097 R2103
VGA@ C2057 VGA@ C2058 162_0402_1%
1.33K_0402_1% .1U_0402_16V7K 1.33K_0402_1% .1U_0402_16V7K

2
4
2 2 CLKA1# 4
VGA@ VGA@ 21,28 CLKA1#

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N16X Lower Rank0 8/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 27 of 60
A B C D E
 A B C D E

VRAM DDR3 chips 21,25,26,27 DQSA[7..0]

DQSA[7..0]

DQSA#[7..0]
21,25,26,27 DQSA#[7..0]
DQMA[7..0]
21,25,26,27 DQMA[7..0]
MDA[63..0]
21,25,26,27 MDA[63..0]
CMDA[30..0]
21,25,26,27 CMDA[30..0]

Upper Rank 1 TOP SIDE

1 1

Rank0 Rank1
Mode E
Address 0..31 32..63 0..31 32..63
CMD0 ODT ODT
U2010 X76@ U2011 X76@
+MEM_VREFCA1 M8 +MEM_VREFCA1 M8
CMD1 CS1*
E3 MDA39 E3 MDA52
27 +MEM_VREFCA1 +MEM_VREFDQ1 H1 VREFCA DQL0 +MEM_VREFDQ1 H1 VREFCA DQL0
27 +MEM_VREFDQ1 VREFDQ DQL1
F7 MDA33
VREFDQ DQL1
F7 MDA50 CMD2 CS0*
F2 MDA36 F2 MDA53
DQL2 DQL2
CMDA9 N3
A0 DQL3
F8 MDA32 CMDA9 N3
A0 DQL3
F8 MDA49 CMD3 CKE CKE
CMDA24 P7 H3 MDA38 Group4 CMDA24 P7 H3 MDA54 Group6
A1 DQL4 A1 DQL4
CMDA10 P3
A2 DQL5
H8 MDA34 CMDA10 P3
A2 DQL5
H8 MDA51 CMD4 A9 A9 A11 A11
CMDA13 N2 G2 MDA37 CMDA13 N2 G2 MDA55
A3 DQL6 A3 DQL6
CMDA26 P8
A4 DQL7
H7 MDA35 CMDA26 P8
A4 DQL7
H7 MDA48 CMD5 A6 A6 A7 A7
CMDA22 P2 CMDA22 P2
A5 A5
CMDA21 R8
A6
CMDA21 R8
A6 CMD6 A3 A3 BA1 BA1
CMDA5 R2 D7 MDA59 CMDA5 R2 D7 MDA44
A7 DQU0 A7 DQU0
CMDA8 T8
A8 DQU1
C3 MDA56 CMDA8 T8
A8 DQU1
C3 MDA41 CMD7 A0 A0 A12 A12
CMDA23 R3 C8 MDA62 CMDA23 R3 C8 MDA46
A9 DQU2 A9 DQU2
CMDA28 L7
A10/AP DQU3
C2 MDA58 CMDA28 L7
A10/AP DQU3
C2 MDA40 CMD8 A8 A8 A8 A8
CMDA4 R7 A7 MDA63 Group7 CMDA4 R7 A7 MDA45 Group5 A5MUB SWAP
A11 DQU4 A11 DQU4
CMDA7 N7
A12 DQU5
A2 MDA60 CMDA7 N7
A12 DQU5
A2 MDA42 CMD9 A12 A12 A0 A0
CMDA14 T3 B8 MDA61 CMDA14 T3 B8 MDA47
A13 DQU6 A13 DQU6
CMDA12 T7
A14 DQU7
A3 MDA57 CMDA12 T7
A14 DQU7
A3 MDA43 CMD10 A1 A1 A2 A2
M7 M7
A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU CMD11 RAS* RAS* RAS* RAS*
CMDA29 M2
BA0 VDD
B2 CMDA29 M2
BA0 VDD
B2 CMD12 A13 A13 A14 A14
CMDA6 N8 D9 CMDA6 N8 D9
BA1 VDD BA1 VDD
CMDA30 M3
BA2 VDD
G7 CMDA30 M3
BA2 VDD
G7 CMD13 BA1 BA1 A3 A3
K2 K2
2 VDD VDD 2
VDD
K8
VDD
K8 CMD14 A14 A14 A13 A13
N1 N1
VDD VDD
21,27 CLKA1
CLKA1 J7
CK VDD
N9 CLKA1 J7
CK VDD
N9 CMD15 CAS* CAS* CAS* CAS*
CLKA1# K7 R1 CLKA1# K7 R1
21,27 CLKA1# CK VDD CK VDD
CMDA19 K9
CKE/CKE0 VDD
R9
+1.5VSDGPU
CMDA19 K9
CKE/CKE0 VDD
R9
+1.5VSDGPU
CMD16 ODT ODT
CMD17 CS1*
CMDA16 K1 A1 CMDA16 K1 A1
ODT/ODT0 VDDQ ODT/ODT0 VDDQ
CMDA17 L2
CS/CS0 VDDQ
A8 CMDA17 L2
CS/CS0 VDDQ
A8 CMD18 CS0*
CMDA11 J3 C1 CMDA11 J3 C1
RAS VDDQ RAS VDDQ
CMDA15 K3
CAS VDDQ
C9 CMDA15 K3
CAS VDDQ
C9 CMD19 CKE CKE
CMDA25 L3 D2 CMDA25 L3 D2
WE VDDQ WE VDDQ
310mAVDDQ E9 310mAVDDQ E9 CMD20 RST RST RST RST
F1 F1
VDDQ VDDQ
DQSA4 F3
DQSL VDDQ
H2 DQSA6 F3
DQSL VDDQ
H2 CMD21 A7 A7 A6 A6
DQSA7 C7 H9 DQSA5 C7 H9
DQSU VDDQ DQSU VDDQ
CMD22 A4 A4 A5 A5
DQMA4 E7
DML VSS
A9 DQMA6 E7
DML VSS
A9 CMD23 A11 A11 A9 A9
DQMA7 D3 B3 DQMA5 D3 B3
DMU VSS DMU VSS
VSS
E1
VSS
E1 CMD24 A2 A2 A1 A1
G8 G8
VSS VSS
DQSA#4 G3
DQSL VSS
J2 DQSA#6 G3
DQSL VSS
J2 CMD25 A10 A10 WE* WE*
DQSA#7 B7 J8 DQSA#5 B7 J8
DQSU VSS DQSU VSS
VSS
M1
VSS
M1 CMD26 A5 A5 A4 A4
M9 M9
VSS VSS
VSS
P1
VSS
P1 CMD27 BA2 BA2
CMDA20 T2 P9 CMDA20 T2 P9
RESET VSS RESET VSS
VSS
T1
VSS
T1 CMD28 WE* WE* A10 A10
ZQ6 L8 T9 ZQ7 L8 T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
CMD29 BA0 BA0 BA0 BA0
1

1
J1
NC/ODT1 VSSQ
B1 J1
NC/ODT1 VSSQ
B1 CMD30 BA2 BA2
3 R2090 L1 B9 R2102 L1 B9 3
243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1
NC/CE1 VSSQ NC/CE1 VSSQ Not Available
VGA@ L9 D8 VGA@ L9 D8
2

2
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
VSSQ VSSQ Command Bit Default Pull-down
96-BALL 96-BALL ODTx 10k
SDRAM DDR3 SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96 DDR3 CKEx 10k
RST 10k
CS* No Termination

+1.5VSDGPU

C2146

C2109

C2108

C2106
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K
C2110

C2151

C2147

C2150

C2148

C2149

C2107

C2152

1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2

VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N16X Lower Rank1 9/9
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 28 of 60
A B C D E
 A B C D E

+19VB +INVPW R_B+ Place closed to JEDP1

+3VS
LCD POWER CIRCUIT +LCDVDD +LCDVDD
LED PANEL Conn.
U8
W=60mils L11
W=60mils +3VS JEDP1
W=60mils W=60mils
1U_0402_6.3V6K
C140
5 1 HCB2012KF-221T30_0805 +INVPW R_B+ 1
IN OUT 1 2 2 1 41
1 2 G1
2 1 1 EMC@ 1 1 3 42
GND 3 G2

1000P_0402_50V7K
C364 @EMC@
SM01000EJ00 3000ma 1 1 W=60mils 4 43
4 3 C368 C365 C375 C419 5 4 G3 44
2 EN OC 220ohm@100mhz SOC_BKL_PW M 5 G4
.1U_0402_16V7K DCR 0.04 68P_0402_50V8J .1U_0402_16V7K .1U_0402_16V7K 6 45
SY6288C20AAC_SOT23-5 C367 2 2 @EMC@ 2 2 BKOFF# 7 6 G5 46
@ 2 2 @ EDP_HPD 7 G6
4.7U_0603_6.3V6K 8
9 8
1 6 SOC_ENVDD +LCDVDD 9 1
10
11 10
12 11
EDP_AUXN_C 13 12
EDP_AUXP_C 14 13
15 14
EDP_TXP0_C 16 15
EDP_TXN0_C 17 16
18 17
EDP_TXP1_C 19 18
EDP_TXN1_C 20 19
21 20
EDP_TXP2_C 22 21
EDP_TXN2_C 23 22
24 23
EDP_TXP3_C 25 24
EDP_TXN3_C 26 25
C371 1 2 .1U_0402_16V7K EDP_TXP0_C 27 26
6 EDP_TXP0 EDP_TXN0_C +TS_PW R 27
C372 1 2 .1U_0402_16V7K 28
6 EDP_TXN0 EDP_TXP1_C SOC_BKL_PW M TS_EN 28
C373 1 2 .1U_0402_16V7K R393 1 @ 2 100K_0402_5% 29
6 EDP_TXP1 EDP_TXN1_C 6 SOC_BKL_PW M 11,38 TS_EN USB20_P6 29
C374 1 2 .1U_0402_16V7K 30
6 EDP_TXN1 EDP_TXP2_C 12 USB20_P6 USB20_N6 30
C388 1 2 .1U_0402_16V7K @EMC@ 31
6 EDP_TXP2 EDP_TXN2_C 12 USB20_N6 I2C_0_SCL 31
C376 1 2 .1U_0402_16V7K C549 1 2 220P_0402_50V7K Touch Screen 32
6 EDP_TXN2 EDP_TXP3_C 11 I2C_0_SCL I2C_0_SDA 32
C387 1 2 .1U_0402_16V7K @EMC@ 33
6 EDP_TXP3 EDP_TXN3_C 11 I2C_0_SDA I2C_TS_RST# 33
C377 1 2 .1U_0402_16V7K BKOFF# C528 1 2 220P_0402_50V7K 34
6 EDP_TXN3 38 BKOFF# 38 I2C_TS_RST# I2C_TS_INT# 34
35
6 I2C_TS_INT# 35
R280 1 @ 2 10K_0402_5% 36
C370 1 2 .1U_0402_16V7K EDP_AUXP_C 37 36
6 EDP_AUXP EDP_AUXN_C +3VS USB20_P7_CAMERA 37
2 6 EDP_AUXN C369 1 2 .1U_0402_16V7K 38 2
USB20_N7_CAMERA 39 38
For Camera 39
40
40
+3VS E-T_0871K-F40N-00L
CONN@
EDP_AUXN_C R613 2 @ 1 100K_0402_5%
EDP_AUXP_C R614 2 @ 1 100K_0402_5% SP010011Z00

R406
0_0402_5%
1 @ 2 EDP_HPD
6 CPU_EDP_HPD
R364
100K_0402_5%
2 1

3 3

I2C Touch Screen +TS_PW R

+3VS R82 1 @ 2 0_0603_5%

+5VS R81 1 @ 2 0_0603_5%

Camera R427 1 @ 2 0_0402_5%

R428 1 @ 2 0_0402_5%
USB20_N7 2 1 USB20_N7_CAMERA
12 USB20_N7 2 1

USB20_P7 3 4 USB20_P7_CAMERA
12 USB20_P7 3 4
L27 @EMC@
DLW 21HN900HQ2L_4P
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 29 of 60
A B C D E
 A B C D E

+3VS_ALS

+5VS W=40mils +HDMI_5V_OUT

+1.5VS W=40mils

0.01U_0402_16V7K

C422
1 2 0_0402_5%

.1U_0402_16V7K
R368 @
U52
1 1

C423
3 ALS_CLK- 4 3 HDMI_R_CK-

.1U_0402_16V7K

.1U_0402_16V7K
OUT 4 3

0.01U_0402_16V7K

0.01U_0402_16V7K
C410

C411
1 2 2
1 1 1 1 1 WCM2012F2S-900T04_0805
IN ALS_CLK+ HDMI_R_CK+

C412
C378 L53 @EMC@1 2
U27 1 2

C413
2 .1U_0402_16V7K
GND 2
2 2 2 2 19 11 +HDMI_5V_OUT R369 1 @ 2 0_0402_5%
1 AP2330W-7_SC59-3 20 VDD15_1 VDD33 1
31 VDD15_2 30 ALS_TX2+ +3VS
40 VDD15_3 OUT_D2+ 29 ALS_TX2-
VDD15_4 OUT_D2- R370 1 @ 2 0_0402_5%
27 ALS_TX1+
C380 2 1 .1U_0402_16V7K HDMI_C_TX2+ 1 OUT_D1+ 26 ALS_TX1-
6 SOC_DP2_P0 IN_D2+ OUT_D1-

4
3
2
1
C379 2 1 .1U_0402_16V7K HDMI_C_TX2- 2 ALS_TX0- 4 3 HDMI_R_D0-
6 SOC_DP2_N0 IN_D2- ALS_TX0+ 4 3
25 RP16
C382 2 1 .1U_0402_16V7K HDMI_C_TX1+ 4 OUT_D0+ 24 ALS_TX0- 2.2K_0804_8P4R_5% WCM2012F2S-900T04_0805
6 SOC_DP2_P1 IN_D1+ OUT_D0-
C381 2 1 .1U_0402_16V7K HDMI_C_TX1- 5 ALS_TX0+ L54 @EMC@1 2 HDMI_R_D0+
6 SOC_DP2_N1 IN_D1- ALS_CLK+ 1 2
22

5
6
7
8
C384 2 1 .1U_0402_16V7K HDMI_C_TX0+ 6 OUT_CLK+ 21 ALS_CLK-
6 SOC_DP2_P2 IN_D0+ OUT_CLK-
+3VS +3VS_ALS 6 SOC_DP2_N2 C383 2 1 .1U_0402_16V7K HDMI_C_TX0- 7 R371 1 @ 2 0_0402_5%
IN_D0- 39 SOC_DP2_CTRL_DATA
1 2 0_0603_5% 1 .1U_0402_16V7K HDMI_C_CLK+ SDA_SRC SOC_DP2_CTRL_CLK SOC_DP2_CTRL_DATA 6
R2554 @ 6 SOC_DP2_P3 C386 2 9 38
1 .1U_0402_16V7K HDMI_C_CLK- IN_CLK+ SCL_SRC HDMI_SDATA SOC_DP2_CTRL_CLK 6
6 SOC_DP2_N3 C385 2 10 33
IN_CLK- SDA_SNK 32 HDMI_SCLK
HDMI_BUF 14 SCL_SNK R372 1 @ 2 0_0402_5%
HDMI_DCIN_EN 13 DDCBUF/SDA_CTL
+3VS_ALS HDMI_EQ 17 DCIN_EN/SCL_CTL 3 SOC_DP2_HPD
EQ/I2C_ADDR HPD_SRC SOC_DP2_HPD 6 ALS_TX1- HDMI_R_D1-
8 4 3
I2C_CTL_EN R380 1 2 100K_0402_5% 4 3
HDMI_HPD 28 12 WCM2012F2S-900T04_0805
HDMI_DCIN_EN HPD_SNK NC_1 +1.5VS ALS_TX1+ HDMI_R_D1+
R1063 1 @ 2 4.7K_0402_5% HPD_SNK with Internal PD 150K 15 L55 @EMC@1 2
R1062 1 @ 2 4.7K_0402_5% HDMI_CFG 18 NC_2 34 HDMI_ISET 1 2
@T212 36 REXT NC_3 37
PD# NC_4 +3VS_ALS

1
HDMI_CFG 23 R373 1 @ 2 0_0402_5%
HDMI_PRE CFG

0.01U_0402_16V7K

0.01U_0402_16V7K
R2043 16
4.99K_0402_1% PRE
1 1

C416

C417
35
GND 41
2 2 2
EPAD R374 1 @ 2 0_0402_5%
PS8201ATQFN40GTR2A0_TQFN40_5X5 2 2

ALS_TX2- 4 3 HDMI_R_D2-
PS8407A --- SA000077R30 4 3
close pin12,37 WCM2012F2S-900T04_0805
ALS_TX2+ L56 @EMC@1 2 HDMI_R_D2+
1 2

R375 1 @ 2 0_0402_5%
Intel Sugesstion

R1059 1 @ 2 20K_0402_5%
HDMI connector
JHDMI1
+3VS_ALS +3VS_ALS HDMI_HPD 19
+3VS_ALS +3VS_ALS 18 HP_DET
+HDMI_5V_OUT +5V
17
HDMI_SDATA 16 DDC/CEC_GND
SDA
1

HDMI_SCLK 15
SCL
1

1
14
Reserved

2
@ R1048 @ R1050 13
4.7K_0402_5% 4.7K_0402_5% @ R1053 @ R1058 HDMI_R_CK- 12 CEC
4.7K_0402_5% 4.7K_0402_5% 11 CK-
2

HDMI_BUF HDMI_PRE HDMI_R_CK+ 10 CK_shield

2

2
HDMI_EQ HDMI_ISET HDMI_R_D0- 9 CK+
D0-
1

8
D0_shield
1

1
D2 HDMI_R_D0+ 7
3 HDMI_R_D1- D0+ 3
@ R1049 @ R1051 @EMC@ 6
4.7K_0402_5% 4.7K_0402_5% @ R1054 @ R1060 YSLC05CH_SOT23-3 5 D1-

1
4.7K_0402_5% 4.7K_0402_5% HDMI_R_D1+ 4 D1_shield 20
2

HDMI_R_D2- 3 D1+ GND 21

2

2
2 D2- GND 22
Reserved for ESD HDMI_R_D2+ 1 D2_shield GND 23
D2+ GND
ACON_HMRB4-AK120C
Enable active DDC buffer; Receiver equalization setting; CONN@
Internal pull down at ~150KΩ , 3.3V I/O Output pre-emphasis setting; Internal pull down at ~150kΩ , 3.3V I/O.
L: default, passive DDC pass-through Internal pull down at ~150kΩ , L: programmable EQ for channel loss up to 5.3dB
DC232004400
H: active DDC buffer with internal pull 3.3V I/O. H: programmable EQ for channel loss up to 10dB
up2.36K resistor L: no pre-emphasis M: programmable EQ for channel loss up to 14dB
M: active DDC buffer without internal pull H: 1.6dB pre-emphasis
up resistor M: 3.0dB pre-emphasis

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 30 of 60
A B C D E
 A B C D E

+3VS +HDMI_5V_OUT
L3
FBMA-L11-160808-800LMT_0603
1 2 +3VS_CRT

1 1 1 1

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K
1 6 SOC_DP1_HPD 1
C4

2
10U_0603_6.3V6M

C1

C2

C3

2.2K_0402_5%

2.2K_0402_5%
1
2 2 2 2
R2530
100K_0402_5%

R16

R17
1

1
2

20
U1

9
DVCC_33

DVCC_33

VDD_DAC_33
SOC_DP1_HPD 1
HPD
C6 1 2 .1U_0402_16V7K DP_CRT_AUXN 27 6 CRT_DATA
6 SOC_DP1_AUXN DP_CRT_AUXP AUX_N VGA_SDA CRT_CLK CRT_DATA 32
6 SOC_DP1_AUXP C5 1 2 .1U_0402_16V7K 26 4 CRT_CLK 32
AUX_P VGA_SCL 8 HSYNC
SOC_DP1_P0_C HSYNC HSYNC 32
6 SOC_DP1_P0 C36 1 2 .1U_0402_16V7K 29 7 VSYNC VSYNC 32
C37 1 2 .1U_0402_16V7K SOC_DP1_N0_C 30 LANE0P VSYNC
6 SOC_DP1_N0 LANE0N CRT_R
15
SOC_DP1_P1_C RED_P CRT_R 32
6 SOC_DP1_P1 C38 1 2 .1U_0402_16V7K 31
C39 1 2 .1U_0402_16V7K SOC_DP1_N1_C 32 LANE1P 12 CRT_G
6 SOC_DP1_N1 LANE1N GREEN_P CRT_G 32
10 CRT_B
+3VS BLUE_P CRT_B 32
22 POL1_SDA
POL1_SDA

4
3
2
1
C9 2 1 2.2U_0402_6.3V6M 23 POL2_SCL
POL2_SCL 75_0804_8P4R_1%
C10 2 1 .1U_0402_16V7K VCCK_12 19 2 CRT_SMB_CLK R18 1 @ 2 0_0402_5% RP23
VCCK_12 SMB_SCL 3 CRT_SMB_SDA R19 1 @ 2 0_0402_5%
C11 2 1 .1U_0402_16V7K 24 SMB_SDA
2 2

5
6
7
8
AVCC_33
C12 2 1 .1U_0402_16V7K VCCK_12 25
AVCC_12 21 LDO_EN
R9 1 2 12K_0402_1% 28 LDO_EN
RRX
18
11 XO
13 BLUE_N 17
14 GREEN_N XI/CKIN
16 GND_DAC
33 RED_N SOC_SML1CLK
EPAD_GND SOC_SML1DATA SOC_SML1CLK 8,20,38
SOC_SML1DATA 8,20,38
10U_0603_6.3V6M RTD2168-CG_QFN32_5X5
2 Address:(layout guide P.11)
Please reserve slave address of
C15

0x64/0x65 and 0x68/0x69 for RTD2168’ s use

1

+3VS +3VS +3VS

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

3 3
1

@
R10

R11

R12

POL_SDA
2

0 1 LDO_EN:
POL2_SCL POL1_SDA LDO_EN
0 X EP *1: Internal 1.2V
4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

0: External 1.2V
1

POL_SCL @
1 *ROM EEPROM
R13

R14

R15

ROM: Internal ROM

2

EP: Programmed external EC

EEPROM: External ROM

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Realtek RTD2168
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 31 of 60
A B C D E
 A B C D E

CRT conn. W=40mils

+HDMI_5V_OUT
1 1

SM01000LU00 ( S SUPPRE_ MURATA BLM15BA220SN1D 0402)

CRT Connector
L2503 EMC@
BLM15BA220SN1D_2P
1 2 CRT_R_2 JCRT1
31 CRT_R
L2505 EMC@ 6
BLM15BA220SN1D_2P T99 @ 11
1 2 CRT_G_2 1
31 CRT_G
L2504 EMC@ 7
BLM15BA220SN1D_2P 12
1 2 CRT_B_2 2
31 CRT_B
8

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J
13
1 1 1 1 1 1 3
9

C2529

C2530

C2531

C2532

C2533

C2534
14
T109 @ 4
2 2 2 2 2 2 10 16
G
15 G 17
5

C-H_13-12201536CP
CONN@

@ R2524 DC060005700
+HDMI_5V_OUT C2535 1 @ 2 0_0603_5% CRT_HSYNC_2
2 2
U2502 .1U_0402_16V7K
1 5 2 1 R2525 CRT_CLK 31
R2526 OE Vcc 1 @ 2 0_0603_5% CRT_VSYNC_2
CRT_DATA 31
0_0402_5% 1 1
2 @ 1 CRT_HSYNC 2 @ @
31 HSYNC IN A PVT modify 12/31 C2536 C2537
form +5VS_6513 change to +HDMI_5V_OUT 10P_0402_50V8J 10P_0402_50V8J
3 4 CRT_HSYNC_1 2 2
GND OUT Y

M74VHC1GT125DF2G_SC70-5

R2528 +HDMI_5V_OUT
0_0402_5% U2503
2 @ 1 1 5
OE Vcc

2 @ 1 CRT_VSYNC 2
31 VSYNC IN A
R2529
0_0402_5%
3 4 CRT_VSYNC_1
GND OUT Y

M74VHC1GT125DF2G_SC70-5

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 32 of 60
A B C D E
 A B C D E

LAN-RTL8411B
+3VALW +3V_LAN

R214
0_0805_5%
1 @ 2 W=60mil W=60mil
IDC=1200mA +LAN_VDD +3V_LAN
W=60mil
60mil U2504
60mil L2506
300mA 1.4A
1 1
5 1 +REGOUT 1 2
IN OUT 2.2UH_HPC252012NF-2R2M_20%

4.7U_0603_6.3V6K
C2538

1U_0402_6.3V6K
C2545

4.7U_0603_6.3V6K
C2547
2
GND
Using for Switch mode 1 1 1 1 1 1 1 1 1 1 1 1 1

.1U_0402_16V7K
C2539

.1U_0402_16V7K
C2540

.1U_0402_16V7K
C2541

.1U_0402_16V7K
C2542

.1U_0402_16V7K
C2543

.1U_0402_16V7K
C2544

.1U_0402_16V7K
C2546

.1U_0402_16V7K
C2548

.1U_0402_16V7K
C2549

.1U_0402_16V7K
C2550
4 3
EN OC The trace length from
2
SY6288C20AAC_SOT23-5 Lx to PIN48 (REGOUT)
C2551 2 2 2 2 2 2 2 2 2 2 2 2 2
LAN_PWR_EN
and from C to Lx must
1U_0402_6.3V6K LAN_PWR_EN 38 < 200mils.
1

Place near Pin 3,8,33,46 Place near Pin 20 Using for Switch mode Place near Pin 11,32,48
11/27: P/N change to SH00000RT00
From EC The trace length
( S COIL 2.2UH +-20% from C to
High active. HPC252012NF-2R2M 1.3A) PIN34,35(VDDREG)
EN threshold voltage min:1.2V must < 200mils.
typ:1.6V max:2.0V
Current limit threshold 1.5~2.8A
+3V_LAN Rising time must >0.5ms and <100ms

reserve EC_PME# pull high 100K to +3VALW_EC PVT modify 01/06

U2505 R2534, R2537, R2539, R2535, R2536
Power Manahement/Isolation change to R-short
ISOLATEB 31
R2533 1 @ 2 0_0402_5% LAN_PME# 39 ISOLATEBPIN
38 EC_PME# LANWAKEB Card Reader
DVT modify 12/04 R2550 1 2 10K_0402_5% 15 SD_D0 R2534 1 @ 2 0_0402_5% SD_D0_R
for WOL pull high to +3V_LAN +3V_LAN SD_D0/MS_D1 SD_D1 SD_D1_R SD_D0_R 34
PCI-Express 14 R2537 1 @ 2 0_0402_5%
2 CLK_PCIE_P1 SD_D1 SD_CLK SD_CLK_R SD_D1_R 34 2
10 CLK_PCIE_P1 23 16 R2538 1 2 10_0402_5% SD_CLK_R 34
CLK_PCIE_N1 24 REFCLK_P SD_CLK/MS_D0 17 SD_CMD R2539 1 @ 2 0_0402_5% SD_CMD_R
10 CLK_PCIE_N1 REFCLK_N SD_CMD/MS_D2 SD_D3 SD_D3_R SD_CMD_R 34
18 R2535 1 @ 2 0_0402_5% 2
PLT_RST_BUF# SD_D3/MS_D3 SD_D2 SD_D2_R SD_D3_R 34
30 19 R2536 1 @ 2 0_0402_5%
10,35 PLT_RST_BUF# CLKREQ_PCIE#1 PERSTBPIN SD_D2/MS_CLK SD_WP SD_D2_R 34
PU at PCH side 29 28 C2554
10 CLKREQ_PCIE#1 CLKREQBPIN MS_BS/SD_WP# SD_WP 34
5P_0402_50V8C
C2552 1 2 .1U_0402_16V7K PCIE_CRX_C_DTX_P5 25 1
12 PCIE_CRX_DTX_P5 PCIE_CRX_C_DTX_N5 HSOP @EMC@
C2553 1 2 .1U_0402_16V7K 26
12 PCIE_CRX_DTX_N5 HSON SD_CD#
12 PCIE_CTX_C_DRX_P5 21 42 close to pin17
HSIP SD_CD# SD_CD# 34
12 PCIE_CTX_C_DRX_N5 22 43
HSIN MS_CD#
Transceiver Interface
LAN_MIDI0+ 1
34 LAN_MIDI0+ LAN_MIDI0- MDIP0
2
34 LAN_MIDI0- LAN_MIDI1+ MDIN0
4
34 LAN_MIDI1+ LAN_MIDI1- MDIP1 +3V_LAN
5 48
34 LAN_MIDI1- LAN_MIDI2+ MDIN1 HV_GIGA
6 11
34 LAN_MIDI2+ LAN_MIDI2- MDIP2 HV_GIGA
7 12 1400mA
34 LAN_MIDI2- LAN_MIDI3+ MDIN2 VDD33
9 32
34 LAN_MIDI3+ LAN_MIDI3- MDIP3 VDD33
10
+3V_LAN 34 LAN_MIDI3- MDIN3
R2552
1

0_0402_5% XTLI 44 33 +LAN_VDD

R2541 XTLO_R 1 @ 2 XTLO 45 CKXTAL1 Clock VDD10 3
CKXTAL2 AVDD10 8
10K_0402_5% AVDD10
300mA
@
GPO Regulator and Reference
2

+REGOUT 36 20
35 REG_OUT VDDTX
+3V_LAN VDDREG
SWR mode 34
ENSWREG
800mA
46 13
+LAN_VDD LV_GEN Card_3V3 +CARD_3V3 Protect cotact Card contact
2 R2542 1 LAN_RST 47
3 2.49K_0402_1% RSET 27 +VDD33_18 3
DV33/18 Write protect Write Enable
(Lock) (Unlock)

4.7U_0603_6.3V6K
C2556
41
Y2500 R2540 1 @ 2GPO 38 LED0
38 LAN_GPO LED1/GPO 1 1 1

.1U_0402_16V7K
C2555
25MHZ_10PF_7V25000014 0_0402_5% 37 LEDs
40 LED2 C2557 Card Uninsert Open Open Open
XTLI 1 3 XTLO_R LED_CR 49 @
1 3 for disable PHY E_Pad 2 2 2
.1U_0402_16V7K
Card insert Open Close Close
GND GND reserve 0 ohm
1 1
10P_0402_50V8J
10P_0402_50V8J 2 4 C2559
C2558 Place near Pin 27
2 2
RTL8411B-CGT_QFN48_6X6

+3VS
1

R2543
1K_0402_5%
2

ISOLATEB
2

R2544
15K_0402_5%
4 4
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN RTL8411B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 33 of 60
A B C D E
 A B C D E

LAN Connector
1 1
T2500
LAN_TERMAL1 24 JRJ45
LAN_MIDI0+ 2 TCT1 MCT1 23 RJ45_MIDI0+ RJ45_MIDI0+ 1
33 LAN_MIDI0+ LAN_MIDI0- TD1+ MX1+ RJ45_MIDI0- PR1+
33 LAN_MIDI0- 3 22
TD1- MX1- RJ45_MIDI0- 2
4 21 PR1-
LAN_MIDI1+ 5 TCT2 MCT2 20 RJ45_MIDI1+ RJ45_MIDI1+ 3
33 LAN_MIDI1+ LAN_MIDI1- TD2+ MX2+ RJ45_MIDI1- PR2+
33 LAN_MIDI1- 6 19
TD2- MX2- RJ45_MIDI2+ 4
7 18 PR3+
LAN_MIDI2+ 8 TCT3 MCT3 17 RJ45_MIDI2+ RJ45_MIDI2- 5
33 LAN_MIDI2+ LAN_MIDI2- TD3+ MX3+ RJ45_MIDI2- PR3-
33 LAN_MIDI2- 9 16
TD3- MX3- RJ45_MIDI1- 6
10 15 PR2-
LAN_MIDI3+ 11 TCT4 MCT4 14 RJ45_MIDI3+ RJ45_MIDI3+ 7 9
33 LAN_MIDI3+ LAN_MIDI3- TD4+ MX4+ RJ45_MIDI3- PR4+ GND
33 LAN_MIDI3- 12 13 10
TD4- MX4- RJ45_MIDI3- 8 GND
PR4-
SANTA_130456-291 40mil

4
3
2
1
GST5009-E CONN@
SP050006B10 75_0804_8P4R_1% RJ45_GND 1 2 LANGND
RP24
DC234005310 C2560
1
40mil 10P_0402_50V8J
C2561

5
6
7
8
.1U_0402_16V7K LANGND

1
2
RJ45_GND @
Place close to TCT pin J15 JP2500
2 2
JUMP_43X118 @EMC@
B88069X9231T203_4P5X3P2-2

2
D1
EMC@
MESC5V02BD03_SOT23-3

1
Card Reader Connector

JREAD1
SD_D3_R 1
33 SD_D3_R CD/DAT3
+CARD_3V3 SD_CMD_R 2
33 SD_CMD_R CMD
3
VSS1
Close to Card Reader CONN 4
VDD
SD_CLK_R

4.7U_0603_6.3V6K
C2564

C2565
33 SD_CLK_R 5
CLK

.1U_0402_16V7K
1 1
3 6 3
VSS2
SD_D0_R 7
2 2 33 SD_D0_R DAT0
SD_D1_R 8 12
33 SD_D1_R DAT1 G1
SD_D2_R 9 13
33 SD_D2_R DAT2 G2
SD_CD# 10 14
33 SD_CD# CD G3
SD_W P 11 15
33 SD_W P WP G4
TAITW _PSDAT4-11GLBS1NN4H2
R156 CONN@
SD_CLK_R 1 @EMC@2 0_0402_5% 1 2
C2566 @EMC@
10P_0402_50V8J
SP07000ZC00
Close to JREAD1 for EMI

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN RJ45/CR SD Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 34 of 60
A B C D E
 A B C D E

Wireless LAN
+3VS 60mil +3VS_W LAN
R212
1 NIOAC@ 2 0_0805_5%

1
1
C458
1
@
C459
1
C460
KEY E +3VS_W LAN
1

4.7U_0603_6.3V6K .1U_0402_16V7K JNGFF1

2 2 2 1 2
.1U_0402_16V7K USB20_P5 3 GND_1 3.3VAUX_2 4
12 USB20_P5 USB20_N5 USB_D+ 3.3VAUX_4
USB2 P5 12 USB20_N5
5
USB_D- LED1#
6 @ T3801
7 8
(For BT) 9 GND_7 PCM_CLK 10
11 SDIO_CLK PCM_SYNC 12
13 SDIO_CMD PCM_OUT 14
+3VS_W LAN 15 SDIO_DAT0 PCM_IN 16
+3VALW SDIO_DAT1 LED2# @ T3802
17 18
U9 19 SDIO_DAT2 GND_18 20
W=60mils SDIO_DAT3 UART_WAKE UART_2_CRXD_DTXD
1U_0402_6.3V6K
C165

5 1 21 22
IN OUT SDIO_WAKE UART_TX UART_2_CRXD_DTXD 11
1 23
SDIO_RST
GND
2 PH +3VS at SOC side, for win7 USB3 debug
UART_2_CTXD_DRXD
@ 24
UART_RX UART_2_CTXD_DRXD 11
4 3 25 26
2 EN OC PCIE_CTX_C_DRX_P6 27 GND_33 UART_RTS 28
12 PCIE_CTX_C_DRX_P6 PCIE_CTX_C_DRX_N6 PET_RX_P0 UART_CTS E51TXD_P80DATA_R
SY6288C20AAC_SOT23-5 29 30 R873 2 @ 1 0_0402_5%
12 PCIE_CTX_C_DRX_N6 PET_RX_N0 CLink_RST E51TXD_P80DATA 38
IOAC@ 31 32 R874 2 1
(link to PICE Port 4) PCIE_CRX_DTX_P6 33 GND_39 CLink_DATA 34 100K_0402_5%
12 PCIE_CRX_DTX_P6 PCIE_CRX_DTX_N6 PER_TX_P0 CLink_CLK
38 W LAN_ON PCIE X1 12 PCIE_CRX_DTX_N6 35
PER_TX_N0 COEX3
36 @ T3803
37 38 @ T3804
CLK_PCIE_P2 39 GND_45 COEX2 40 T3805
10 CLK_PCIE_P2 CLK_PCIE_N2 REFCLK_P0 COEX1 SUSCLK_R @
41 42 @ T3806
10 CLK_PCIE_N2 REFCLK_N0 SUSCLK(32KHz) W L_RST#_R
43 44 R440 1 @ 2 0_0402_5%
CLKREQ_PCIE#2 GND_51 PERST0# E51RXD_P80CLK_R PLT_RST_BUF# 10,33
(From PCH CLKOUT5) 10 CLKREQ_PCIE#2 45 46 R872 2 @ 1 0_0402_5%
W LAN_PME# CLKREQ0# W_DISABLE2# W L_OFF# E51RXD_P80CLK 38
PCIE CLK 38 W LAN_PME#
47
PEWAKE0# W_DISABLE1#
48
W L_OFF# 38
49 50
2
NGFF WL+BT (KEY E) R3807
51
53
GND_57
RSVD/PCIE_RX_P1
I2C_DAT
I2C_CLK
52
54 E51RXD_P80CLK mulitplexed with
2

2 1 10K_0402_5% 55 RSVD/PCIE_RX_N1 I2C_IRQ 56

+3VS_W LAN
57 GND_63 RSVD_64 58
BT_ON function
R3808 59 RSVD/PCIE_TX_P1 RSVD_66 60
2 @ 1 10K_0402_5% 61 RSVD/PCIE_TX_N1 RSVD_68 62
+3VS_W LAN GND_69 RSVD_70
63 64
65 RSVD_71 3.3VAUX_72 66
67 RSVD_73 3.3VAUX_74
GND_75 68
69 GND1
GND2
BELLW _80152-3221
CONN@
SP070013E00

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M.2 Key E (WLAN)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 35 of 60
A B C D E
 A B C D E

SATA HDD Conn. SATA ODD Conn.

1 1
JODD1
JHDD1
1
1 C401 1 2 0.01U_0402_16V7K SATA_CTX_C_DRX_P1 2 GND
SATA_CTX_DRX_P0 SATA_CTX_C_DRX_P0 GND 12 SATA_CTX_DRX_P1 SATA_CTX_C_DRX_N1 A+
12 SATA_CTX_DRX_P0 HDD@ C392 1 2 0.01U_0402_16V7K 2 12 SATA_CTX_DRX_N1 C402 1 2 0.01U_0402_16V7K 3
SATA_CTX_DRX_N0 HDD@ C393 1 2 0.01U_0402_16V7K SATA_CTX_C_DRX_N0 3 A+ 4 A-
12 SATA_CTX_DRX_N0 A- SATA_CRX_C_DTX_N1 GND
4 C403 1 2 0.01U_0402_16V7K 5
SATA_CRX_DTX_N0 SATA_CRX_C_DTX_N0 GND 12 SATA_CRX_DTX_N1 SATA_CRX_C_DTX_P1 B-
HDD@ C391 1 2 0.01U_0402_16V7K 5 C405 1 2 0.01U_0402_16V7K 6
12 SATA_CRX_DTX_N0 SATA_CRX_DTX_P0 SATA_CRX_C_DTX_P0 B- 12 SATA_CRX_DTX_P1 B+
HDD@ C394 1 2 0.01U_0402_16V7K 6 7
12 SATA_CRX_DTX_P0 B+ GND
7
GND +5VS R211 +5VS_ODD
0_0805_5% 80mils 8
R308 8 1 NIOAC@ 2 +5VS_ODD 9 DP
+3VS V33 +5V
0_0402_5% 9 10
+3VS_HDD V33 ODD_MD +5V

10U_0603_6.3V6M

.1U_0402_16V7K
1 @ 2 10 1 1 11
V33 MD

C404

C407
11 12 14
12 GND T185 @ 13 GND GND 15
13 GND GND GND
R49 1 @ 2 0_0805_5% +5VS_HDD 14 GND 2 2
+5VS V5
15 SANTA_201501-2
16 V5 CONN@
17 V5

41 G_INT2 R190 1 @ 2 0_0402_5% G_INT2_R 18 GND SP01001MV00

19 Reserved 23
20 GND GND 24
21 V12 GND
22 V12
V12
+3VS +5VS_HDD
2 2
SANTA_192602-1 +5VS
CONN@ +5VS_ODD
100mils U66
DC021409221 5 1
IN OUT
10U_0603_6.3V6M
C420

1 1
1

2
C390 C397 GND
.1U_0402_16V7K HDD@ .1U_0402_16V7K ODD_EN 4 3 ODD_OC# @ T187
38 ODD_EN
2

2 @ 2 @ EN OC
SY6288C20AAC_SOT23-5
IOAC@

+3VS
+3VS

SATA HDD Conn.

1

0.01U_0402_16V7K
1 BA@ 1
R589
JHDD2
4.7K_0402_5% C425

C418
@ .1U_0402_16V7K
U2506 2 2 12
BA@
2

7 10 11 GND
EN VDD 20 GND
3 VDD 3
SATA_CTX_DRX_P0 BA@ C406 2 1 SATA_CTX_C_DRX_P0_1 0.01U_0402_16V7K 1
SATA_CTX_DRX_N0 BA@ C409 2 1 SATA_CTX_C_DRX_N0_1 0.01U_0402_16V7K 2 A_INp 6 1 R660 2 BA@ 10
A_INn NC 16 4.99K_0402_1% RDSATA_PTX_DRX_P0 C534 1 2 BA@ 0.01U_0402_16V7K RDSATA_PTX_C_DRX_P0 9 GND
SATA_CRX_DTX_P0 BA@ C399 2 1 SATA_CRX_C_DTX_P0_1 0.01U_0402_16V7K 5 NC RDSATA_PTX_DRX_N0 C535 1 2 BA@ 0.01U_0402_16V7K RDSATA_PTX_C_DRX_N0 8 TXP
SATA_CRX_DTX_N0 BA@ C400 2 1 SATA_CRX_C_DTX_N0_1 0.01U_0402_16V7K 4 B_OUTp 9 APE0 7 TXN
B_OUTn A_PRE0 8 BPE0 RDSATA_PRX_DTX_N0 C536 1 2 BA@ 0.01U_0402_16V7K RDSATA_PRX_C_DTX_N0 6 GND
APE1 19 B_PRE0 RDSATA_PRX_DTX_P0 C537 1 2 BA@ 0.01U_0402_16V7K RDSATA_PRX_C_DTX_P0 5 RXN
BPE1 17 A_PRE1 15 RDSATA_PTX_DRX_P0 4 RXP
B_PRE1 A_OUTp 14 RDSATA_PTX_DRX_N0 3 GND
A_OUTn +5VS 5V
TEST 18 2
3 TEST 11 RDSATA_PRX_DTX_P0 1 5V
R665 2 @ 1 4.7K_0402_5% 13 GND B_INp 12 RDSATA_PRX_DTX_N0 5V
+3VS GND B_INn
21 ACES_51625-01001-001
EPAD CONN@
PS8520CTQFN20GTR2-A_TQFN20_4X4 DC021407091
2

BA@
R659
+3VS 4.7K_0402_5% USE 8527 re-driver
BA@ +5VS
R338 1 BA@ 2 4.7K_0402_5% APE0
SA00007JU00
1

R335 1 BA@ 2 4.7K_0402_5% BPE0

100mils
R659 change to 0

10U_0603_6.3V6M
C426
R332 1 @ 2 4.7K_0402_5% APE1 ohm when 8520 use 1

.1U_0402_16V7K
C414
R337 1 @ 2 4.7K_0402_5% BPE1 BA@

2
R334 1 @ 2 4.7K_0402_5% TEST 2
4 BA@ 4

R586 1 @ 2 4.7K_0402_5% APE0

R339 1 @ 2 4.7K_0402_5% BPE0

R588 1 BA@ 2 4.7K_0402_5% APE1

Security Classification Compal Secret Data Compal Electronics, Inc.
R587 1 BA@ 2 4.7K_0402_5% BPE1 2014/11/10 2016/11/10 Title
Issued Date Deciphered Date
R351 1 BA@ 2 4.7K_0402_5% TEST
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ODD/ HDD Re-Driver
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 36 of 60
A B C D E
 A B C D E

For RF request +5VALW

USB3.0 (Port 1) R473

R474
1
1
@
@
2 0_0402_5%
2 0_0402_5%
USB3_CTX_L_DRX_P1
For ESD request

1 1
D15 EMC@
10 9 USB3_CTX_L_DRX_P1
C483 EMC@
.1U_0402_16V7K
1 2 5
U25
1
+USB3_VCCA

USB3_CTX_C_DRX_N1 USB3_CTX_L_DRX_N1 IN OUT W=60mils

12 USB3_CTX_DRX_N1 C482 1 2 2 1
2 1 USB3_CTX_L_DRX_N1 2 2 USB3_CTX_L_DRX_N1
.1U_0402_16V7K 9 8 2
GND
C484 1 2 USB3_CTX_C_DRX_P1 3 4 USB3_CTX_L_DRX_P1 USB3_CRX_L_DTX_P1 4 4 7 7 USB3_CRX_L_DTX_P1 USB_EN 4 3 R454 1 @ 2 0_0402_5%
12 USB3_CTX_DRX_P1 3 4 38 USB_EN EN OC USB_OC0# 12
.1U_0402_16V7K
L24 @EMC@ USB3_CRX_L_DTX_N1 5 5 6 6 USB3_CRX_L_DTX_N1 SY6288C20AAC_SOT23-5 1
DLW21HN900HQ2L_4P
3 3 C612
1 .1U_0402_16V7K 1
8 2
@
R475 1 @ 2 0_0402_5% L05ESDL5V0NA-4 SLP2510P8
R476 1 @ 2 0_0402_5%
+USB3_VCCA
USB3_CRX_DTX_N1 2 1 USB3_CRX_L_DTX_N1
12 USB3_CRX_DTX_N1 2 1
W=100mils
USB3_CRX_DTX_P1 3 4 USB3_CRX_L_DTX_P1
12 USB3_CRX_DTX_P1 3 4 1 1
L25 @EMC@ C486 + C487
DLW21HN900HQ2L_4P .1U_0402_16V7K
150U_6.3V_M_D2 2
2 EMC@

6
D4 EMC@
3 U2DP1_L USB3.0 Conn.
I/O4 I/O2
Note: (A4WAS PVT) JUSB1
Delete 0 ohm path for DFX request +USB3_VCCA 1
U2DN1_L VBUS
Avoid Common Mode Choke Shift 2
D-
5 2 U2DP1_L 3
USB20_P1 2 1 U2DP1_L VDD GND 4 D+
12 USB20_P1 2 1 USB3_CRX_L_DTX_N1 GND
5
USB3_CRX_L_DTX_P1 6 StdA-SSRX- 10
USB20_N1 3 4 U2DN1_L 4 1 U2DN1_L 7 StdA-SSRX+ GND 11
12 USB20_N1 3 4 I/O3 I/O1 USB3_CTX_L_DRX_N1 8 GND-DRAIN GND 12
L26 EMC@ AZC099-04S.R7G_SOT23-6 USB3_CTX_L_DRX_P1 9 StdA-SSTX- GND 13
DLW21HN900HQ2L_4P StdA-SSTX+ GND
LOTES_AUSB0015-P001A
CONN@
2
DC23300AI00 2

USB3.0 (Port 2) R477

For RF request
1 @ 2 0_0402_5%
For ESD request
D16 EMC@
+5VALW

R478 1 @ 2 0_0402_5% USB3_CTX_L_DRX_P2 1 1 10 9 USB3_CTX_L_DRX_P2 C493 EMC@

.1U_0402_16V7K +USB3_VCCB
C490 1 2 USB3_CTX_C_DRX_N2 2 1 USB3_CTX_L_DRX_N2 USB3_CTX_L_DRX_N2 2 2 9 8 USB3_CTX_L_DRX_N2 1 2
12 USB3_CTX_DRX_N2 2 1
.1U_0402_16V7K U26
USB3_CRX_L_DTX_P2 4 4 7 7 USB3_CRX_L_DTX_P2 1 2 C141 @ 5 1
USB3_CTX_C_DRX_P2 USB3_CTX_L_DRX_P2 IN OUT W=60mils
12 USB3_CTX_DRX_P2 C485 1 2 3 4 1U_0402_6.3V6K
3 4 USB3_CRX_L_DTX_N2 5 5 USB3_CRX_L_DTX_N2
.1U_0402_16V7K 6 6 2
L28 @EMC@ GND
DLW21HN900HQ2L_4P 3 3 38 4 3 R467 1 @ 2 0_0402_5%
USB_CHARGE_2A EN OC USB_OC1# 12
R479 1 @ 2 0_0402_5% 8 SY6288C20AAC_SOT23-5 1
R480 1 @ 2 0_0402_5%
L05ESDL5V0NA-4 SLP2510P8 C614
USB3_CRX_DTX_N2 2 1 USB3_CRX_L_DTX_N2
12 USB3_CRX_DTX_N2 2 1 .1U_0402_16V7K
2
@
USB3_CRX_DTX_P2 3 4 USB3_CRX_L_DTX_P2 D5 EMC@
12 USB3_CRX_DTX_P2 3 4 USB20_P2_L
6 3
L30 @EMC@ I/O4 I/O2
DLW21HN900HQ2L_4P

+USB3_VCCB 5 2
VDD GND

3 3

4 1 USB20_N2_L
I/O3 I/O1
Note: (A4WAS PVT) AZC099-04S.R7G_SOT23-6
Delete 0 ohm path for DFX request
Avoid Common Mode Choke Shift
+USB3_VCCB
U2DP2 2 1 USB20_P2_L
2 1
W=100mils
U2DN2 3
3 4
4 USB20_N2_L
1 1
USB/B (USB Port 3, + AUDIO) JUSB3
L29 EMC@ C489 + C488 HPOUT_L_1 1
40 HPOUT_L_1 HPOUT_R_1 1
DLW21HN900HQ2L_4P .1U_0402_16V7K 40 HPOUT_R_1 2
150U_6.3V_M_D2 2 SLEEVE 3 2
2 EMC@ 40 SLEEVE 3
RING2 4
USB3.0 Conn 40
40
RING2
HP_PLUG#
HP_PLUG#
GNDA
5
6
4
5
JUSB2 7 6

USB Host Charger USB20_N2_L

USB20_P2_L
1
2
3
VBUS
D- 12 USB20_P3
USB20_P3
USB20_N3
8
9
10
7
8
9
CB SELCDP D+ 12 USB20_N3 10
4 USB_EN 11
USB3_CRX_L_DTX_N2 5 GND 12 11
0 X DCP(Dedicated Charging Port)
USB3_CRX_L_DTX_P2 StdA-SSRX- 12
autodetect with mouse/keyboard wakeup 6 10 13 15
+3VLP 7 StdA-SSRX+ GND 11 14 13 GND 16
USB3_CTX_L_DRX_N2 GND-DRAIN GND +5VALW 14 GND
1 0 S0 charging with SDP(Standard Downstream Port) only 8 12
USB3_CTX_L_DRX_P2 9 StdA-SSTX- GND 13
StdA-SSTX+ GND ACES_51524-0140N-001
1

1 1 S0 charging with CDP(Charging Downstream Port) or

4
SDP only R853 LOTES_AUSB0015-P001A SP010021H00 4
10K_0402_5% CONN@ CONN@
U77 DC23300AI00
2

R854 1 @ 2 8 1 USB_CEN
38 USB_CB CB CEN USB_CEN 38
0_0402_5% 7 2 U2DN2
12 USB20_N2 6 TDM DM 3 U2DP2
12 USB20_P2 TDP DP
5 4 R857 1 @ 2
+5VALW
1
VDD SELCDP 9 10K_0402_5%
+5VALW Security Classification Compal Secret Data Compal Electronics, Inc.
Thermal Pad
Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title
C966 SLG55594AVTR_TDFN8_2X2
.1U_0402_16V7K
2
SA00006L600
USB_SELCDP 38
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB3.0 Conn/USB_B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 37 of 60
A B C D E
 A B C D E

+3VLP_EC +3VLP_ECA Board ID

+3VLP L4901 +3VLP_EC
JP4901 FBMA-L11-160808-800LMT_0603
1 2 1 2 +3VLP_ECA
1 2

2
JUMP_43X39 R4902
+3VALW_1.8VALW_PGPPA

.1U_0402_16V7K

.1U_0402_16V7K
@ 1 1 1 Ra 100K_0402_1%

C4901

C4902
C4917

1
EC_RST#

0_0402_5%
1 2 C4907

1
1
AD_BID

R4952
1000P_0402_50V7K For Power consumption .1U_0402_16V7K
2 2 R4953 @ 2
Measurement

1
0_0402_5% 1
ECAGND R4903
@ ECAGND 44

2
Rb 20K_0402_1% C4908

2
1 +3VCC_LPC 1
.1U_0402_16V7K
2
@

2
+3VLP_EC

111
125
22
33
96

67
9
U4901
1 @ 2 EC_PME#
Analog Board ID definition,

VCC0
VCC_LPC
VCC
VCC
VCC

VCC

AVCC
R4949 47K_0402_5%
EC_PME# PU +3V_LAN at LAN side Please see page 3.
ESPI Bus Pin : 1~5.7.8.10.12.14
LPC Bus Pin : 3~5.7.8.10.12.13 SUSPWRDNACK 1 21 EC_VCCST_PG_R
10 SUSPWRDNACK EC_KBRST# 2 GATEA20/GPIO00 EC_VCCST_PG/GPIO0F 23 EC_VCCST_PG_R 10,42 I2C_TS_RST# 100K_0402_5% 2
BEEP# 1 R616
TPM_SERIRQ 3 KBRST#/GPIO01 BEEP#/GPIO10 26 I2C_TS_RST# BEEP# 40
8,39 TPM_SERIRQ LPC_FRAME# 4 SERIRQ EC_FAN_PW M/GPIO12 27 DGPU_AC_DETECT I2C_TS_RST# 29
8,39 LPC_FRAME# LPC_AD3_R LPC_FRAME# PWM Output AC_OFF/GPIO13 DGPU_AC_DETECT 11,20
For turn off internal LPC module of KB9032 5
8,39 LPC_AD3_R LPC_AD2_R 7 LPC_AD3
8,39 LPC_AD2_R LPC_AD1_R LPC_AD2 BATT_TEMP USB_CB
ESPI@ 8 63 2 @ 1
1 2 ESPI_RST# 8,39 LPC_AD1_R LPC_AD0_R 10 LPC_AD1 VCIN1_BATT_TEMP/AD0/GPIO38 64 VCIN1_BATT_DROP BATT_TEMP 44,45
8,39 LPC_AD0_R LPC_AD0LPC & MISC VCIN1_BATT_DROP/AD1/GPIO39 ADP_I VCIN1_BATT_DROP 44
4.7K_0402_5% R4943
R4954 47K_0402_5% 65
ESPI_CLK_R ADP_I/AD2/GPIO3A AD_BID ADP_I 44,45
12 AD Input 66 R4943 for 9032 only
ESPI@ 8 ESPI_CLK_R PLT_RST# 13 CLK_PCI_EC AD_BID/AD3/GPIO3B 75 WLAN_PME#
PLT_RST# 10,20,39 PLT_RST# EC_RST# PCIRST#/GPIO05 AD4/GPIO42 EC_PME# WLAN_PME# 35
1 2 37 76
41 EC_RST# EC_SCI# 20 EC_RST# AD5/GPIO43 EC_PME# 33
R4950 47K_0402_5% Combine w/ SMI OPMODE(PIN70 Internal Pull High) :
6 EC_SCI# WLAN_ON EC_SCI#/GPIO0E
38 Pull Up : Intel eSPI Master Attached Flash Sharing Topology
35 WLAN_ON CLKRUN#/GPIO1D
1 2
C4916 @EMC@ 100P_0402_50V8J 68 LAN_PWR_EN --> For KB9032 Only.
39 KSI[0..7] DA0/GPIO3C USB_CB LAN_PWR_EN 33 Pull Down : Intel Legacy Wire-OR share ROM.
DA Output EN_DFAN1/DA1/GPIO3D 70
EN_DFAN1 USB_CB 37 --> For KB9022/9032 Use
Reserved for ESD 2014/9/17 KSI0 55 71
EN_DFAN1 41
KSI1 56 KSI0/GPIO30 DA2/GPIO3E 72 KBL_EN
1 2 AC_IN 57 KSI1/GPIO31 DA3/GPIO3F KBL_EN 39
KSI2
C4915 100P_0402_50V8J KSI3 58 KSI2/GPIO32 83 EC_MUTE#
59 KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A 84 USB_EN EC_MUTE# 40
KSI4
60 KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B 85 USB_CEN USB_EN 37
2 @EMC@ @EMC@ KSI5 2
2 1 2 1 ESPI_CLK_R 61 KSI5/GPIO35 PSCLK2/GPIO4C 86 PM_SLP_S0# USB_CEN 37
KSI6 PS2 Interface
KSI6/GPIO36 PSDAT2/GPIO4D TP_CLK PM_SLP_S0# 6,10 SYS_PWROK_R
C4910 R4904 33_0402_5% KSI7 62 87 1 @ 2 SYS_PWROK 10,42
39 KSO[0..17] KSO0 39 KSI7/GPIO37 TP_CLK/GPIO4E 88 TP_DATA TP_CLK 39
22P_0402_50V8J R4956 0_0402_5%
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA 39
KSO1 40 TP_CLK/DATA PU at PTP side
KSO2 41 KSO1/GPIO21
KSO3 42 KSO2/GPIO22 97 ENBKL +3VS
KSO3/GPIO23 ENKBL/GPXIOA00 TP_PWR_EN ENBKL 6
KSO4 43 98
KSO5 44 KSO4/GPIO24 W OL_EN/GPXIOA01 99 ME_EN TP_PWR_EN 39
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 VCIN0_PH ME_EN 9
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH1/GPXIOD00 VCIN0_PH 44
KSO8 47 KSO7/GPIO27 GPU_ALERT R634 1 VGA@ 2 10K_0402_5%
KSO8/GPIO28 SPI Device Interface USB_SELCDP
KSO9 48 119
49 KSO9/GPIO29 MISO/GPIO5B 120 EC_GPIO5C USB_SELCDP 37 GPU_OVERT R635 1 VGA@ 2 10K_0402_5%
KSO10 T205 @
KSO11 50 KSO10/GPIO2A MOSI/GPIO5C 126 EC_GPIO58
R4951
KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 EC_GPIO5A T203 @
0_0402_5% KSO12 51 128 T204 @
1 @ 2 EC_KBRST# KSO13 52 KSO12/GPIO2C SPICS#/GPIO5A
8 EC_KBRST#_R
53 KSO13/GPIO2D
KSO14
KSO15 54 KSO14/GPIO2E 73 GPU_ALERT +3VLP_EC
KSO15/GPIO2F EC_CIR_RX/AD6/GPIO40 SYS_PWROK_R GPU_ALERT 20
KSO16 81 74
KSO17 82 KSO16/GPIO48 SYS_PW ROK/AD7/GPIO41 89 BATT_4S
+3VLP_EC KSO17/GPIO49 GPIO50 BATT_BLUE_LED# BATT_4S 45 LID_SW#
90 R618 1 2 100K_0402_1%
BATT_CHG_LED#/GPIO52 ODD_EN BATT_BLUE_LED# 39
91
1 2 2.2K_0402_5% EC_SMB_CK1 EC_SMB_CK1 77 CAPS_LED#/GPIO53 92 PWR_LED ODD_EN 36
R490 GPIO
1 2 2.2K_0402_5% EC_SMB_DA1 44,45 EC_SMB_CK1 EC_SMB_DA1 78 EC_SMB_CLK1/GPIO44 PW R_LED#/GPIO54 93 BATT_AMB_LED# PWR_LED 39
R491
44,45 EC_SMB_DA1 SOC_SML1CLK 79 EC_SMB_DAT1/GPIO45 BATT_LOW _LED#/GPIO55 95 BATT_AMB_LED# 39
SYSON
8,20,31 SOC_SML1CLK SOC_SML1DATA EC_SMB_CLK2/GPIO46 SYSON/GPIO56 EC_TP_INT# SYSON 13,42,47
PU at CPU side 8,20,31 SOC_SML1DATA
80 121
EC_TP_INT# 6,39
For Thermal Portect Shutdown
EC_SMB_DAT2/GPIO47 VR_ON/GPIO57 127 USB_CHARGE_2A D23
DPW ROK_EC/GPIO59 USB_CHARGE_2A 37
SM Bus RB751V-40_SOD323-2
MAINPWON 1 2 3V_EN
PM_SLP_S3# 6 100 EC_RSMRST# 3V_EN 46
6,10,42 PM_SLP_S3# ESPI_RST# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_LID_OUT# EC_RSMRST# 6,10
14 101
3 8 ESPI_RST# 15 GPIO07 GPXIOA04 102 VCIN1_ADP_PROCHOT EC_LID_OUT# 11 3V_EN_R 1 2 3
SPOK R4901 1 2
46,49 SPOK TP_EN 16 GPIO08 VCIN1_ADP_PROCHOT/GPXIOA05 103 VCOUT1_PROCHOT VCIN1_ADP_PROCHOT 44
R492 1M_0402_5%
39 TP_EN TS_EN 17 GPIO0A VCOUT1_PROCHOT#/GPXIOA06 104 MAINPWON 1K_0402_5%
11,29 TS_EN WL_OFF# 18 GPIO0B VCOUT0_MAIN_PW R_ON/GPXIOA07 105 BKOFF#
MAINPWON 41,44,46
35 WL_OFF# AC_PRESENT GPIO0C BKOFF#/GPXIOA08 LAN_GPO BKOFF# 29
19 GPIO GPO 106
10 AC_PRESENT GPU_OVERT AC_PRESENT/GPIO0D GPXIOA09 3V_EN_R LAN_GPO 33
25 107
20 GPU_OVERT FAN_SPEED1 PW M2/GPIO11 PCH_PW R_EN/GPXIOA10 DCHG_I
28 108
41 FAN_SPEED1 VR_ON FAN_SPEED1/GPIO14 PW R_VCCST_PG/GPXIOA11 DCHG_I 45
29 R4960
42,50 VR_ON E51TXD_P80DATA 30 FANFB1/GPIO15 0_0402_5%
35 E51TXD_P80DATA E51RXD_P80CLK EC_TX/GPIO16 AC_IN VCOUT1_PROCHOT
31 110 1 2
35 E51RXD_P80CLK PCH_PWROK EC_RX/GPIO17 VCIN1_AC_IN/GPXIOD01 EC_ON AC_IN 45
32 112
10,42 PCH_PWROK PWR_SUSP_LED# 34 PCH_PW ROK/GPIO18 EC_ON/GPXIOD02 114 EC_ON 46 DGPU_AC_DETECT SW_PROCHOT#
ON/OFFBTN#
39 PWR_SUSP_LED# VR_PWRGD SUSP_LED#/GPIO19 ON/OFF#/GPXIOD03 LID_SW# ON/OFFBTN# 6,39
36 GPI 115
50 VR_PWRGD NUM_LED#/GPIO1A LID_SW #/GPXIOD04 116 LID_SW# 39
SUSP#
SUSP#/GPXIOD05 SUSP# 13,42,45,47,49

3
117 SW_PROCHOT#
GPXIOD06 118 H_PECI_R 1 2
PBTN_OUT# PECI/GPXIOD07 H_PECI 6
122 R4944 43_0402_1%
6,10 PBTN_OUT# PM_SLP_S4# 123 PBTN_OUT#/GPIO5D 124 VCOUT1_PROCHOT 2 5 VCOUT1_PROCHOT
6,10,42 PM_SLP_S4# PM_SLP_S4#/GPIO5E V18R/VCC_IO2 +3VLP_EC Q2010A Q2010B
AGND

DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
GND
GND
GND
GND
GND

4
@ @
2015/1/9 acer require:
KB9022QD_LQFP128_14X14
reserved protect circuit when
11
24
35
94
113

ECAGND 69

20mil
CO-LAY with KB9032QA (SA000080J00) adaptor 107% happen
C4909 1 2 BATT_TEMP
100P_0402_50V8J
For abnormal shutdown L4902 2 1
FBMA-L11-160808-800LMT_0603
D25
RB751V-40_SOD323-2 R4936 1 @ 2 0_0402_5% VR_HOT#
SPOK 1 2 EC_RSMRST# VR_HOT# 50
4 4

D26 H_PROCHOT# R4938 1 @ 2 0_0402_5% SW_PROCHOT#

6,45 H_PROCHOT#
RB751V-40_SOD323-2
1 2 PCH_PWROK

D27
RB751V-40_SOD323-2
Security Classification Compal Secret Data Compal Electronics, Inc.
1 2 EC_VCCST_PG_R
Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC ENE KB9022
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Friday, July 17, 2015 Sheet 38 of 60
A B C D E
 A B C D E

KB Conn. JKB1

ON/OFF BTN
R534
30
29
28
GND2
GND1
TP/B Conn. +3VALW +3V_PTP

100K_0402_5% ON/OFFBTN# 27 28 +3V_PTP

2 1 KSO0 26 27
+3VLP 26
KSO1 25 U13
25

4.7U_0603_6.3V6K
KSO2 24 +3VALW 2 @ 1 5 1
ON/OFFBTN# KSO3 23 24 0_0402_5% R462 IN OUT
6,38 ON/OFFBTN# 23 1

C2563
KSO4 22 +3VS 2 @ 1 2
KSO5 21 22 0_0402_5% R463 GND
KSO6 20 21 @ C663 +3V_PTP 4 3
SW3 KSO7 19 20 .1U_0402_16V7K EN OC 2
19 JTP1 2
Test Only EVQPLDA15_4P KSO8 18 2 1 SY6288C20AAC_SOT23-5
1 18 1

2
1 3 KSO9 17 1 C2562
KSO10 16 17 TP_CLK 2 1 1U_0402_6.3V6K
BOT 2 4 15 16 TP_DATA 3 2 R633 1
KSO11 EC PS2 TP_PWR_EN 38
KSO12 14 15 4 3 10K_0402_5%
@ KSO13 13 14 I2C_1_SDA_R 5 4
6
5

1
KSO14 12 13 I2C_1_SCL_R 6 5 EC_TP_INT#
11 12 PCH I2C EC_TP_INT# 7 6
KSO15
11 6,38 EC_TP_INT# TP_EN 7 TP_PWR_EN follow SYSON behavior
KSO16 10 38 TP_EN 8
KSO17 9 10 9 8
KSI0 8 9 10 GND
KSI1 7 8 GND
KSI2 6 7
KSI3 5 6 ACES_51524-00801-001
KSI4 4 5 CONN@ +3V_PTP
KSI5 3 4
KSI[0..7] KSI6 2 3 SP01001A910
KSI[0..7] 38 2
KSI7 1
1

1
KSO[0..17]
KSO[0..17] 38 +3V_PTP
ACES_85201-2805 R2507 R2509
CONN@ 4.7K_0402_5% 4.7K_0402_5%
SP01000GO00 +3V_PTP

2
1

1
R2639 R2640
2.2K_0402_5% 2.2K_0402_5%

KB BackLight Conn. Reserve

TP_CLK
TP_DATA TP_CLK 38
Q2012A
TP_DATA 38

2
DMN66D0LDW-7_SOT363-6

100P_0402_50V8J
2

C553

C551
100P_0402_50V8J
I2C_1_SCL_R
1 1
+5VS JBL1 6 1
11 I2C_1_SCL
U10 1 @EMC@
5 1 +5VS_BL 2 1 1 @ 2 @EMC@
IN OUT 3 2 R2641 0_0402_5% 2 2
2 4 3
2 GND 4 2

38 KBL_EN 1 @ 2 4 3 5
R592 EN OC 6 GND R2642 1 @ 2 0_0402_5%
0_0402_5% SY6288C20AAC_SOT23-5 GND
KB@ ACES_51524-0040N-001 3 4 I2C_1_SDA_R
11 I2C_1_SDA
CONN@
Q2012B
1 SP010022M00 DMN66D0LDW-7_SOT363-6

5
C524 +3V_PTP
.1U_0402_16V7K
2
@

TPM Board for 2015 Lid Switch 2 (reserve for 15")

+3VALW +3VLP
JLID1
Lid Switch
1
+3VALW R2600 +3VALW_TPM +3VS R2601 +3VS_TPM LID_SW# 2 1
2
(Hall Effect Switch)
0_0603_5% 0_0603_5% 3
1 @ 2 1 @ 2 4 3 +3VLP
5 4
BATT_AMB_LED# 5
10U_0603_6.3V6M

.1U_0402_16V7K
C2601

10U_0603_6.3V6M

.1U_0402_16V7K
C2603

.1U_0402_16V7K
C2604

.1U_0402_16V7K
C2605

1 1 1 1 1 1 6
BATT_BLUE_LED# 6
C2600

C2602

7
PWR_SUSP_LED# 8 7 U3
PWR_LED# 9 8 3 LID_SW#
2 TPM@ 2 TPM@
near pin5 2 TPM@ 2 2
TPM@ 2
TPM@ TPM@ 10 9 2 OUT LID_SW# 38
10 VDD 1
GND
1
3 11 APX8132AI_TSOT-23-3 1 3
12 GND1 C7 C8 @EMC@
GND2 .1U_0402_16V7K
near pin10, 19, 24 2 10P_0402_50V8J
ACES_50506-01041-P01 2
CONN@
SP01001FR00 SA00008K800, S IC APX8132AI-TRG SOT-23 3P HALL SENSOR
BADD SELECTION ACES_50506-01041-P01_10P-NPM

0 EEh - EFh

* 1 7Eh - 7Fh
U2600
5 +3VALW_TPM 100 1% :SD034100080 Battery LED
LED
1 VSB 10 R1 LED1
2 GPIO0/XOR_OUT VDD 19
+3VS_TPM Dual Amber+Blue 150 1% :SD034150080 1.1K_0402_1% R2634
GPIO3/BADD with Internal PH (default) 6 GPIO1 VDD 24 301 1% :SD034301080 BATT_AMB_LED# 2 1 3
O
1 @ 2 0_0402_5%
GPIO2/GPX VDD 38 BATT_AMB_LED# +5VALW
0_0402_5% 1 @ 2 R2602 TPM_BADD 9 LTST-S115TBKF-CA (SC50000C500) 680 1% :SD034680080
PM_CLKRUN# 15 GPIO3/BADD 8 R2633
8 PM_CLKRUN# GPIO4/CLKRUN# TEST ------------------------------------ BATT_BLUE_LED#
120 5% :SD028120080 2 1 2 1 1 @ 2 0_0402_5%
CLKRUN PH 10K to +3VS at PCH side LPC_AD0_R 26
Vf @ 5 mA : 38 BATT_BLUE_LED# B +3VLP
8,38 LPC_AD0_R LPC_AD1_R 23 LAD0/MISO 560 5% :SD028560080 R2
8,38 LPC_AD1_R LAD1/MOSI
8,38 LPC_AD2_R
LPC_AD2_R 20 3 ----------------------------------- 200 5% :SD028200080 1.6K_0402_1% LTST-S115KFTBKT-CA_AMBER-BLUE
LPC_AD3_R 17 LAD2/SPI_IRQ# NC 12 R453
8,38 LPC_AD3_R LAD3 NC 13
UD5: 1.7 ~ 2.3V 0_0402_5%
LPCPD# had internal PH NC 14 (3.3-1.7)/300=5.71 mA 1 @ 2 PWR_LED#
28 NC (3.3-2.3)/300=3.57 mA
LPCPD# Power LED

1
CK_LPC_TPM D
8 CK_LPC_TPM
21
LCLK/SCLK
R min: 100 ohm Q17
LPC_FRAME# 22 2 L2N7002LT1G_SOT23-3
8,38 LPC_FRAME# PLT_RST# LRFAME#/SCS# R max 700 ohm 38 PWR_LED
16 4 G R3 LED2
10,20,38 PLT_RST# LRSET#/SPI_RST# GND
1
TPM_SERIRQ 27 11 S 560_0402_1%

3
8,38 TPM_SERIRQ 7 SERIRQ GND 18 R535 PWR_SUSP_LED# 2 1 3
O
SERIRQ PH 10K to +3VS at PCH side PP GND ----------------------------------------- 38 PWR_SUSP_LED#
25 100K_0402_5%
4
GND CB5: 2.65~3.05V R6
4

(3.3-2.65)/50=13.00 mA avoid flash issue when PWR_LED# 2 1 2 1 +3VALW

2

NPCT650AA0WX_TSSOP28 (3.3-3.05)/100=5.0 mA abnormall shutdown 430_0402_1%

B

SA00007IO00 R min: 50 ohm

R max:475 ohm LTST-S115KFTBKT-CA_AMBER-BLUE
TPM@

Security Classification Compal Secret Data Compal Electronics, Inc.

CK_LPC_TPM R2603 1 2 33_0402_5% C2606 1 2 22P_0402_50V8J
Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

@EMC@ @EMC@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB & TP & TPM Connector & LED
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Monday, June 22, 2015 Sheet 39 of 60
A B C D E
 A B C D E

HD Audio Codec +PVDD_HDA

SM01000EJ00 3000ma 220ohm@100mhz DCR 0.04 +5VS +VDDA

40mil J1 Int. Speaker Conn.
L2003 2 1 40mil 1 2 40mil 40mil JSPK1
+VDDA SPK_R+
HCB2012KF-221T30_0805 1 1 1 SPKR+ EMC@1 R2120 2 PBY160808T-121Y-N_2P 1
1

1
SPK_R-

10U_0603_6.3V6M
C2112

.1U_0402_16V7K
C2113

.1U_0402_16V7K
C2114

.1U_0402_16V7K
C2111
JUMP_43X118 4.75V SPKR- EMC@1 R2121 2 PBY160808T-121Y-N_2P
SPK_L+
2
2
@ SPKL+ EMC@1 R2122 2 PBY160808T-121Y-N_2P 3 5
SPKL- EMC@1 R2123 2 PBY160808T-121Y-N_2P SPK_L- 4 3 G1 6
(output = 300 mA)

2
2 2 @ +AVDD1_HDA 2 4 G2

3
@EMC@ PVT modify 01/16 ACES_88266-04001
EMI request for solve EMI noise CONN@ GND
GND
GND GND SP02000K200
Place near Pin46 D2003 D2004
Place near Pin41 Reserved for ESD MESC5V02BD03_SOT23-3 MESC5V02BD03_SOT23-3
1 @EMC@ @EMC@ 1
20mil
C2133 1 2 10U_0603_6.3V6M R2119 1 @ 2
GND +VDDA

1
10U_0603_6.3V6M
C2117
1 1

1
.1U_0402_16V7K
C2115

.1U_0402_16V7K
C2116
Pin9 need to matching with SOC HDA C2120 1 2 .1U_0402_16V7K 0_0603_5%
interface. GND GND
R471 2 @ 1 0_0402_5% +3VS_DVDDIO
+3VS Place near Pin9

2
2 @ 2 @
+3VS_DVDD
R481 1 @ 2 33_0402_5% DMIC_CLK
9 PCH_DMIC_CLK DMIC_DATA
GNDA R482 1 @ 2 33_0402_5%
R470 2 @ 1 0_0402_5%
20mil 9 PCH_DMIC_DATA
+3VS Place near Pin26
1 1 +1.8VS_VDDA DMIC_CLK_1

.1U_0402_16V7K
C2119
C2118 R472 2 @ 1
+1.8VS R483 1 2 0_0402_5%
DMIC_DATA_1 R484 1 2 0_0402_5%
1

1
.1U_0402_16V7K
C2121

C2122
10U_0603_6.3V6M
10U_0603_6.3V6M 0_0402_5%
2 2

2
2 @
GND GNDA
Place near Pin1

41

46

26

40
1

9
U2012 Place near Pin40

PVDD1

PVDD2

AVDD1

AVDD2
DVDD

DVDD-IO
10P_0402_50V8J 2 1 C2689 DMIC_CLK_1

@EMC@
Reserved for RF LINE1-L 22
LINE1-R 21 LINE1-L(PORT-C-L)
LINE1-R(PORT-C-R) SPK-OUT-L-
43 SPKL- Digital MIC Dual-MIC
42 SPKL+
U2012 24 SPK-OUT-L+ MIC BOM upload by Audio Team
23 LINE2-L(PORT-E-L) 45 SPKR+ +3VS
LINE2-R(PORT-E-R) SPK-OUT-R+ 44 SPKR-
RING2 17 SPK-OUT-R-
2 40mil SLEEVE 18 MIC2-L(PORT-F-L) /RING2 MIC2 @
2
Combo MIC MIC2-R(PORT-F-R) /SLEEVE 32 HP_LEFT +3VS 6 5 DMIC_DATA
ALC283-CG_MQFN48_6X6 +MICBIAS 31 HPOUT-L(PORT-I-L) 33 HP_RIGHT MIC1 @ VDD DATA
+MICBIAS LINE1-VREFO-L HPOUT-R(PORT-I-R) DMIC_DATA_S DMIC_CLK
283@ 30 6 5 2 4
SA000060500 LINE1-VREFO-R 10 HDA_SYNC_R VDD DATA R460 CS CLK
DMIC_DATA_1 SYNC HDA_BIT_CLK_R HDA_SYNC_R 9 DMIC_CLK
2 6 2 4 2 2DMIC@1 1 3
DMIC_CLK_1 3 GPIO0/DMIC-DATA BCLK HDA_BIT_CLK_R 9 CS CLK ENHANCE GND
R2129
GPIO1/DMIC-CLK

3
1 @EMC@2 1 2 C2123 @EMC@ GND 1 3 0_0402_5% S MIC ST MP45DT02TR
ENHANCE GND

2
R2126 0_0402_5% 22P_0402_50V8J

2
EC_MUTE# 47 5 HDA_SDOUT_R S MIC ST MP45DT02TR
PDB SDATA-OUT HDA_SDOUT_R 9 2
EMC@ HDA_RST#_R 11 8 HDA_SDIN0_AUDIO 1 R2127 2 R464

.1U_0402_16V7K
RESETB SDATA-IN HDA_SDIN0 9
C2143 1 2 100P_0402_50V8J 33_0402_5% @ 0_0402_5%
200K_0402_1% 48 D58 R456 1DMIC@

1
255@ MONO_IN 12 SPDIF-OUT/GPIO2 MESC5V02BD03_SOT23-3 0_0402_5% 1 D2009

C2141
10mil

1
SD034200380 PCBEEP 16 @EMC@ 1DMIC@ MESC5V02BD03_SOT23-3
HP_PLUG# R2129
Close codec SENSE_A MONO-OUT
2 283@ 1 39.2K_0402_1% 13 @EMC@
37 HP_PLUG# +MIC2_VREFO

1
R2684 2 255@ 1 100K_0402_1% 14 SENSE A
+3VS SENSE B
1 29 10U_0603_6.3V6M2 1 C2124 GND

1
37 MIC2-VREFO
C2125 35 CBP 7 10U_0603_6.3V6M2 1 C2126
CBN LDO3-CAP GNDA
2.2U_0402_6.3V6M 39
2 LDO2-CAP 27 10U_0603_6.3V6M2 1 C2127 R526 Realtek add request
LDO1-CAP GNDA
36
+3VS_DVDD CPVDD 1 R2137 2 10mil
Pin20
ALC283 : NC VREF
28 CODEC_VREF 100K_0402_5% Headphone Out
R2131 1 @ 2 0_0402_5% 20 1 1 1
ALC255/256 : Power for combo jack depop +3VALW CPVREF

.1U_0402_16V7K
C2129

2.2U_0402_6.3V6M
C2130
circuit at system shutdown mode 15 20K_0402_1% 1 283@ 2 R2132 GNDA @
JDREF

10U_0603_6.3V6M
C2131
10U_0603_6.3V6M 2 1 C2128 19 34 CPVEE
GNDA MIC-CAP CPVEE
Close codec 2 2 2
Pin4 1 @
ALC283 : DVSS R2683 2 283@ 1 0_0402_5% 4
ALC255/256 : DC DET (For Japen customer only) DVSS
49 25 C2132
Thermal PAD AVSS1 38 2.2U_0402_6.3V6M
AVSS2 2

3 ALC255-CG_MQFN48_6X6 Place next pin27 3

SA000082700 GND
255@ +MIC2_VREFO
GND Pin15
GNDA ALC283 : Ref. Resistor for Jack Detect GNDA
ALC255/256 : Jack Detect for SPDIF-OUT and SPK-OUT port

1
R2133 R2134
R2138 C2144 2.2K_0402_5% 2.2K_0402_5%
22K_0402_5% 1U_0402_6.3V6K
2 1 BEEP#_R 1 2 MONO_IN
38 BEEP#

2
SLEEVE
SLEEVE 37
2

R2140 1 RING2 RING2 37

22K_0402_5% @EMC@
100P_0402_50V8J
C2134

4.7K_0402_5%
R2141

2 1
9 SPKR
2
1

+3VS +3VS +3VLP

HP_LEFT R2135 1 @ 2 0_0603_5% HPOUT_L_1

GND HPOUT_L_1 37
2

@ RING2
2

R2142 @ R2144 HP_RIGHT R2151 1 @ 2 0_0603_5% HPOUT_R_1

HPOUT_R_1 37
100K_0402_5% R2143 283@
100K_0402_5% 100K_0402_5%
LINE1-L 1 2
1

C2135 4.7U_0603_6.3V6K
1

5 1 2
D
G LINE1-R
J11 J12 S Q2003A C2136 4.7U_0603_6.3V6K
JUMP_43X39 JUMP_43X39 283@ +MICBIAS D2006
DMN66D0LDW-7_SOT363-6

1 2 1 2 10K_0402_5% 2 2 R2145 1
@ 1 2 @ 1 2 DMN66D0LDW-7_SOT363-6 4.7K_0402_5%
6

4 R2147 2 @ 1 Q2003B 1 4
38 EC_MUTE# 2
D
J9 J10 G

JUMP_43X39 JUMP_43X39 R2148 2 283@ 1 S 3 2 R2146 1

1 2 1 2 9 HDA_RST#_R
283@ GNDA 4.7K_0402_5%
1

@ 1 2 @ 1 2 10K_0402_5% BAT54A-7-F_SOT23-3
1 2
J2 J3
JUMP_43X39 JUMP_43X39 @ C2139 GND
1 2 1 2 1U_0402_6.3V6K
@ 1 2 @ 1 2
GND
J4 J5 Security Classification Compal Secret Data Compal Electronics, Inc.
JUMP_43X39 JUMP_43X39 Issued Date 2014/11/10 2016/11/10 Title
1 2 1 2 To solve the background noise while combo jack Deciphered Date
@ 1 2 @ 1 2
connecting to an active THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec ALC283/ALC255 Colay
speaker and system entry into S3/S4/S5 without analog AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
GND GNDA GND GNDA power Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 40 of 60
A B C D E
 A B C D E

FAN1 Conn Screw Hole

+5VS C632
4.7U_0603_10V6K
1 2 H17
1 1
H3 H4 H5 H6 H9 H10 H11 H21 H_3P3 FD1 FD2
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P3
U31
1 8 @ @
EN GND

1
2 7
VIN GND

1
+VCC_FAN1 3 6 FIDUCIAL_C40M80 FIDUCIAL_C40M80
2 @ 1 4 VOUT GND 5
38 EN_DFAN1 VSET GND FD3 FD4
R515 NCT3942S SOP 8P @ @ @ @ @ @ @ @ @
1
0_0402_5%
C626 H13 H14 H15 H16 H20 H22 H24 @ @

1
.1U_0402_16V7K H_4P0 H_4P0 H_4P0 H_4P0 H_4P0 H_3P0 H_3P0
2 FIDUCIAL_C40M80 FIDUCIAL_C40M80
@

1
C627
4.7U_0603_10V6K
+3VS 1 2 @ @ @ @ @ @ @

@ C631
1

1000P_0402_50V7K
R516 1 2
10K_0402_5%
40mil
JFAN1
2

+VCC_FAN1 1
2 1 4
38 FAN_SPEED1 2 GND
3 5
3 GND H12 H18
1
C630 H_3P7X3P2N H_6P0N
2 1000P_0402_50V7K ACES_88231-03041 H23 H25 H_3P7X3P2N H_6P0N 2
@EMC@ CONN@ H_3P5X3P0N H_3P0N
2
SP020020710
@ @ @ @

1
G-Sensor reserved for BA serial +3VS
Reset Circuit
+3VLP

R2632 1 @ 2 0_0402_5%
MAINPWON 38,44,46

2
R349 R2631 1 @ 2 0_0402_5%
EC_RST# 38
1

10K_0402_5%
R521 +3VS
10K_0402_5%

6
BA@ U2 BA@
1 C633 1 2 10U_0603_6.3V6M BI_GATE# 2 G
D
2

8 Vdd_IO BA@ Q2005B

4 CS 14 C628 1 2 0.1U_0402_16V4Z
BI_GATE PH to +RTCVCC at PWR side S

DMN66D0LDW-7_SOT363-6
8,18,19 SOC_SMBCLK SCLSPC Vdd

1
3
6 1
8,18,19 SOC_SMBDATA 7 SDA/SDI/SDO BI_GATE 5 G
D

R519 1 @ 2 10K_0402_5% SDO/SA0 11 G_INT# 44 BI_GATE S C347

+3VS INT1 G_INT2 G_INT# 11
R520 1 BA@ 2 10K_0402_5% 16 9 Q2005A .1U_0402_16V7K
ADC1 INT2 G_INT2 36

4
15 DMN66D0LDW-7_SOT363-6 2
13 ADC2 10 INT1/2 all High Active
ADC3 RES No need external PU
2
3
3 NC 5 3
NC GND 12
GND
LIS3DHTR_LGA16_3X3
BA@

LIS3DH
SA0 ->0, Address is 0011 000 (0x30h)
SA0 ->1, Address is 0011 001 (0x32h)
Debug SW

Reset But t on BI SW BI SW
Reset But t on SW4 SW5
1 BI_GATE 1 BI_GATE
1 1
SW2
2 2
1 2 BI_GATE 2 2
3 3
3 3
SKPMAME010_2P 4 4
GND GND
GND
5 1-2 : Battery Off GND
5
6 6
GND 7
2-3 : Battery ON GND 7
GND GND
4 MSS312-Q-T-R(913)_3P MSS312-Q-T-R(913)_3P 4
MDN@ MDY@
Place BOT Side
Place TOP Side
Reserved for memory door only

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FAN & Screw Hole & G-Sensor
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Thursday, July 16, 2015 Sheet 41 of 60
A B C D E
 A B C D E

DC & VGA Interface For Power ON/Off Sequence

Q2014B
+3VALW DMN66D0LDW-7_SOT363-6
4 3
EC_VCCST_PG_R 10,38

1
U11 @ J36 MOW14, For tCPU28 200us(max)
1 14 +3VS_OUT 1 2 R1000 SLP_S3# to VCCST_PWRGD deassertion
+3VALW +3VS

5
R927 2 VIN1 VOUT1 13 1 2 100K_0402_5% PM_SLP_S3
0_0402_5% VIN1 VOUT1 JUMP_43X118

5
SUSP# 1 @ 2 3VS_ON 3 12 1 2

2
ON1 CT1 C976 1000P_0402_50V7K
C980 1 2 +5VALW 4 11 4 3
VBIAS GND VR_ON 38,50

6
@ .1U_0402_16V7K Q2014A
1 5VS_ON 1
R926 2 @ 1 0_0402_5% 5 10 1 2 DMN66D0LDW-7_SOT363-6 Q2013B MOW14, For tPLT17 200us(max)
ON2 CT2 C967 1000P_0402_50V7K DMN66D0LDW-7_SOT363-6 SLP_S3# to IMVP VR_ON deassertion
+5VALW 6 9 @ J37 2
VIN2 VOUT2 +5VS_OUT 1 6,10,38 PM_SLP_S3#
C979 1 2 7 8 2 +5VS
VIN2 VOUT2 1 2

2
@ .1U_0402_16V7K

1
15 JUMP_43X118
GPAD 1 6 SUSP#
EM5209VF_DFN14_2X3
Q2013A MOW14, For tPLT18 200us(max)
DMN66D0LDW-7_SOT363-6 SLP_S3# to VCCIO VR disable
Q2018A
DMN66D0LDW-7_SOT363-6
1 6
+1.35V_VDDQ +5VALW SYS_PWROK 10,38
@
+5VALW +0.675VS_VTT

2
2
2

2
R573 R554

5
R552 R566 470_0603_5% 100K_0402_5%
100K_0402_5% @ @ 470_0603_5% @ @
4 3
PCH_PWROK 10,38

1
+3VALW
+0.675VS_VTT_R
1

1
+1.35V_VDDQ_R SYSON# Q2018B @
SUSP DMN66D0LDW-7_SOT363-6

1
6

R1002
100K_0402_5%
SYSON# 2 5 SYSON
SYSON 13,38,47
2 5 SUSP Q40A Q40B
13,38,45,47,49 SUSP#

2
Q2006B DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6 PM_SLP_S4

4
1

Q2006A @ @ @
1

5
R555 @ DMN66D0LDW-7_SOT363-6 Q2016A
2 10K_0402_5% DMN66D0LDW-7_SOT363-6 2
@ 4 3 SYSON
DMN66D0LDW-7_SOT363-6 2
6,10,38 PM_SLP_S4#
2

Q2016B
MOW14, For tPLT15 200us(max)

1
DMN66D0LDW-7_SOT363-6 SLP_S4# to VDDQ ramp down

+5VALW +1.05VSDGPU

2
R1001 R574
+3VS to +3VSDGPU_AON for GPU 100K_0402_5% 47_0603_5%
VGA@ VGA@

1
+3VSDGPU_AON
DGPU_PWROK# +1.05VSDGPU_R
+3VS

6
U12 100mil(1.5A)
5 1
IN OUT
2 DGPU_PWROK 5 2 DGPU_PWROK#
GND 2 10,20,54,55 DGPU_PWROK
Q2008A
3 DGPU_PWR_EN 4 3 C621 Q2008B DMN66D0LDW-7_SOT363-6 3

1
EN OC VGA@ DMN66D0LDW-7_SOT363-6 VGA@
2 1 4.7U_0603_6.3V6K
C620 SY6288C20AAC_SOT23-5 VGA@
4.7U_0603_6.3V6K VGA@
VGA@
1

+5VALW +VGA_CORE

+5VALW +1.5VSDGPU
2

2
R994 R572

2
100K_0402_5% 47_0603_5%
+3VS to +3VSDGPU_MAIN for GC6-2.0 @ @ R998 R571
100K_0402_5% 47_0603_5%
1

1
+3VSDGPU_MAIN DGPU_PWR_EN# +VGA_CORE_R @ @
+3VSDGPU_AON

1
R213
3

0_0805_5% 1.5VS_DGPU_PWR_EN# +1.5VSDGPU_R

1 NGC6@ 2

6
+3VS 5 2 DGPU_PWR_EN#
11 DGPU_PWR_EN
U14 Q2007A
5 1 Q2007B DMN66D0LDW-7_SOT363-6 1.5VS_DGPU_PWR_EN 5 2 1.5VS_DGPU_PWR_EN#
20,53 1.5VS_DGPU_PWR_EN
4

IN OUT
2

100mil(1.5A) DMN66D0LDW-7_SOT363-6 @ Q45A

2
2 2 2 @ Q45B DMN66D0LDW-7_SOT363-6

1
C624 GND R996 R999 DMN66D0LDW-7_SOT363-6 @
4 4
GC6@ 4 3 C625 100K_0402_5% 100K_0402_5% @
1U_0402_6.3V6K EN OC GC6@ @ @
1

1 SY6288C20AAC_SOT23-5 1 4.7U_0603_6.3V6K

1
GC6@

20,55 3VSDGPU_MAIN_EN

3VSDGPU_MAIN_EN From GPU

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 42 of 60
A B C D E
 A B C D E

+19V_ADPIN HCB2012KF-121T50_0805
EMI@ PL101 +19V_VIN
change PL101
1 2 SM01000C000 to comm
part SM01000P200
@ PJP101
ACES_50305-00441-001_4P

1
1

1
EMI@ EMI@ PC104
2 PC102 1000P_0603_50V7K

2
1 3 100P_0603_50V8 1

2
4
GND
GND

2011/10/13
for EN9012 application, delete the 51_ON# circuit
2 2

2011/10/12
delete the pre-CHG circuit

@ PR101
0_0402_5%
1 2
+3VLP +CHGRTC
3 3

- PBJ101 @ + PR102
560_0603_5%
PR103
560_0603_5%
2 1 1 2 1 2
+RTCBATT

ML1220T13RE

4 4

Security Classification
2014/11/10
Compal Secret Data
2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
PWR DCIN / Pre-charge
Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 43 of 60
A B C D E
 A B C D E

2013/07/23
change PC5 and PC6 function field from 37.1 to 47.1

+3VLP

1 1

1
@ PC205

1
PR207 100_0402_1% 0.1U_0603_25V7K
MB:Battery Con Put TOP Side

2
1 2
EC_SMB_DA1 38,45
PR205 100_0402_1% @ PR215 @ PR214
1 2 10K_0402_1%
EC_SMB_CK1 38,45 <45,47> 10K_0402_1%

2
1
@ PU201
Battery Bot Side PR202 @ PR213 1 8
100K_0402_1% VCC TMSNS1
200K_0402_1% (Common Part)
1 2 2 7 2 1
PIN1 GND @ PJP201 +3VLP GND RHYST1 SL200002H00

1
PIN2 GND 1 2
1
1 2 38,41,46 MAINPWON
MAINPWON 3
OT1 TMSNS2
6 @ PR216
47K_0402_1%
PIN3 SMD 2 3 EC_SMB_DA1-1 BATT_TEMP 38,45 4 5 @ PH202
3 4 EC_SMB_CK1-1 PR203 1K_0402_1% OT2 RHYST2 100K_0402_1%_NCP15WF104F03RC
PIN4 SMC 4 5 BATT_TS G718TM1U_SOT23-8

2
5 6
PIN5 TEMP 6 7
BATT_B/I

PIN6 BI 7 8
8 9 +RTCVCC
PIN7 Batt+ GND 10
PIN8 Batt+ GND
CVILU_CI9908M2HR0-NH

1
PR212
100K_0402_5% PQ201 Change to SB00000QO00,
SB501380010(BSS138LT1G Del)

2
D

1
2 2
2 PQ201
41 BI_GATE G BSS138LT1G_SOT23-3
S

3
+17.4V_BATT+ 2014/09/25 update
EMI@ PL201
For KB9022
change PL201, PL202
HCB2012KF-121T50_0805
1 2
+17.4V_BATT sense 20mΩ Active Recovery
SM01000C000 to comm EMI@ PL202
part SM01000P200 HCB2012KF-121T50_0805
1 2 45W PR206 58.5W,0.61V 45W,0.47V
10K ohm
SD034100280
PC201
65W PR206 84.5W,0.61V 65W,0.47V
1

EMI@ PC202 EMI@

1000P_0402_50V7K 0.01U_0402_25V7K
19.1K ohm PH1 under CPU botten side :
2

SD034191280 CPU thermal protection at 89 +-3 degree C

Recovery at 56 +-3 degree C
+3VLP_ECA
2013/06/07
Add for ENE9022 Battery Voltage drop detection.
Connect to ENE9022 pin64 AD1. 2013/07/23
change PC5 and PC6 function field from 37.1 to 39.7

1
3 3
65W@ PR206 PR204
19.1K_0402_1% 45W@ PR206 18.7K_0402_1%
10K_0402_1%
+19VB_5V 1 2
VAL50/ZAL20 Battery is 3-cell NVDC design.

2
ADP_I 38,45
VCIN0_PH 38
B+=9V
Change PR12=50k if Battery is 2-cell NVDC design (Common Part)
B+=6V SL200002H00
1

VCIN1_ADP_PROCHOT 38 PC203 must close to EC pin

1
@ PR209

2
PH201 @ PC203

1
80.6K_0402_1%
@ PR210 PR208 100K_0402_1%_NCP15WF104F03RC 0.1U_0402_25V6
2

1
0_0402_5%
T202 T201 must close to PH201

2
1 2 10K_0402_1%
VCIN1_BATT_DROP 38 2 T202@
1

T201@
2

@ PC204 @ PR211
ECAGND 38
0.1U_0402_25V6 10K_0402_1%
1

4 4

Security Classification
2014/11/10
Compal Secret Data
2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
PWR-BATTERY CONN/OTP
Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Monday, June 22, 2015 Sheet 44 of 60
A B C D E
 A B C D E

PR302
D

1
1M_0402_1%
2 1 2
PQ301 +19VB
G 2N7002KW _SOT323-3 2014/9/25 +17.4V_BATT_CHG
PQ302
PR303 S PR304 10m ohm chang -->20m ohm

3
2 1 AON7506_DFN33-8-5
+19V_P1 +19V_P2 SD00000S120 1
PQ303 3M_0402_5% PQ304 2
AON7506_DFN33-8-5
MDU1512RH_POW ERDFN56-8-5
1 1
PR304
0.02_1206_1% EMI@ PL302
+19V_CHG 5 3

2 2 1UH_2.8A_30%_4X4X2_F
5 3 3 5 1 4 1 2
+19V_VIN

4
2 3 PC302
1 2

0.047U_0603_25V7M
4

4
1 1

1000P_0603_50V7

2200P_0402_50V7K
0.022U_0603_25V7K

10U_0805_25V6K

10U_0805_25V6K
1

1
PC301

PC303
ACP ACN

4.7_0603_1%

68P_0402_50V8J

4.02K_0402_1%
1

10_0402_1%
PR301

@EMI@ PC306

EMI@ PC307

PC308

PC309

PR306

PR307
2

2
PC311
PC310

1
0.1U_0402_25V6 PC312

10U_0805_25V6K
1

10U_0805_25V6K
2 1 1 2 1 2

2
2

1
@ PC304

@PC305
0.01U_0402_25V7K~N
0.1U_0603_25V7K
2014/9/30

2
BATDRV_CHGR
PC301 change to SE025102K80 PR308
4.02K_0402_1%
1 2 ACDRV_CHGR

1
@ PR309 @ PR310 BATSRC_CHGR
0_0402_5% 0_0402_5%
2 1CMSRC_CHGR
PR305

2
4.02K_0402_1%

ACN_CHGR
ACP_CHGR
+19V_VIN
PD301 PR312 @ PC313
S SCH DIO BAS40CW SOT-323 10_1206_5% 1000P_0402_50V7K
3 1 2
+19V_VIN
1

1 2 1
PR311 2 ACDRV_CHGR
+19VB
422K_0402_1% PC314 1U_0603_25V6K +6V_CHG_REGN
2 1 PC316 PQ305
MDV1528URH_PDFN33-8-5
2

5
2 ACDET PU301 2.2U_0805_25V6K 2
1 2

ACDRV

ACP

ACN
28
VCC PR314
66.5K_0402_1%
1

CMSRC_CHGR 3 24 0_0603_5%
CMSRC REGN
1

1 2DH_CHGR_R 4
PR313

@ PR316 PC317
PC315 6 0_0603_5% 0.047U_0603_25V7M
2200P_0402_25V7K ACDET 25 BST_CHGR 1 2BST_CHGR_R 1 2
2

1 2 EC_SMB_DA1_CHGR 11 BTST
38,44 EC_SMB_DA1 @ PR317 0_0402_5% (Common Part) +17.4V_BATT
2

SDA
Choke 2.2uH SH00000YV00

3
2
1
1 2 EC_SMB_CK1_CHGR 12 26 UG_CHGR PR318
38,44 EC_SMB_CK1 SCL HIDRV
@ PR315 0_0402_5% PL301 0.01_1206_1%
ACPRN_CHGR 5 2.2UH_PCMB063T-2R2MS_8A_20%
38,44 ADP_I PC318 PR333 0_0402_5% ACOK 27 LX_CHGR 1 2 1 4
1 2 1 2 7 PHASE
IADP 2 3

1
100P_0603_50V8 8 23 LG_CHGR

4.7_1206_5%
IDCHG LODRV

MDV1527URH_POWERDFN33-8-5
5
38 DCHG_I

@EMI@ PR319
@ PC319 PR320 @ 316K_0402_1%
1 2 9 1 2

10U_0805_25V6K

10U_0805_25V6K
PMON +5VALW
@

PR331
100P_0603_50V8 0_0402_5% 10 22 PR332 316K_0402_1% SRP SRN

1SNUB_CHGR 2
/PROCHOT GND

1
1 2 1 2

PC320

PC321
50 PSYS_MON +3VLP 4
@

PR321 PR322 100K_0402_1%

2
0_0402_5% 13 21 ILIM_CHGR 1 2
1 2 CMPIN ILIM PR323

680P_0603_50V7K
6,38 H_PROCHOT# 14 10_0402_1%

3
2
1
CMPOUT 20 SRP_CHGR 1 2

@EMI@ PC323
SRP

PQ306
15 19 SRN_CHGR 1 2
38,44 BATT_TEMP

2
/BATPRES SRN
3
For 4S per cell 4.35V battery PR324 3
16 18 BATDRV_CHGR 10_0402_1% PC324
/TB_STAT BATDRV 0.1U_0402_25V6
ACDET 29 17 BATSRC_CHGR 1 2
PWPD BATSRC

BQ24780RUYR_W QFN28_4X4
1

PR328

0.1U_0402_25V6

0.1U_0402_25V6
2M_0402_1%

1
PC325

PC326
2

2
1

@ PR329
20140930 0_0402_5%

PDTC115EU_SOT323-3_SB301150200-->X1 +6V_CHG_REGN
1 2

LTC015EUBFS8TL_UMT3F_SB00000RM00-->AP
PQ307
PR330 LTC015EUBFS8TL_UMT3F
1

100K_0402_1%
1 2 2 PR325
38 BATT_4S
10K_0402_1%
PR326
10K_0402_1%
2

1 2 ACPRN_CHGR
38 AC_IN
3
1

PQ308 D
1

2
13,38,42,47,49 SUSP# G
4 PR327 4

S 2N7002KW _SOT323-3 12K_0402_1%

3

Security Classification
2014/11/10
Compal Secret Data
2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
BQ24780
Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 45 of 60
A B C D E
 A B C D E

Module model information PR402

499K_0402_1%
ENLDO_3V5V 1 2
TPS51225C_V1.mdd +19VB

1
150K_0402_1%
PR404
EN1 and EN2 dont't floating

2
PU401
1 +19VB EMI@ PL401 SY8286BRAC_QFN20_3X3 @ PR401 1
HCB2012KF-121T50_0805 0_0603_5% PC401
+19VB_3V BST_3V

2200P_0402_50V7K
1 2 1 2 1 2

10U_0805_25V6K
@EMI@ PC403

EMI@ PC404
0.1U_0402_25V6
0.1U_0603_25V7K

1
5*5*3 Common part SH000016800

PC405

BS
IN

IN

IN

IN
PL402

2
LX_3V6 20 LX_3V 1 2
LX LX +3VALWP
7 19 1.5UH_PCMB053T-1R5MS_6A_20%
GND LX

@EMI@

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
PR405
1

1
680P_0603_50V7K 4.7_1206_5%
8 18
+3VALWP GND GND

PC407

PC408

PC409

PC410
9 17
+3VLP

2
PG LDO

1 3V_SN
10 16

2
NC NC

1
Check pull up resistor of SPOK at HW side PC411

OUT
EN2

EN1
21

NC
4.7U_0603_6.3V6M

FF

2
PR406 GND
100K_0402_5%

11

12

13

14

15

@EMI@

PC412
3.3V LDO 150mA~300mA

2
Vout is 3.234V~3.366V Ipeak=4.65A
38,49 SPOK
ENLDO_3V5V
Imax=3.25A
PC402 PR403
1000P_0402_25V8J1K_0402_5%
TDC=6A Iocp=10A
3V_FB 1 2 1 2
38 3V_EN

2 2
+19VB +19VB_5V
EMI@ PL403 @ PR408
PC418
HCB2012KF-121T50_0805 PU402 SY8286CRAC_QFN20_3X3 0_0603_5%
1 2 +19VB_5V BST_5V1 2 1 2

1
0.1U_0603_25V7K

BS
IN

IN

IN

IN
LX_5V 6
2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

20 5*5*3 Common part SH000016800

0.1U_0402_25V6

LX LX PL404
7 19 LX_5V 1 2
GND LX +5VALWP
1

1
PC414

PC415

EMI@ PC416

@EMI@ PC417

8 18 1.5UH_PCMB053T-1R5MS_6A_20% @ @
GND GND

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
PC419 4.7U_0603_6.3V6M
2

1
9 17 1 2
PG VCC

1
PR409

PC420

PC421

PC422

PC423

PC424

PC425
4.7_1206_5%
1 SPOK_R

@EMI@
10 16

2
NC NC

OUT

LDO
EN2

EN1
21

FF
GND

2
PR413 @
11

12

13

14

15
0_0402_5%
VL

1 5V_SN
4.7U_0603_6.3V6M
5V LDO 150mA~300mA
2

680P_0603_50V7K
PC427
SPOK
ENLDO_3V5V

PC426
2

@EMI@

2
5V_EN

3 Vout is 4.998V~5.202V 3
PC413 PR407
1000P_0402_25V8J 1K_0402_5%
5V_FB 1 2 1 2 TDC=6A Ipeak=9A
Imax=6.25A
PR410
2.2K_0402_5% Iocp=10A
1 2
38 EC_ON @ PR411
0_0402_5% @ PJ401
1 2 +3VALWP 1 2 +3VALW
38,41,44 MAINPWON 1 2
JUMP_43X118

5V_EN
1M_0402_1%

4.7U_0402_6.3V6M
1

@ PJ402
1
PR412

PC428

+5VALWP 1 2 +5VALW
1 2
JUMP_43X118
2
2

4 4

Security Classification
2014/11/10
Compal Secret Data
2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
PWR-3.3VALWP/5VALWP
Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 46 of 60
A B C D E
 A B C D E

Module model information

RT8207M_V1.mdd For Single layer
RT8207M_V2.mdd For Dual layer

1 1

Pin19 need pull separate from +1.35VP.

+19VB_1.35VP If you have +1.35V and +0.675V sequence question, 0.675Volt +/- 5%
EMI@ PL501 you can change from +1.35VP to +1.35VS. TDC 0.7A
HCB2012KF-121T50_0805
1 2 +19VB_1.35VP PR502 Peak Current 1A
+19VB_CPU 2.2_0603_5%
BST_1.35VP_R 1 2 BST_1.35VP

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
1 +1.35VP

1
change PL501 @EMI@ PC502

EMI@ PC503

PC504

PC505
SM01000C000 to comm UG_1.35VP +0.675VSP
2

2
part SM01000P200
PQ503 LX_1.35VP

10U_0603_6.3V6M

10U_0603_6.3V6M
5

1
PC506

1
PC507

PC508
0.1U_0603_25V7K

16

17

18

19

20
2
PU501

2
2 2

VLDOIN
PHASE

UGATE

BOOT

VTT
4 21
PAD
Choke 1.5uH SH000016700 LG_1.35VP 15 1
Common Part 7*7*3 LGATE VTTGND

1
2
3
PL502 MDV1528URH_PDFN33-8-5 14 2
1.5UH_PCMC063T-1R5MN_9A_20% PR503 PGND VTTSNS
13.7K_0402_1%
1 2LX_1.35VP 1 2 CS_1.35VP 13 3
+1.35VP PC509 CS RT8207MZQW _W QFN20_3X3 GND
1

5 1U_0402_10V6K
PQ502 1 2 12 4 VTTREF_1.35VP
@EMI@ PR504 PR505 VDDP VTTREF
330U_2.5V_M

1
+
Update Pc510 change 4.7_1206_5% 5.1_0603_5%
VDD_1.35VP
1 2 11 5
PC510

to Common Part +5VALW +1.35VP

1 2

VDD VDDQ

1
PGOOD
4 PC516
SF000006S00 20141227

TON
1

1
2 @EMI@ PC518 PC517 0.033U_0402_16V7K

FB
S5

S3

2
680P_0402_50V7K
2

SI7716ADN-T1-GE3_POW ERPAK8-5 1U_0402_10V6K PR511

1
2
3

10

6
2.2_0402_1%

FB_1.35VP
2

TON_1.35VP
change PQ502 form 7506

EN_1.35VP

EN_0.675VSP
PR506
to 7716, 20150108 8.2K_0402_1%
+5VALW PR507 1 2 +1.35VP
453Kohm-->455KHz +19VB_1.35VP
887K_0402_1%
1 2
3 3

1
Vout=0.75V* (1+Rup/Rdown)
@ PR501 PR508 =0.75*(1+(8.06/10))
0_0402_5% 10K_0402_1%
1 2 =1.354V 0.2%

2
13,38,42 SYSON Vout=0.75V* (1+Rup/Rdown)
=0.75*(1+(8.2/10))

1
@ PC501
0.1U_0402_10V7K
=1.365V 1.1%

2
@ PR509
0_0402_5% @ PJ501
MOSFET: 3x3 DFN 13,38,42,45,49 SUSP#
1 2 JUMP_43X118
+1.35VP 1 2 +1.35V_VDDQ
H/S Rds(on): 27mohm(Typ), 34mohm(Max) 1 2
Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C @ PR510
0_0402_5%
L/S Rds(on): 9.9mohm(Typ), 13mohm(Max) 1 2
7 SM_PG_CTRL
Idsm: 13.5A@Ta=25C, 11A@Ta=70C

1
@ PC519 @ PJ502
Choke: 7x7x3 JUMP_43X39
0.1U_0402_10V7K 1 2
Rdc=8.3mohm(Typ), 10mohm(Max) +0.675VSP +0.675VS_VTT

2
1 2
Mode Level +0.675VSP VTTREF_1.35V
S5 L off off Switching Frequency: 285kHz
4
S3 L off on Ipeak=10A
4

S0 H on on Iocp~13A
OVP: 110%~120%
Note: S3 - sleep ; S5 - power off VFB=0.75V, Vout=1.3545V
MOSFET footprint: SIS412DN Compal Secret Data
Security Classification
2014/11/10 2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL RT8207P
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 47 of 60
A B C D E
 A B C D E

Module model information

SYX196D_V3.mdd

EN pin don't floating

If have pull down resistor at HW side, pls delete PR702
+19VB_1VALW
1 1
@EMI@ PR605 @EMI@ PC602
4.7_1206_5% 680P_0603_50V7K @ PJ601
EMI@ PL601 1 2 SNUB_1VALW 1 2 JUMP_43X118
HCB2012KF-121T50_0805 PU601 (Common Part) 1 2
+19VB_1VALW +1.0VALWP 1 2 +1.0VALW_PRIM
+19VB 1 2 2
IN PG
9 @ PR606
0_0603_5%
PC603 SH00000YE00

10U_0805_25V6K
0.1U_0402_25V6
3 1 BST_1VALW 1 2 BST_1VALW_R1 2 PL602

2200P_0402_50V7K
IN BS

1
1UH_11A_20%_7X7X3_M

EMI@ PC604

@EMI@ PC605

PC606
LDO_3V LX_1VALW
4
IN LX
6
0.1U_0603_25V7K
1 2
+1.0VALWP

2
5 19

14K_0402_1%

330P_0402_50V7K

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

220U_B2_4VM_R35M
IN LX
1

1
1

1
@ PR607 7 20

PR608

PC608

PC609

PC610

PC611

PC612
GND LX +
Rup

PC615
8 14 FB_1VALW
0_0402_5%

2
GND FB
2

2
ILMT_1VALW 18 17 LDO_3V 2
change PL601 GND VCC
@

SM01000C000 to comm
1

1
EN_1VALW 11 10
EN NC
@ PR609
part SM01000P200 PC613 FB = 0.6V

1
ILMT_1VALW 13 12 2.2U_0402_6.3V6M

2
ILMT NC PR610
0_0402_5%
+3VALW 15 16
Rdown
2

BYP NC 20K_0402_1%
21

2
PAD
SY8288RAC_QFN20_3X3 Pin 7 BYP is for CS.

1
The current limit is set to 6A, 8A or 12A when this pin Common NB can delete +3VALW and PC15
PC614
is pull low, floating or pull high 1U_0402_6.3V6K

2
Vout=0.6V* (1+Rup/Rdown)
=0.6*(1+(14/20))
Vout=1.02V
2 2
@ PR602
0_0402_5%
1 2
+1.8VALW_PG 49

@ PR603
10K_0402_1%
EN_1VALW 1 2
+3VALW
1

@ PC601
PR601
0.22U_0402_10V6K
2

1M_0402_1%
2

Function Field :
VCCEDPIO : IC-35.21 , others - 35.22
VCCEDRAM : IC-35.25 , others - 35.26

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
VCCP
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, July 14, 2015 Sheet 48 of 60
A B C D E
 A B C D E

1 1

Module model information

SY8032_V2.mdd

@ PJ702
JUMP_43X79
1 2
+1.8VALWP 1 2 +1.8VALW_PRIM
VIN_1.8VALW

PC702
22U_0603_6.3V6M
Imax= 2A, Ipeak= 3A
2 FB=0.6V 2
1 2 PU701
SY8032ABC_SOT23-6
@ PJ701 PL701
JUMP_43X79 1UH_2.8A_30%_4X4X2_F
1 2 VIN_1.8VALW 4 3 LX_1.8VALW 1 2
+3VALW 1 2 IN LX +1.8VALWP
5 2
48 +1.8VALW_PG PG GND
PR702

68P_0402_50V8J
1
100K_0402_1% 6 1

22U_0603_6.3V6M

22U_0603_6.3V6M
FB EN

1
1 2 @EMI@ PR703

PC703
+3VALW

1
PR704 +1.8VALWP:

PC704

PC705
4.7_0603_5% Imax=0.19A Ipeak=0.27A

2
20K_0402_1%

2
1 2 EN_1.8VALW
38,46 SPOK

2
Rup

SNUB_1.8VALW
1

@ PR705
0_0402_5% PR701 1 @ PC701 FB_1.8VALW

1M_0402_1% 0.1U_0402_16V7K
2

1
2

PR707

1
@EMI@ PC706
10K_0402_1%
Rdown
680P_0402_50V7K

2
Vout=0.6V* (1+Rup/Rdown)
Note: Vout=0.6V* (1+(20/10))=1.8V
When design Vin=5V, please stuff snubber
to prevent Vin damage
+3VALW

+3VALW
1

3 3

@ PJ703
1

JUMP_43X79
1
2

PC707
2

1U_0402_6.3V6K
2

VIN_1.5VS
VIN_1.5VS
1

PC708
Ultra Low Dropout 0.23V(typical) at 3A Output Current
4.7U_0603_6.3V6K
2

PU702
5 VIN_1.5VS +1.5VSP:
VPP

VIN
7
POK 9
Current limit = 4.7A(min) Imax=0.5A Ipeak=0.75A
TPAD
3 0.4%
VO @ PJ704
1 2 EN_1.5VS 8 4 JUMP_43X79
13,38,42,45,47 SUSP# VEN VO +1.5VSP 1 2
1K_0402_1%
GND

+1.5VSP +1.5VS
0.01U_0402_25V7K

1 2
1

@ PR708 2
ADJ
1

0_0402_5%
PR709

PC709

PR710 @ PC710 G971ADJF11U_SO8

Rup
1

0.1U_0402_16V7K
2

47K_0402_5%
2

FB_1.5VS PC711
2

22U_0603_6.3V6M
2
1

PR711

Rdown 1.13K_0402_1%
2

4 4
Vout=0.8V* (1+Rup/Rdown)
Vout=0.8V* (1+(1/1.13)) = 1.507V

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
SY8032
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, July 14, 2015 Sheet 49 of 60
A B C D E
 A B C D E

Change
PR808 to 24.9k ohm
PR822 to 24.9k ohm
PC802
0.01U_0402_25V7K PR802
PR846 to 2.43k ohm
1.5K_0402_1% PR867 to 2.43k ohm
1 2 1 2 PR842 to 36.5k ohm
PR836 to 71.5k ohm
PR859 to 10k ohm
1 2 20150225
1 1
PC803 PC804
1000P_0402_50V7K 15P_0402_50V8J
1 2

1000P_0402_50V7K
PR803 100_0402_1%

24.9K_0402_1%
1

2
1 2 @ PR804 PR805 CSN_1b 51
+VCC_SA

1
0_0402_5% 2.61K_0402_1%
1 2 VSPP_1b 1 2 VSP_1b PH802
13 VCCSA_SENSE

PR80845

1
PSYS_MON
1
PC805 100K_0402_1%_NCP15WF104F03RC

PC806

4700P_0402_25V7K
1000P_0402_50V7K place

0.015u_0402_25V7K
2
@ PR807 0_0402_5% close

1 2
2

1
1 2 VSNN_1b 1 2VSN_1b

PC809

PC833
13 VSSSA_SENSE to L4
1 2 @ PR806 1 2 PR816

2
PR809 100_0402_1% 0_0402_5% PR811 @ PC807 15K_0402_1%
20K_0402_1% 1000P_0402_50V7K
1 2 @ PR812 1 2
+VCC_GT

2
PR810 100_0402_1% 0_0402_5% 2 1
15 VCCGT_SENSE 1 2 VSP_2ph PR818 SW_1b 51 +3VS

1
2 1 8.25K_0603_1% PR821
@ PR813 PC808 PR814 PR819 113K_0402_1% 10K_0402_1%
0_0402_5% 1000P_0402_50V7K 1K_0402_1% 1 2

2
1 2 VSNN_2ph 1 2 VSN_2ph VR_PWRGD 38
15 VSSGT_SENSE
PC811 220P_0402_50V7K

1
1 2 1 2
PR815 PR817 PC810 +1.0V_VCCST
100_0402_1% 49.9_0402_1% 1000P_0402_50V7K 1 2 close to the longer distance phase(81208 or 81210)

1
VR_ON 38,42 Alert,Data,Clk.

1K_0402_1%

24.9K_0402_1%
@ PR863

1 2
0_0402_5% PWM_1b 51

470P_0402_50V7K

0.1U_0402_16V7K
4.75K_0402_1% PR820

110_0402_1%

100_0402_1%
45.3_0402_1%
2

1
place PC812 DRVON 51

110_0402_1%
2

1
close 470P_0402_50V7K

PC813
2
PR829

PC815

PR828
to L2

2
23E@ PR825 PH803 8.25K_0603_1%

49

48
47
46
45
44
43
42
41
40
39
38
37

2
2
110K_0402_1% THERM_ 220K 5% 0402 PC814 PR834 1 2

PR823

PR822
SW_1a 51

1000P_0402_50V7K

2
1 2 15P_0402_50V8J 49.9_0402_1% @

VSN_2ph
VSP_2ph

VSP_1b
VSN_1b
COMP_1b
ILIM_1b
CSN_1b
CSP_1b
IOUT_1b

EN
TAB

PSYS

VR_RDY

2
1
23E@ PR833 1 2 VR_HOT# 38

PR824

PR826

PR866
PR835
2 15.4K_0402_1% 15K_0402_1% 2

1 1
PR830 1 36 @ PR860 1 2

2
PR825 69.8K_0603_1% 165K_0402_1% 2 IOUT_2ph PWM_1b 35 1 0_0402_5%
2 @ PC819

PC816

2200P_0402_25V7K
0.033U_0402_16V7K
SWN_GT1 DIFFOUT_2ph DRVON
22@ 1 2 1 2 1 2 22@ PR833 3 34 SCLK PR862 SOC_SVID_CLK 15 470P_0402_50V7K place

2
FB_2ph SCLK
1

1
PR831 12.4K_0402_1% 4 PU801 33 ALERT# 10_0402_1% 1 2 close

PC820

PC834
COMP_2ph ALERT# SOC_SVID_ALERT#_R 15
75K_0402_1% 1 2 5 32 SDIO 1 2 SOC_SVID_DAT 15 PH804 to L1
ILIM_2ph SDIO

1
PC817 PC818 220P_0402_50V7K 6 NCP81208 31 1 2 100K_0402_1%_NCP15WF104F03RC
2

1000P_0402_50V7K 2 7 CSCOMP_2ph VR_HOT# 30 PR869 100_0402_1% 2 1

8 CSSUM_2ph IOUT_1a 29 PR836 71.5K_0402_1%
51 CSN_GT1

2
1 2 9 CSREF_2ph CSP_1a 28
+5VS @ PR868 0_0402_5% 10 CSP2_2ph CSN_1a 27
CSN_1a 51

ROSC_COREGT
0.1U_0402_16V7K

1 2 11 CSP1_2ph ILIM_1a 26

ADDR_VBOOT

0.015u_0402_25V7K
TSENSE_2ph COMP_1a
1

1
TSENSE_1ph
RSOC_SAUS

ICCMAX_2ph
1 2 12 25

PR842
+19VB
100K_0402_1%_NCP15WF104F03RC

ICCMAX_1a
ICCMAX_1b

36.5K_0402_1%
VRMP VSN_1a

PWM1_2ph
PWM2_2ph

1
PC821 @ PR864 PR801 PC826
1

PWM_1a
0.01U_0402_50V7K 0_0402_5% 1K_0402_1% PC824

VSP_1a
PC822

1000P_0402_50V7K

0.01U_0402_50V7K
2

2
1

1
2200P_0402_50V8J
PH801

PC801

PC825
61.9K_0402_1%

VCC

1 2
1 2 @ PR865 PR840 PC829

1
PR845 2.26K_0402_1% PC827 0_0402_5% 100_0402_1% 15P_0402_50V8J

2
1 2 1000P_0402_50V7K VSN_1a 1 2 1 2 2 1
51 SWN_GT1
2

13
14
15
16
17
18
19
20
21
22
23
24
PR850 PR843 1K_0402_1%
PR844

1
1 2 PR848
1 0 0 度C +5VS 2_0402_1% PC828 1000P_0402_50V7K
VSSSENSE 15
2.49K_0402_1%

2
place @ PR847

24K_0402_1%
33.2K_0402_1%

2
1

1
close PR846 2.43K_0402_1% 0_0402_5%

1
1 2 1 2

PR853

PR854
to U2 PC831
VCCSENSE 15
1U_0603_10V6K VSP_1a 1 2 1 2 2 1
+VCC_CORE

2
PC830 PR851

2
1000P_0402_50V7K PR867 2.43K_0402_1% 100_0402_1%

1 2

1
@ PR852

1000P_0402_50V7K
0_0402_5%

61.9K_0402_1%
1

1
2
PWM_1a 51 PH805

PC832
100K_0402_1%_NCP15WF104F03RC
3 3

PR855
place

2
23E@ PR856 close

10K_0402_1%
PR856 48.7K_0402_1%

PR857 88.7K_0402_1%

PR858 15.4K_0402_1%
52.3K_0402_1% to U1

1
2

2
PR859
22@

PWM1_2ph 51

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
IMVP8, NCP81206
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 50 of 60
A B C D E
 A B C D E

+19VB

EMI@ PL9002
HCB2012KF-121T50_0805
+19VB_CPU 1 2
change PL9002, PL9003
InputCapacitor:
10uF_0805_X5R_25V EMI@ PL9003 SM01000C000 to comm VCC:
HCB2012KF-121T50_0805 Imax=19.6A Ipeak=28A Iocp=34A
1 2 part SM01000P200
VCCGT:

10U_0805_25V6K

10U_0805_25V6K

2200P_0402_50V7K
EMI@ PC9003
1 Imax=25.9A Ipeak=37A Iocp=44A

68U_25V_M_R0.36
Height 8 mm

@EMI@ PC9015

PC9004
MDU1516URH_POWERDFN56-8-5

0.1U_0402_25V6
1

1
1 + 1
PR9001 PC9001

PC9014

PC9002
100u_SF000000I80

5
2.2_0603_5% 0.22U_0603_16V7K VCCSA:
1 2 1 2 Imax=4.5A Ipeak=3.15A Iocp=5.4A

2
2 Height 6 mm
68u_SF000000W00
4
PU9001
NCP81253MNTBG_DFN8_2X2
(Common Part) +VCC_CORE

PQ9002
1 8 HG_VCORE SH000011H00 7*7*4

3
2
1
BST DRVH PL9001 0.22UH 20% FDUE0640J -H 25A
2 7 SW_VCORE 1 4
50 PWM_1a PWM SW

50 DRVON 3 6 2 3
EN GND

5
MDU1511RH_POWERDFN56-8-5

MDU1511RH_POWERDFN56-8-5
4 5

@EMI@ PR9002
+5VS
PAD

VCC DRVL

4.7_1206_5%
1
1

CSN_1a 50
9

LG_VCORE LG_VCORE
4 4 DCR=0.98m ohm +-5%
PC9049
4.7U_0603_6.3V6K

Common part SH000011H00

2

2
3
2
1

3
2
1
PQ9001

PQ9003

PC9073
680P_0603_50V7K
1
2
SW_1a 50

@EMI@
PR9005 PC9083 +19VB_CPU
2.2_0603_5% 0.22U_0603_16V7K

10U_0805_25V6K

10U_0805_25V6K
2200P_0402_50V7K
1 2 1 2 InputCapacitor:

EMI@ PC9086
2 2

@EMI@ PC9085
10uF_0805_X5R_25V

0.1U_0402_25V6
1

1
PQ9005

PC9087

PC9088
MDU1516URH_POWERDFN56-8-5

2
PU9003
NCP81151MNTBG_DFN8_2X2 4 (Common Part) +VCC_GT
1 9
BST FLAG SH000011H00 7*7*4
2 8 HG1_GT
50 PWM1_2ph PWM DRVH PL9005 0.22UH 20% FDUE0640J -H 25A

3
2
1
DRVON 3 7 SW1_GT 1 4 +VCC_GT
EN SW

+5VS 4
VCC GND
6 2 3 DCR=0.98m ohm +-5%
Common part SH000011H00

5
5 PR9009 10_0402_1%

MDU1511RH_POWERDFN56-8-5

@EMI@ PR9010
MDU1511RH_POWERDFN56-8-5
DRVL

1
1 2

4.7_1206_5%
1
CSN_GT1 50

PC9090
4.7U_0603_6.3V6K
2
LG1_GT 4 LG1_GT 4
SWN_GT1 50

PC9092
680P_0603_50V7K
3
2
1

3
2
1

1
PQ9009

PQ9007

2
InputCapacitor:

@EMI@
10uF_0805_X5R_25V +19VB_CPU
10U_0805_25V6K

10U_0805_25V6K

2200P_0402_50V7K
EMI@ PC9118
@EMI@ PC9117
0.1U_0402_25V6
1

3 3
PC9115

PC9116

PR9013 PC9119
2

2.2_0603_5% 0.22U_0603_16V7K
1 2 1 2

HG_SA
AON7934
Rds(on)=12.4~15.8m ohm
PU9004 PQ9008
4

NCP81253MNTBG_DFN8_2X2 AON7934_DFN3X3A8-10 DCR=4~4.2m ohm +-5%

Common part SH00000ID00
+VCC_SA
D1

D1

D1

G1

1 8
BST DRVH PL9006 0.47UH 20% MMD-06CZ 17.5A
2 7 10 9 SW_SA 1 4
50 PWM_1b PWM SW D1 D2/S1
DRVON 3 6 2 3
@EMI@ PR9014

EN GND
G2
S2

S2

S2

4.7_1206_5%
1

4 5
+5VS
PAD

VCC DRVL
5

8
1

9
PC9154
4.7U_0603_6.3V6K

CSN_1b 50
2

PC9155
680P_0603_50V7K
1

SW_SA SW_1b 50
2

LG_SA
@EMI@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Power Train
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 51 of 60
A B C D E
 1

1.0
Rev

60
of
52
Compal Electronics, Inc.

Sheet
A4WAS M/B LA-C611P
E

E
Tuesday, June 16, 2015
Power Train Document Number
+VCC_SA

PC9162
1U_0201_4V6M
+VCC_SA

1 2
Date:
Title

Size

PC9125 PC9141 PC9161

@

22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M

C
1uF_0201*7

1 2 1 2 1 2
PC9124 PC9140 PC9160
@

22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M

1 2 1 2 1 2
PC9123 PC9139 PC9159
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
@

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

1 2 1 2 1 2
2016/11/10

PC9122 PC9138 PC9158

22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
22uF_0603*12

1 2 1 2 1 2
PC9121 PC9137 PC9157
20140703

22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M

1 2 1 2 1 2
PC9120 PC9136 PC9156
22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M Deciphered Date
1 2 1 2 1 2 Compal Secret Data
D

D
2014/11/10
+VCC_GT

+VCC_GT

PC9143
PC9104 PC9114 PC9135 PC9171 PC9153 1U_0201_4V6M
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M

Security Classification
1 2
1 2 1 2 1 2 1 2 1 2 PC9142
PC9103 PC9113 PC9134 PC9169 PC9152 1U_0201_4V6M

Issued Date
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M
1 2
1 2 1 2 1 2 1 2 1 2 PC9184
PC9102 PC9112 PC9133 PC9164 PC9151 1U_0201_4V6M
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M
1 2
1 2 1 2 1 2 1 2 1 2 PC9185
1uF_0201*12

PC9101 PC9111 PC9132 PC9163 PC9150 1U_0201_4V6M

1uF_0201*12

22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M

1 2
1 2 1 2 1 2 1 2 1 2 PC9182
@

PC9100 PC9110 PC9131 PC9167 PC9149 1U_0201_4V6M

C

C
1uF_0201*14

22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M

1uF_0201*6

1uF_0201*14
1uF_0201*6

1 2
1 2 1 2 1 2 1 2 1 2 PC9183
@

PC9099 PC9109 PC9130 PC9165 PC9148 1U_0201_4V6M

22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M

比比 ,
1 2

1 SE00000UC00.
1 2 1 2 1 2 1 2 1 2 PC9181
@
22uF_0603*29

PC9098 PC9108 PC9129 PC9168 PC9147 1U_0201_4V6M

22uF_0603*26

SE00000U200比
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M
1 2
1 2 1 2 1 2 1 2 1 2 PC9178
@

PC9097 PC9107 PC9128 PC9170 PC9146 1U_0201_4V6M

22uF_0603*32

22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M

22uF_0603*38
unpop: 22uF_0603*10

unpop: 22uF_0603*16

1 2
1 2 1 2 1 2 1 2 1 2
PC9096 PC9106 PC9127 PC9145 PC9176
@
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M
1 2 1 2 1 2 1 2 1 2
D2*2

PC9095 PC9105 PC9126 PC9093 330U_D2_2V_Y PC9144 PC9175

D2*1

故 1u_020
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M

1u_0201
20140703

20140923

20150504

+
1

1 2 1 2 1 2 1 2 1 2
23E:

D2*1

D2*1
22:

(Common Part)
SGA00009S00
+VCC_CORE
B

B
PC9021 PC9038 PC9062 PC9052 PC9026 PC9048 PC9072 PC9078

+VCC_CORE
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9008 PC9037 PC9061 PC9051 PC9013 PC9047 PC9071 PC9077
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9007 PC9036 PC9060 PC9050 PC9025 PC9046 PC9070 PC9076
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9020 PC9035 PC9059 PC9180 PC9012 PC9045 PC9069 PC9075

@
543016_543016_SKL_PDG_UY_1_0_pub

22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M

Total VCORE Output Capacitor:

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9019 PC9034 PC9058 PC9179 PC9024 PC9044 PC9068 PC9074

@
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9018 PC9033 PC9057 PC9177 PC9023 PC9043 PC9067 PC9172

@
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
0201_3PCS

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
PC9006 PC9032 PC9056 PC9022 PC9042 PC9066 PC9173

@
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
22uF_0603_33PCS
1uF_30201_35PCS

1 2 1 2 1 2 1 2 1 2 1 2 1 2
330uF_R9_2PCS

PC9017 PC9031 PC9055 PC9011 PC9041 PC9065 PC9174

@
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
2014/09/23

1 2 1 2 1 2 1 2 1 2 1 2 1 2
0603_3PCS

PC9005 PC9030 PC9054 PC9028 330U_D2_2V_Y PC9010 PC9040 PC9064

A

A
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M

@
UNPOP

+
1

2
1 2 1 2 1 2 1 2 1 2 1 2
PC9016 PC9029 PC9053 PC9027 330U_D2_2V_Y PC9009 PC9039 PC9063
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M

2@
+
1
1 2 1 2 1 2 1 2 1 2 1 2

(Common Part)
SGA00009S00
1

4
 A B C D E

1 1

2 @VGA_EMI@
Imax=7A Ipeak=10A 2
@VGA_EMI@
PR1004 PC1003
VGA@ 4.7_1206_5% 680P_0603_50V7K
PL1001 VGA@ 1 2SNB_1.5VSDGPUP
1 2
HCB2012KF-121T50_0805
+19VB_1.5VSDGPUP
PU1001 @ PR1001 VGA@ PC1001 (Common Part)
1 2 2 9 0_0603_5%
+19VB IN PG 0.1U_0603_25V7K
SH00000YE00
10U_0805_25V6K

3 1 BST_1.5VSDGPUP
1 2 1 2 PL1002 VGA@
1.527V 1.8%
2200P_0402_50V7K

0.1U_0402_25V6

IN BS
1

1UH_PCMB063T-1R0MS_12A_20%
@VGA_EMI@ PC1004

PC1007

LX_1.5VSDGPUP
change PL1001 4 6 1 2
+1.5VSDGPUP
VGA_EMI@ PC1006

IN LX
2

SM01000C000 to comm 5 19

GM4G@ PR1005
25.5K_0402_1%

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
IN LX

1
GT@ PR1005 GM2G@ PR1005
part SM01000P200

330P_0402_50V7K
1

1
7 20
VGA@

30.9K_0402_1% 30.9K_0402_1%
GND LX

VGA@ PC1008

VGA@ PC1009

VGA@ PC1010

VGA@ PC1011

VGA@ PC1012

VGA@ PC1013

@VGA@ PC1014

@VGA@ PC1015
8 14

2
GND FB

2
18 17 LDO_3V_1.5VSDGPUP
GND VCC
Rup
1
1.5VS_DGPU_EN 11 10 VGA@
EN NC PC1016 FB = 0.6V

1
ILMT_1.5VSDGPUP 13 12 2 2.2U_0402_6.3V6M
ILMT NC

@
15 16 PR1006 PJ1002
+3VALW BYP NC 20K_0402_1% 1 2
+1.5VSDGPUP 1 2 +1.5VSDGPU
1

VGA@ 21
Rdown

2
PAD

VGA@
PC1017 JUMP_43X118
1U_0402_6.3V6K SY8288RAC_QFN20_3X3
3 3
2

Pin 7 BYP is for CS.

Common NB can delete +3VALW and PC15

LDO_3V_1.5VSDGPUP Brand
VGA Name VRAM Size Voltage VFB=0.6V
Vout=0.6V* (1+Rup/Rdown)
1

VGA@ PR1002
PR1007 40.2K_0402_1% 2GB 1.5V(or 1.35V) Vout=1.365V
0_0402_5%
1.5VS_DGPU_EN 1 2 1.5VS_DGPU_PW R_EN 20,42 N16S-GT NV940
2

ILMT_1.5VSDGPUP
4GB 1.5V(or 1.35V)
Vout=0.6V* (1+(25.5/20))=1.356
VGA@ PC1002
0.1U_0402_16V7K
1

@VGA@
@

1M_0402_1% Change PR1002 from

PR1008
10K to 40.2K for non 2GB 1.5V(or 1.35V) Vout=0.6V* (1+(30.9/20))=1.527
2

0_0402_5% PR1003
GC6. 20141219
N16V-GM NV920
2

4GB Only 1.35V

The current limit is set to 8A, 12A or 16A when this pin
4 is pull low, floating or pull high 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
1.5VSDGPUP
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A3 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 53 of 60
 A B C D E

1 1

Module model information

SY8032_V2.mdd

@ PJ1102
JUMP_43X79
1 2
+1.05VSDGPUP 1 2 +1.05VSDGPU

VIN_1.05VS
VGA@
PC1102 (Common Part)
22U_0603_6.3V6M
2 VGA@ SH00000YG00 4*4*2 2
1 2 PU1101
SY8032ABC_SOT23-6
@ PJ1101 PL1101 VGA@
JUMP_43X79 1UH_2.8A_30%_4X4X2_F
VIN_1.05VS LX_1.05VS
+3VS
1
1 2
2 4
IN LX
3 1 2
+1.05VSDGPUP Imax= 0.7A, Ipeak= 1.1A

VGA@
5 2 PR1101
PG GND

68P_0402_50V8J
6 1 @VGA_EMI@

VGA@ PR1102
7.68K_0402_1%

22U_0603_6.3V6M

22U_0603_6.3V6M
FB EN

1
PC1103

1
@ PR1103 4.7_0603_5%

PC1104

PC1105
0_0402_5%

2
1 2 EN_1.05VS
10,20,42,55 DGPU_PWROK

2
Rup

1SNUB_1.05VS

VGA@

VGA@
1

PR1104
10K_0402_1% PR1105 1 @ PC1106 FB_1.05VS
1 @ 2
+3VSDGPU_AON 1M_0402_1% 0.1U_0402_16V7K PC1101 VGA@
2

1
@VGA_EMI@
2

VGA@ PR1106
680P_0402_50V7K
Rdown

2
10K_0402_1%

2
Note:
When design Vin=5V, please stuff snubber
to prevent Vin damage
Vout=0.6V* (1+Rup/Rdown)
=>0.6V*(1+(7.68/10)=1.061 (1.01%)
=>0.6V*(1+(7.87/10)=1.072 (2.1%)
3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
SY8032
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 54 of 60
A B C D E
 A B C D E

PSI : unmount PRV5 for 2 phase select +19VB_VGA PL1201

PSI 20

20
VGA_EMI@

DGPU_VID
1 phase with DEM 0V to 0.8V HCB2012KF-121T50_0805
1 phase with CCM 1.2V to 1.8V +3VS +3VSDGPU_AON +19VB_VGA 2 1
2 phase with CCM 2.4V to 5.5V +19VB
NOGC6@ PR1202

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
EN High Threshold = 1.6V

@VGA_EMI@ PC1205
0.1U_0402_25V6
20K_0402_1%
change PL1201

10K_0402_5%

10K_0402_5%

2200P_0402_50V7K
2

1
VGA_EN 1 2
SM01000C000 to comm

1
@VGA@ PR1203

@ PR1204

@ PR1205

VGA@ PC1202

VGA@ PC1203

VGA@ PC1204

VGA@ PC1207

VGA_EMI@ PC1208
0_0402_5%
VGA@ PR1208

VGA@ PC1209
part SM01000P200

0.1U_0402_16V7K

2
1
20K_0402_1%

2
VREF_VGA 2 1 1 2

MDU1516URH_POWERDFN56-8-5
3VSDGPU_MAIN_EN 20,42

5
1 1

2
GC6@ PR1206
20K_0402_1%
VGA@ PR1207
0_0603_5%
VGA@ PR1211 VGA@ PR1209 UG1_VGA 1 2 UG1_VGA_R 4
2K_0402_1% 20K_0402_1%
2 1 2 1REFADJ

VGA@ PL1202

PQ1201
3
2
1
1

VGA@ BST1_VGA1 2 BST1_VGA_R

PR1210 1 VGA@ 0.36UH_PDME064T-R36MS1R405_24A_20%
18K_0402_1% PC1210 @ PR1201 +VGA_CORE

1
2700P_0402_50V7K 0_0603_5% VGA@ PC1201 LX1_VGA 1 2
2

UGATE1

BOOT1
VID

EN
PSI
1 2

2
0.1U_0603_25V7K

@VGA_EMI@
680P_0402_50V7K 4.7_1206_5%
2

MDU1511RH_POWERDFN56-8-5
@VGA@ PR1224 6 20 LX1_VGA

PR1212
0_0402_5% REFADJ PHASE1
1 1

560U_2.5V_M

560U_2.5V_M
1SNUB_VGA1 1
REFIN_VGA 7 19 LG1_VGA 4 + +

PC1211

PC1212
2

NVVDD_GND_SENSE_R VGA@ PC1213 REFIN LGATE1 @VGA@ PR1213

.1U_0603_25V7K 0_0402_5%

1
1 2 VREF_VGA 8 PU1201 18 PVCC_VGA 1 2 2 2

PR1214

@VGA_EMI@
VREF VGA@ PVCC +5VS

13K_0402_1%

3
2
1
1

VGA@

VGA@
RT8812AGQW _W QFN20_3X3 VGA@ PC1214

PQ1202

PC1215
TON_VGA 9 17 LG2_VGA
TON LGATE2 1U_0603_10V6K

2
2 1

VGA@
+19VB
+19VB

2
2 VGA@ PR1215 10 16 2
RGND PHASE2

UGATE2
PGOOD
499K_0402_1%

BOOT2
VSNS
+19VB_VGA
GND

MDU1516URH_POWERDFN56-8-5
SS

5
PR1216 LX2_VGA
100_0402_1%
21

11

12

13

14

15
1 2

1
VGA@ PC1216
@VGA@ PR1218 UG2_VGA_R 4
0_0402_5% @ PR1217 0.1U_0603_25V7K

2
1 2 NVVDD_GND_SENSE_R 0_0603_5% VGA@ PL1203
22 VSSSENSE_VGA BST2_VGA 1 2 BST2_VGA_R
1

@VGA@ PC1218 0.36UH_PDME064T-R36MS1R405_24A_20%

PQ1203
3
2
1
1

@VGA@ PC1217 @ PR1219

.1U_0402_16V7K 0_0603_5% +VGA_CORE
2

@VGA@ PR1220 1000P_0402_50V7K UG2_VGA 1 2 UG2_VGA_R LX2_VGA 1 2

2

0_0402_5%

@VGA_EMI@
4.7_1206_5%
2
1 2 NVVDD_SENSE_R
22 VCCSENSE_VGA

MDU1511RH_POWERDFN56-8-5

PR1222
DGPU_PWROK 10,20,42,54
PR1221 N16S-GT EDP continuous:26A peak: 51A
100_0402_1% VGA@ PR1223 L side Rds(on): 3mohm(Typ), 3.8mohm(Max)

1SNUB_VGA2 1
1 2 10K_0402_5%
+VGA_CORE 2 1 +3VS LG2_VGA 4
Idsm: 11A@Ta=25C, 14A@Ta=70C

680P_0402_50V7K
CHOKE:0.36uH, DCR 1.4m ohm, L/2 over 36A

@VGA_EMI@
FSW = 304Khz

PC1219
3
2
1
3 3

PQ1204
(R=499K-->304Khz) (R=620K-->245Khz)
Imax=35A
Ipeak-51A

2
OCP = 61A
OVP=Vout*(145%~155%)
PWM-VID Spec and component Values
+VGA_CORE Under Remove GPU OTP circuit for HW request
PWM-VID Spec Config B Config C Config D GPU Core GB2-64 package
Vmin 0.6V 0.65V 0.9V
4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
VGA@ PC1320

VGA@ PC1338

VGA@ PC1322

VGA@ PC1323

VGA@ PC1324

VGA@ PC1325

VGA@ PC1326

VGA@ PC1327

VGA@ PC1328

VGA@ PC1329
Vmax 1.2V 1.15V 1.15V
1

1
Vboot 0.9V 0.9V 1.028V
2

Voltage step 6.25mV 25mV 12.5mV 2 +VGA_CORE

+VGA_CORE Near GPU Core
N of Voltage level 96 20 20
Rrefadj PR 20K 39K 27K
1U_0402_10V7

1U_0402_10V7

1U_0402_10V7

1U_0402_10V7

47U_0805_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
PC1330

PC1331

PC1332

PC1333
0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
VGA@ PC1334

VGA@ PC1335

VGA@ PC1336

VGA@ PC1337

VGA@ PC1339

VGA@ PC1340

VGA@ PC1341

VGA@ PC1342

VGA@ PC1343

VGA@ PC1344

VGA@ PC1345
1

22U_0603_6.3V6M
PC1321
Rref1 PR 20K 30K 7.5K
1

1
Rboot PR 2K 3K 0
2

2
2

2
Rref2=PR1209 PR 18K 24K 6.2K
@RF@_VGA@

@RF@_VGA@

@RF@_VGA@

@RF@_VGA@

VGA@
4 +PR1212 4
PR 0 3K 1.74K
C PC 2.7nf 1.8nf 5.6nf
N16S-GT
Security Classification Compal Secret Data Compal Electronics, Inc.
N16V-GM
Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL NVIDIA VGA_CORE
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Monday, June 22, 2015 Sheet 55 of 60
A B C D E
 A B C D E

2.2K 2.2K

2.2K
+3VALW_PRIM 2.2K
+3VS
BH10 SOC_SMBCLK
2N7002DW SO-DIMM 1
BG12 SOC_SMBDATA
SO-DIMM 2
1
Skylake 1

SOC
G-Sensor
SOC_SML0CLK 499

499
+3VALW_PRIM
SOC_SML0DATA

2.2K

2.2K
+3VALW_PRIM
SOC_SML1CLK

SOC_SML1DATA

2 2

2.2K

2.2K
+3VLP_EC

77 EC_SMB_CK1 100 ohm 7

SCL1 BATTERY
78 EC_SMB_DA1 100 ohm
SDA1 6
CONN

0 ohm EC_SMB_CK1_CHGR
12
0 ohm EC_SMB_DA1_CHGR
11 Charger

KBC SCL2 79 SOC_SML1CLK

SDA2 80 SOC_SML1DATA

3
KB9022 3

1.8K

1.8K +3VSDGPU_AON
I2CS_SCL
2N7002DW I2CS_SDA VGA

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SMBUS_Routing_Table
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 56 of 60
A B C D E
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

01 Design Change. change to the latest 2015 for MOSFET application. 01 45 change PQ305 to MDV1528 & PQ306 MDV1527 EVT

02 Design Change. change to the latest 2015 for MOSFET application. 01 47 change PQ503 to MDV1528 EVT
D D

03 Design Change. change to the latest 2015 for MOSFET application. 01 51 change PQ9002 & PQ9005 to MDU1516 EVT

04 Design Change. change to the latest 2015 for MOSFET application. 01 51 change PQ9001, PQ9003, PQ9007 & PQ9009 to MDV1511 EVT

05 Design Change. change to the latest 2015 for MOSFET application. 01 57 change PQ1201 & PQ1203 to MDU1516 EVT

06 Design Change. change to the latest 2015 for MOSFET application. 01 57 change PQ1202 & PQ1204 to MDU1511 EVT
power off pulse
07 issue when S0 -> S5. +0.675VS have a pulse when S0->S5 as attached. 01 47 change Pu501 8207P to 8207M EVT
power off pulse
08 issue when S0 -> S5. 8207M output cap is use 330uF poscap 01 47 Delete PC510~PC515 22u*6 EVT
power off pulse
09 issue when S0 -> S5. 8207M output cap is use 330uF poscap 01 47 Add PC510 330u*1 EVT
power off pulse
10 8207M frequency is different with 8207P 02 47 change PR507 to 887k ohm DVT
C C

issue when S0 -> S5.

11 Design Change. Tune +1.5VSDGPUP enable time 02 53 change PR1002 to 40.2k ohm DVT

12 Stop use Anpec LDO Anpec LDO is EOL 02 49 change Pu702 to G971 DVT

13 DFB request pin is too small, avoid open solder 02 44 Change PJP201 SP021210250 (ACES_50458-00801-001_8P-T) to SP020017H00
(CVILU_CI9908M2HR0-NH_8P) DVT

Change
PR808 to 24.9k ohm
PR822 to 24.9k ohm
PR846 to 2.4k ohm
14 Tune CPU transient Tune CPU transient 02 50 PR867 to 2.4k ohm DVT
PR842 to 36.5k ohm
PR836 to 69.8k ohm
PR859 to 10k ohm
B B

15 Design Change. 02 45 Change PC315 0.1u to 2200p DVT

16 Design Change. change 1V output from 1.011V to 1.02V 02 48 Change PR608 13.7k to 14k ohm DVT

Change
17 Tune CPU transient Tune CPU transient 02 50 PR846 to 2.43k ohm
PR867 to 2.43k ohm DVT
PR836 to 71.5k ohm

18 Design Change Change to common part 02 53 Change PL9002, PL9003, PL1001 & PL1201 to common part (HCB2012KF-121T50_0805)
DVT

19 thermal request change PH1 from 92degree to 89degree 02 44 Change PR204 from 16.9k ohm to 18.7k ohm

A A

Security Classification
2014/11/10
Compal Secret Data
2016/11/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
PIR
Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 57 of 60
5 4 3 2 1
 A B C D E

Version change list (P.I.R. List) Page 1 of 3 for HW

Item Page Title Date Issue Description Solution Description Phase Rev.
1 11 CPU 1/9 NA Reserved RC189(0 ohm) for DGPU_AC_DETECT DVT 0.2
Change net from VCOUT1_PROCHOT# to VCOUT1_PROCHOT
Change U4901.117 from SEN_DET# to SW_PROCHOT#
Reserved protect circuit when adaptor 107% happen, requrie from DVT 0.2
1
2 38 EC 1/9 Acer Reserved Q2010A/B for SW_PROCHOT# and DGPU_AC_DETECT 1

Add R4960 for SW_PROCHOT# and VCOUT1_PROCHOT

Rename R4938.2 to SW_PROCHOT#
3 38 EC 1/9 Remove unuse part Delete R4905, R619, R4958 DVT 0.2
4 10 CPU 1/12 SYS_RESET# Pull-up to ALWAYS power rails Change RPC11.6 to +3VALW_PRIM DVT 0.2
5 11 CPU 1/12 Reserved PD for G_INT# Reserved RC117 for G_INT# DVT 0.2
6 11 CPU 1/12 NA Move RC212 to Page06 and add note for EC_SCI# DVT 0.2
7 11 CPU 1/12 Separate RPC18 for easy PU Change RPC18 to RC126, RC127 (1K) and RC128, RC129 (2.2K) DVT 0.2
8 17 CPU 1/12 Reserved for Cannonlake-U (2014MOW52) Connect UC1.U11/U12 to +1.8VALW_PRIM and reserved CC79 for UC1.U11/U12 DVT 0.2
9 18, 19 Memory 1/12 Change CIS Symbol and Footprint Change CD16,CD46 PN to SGA00009S00 DVT 0.2
10 29, 37 USB 1/12 Change CIS Symbol and Footprint Change L24,L25,L26,L28,L29,L30, L27 CIS Symbol to SM070003Y00 DVT 0.2
11 33 LAN 1/12 Reserved path for +3V_LAN Reserved R214 0_0850 for +3V_LAN DVT 0.2
12 35 WLAN 1/12 Disconnect SUSCK to M.2 connector to avoid leakage current R426 change to 0_0402 @ DVT 0.2
13 37, 38 USB 1/12 Control USB Charger behavior when disabel USB charger funct i on Change R854.1 from SUSP# to USB_CB and U4901.70 from OPMODE to USB_CB DVT 0.2
14 38 EC 1/12 Board ID change to DVT Change R4903 from 0_0402_5% to 12K_0402_5% DVT 0.2
15 38 EC 1/12 Remove unuse part Delete R4957, R4959 DVT 0.2
2
Change R3 to 560 ohm and change R6 to 430 ohm 2
16 39 LED 1/12 LED light adjust Change R2633.2 to +3VLP DVT 0.2

17 39 LID 1/12 Change Hall Sensor IC Change U3 to SA00008K800 (ANPEC) DVT 0.2
18 39 PTP 1/12 Add level shift for PTP I2C interface Add Q2012A/B, R2641, R2642, R2639, R2640
DVT 0.2
11 Change RC128,RC129 PU to +3VALW_PGPPC
19 41 Others 1/12 Follow DFX requriement Change H17 from 3P2 to 3P3 DVT 0.2
20 42 Sequence 1/12 For power off sequence Add R1000, R1002, Q2013, Q2014, Q2016 for tCPU17, tCPU18, tCPU28, tPLT15 DVT 0.2
21 06 Debug 1/15 Reserved for power on select Reserved RC53, RC54 for JAPS1.11 DVT 0.2
22 36 HDD 1/15 Pin def i nit on modif y JHDD2.10 connect to GND DVT 0.2
23 39 Others 1/15 Pin def i nit on modif y JLID1.2 change to LID_SW#, JLID1.3 NC DVT 0.2
24 08 SPI 1/20 Remove/Un-Pop unuse part Del RC203 and change un-pop RPC6 DVT 0.2
25 09, 40 DMIC 1/20 Reserved DMIC path from SOC Reserved R481, R482 for PCH_DMIC_CLK/DATA from UC1.H5/D7
DVT 0.2
Add R483, R484 0_0402 for Audio DMIC
26 22 NV 1/20 Update HYNIX C die straps table Update HYNIX C die straps table DVT 0.2
27 30 Others 1/20 Remove unuse part Del R377, R378, R376 DVT 0.2
28 35 WLAN 1/20 Separate M.2 pin32 and 46 for Intel WLAN 3165 JNGFF1.32 change to NC (for Intel 3165) DVT 0.2
3 29 38 Sequence 1/20 For power down sequence Add D27 for EC_VCCST_PG_R DVT 0.2 3

30 39 LED 1/20 Update CIS Symbol and Footprint Update LED1, LED2 CIS Symbol DVT 0.2
31 40 Audio 1/20 Update BOM Structure Change R2135, R2151 to EMC@ DVT 0.2
32 40 Audio 1/20 Adjust MONO_IN input voltage Change R2140 to 27K and R2138 to 27K(@) DVT 0.2
33 41 Others 1/20 Change reset signal Mount R2631 and un-mount R2632 DVT 0.2
0_0603 to R-Short: R2075, R81, RC176, RC209
34 Others 1/20 Change 0 ohm to R-Short 0_0402 to R-Short: R2131, RC172, R472, R927, R2552, R4953, R4956, RC178, DVT 0.2
RC197, R427,R428
35 20 NV 1/28 Remove unuse part Del D2002, R2055 DVT 0.2
36 30 HDMI 1/28 Remove unuse part DEL ZZZ1 (HDMI ROYALTY) DVT 0.2
37 30 HDMI 1/28 Change U52 main source (HDMI power switch) U52 change to SA00004ZA00 DVT 0.2
38 38 EC 1/28 Un-use part change to @ R4943 change to @ DVT 0.2
Change JXDP1 CIS symbol to CMC CIS Symbol(JPCMC1)
40 06 CMC 2/4 Change XDP to CMC
Del RPC3, RC22, RC25, RC20, RC14, CC120, CC121, RPC4 DVT 0.2
Rerout i ng RPC2, RPC4, RPC15, RC23, RC151
Add RC17, RC55, RC56
Change RC37 to @
4
Change XDP@ to CMC@ 4

41 08 LPC 2/4 Change 0 ohm to R-Short Change RPC8 to RC144~ RC147 0 ohm R-short DVT 0.2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
PIR-HW1
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 58 of 60
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Version change list (P.I.R. List) Page 2 of 3 for HW

Item Page Title Date Issue Description Solution Description Phase Rev.
42 10 2/4 Remove unuse part Del RC108 DVT 0.2
43 10 SOC 2/4 Add T164/T165 for CLK_CPU_ITP/CLK_CPU_ITP# Add T164/T165 for CLK_CPU_ITP/CLK_CPU_ITP# DVT 0.2
44 10 SOC 2/4 Change Material of AND gate Change UC3 to SA00000OH00 DVT 0.2
1
45 12 SOC 2/4 Follow PCH EDS1.2 add PD resistor when un-use USB Add RC130, RC131 for USB2_ID and USB2_VBUSSENSE DVT 0.2 1

46 10 SOC 2/5 Reserved PD resistor (2014MOW48) Reserved RC136 for Cannonlake-U DVT 0.2
47 13 SOC 2/5 Reserved path for VCCIO Reserved U4902, C977 DVT 0.2
48 06 SOC 2/9 Reserved path for TP_INT# Reserved RC137 DVT 0.2
49 17 SOC 2/9 Reserved power source for U11/U12 Add RC57 for UC1.U11/U12 DVT 0.2
50 19 DIMM 2/9 Remove un-use part Del CD46 DVT 0.2
51 29,37 USB Chock 2/9 Swap net because update CIS Symbol SWAP net of L24,L25,L26,L28,L29,L30,L27 DVT 0.2
52 10 Crystal 2/11 Update 32.768KHz Crystal to 9pF Change YC2 PN to SJ10000L000 DVT 0.2
53 41 D-Cover 2/25 Reserved SW5 for memory door on D-Cover Reserved SW5(@) DVT 0.2
54 14 PCH 2/26 Reserved for Intel PDG1.2 Table52-9 Reserved CC123, CC124,CC125 DVT 0.2
55 40 DMIC 3/2 Follow PDG1.2 Table28-3 R481,R482 change to 33 ohm DVT 0.2
56 08 SPI 3/3 2015MOW06 no need PU1K on SPI_IO2/IO3 Un-Mount RC47 DVT 0.2
57 08 Crystal 3/3 Modify for 9pF Cyrstal Change CC15,CC16 to 8.2pF DVT 0.2
58 18,19 Memory 3/3 Mount decoupling capacitor Mount and change CD1, CD17, CD28, CD47 to 0.1U_0402 DVT 0.2
59 35 SUSCLK 3/3 Del SUSCLK and reserved TP(Reqruie from Acer) Del R426, C85 and add T3806 DVT 0.2
60 39 Others 3/3 Un-mount un-use part Un-mount SW3 DVT 0.2
change RC202, RC49, RC50, RPC7 PU to +3VALW_PRIM
2 2
add Q2017, RC220, RC221, RC222, RC223
61 08 SMBUS 3/3 Add level shift for SOC_SMBCLK/SOC_SMBDATA DVT 0.2
change net name from SOC_SMBCLK/SOC_SMBDATA to
SOC_SMBCLK_1/SOC_SMBDATA_1
change RPC7 PU to 2.2K
62 08 Others 4/1 Delete reserved component Del RPC8, RC45, RPC6 PVT 0.3
Change RPC5 and RC52 to 15 ohm with 8M_SINGLE@
63 08 SMBUS 4/1 Add BOM Structure for SPI ROM Add RPC5 and RC52 33 ohm with 8M_DUAL@ PVT 0.3
Add reserved component UC2 with 8M_DUAL@
64 08 SMBUS 4/1 Delete EC SPI path Del RPC6 PVT 0.3
65 08 SPI 4/1 MOW36 QS sample no need to PD Change RC51 to ES@ PVT 0.3
66 13,39,41 Others 4/1 Change 0 ohm to R-Short 0_0402 to R-Short: R2631, R2634, RC168, RC186 PVT 0.3
67 37 Others 4/1 SMT require delete un-use 0 ohm to avoid USB Del R458, R461, R465, R466 PVT 0.3
chock solder issue
68 38 LID 4/1 For 2nd source hall sensor soultion Mount R618 PVT 0.3
69 30,31 Others 4/1 PD for HPD signal Add R380 PD100K, Mount R2530 PVT 0.3
70 38 Others 4/1 Board ID Change for PVT change R4903 to 15K PVT 0.3
3
71 42 Others 4/8 Add discharge circuit for +1.05VSDGPU Mount Q2008, R574, R1001 PVT 0.3
3

0_0402 to R-Short: R368,R369, R370, R371, R372,R373, R374, R375

72 30,37,40 Others 4/14 Change 0 ohm to R-Short R473, R474, R475, R476, R477, R478, R479, R480 PVT 0.3
0_0603 to R-Short: R2135, R2151
73 37,38 Others 4/16 Change U77 pin4 control by EC GPIO link U77.4 to U4901.119 PVT 0.3
Un-mount R857
74 12 CPU 4/17 Follow MOW10, USB2_ID/USB2_VBUSSENSE connect to GND Change RC130, RC131 to 0 ohm PVT 0.3
75 40 Audio 4/17 Beep Sound Path from EC Change R2138, R2140 to 22K and mount R2138 PVT 0.3
76 06 CPU 4/22 Add test point for CATERR# Add T166 PVT 0.3
77 06 Others 4/22 Cancel JAPS1 Mask to avoide soldering issue change JAPS1 footprint to ACES_50506-01841-P01_18P-NPM PVT 0.3
78 22, 25 GPU 4/30 Add Samsung E-Die VRAM Information Add X76629BOL13/X76629BOL14 PVT 0.3
79 03, 07 CPU 4/30 Add QS sample CPU for BOM Selection Add UC1 with QJFC@/QJ8N@/QJ8L@ PVT 0.3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/11/10 Deciphered Date 2016/11/10 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
PIR-HW2
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A4WAS M/B LA-C611P
Date: Tuesday, June 16, 2015 Sheet 59 of 60
A B C D E
 A B C D E

Version change list (P.I.R. List) Page 3 of 3 for HW

Item Page Title Date Issue Description Solution Description Phase Rev.
80 42 Others 5/14 BOM Error Change R574, R1001, Q2008 to VGA@ Pre-MP 1.0
81 38 Others 5/28 For abnormal shutdown Mount D26 Pre-MP 1.0
82 38 Others 5/28 Board ID change to Rev1.0 Change R4903 to 20K_0402_1% Pre-MP 1.0
1
83 01 Others 6/17 Update PCB Rev10 PN Update PCB PN to DAZ1DR00100 Pre-MP 1.0 1

84 39 Others 6/22 Cancel the MASK of JLID1 Change JLID1 to ACES_50506-01041-P01_10P-NPM Pre-MP 1.0
85 38 Others 7/14 Add C4917 for EC_RST# Add C4917 Pre-MP 1.0
86 39 Others 7/14 Add S spec number for i3/i5/i7 CPU add SR2EU@/SR2EY@/SR2EZ@ for UC1 MP number Pre-MP 1.0

2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/10/30 Deciphered Date 2014/05/24 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR-HW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Z5WAH M/B LA-B161P
Date: Friday, July 17, 2015 Sheet 60 of 60
A B C D E