SSM4501GM

N AND P-CHANNEL ENHANCEMENT

MODE POWER MOSFET
PRODUCT SUMMARY
N-CH BVDSS 30V
D2
Simple Drive Requirement D2 RDS(ON) 28mΩ
D1
Low On-resistance D1
ID 7A
Fast Switching
S2
G2 P-CH BVDSS -30V
G1
SO-8 S1 RDS(ON) 50mΩ
DESCRIPTION ID -5.3A
The advanced power MOSFETs from Silicon Standard Corp.
provide the designer with the best combination of fast switching,
ruggedized device design, low on-resistance and cost-effectiveness.

The SO-8 package is universally preferred for all commercial-

industrial surface mount applications and suited for low voltage
applications such as DC/DC converters.
D1 D2

Pb-free; RoHS-compliant
G1 G2

S1 S2
ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Rating Units

N-channel P-channel
VDS Drain-Source Voltage 30 -30 V
VGS Gate-Source Voltage ±20 ±20 V
3
ID@TA=25℃ Continuous Drain Current 7 -5.3 A
3
ID@TA=70℃ Continuous Drain Current 5.8 -4.7 A
1
IDM Pulsed Drain Current 20 -20 A
PD@TA=25℃ Total Power Dissipation 2 W
Linear Derating Factor 0.016 W/℃
TSTG Storage Temperature Range -55 to 150 ℃
TJ Operating Junction Temperature Range -55 to 150 ℃

THERMAL DATA
Symbol Parameter Value Unit
3
Rthj-amb Thermal Resistance Junction-ambient Max. 62.5 ℃/W

08/17/2007 Rev.1.00 www.SiliconStandard.com 1

 SSM4501GM

N-CH ELECTRICAL CHARACTERISTICS

o
@Tj=25 C (unless otherwise specified)

Symbol Parameter Test Conditions Min. Typ. Max. Units

BVDSS Drain-Source Breakdown Voltage VGS=0V, ID=250uA 30 - - V
ΔBVDSS/ΔTj Breakdown Voltage Temperature Coefficient Reference to 25℃, ID=1mA - 0.02 - V/℃
2
RDS(ON) Static Drain-Source On-Resistance VGS=10V, ID=7A - - 28 mΩ
VGS=4.5V, ID=5A - - 42 mΩ
VGS(th) Gate Threshold Voltage VDS=VGS, ID=250uA 1 - 3 V
gfs Forward Transconductance VDS=10V, ID=7A - 13 - S
o
IDSS Drain-Source Leakage Current (Tj=25 C) VDS=30V, VGS=0V - - 1 uA
Drain-Source Leakage Current (Tj=70oC) VDS=24V, VGS=0V - - 25 uA
IGSS Gate-Source Leakage VGS=±20V - - ±100 nA
2
Qg Total Gate Charge ID=7A - 8.4 - nC
Qgs Gate-Source Charge VDS=24V - 2.1 - nC
Qgd Gate-Drain ("Miller") Charge VGS=4.5V - 4.7 - nC
2
td(on) Turn-on Delay Time VDS=15V - 6 - ns
tr Rise Time ID=1A - 5.2 - ns
td(off) Turn-off Delay Time RG=3.3Ω,VGS=10V - 18.8 - ns
tf Fall Time RD=15Ω - 4.4 - ns
Ciss Input Capacitance VGS=0V - 645 - pF
Coss Output Capacitance VDS=25V - 150 - pF
Crss Reverse Transfer Capacitance f=1.0MHz - 95 - pF

SOURCE-DRAIN DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Units
IS Continuous Source Current ( Body Diode ) VD=VG=0V , VS=1.2V - - 1.7 A
2
VSD Forward On Voltage Tj=25℃, IS=7A, VGS=0V - - 1.2 V

08/17/2007 Rev.1.00 www.SiliconStandard.com 2

 SSM4501GM

P-CH ELECTRICAL CHARACTERISTICS

o
@Tj=25 C (unless otherwise specified)

Symbol Parameter Test Conditions Min. Typ. Max. Units

BVDSS Drain-Source Breakdown Voltage VGS=0V, ID=-250uA -30 - - V
ΔBVDSS/ΔTj Breakdown Voltage Temperature Coefficient Reference to 25℃, ID=-1mA - -0.03 - V/℃
2
RDS(ON) Static Drain-Source On-Resistance VGS=-10V, ID=-5.3A - - 50 mΩ
VGS=-4.5V, ID=-4.2A - - 90 mΩ
VGS(th) Gate Threshold Voltage VDS=VGS, ID=-250uA -1 - -3 V
gfs Forward Transconductance VDS=-10V, ID=-5.3A - 8.5 - S
o
IDSS Drain-Source Leakage Current (Tj=25 C) VDS=-30V, VGS=0V - - -1 uA
o
Drain-Source Leakage Current (Tj=70 C) VDS=-24V, VGS=0V - - -25 uA
IGSS Gate-Source Leakage VGS= ± 20V - - ±100 nA
2
Qg Total Gate Charge ID=-5.3A - 20 - nC
Qgs Gate-Source Charge VDS=-15V - 3.5 - nC
Qgd Gate-Drain ("Miller") Charge VGS=-10V - 2 - nC
2
td(on) Turn-on Delay Time VDS=-15V - 12 - ns
tr Rise Time ID=-1A - 20 - ns
td(off) Turn-off Delay Time RG=6Ω,VGS=-10V - 45 - ns
tf Fall Time RD=15Ω - 27 - ns
Ciss Input Capacitance VGS=0V - 790 - pF
Coss Output Capacitance VDS=-15V - 440 - pF
Crss Reverse Transfer Capacitance f=1.0MHz - 120 - pF

SOURCE-DRAIN DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Units
IS Continuous Source Current ( Body Diode ) VD=VG=0V , VS=-1.2V - - -1.7 A
VSD Forward On Voltage2 Tj=25℃, IS=-2.6A, VGS=0V - - -1.2 V

Notes:
1.Pulse width limited by Max. junction temperature.
2.Pulse width <300us , duty cycle <2%.
2
3.Surface mounted on 1 in copper pad of FR4 board ; 135℃/W when mounted on Min. copper pad.

08/17/2007 Rev.1.00 www.SiliconStandard.com 3

 SSM4501GM

N-Channel

36 36
10V 10V
8.0V 8.0V
6.0V 6.0V
5.0V 5.0V

V GS =4.5V
ID , Drain Current (A)

ID , Drain Current (A)

24 24
V GS =4.5V

12 12

T C =25 o C T C =150 o C

0 0
0 2 3 5 6 0 2 3 5 6

V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

90 2

I D =7.0A I D =7.0A
T C =25 ℃ V GS = 10V

70

1.4
Normalized RDS(ON)
RDS(ON) (mΩ )

50

0.8

30

10
0.2
2 6 10 14 -50 0 50 100 150

V GS (V) T j , Junction Temperature ( o C)

Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance

v.s. Junction Temperature

08/17/2007 Rev.1.00 www.SiliconStandard.com 4

 SSM4501GM

N-Channel

8 2.4

6 1.8
ID , Drain Current (A)

PD (W)
4 1.2

2 0.6

0 0
25 50 75 100 125 150 0 50 100 150

o T c ,Case Temperature ( o C)
T c , Case Temperature ( C)

Fig 5. Maximum Drain Current v.s. Fig 6. Typical Power Dissipation

Case Temperature

100 1

Duty Factor = 0.5

0.2
Normalized Thermal Response (Rthja)

10
0.1
1ms 0.1
0.05
ID (A)

1 10ms 0.02

100ms 0.01

PDM
0.01
t
1s
0.1 Single Pulse T

T C =25 o C 10s
Duty Factor = t/T
Single Pulse DC Peak Tj = P DM x R thja + Ta
o
Rthja=135 C/W

0.01 0.001
0.1 1 10 100 0.0001 0.001 0.01 0.1 1 10 100 1000

V DS (V)
t , Pulse Width (s)

Fig 7. Maximum Safe Operating Area Fig 8. Effective Transient Thermal Impedance

08/17/2007 Rev.1.00 www.SiliconStandard.com 5

 SSM4501GM

N-Channel

f=1.0MHz
12 10000

I D =7.0A
VGS , Gate to Source Voltage (V)

V DS= 1 6 V 1000
V DS =20V Ciss
V DS =24V

C (pF)
6

Coss
100 Crss
3

0 10
0 4 8 12 16 1 7 13 19 25 31

Q G , Total Gate Charge (nC) V DS (V)

Fig 9. Gate Charge Characteristics Fig 10. Typical Capacitance Characteristics

100 3

2.5

10

T C = 150 o C T C =25 o C
VGS(th) (V)
IS(A)

1 1.5

0.1

0.5

0.01 0
0 0.4 0.8 1.2 -50 0 50 100 150

V SD (V) T j , Junction Temperature ( o C )

Fig 11. Forward Characteristic of Fig 12. Gate Threshold Voltage v.s.
Reverse Diode Junction Temperature

08/17/2007 Rev.1.00 www.SiliconStandard.com 6

 SSM4501GM

N-Channel

VDS
RD 90%

VDS TO THE
D OSCILLOSCOPE

0.5 x RATED VDS

RG G
10%
+ S
VGS
10V VGS
-

td(on) tr td(off) tf

Fig 13. Switching Time Circuit Fig 14. Switching Time Waveform

VG

VDS

TO THE
QG
D OSCILLOSCOPE
4.5V
0.8 x RATED VDS
G QGS QGD

S VGS
+
1~ 3 mA
-
I I
G D

Charge Q

Fig 15. Gate Charge Circuit Fig 16. Gate Charge Waveform

08/17/2007 Rev.1.00 www.SiliconStandard.com 7

 SSM4501GM

P-Channel

20 20
10V 10V
8.0V 8.0V
6.0V 6.0V

15 15

-ID , Drain Current (A)

-ID , Drain Current (A)

V GS =4. 0 V
V GS =4. 0 V
10 10

5 5

T C =25 o C T C =150 o C

0 0
0 1 2 3 4 0 1 2 3 4

-V DS , Drain-to-Source Voltage (V) -V DS , Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

90 1.8

I D =-5.3A
I D =-5.3A
T C =25 ℃
80 1.6 V GS = -10V

70 1.4
Normalized RDS(ON)
RDS(ON) (mΩ )

60 1.2

50 1

40 0.8

30 0.6
3 4 5 6 7 8 9 10 11 -50 0 50 100 150

-V GS (V) T j , Junction Temperature ( o C)

Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance

v.s. Junction Temperature

08/17/2007 Rev.1.00 www.SiliconStandard.com 8

 SSM4501GM

P-Channel

6 2.4

1.8
-ID , Drain Current (A)

PD (W)
3 1.2

0.6

0 0
25 50 75 100 125 150 0 50 100 150
o
T c , Case Temperature ( C) T c ,Case Temperature ( o C)

Fig 5. Maximum Drain Current v.s. Fig 6. Typical Power Dissipation

Case Temperature

100 1

Duty Factor = 0.5

Normalized Thermal Response (R thja)

0.2

10

1ms 0.1
0.1

0.05
-ID (A)

1
10ms 0.02

100ms 0.01
PDM

t
0.01
1s T
Single Pulse
0.1
Duty Factor = t/T
10s Peak Tj = P DM x Rthja + Ta
o
T C =25 C DC Rthja=195 oC/W

Single Pulse
0.01 0.001
0.1 1 10 100 0.0001 0.001 0.01 0.1 1 10 100 1000

-V DS (V) t , Pulse Width (s)

Fig 7. Maximum Safe Operating Area Fig 8. Effective Transient Thermal Impedance

08/17/2007 Rev.1.00 www.SiliconStandard.com 9

 SSM4501GM

P-Channel

14
f=1.0MHz
10000

12
I D =-5.3A
-VGS , Gate to Source Voltage (V)

10

V DS =-10V 1000
Ciss
8 V DS =-15V

C (pF)
V DS =-20V
Coss
6

100 Crss
4

0
10
0 5 10 15 20 25 30
1 5 9 13 17 21 25 29

Q G , Total Gate Charge (nC) -V DS (V)

Fig 9. Gate Charge Characteristics Fig 10. Typical Capacitance Characteristics

3
100.00

2.5

10.00

2
-VGS(th) (V)

T j =150 o C T j =25 o C
-IS(A)

1.00 1.5

0.10

0.5

0.01 0
0.1 0.4 0.7 1 1.3 -50 0 50 100 150

-V SD (V) T j ,Junction Temperature ( o C)

Fig 11. Forward Characteristic of Fig 12. Gate Threshold Voltage v.s.
Reverse Diode Junction Temperature

08/17/2007 Rev.1.00 www.SiliconStandard.com 10

 SSM4501GM

P-Channel

VDS
RD 90%

VDS TO THE
D OSCILLOSCOPE

0.5 x RATED VDS

RG G
10%
S
-10 V
VGS
VGS

td(on) tr td(off) tf

Fig 13. Switching Time Circuit Fig 14. Switching Time Waveform

VG

VDS

TO THE QG
D OSCILLOSCOPE
-10V
0.5 x RATED VDS
G QGS QGD
S VGS

-1~-3mA

I ID
G

Charge Q

Fig 15. Gate Charge Circuit Fig 16. Gate Charge Waveform

08/17/2007 Rev.1.00 www.SiliconStandard.com 11

 SSM4501GM

Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no
guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of
Silicon Standard Corporation or any third parties.

08/17/2007 Rev.1.00 www.SiliconStandard.com 12