Scribd
Upload
85 views

MP 80863 PDF

1) The document describes the signals of the 8086 microprocessor, including address, data, status and control lines. 2) It explains the minimum and maximum mode of operation, with diagrams of the pin configurations and signal timings for memory reads, writes and I/O operations. 3) The modes of operation include single processor minimum mode and multi-processor maximum mode.

Uploaded by

mine
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
85 views

MP 80863 PDF

1) The document describes the signals of the 8086 microprocessor, including address, data, status and control lines. 2) It explains the minimum and maximum mode of operation, with diagrams of the pin configurations and signal timings for memory reads, writes and I/O operations. 3) The modes of operation include single processor minimum mode and multi-processor maximum mode.

Uploaded by

mine
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 21

Microprocessors and Microcontrollers – 11EC311

Signal Description of 8086


Pin Diagram of 8086

07/08/19 8086 Signal Description - MPMC 2


Signal Description
AD15-AD0:
●
Time Multiplexed Address/Data Line
●
T1- Address Cycle
●
T2, T3, TW, T4- Data Cycle
●
T are clock states of machine cycle
S4 S3 Indication
A19/S6- A16/S3: 0 0 Alternate Data
●
Time Multiplexed Address/Status Lines 0 1 Stack
●
During T1- Address line 1 0 Code or None
●
During I/O these lines are low. 1 1 Data
●
S5 -- status of IE Flag at beginning of each cycle.
●
S4 , S3 indicate segment register used for memory
●
Latches separate addr and status bits
●
S6 is always low
07/08/19 8086 Signal Description - MPMC 3
Signal Description

●
BHE/S7: BUS HIGH ENABLE BHE A0 Indication
– Indicates a transfer over D8-D15 0 0 Whole Word
– S7 is not currently used. 0 1 Upper byte from/
●
RD: Read to odd addr

– 0 – Performing Read 1 0 Lower byte from/


to even addr

●
READY: 1 1 None
– Acknowledgement from slow devices that they completed transfer
●
TEST:
– 0 – Execution continues
– 1 – Idle State
– Examined by WAIT instruction
07/08/19 8086 Signal Description - MPMC 4
Signal Description
●
INTR: Interrupt Request
– Level triggered input
– Sampled during last clock cycle of each instruction to
determine availability of request.
●
NMI: Non-maskable interrupt
– Causes type 2 interrupt ( Cannot be Masked)
●
RESET:
–Stops execution and starts from FFFF0H
●
CLK: Clock Input
–Square wave of 33% duty Cycle. Range: 5Mhz- 10 MHz
●
VCC: +5V
●
GND: Ground
●
MN/MX: 1-- Min Mode 0-- Max Mode
07/08/19 8086 Signal Description - MPMC 5
Signal Description – Minimum Mode Pins
●
M/IO: Memory/IO Operation
– 0 – I/O Operation
– 1 – Memory Operation
– Active from T4 to present T4
●
INTA: Interrupt Acknowledge
–0 – Processor accepted interrupt.
– Low during T2,T2,TW of interrupt acknowledge
cycle.
●
ALE: Address Latch Enable
– Indicates availability of valid address on
address/data line
– Connected to latch enable input of Latches
07/08/19 8086 Signal Description - MPMC 6
Signal Description – Minimum Mode Pins
●
DT/R:Data Transmit or receive
–1-Transmit
– 0- Receive
– Same timing as M/IO
●
DEN: Data Enable
Availability of valid data over address/data lines
–
– Used to enable transreceivers to separate data from
multiplexed address/data signal.
– Active from middle of T2 to middle of T4.
●
HOLD/HLDA: Hold Acknowledge.
– 1 – Another master is requesting bus access
– After hold processer gives hold acknowledge signal in
middle of next clock cycle after current instruction cycle.
– 0 – HDLA is also low
07/08/19 8086 Signal Description - MPMC 7
Signal Description – Maximum Mode Pins

● S2,S1,S0: S2 S1 S0 Indication
– Status lines 0 0 0 Interrupt
– Active from T4 to current T1,T2 Acknowledge
0 0 1 Read I/O Port
●
LOCK:
0 1 0 Write I/O Port
– 0 – Other system bus
0 1 1 Halt
masters will be prevented
1 0 0 Code access
from gaining system bus.
1 0 1 Read memory
– Activated by LOCK prefix
1 1 0 Write memory
Instruction.. 1 1 1 Passive

07/08/19 8086 Signal Description - MPMC 8


Signal Description – Maximum Mode Pins

● QS1, QS0 – Queue Status QS1 QS0 Indication


– Status of prefetch queue. 0 0 No Operation
0 1 First byte of opcode
from the queue
● RQ/GT0, RQ/GT1:
1 0 Empty Queue
– Request/Grant 1 1 Subsequent byte
– Used by other local bus from the queue

masters to force the processor to release the local bus at


end of processor’s current bus cycle.
– RQ/GT0 have high priority than RQ/GT1.

07/08/19 8086 Signal Description - MPMC 9


General Timing Diagram

07/08/19 8086 Signal Description - MPMC 10


Possible Operations

●
Memory Read
●
Memory Write
●
IO Read
●
IO Write

07/08/19 8086 Signal Description - MPMC 11


Modes of Operation: Minimum Mode

●
Single Processor Mode
●
Latches are D-Flipflops( 74LS373/8282)
– Demux address from addr/data signal
– 3 octal latches are required
●
Transreceivers are bidirectional buffers(74245)
– Demux data from addr/data signal
– Controlled using DEN and DT/R
– 2 octal data buffers
●
M/IO, RD , DEN indicate type of data transfer.

07/08/19 8086 Signal Description - MPMC 12


8086 Minimum Mode

07/08/19 8086 Signal Description - MPMC 13


Minimum Mode Read Cycle Timing Diagram

07/08/19 8086 Signal Description - MPMC 14


Minimum Mode Write Cycle Timing Diagram

07/08/19 8086 Signal Description - MPMC 15


Modes of Operation: Maximum Mode

●
Multi Processor Mode
●
Bus controller chip IC8288 derives outputs from given
signals.
ALE,DEN,DT/R,MRDC,MWTC,AMWC,IORC,IOWC,AIOWC
●
Memory Read Control, Memory Write Control
●
Advanced Memory Write Control
●
IO Read Control, IO Write Control
●
Advanced IO Write Control

07/08/19 8086 Signal Description - MPMC 16


8086 Maximum Mode

07/08/19 8086 Signal Description - MPMC 17


Maximum Mode Memory Read Timing Diagram

07/08/19 8086 Signal Description - MPMC 18


Maximum Mode Memory Write Timing Diagram

07/08/19 8086 Signal Description - MPMC 19


References

●
https://www.sites.google.com/site/sripathroykoganti/my-forms
●
D.V.Hall “Microprocessor and Interfacing”, 2nd Edition Tata McGraw
Hill Publishing Company,2006.
●
A.K. Ray & K. M Bhurchandi, “Advanced Microprocessors &
peripherals”, Tata Mc Graw Hill Publishing Company 2002.
●
Rajkamal, “Microcontrollers - Architecture, Programming, Interfacing
& System Design”, 2 nd edition, Pearson Education.

07/08/19 8086 Signal Description - MPMC 20


Thank You

07/08/19 8086 Signal Description - MPMC 21

You might also like