Lab 3 OR and XOR Logic Gates

Objectives

The following are objectives of this lab:

1. Show the truth tables for the OR and XOR gates agree with the theoretical tables.
2. Use the OR and XOR gates with frequency input and oscilloscope output.
3. Use OR and XOR gates to provide circuits with a variety of functions including 1’s and 2’s
complement arithmetic.

Materials Needed

1. One 7432 OR gate

2. One 7486 XOR gate
3. Four LEDs
4. Resistors: nine 330 Ω, one 1.0 kΩ
5. One 8-position DIP switch
6. One SPST switch (wire may be substituted)

Project Statement
Operation of an n-input OR gate is summarized as follows:

Output is HIGH if any input is HIGH, otherwise the output is LOW

Inputs Output Table 3-1(a)

A B X
0 0 0 Truth table for 2-input OR gate
0 1 1
1 0 1
1 1 1

Operation of an XOR gate as follows:

Output is HIGH if only one input is HIGH: otherwise the output is low

Inputs Outputs Table 3-1(b)

A B X
0 0 0 Truth table for XOR gate
0 1 1
1 0 1
1 1 0

Lab 3 – OR XOR Logic Gates 1

Pre-lab Questions
1. Use 2-input NAND gates and build the XOR function:

2. Using only 2-input OR gates, implement a 3-input OR function:

Procedure
Logic Functions for the OR and XOR Gates

1. Use the data sheets for the 7432 quad 2-input OR gate and for the 7486 quad 2-input
XOR. Find connections for Vcc and 0 V pin connections on the data sheet. Review the
Truth Table on the next page for the OR gate – Table 3-2. As in Lab 3, apply the logic 1
through a 1.0 kΩ and a logic 0 by connecting to 0 V. Use the DMM to measure output
voltage states for all states of the input. Repeat the process for the XOR gate – Table 3-
3.

0V 5V
-+ -+ 5V From Fig. 3-2 Basic Layout to
Test for States of Truth Table
=1 1KΩ

=1 1KΩ
Vcc
0V
the
chip

=0
=0

DMM

(set to Volt)

Lab 3 – OR XOR Logic Gates 2

 Inputs Measured
Output
A B Output Voltage Table 3-2
OR gate
0 0

0 1

1 0

1 1

Inputs Measured
Output Table 3-3
A B Output XOR gate
Voltage
0 0

0 1

1 0

1 1

2. Construct the circuit below in Figure 3-1. Set the input on pin 2 of the XOR from the
pulse generator (set to TTL pulse). Set the frequency to 1 kHz and sketch the input and
output in the graph at right. Observe the input and the output with S open (high = 1)
and then closed (low = 0).

+5V
+5V
330Ω Pin 2
1.0KΩ
(input):
S 1

3 Output (pin 3)
2
with S1 open

0V Frequency Generator
(set to 1K Hz, TTL)
Output (pin 3)
0V with S1 closed

Fig. 3-1 Frequency Input

XOR Gate Output

Lab 3 – OR XOR Logic Gates 3

3. Build the circuit below and test the circuit with the complement switch first open and
then closed. Fill in the truth table Table 3-4a and b.
+5V

330Ω 330Ω 330Ω 330Ω +5V

330Ω
D3
Q3

+5V
0V 330Ω
D2
Q2
+5V
0V 330Ω
D1
Q1
+5V
0V 330Ω
D0
Q0
+5V
0V 1.0KΩ
complement

Fig. 3-2
1's or 2's
0V
Complement

Notice the arrangement of LEDs and resistors at the input and output section of the
circuit. These are shown in the Fig. 3-3 below.

0V 5V Input
-+ LEDs
-+ D3
330Ω
DIP D2
SW
D1
D0
8
4
2
1

Fig. 3-3 Arrangement of

D1 D
3
Input and Output LEDs
D2 D0

Q 0 Q1 Q2 Q3
Output
330Ω LEDs
Q3
Q2
Q1
Q0

Lab 3 – OR XOR Logic Gates 4

 Table 3-4a Table 3-4b
Complement Switch Open Complement Switch Closed
Inputs Outputs Inputs Outputs

D3 D2 D1 D0 Q3 Q2 Q1 Q0 D3 D2 D1 D0 Q3 Q2 Q1 Q0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 0

0 0 1 1 0 0 1 1

0 1 0 0 0 1 0 0

0 1 0 1 0 1 0 1

0 1 1 0 0 1 1 0

0 1 1 1 0 1 1 1

1 0 0 0 1 0 0 0

1 0 0 1 1 0 0 1

1 0 1 0 1 0 1 0

1 0 1 1 1 0 1 1

1 1 0 0 1 1 0 0

1 1 0 1 1 1 0 1

1 1 1 0 1 1 1 0

1 1 1 1 1 1 1 1

Conclusion:

Lab 3 – OR XOR Logic Gates 5

Use the following diagrams to wire your circuits:

Lab 3 – OR XOR Logic Gates 6