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Trench angle: a key design factor for a deep trench superjunction MOSFET
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2015 Semicond. Sci. Technol. 30 125008
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Semiconductor Science and Technology
Semicond. Sci. Technol. 30 (2015) 125008 (5pp) doi:10.1088/0268-1242/30/12/125008
Trench angle: a key design factor for a deep
trench superjunction MOSFET
Hyemin Kang, Jaegil Lee, Kwangwon Lee and Youngchul Choi
Department of Technology Development in Fairchild Semiconductor Incorporation, Kyunggi-Do 420-711,
Korea
Received 30 June 2015, revised 4 October 2015
Accepted for publication 7 October 2015
Published 30 October 2015
Abstract
Why is the development of a deep trench superjunction (SJ) MOSFET above 600 V and under
8.0 mohm·cm2 difficult? A deep trench SJ MOSFET is expected to have a low turn-on
resistance because the post thermal process after the epitaxial process, which is normally used in
a multi-step epitaxy structure, is unnecessary. When designing a deep trench SJ MOSFET, the
trench angle is the most important factor because this determines the breakdown voltage (BV)
and BV variations. In this paper, we investigated how the trench angle affects the BV and BV
window as a condition of the possible thermal process. By employing a physical concept,
ΔCharge, we explained why the maximum BV is decreased and the BV window is increased as
the trench angle decreases. Also, we systematically scrutinized the transition of the vertical
electric field by varying the trench angle. Furthermore, in a real case, the principle of the trench
angle which contributes to the deviation of the charge imbalance and specific resistance of SJ is
described. Finally, we discuss the challenge of SJ MOSFET development in the industry.
Keywords: superjunction, MOSFET, deep trench, simulation
(Some figures may appear in colour only in the online journal)
1. Introduction as technology is evolving, the deep trench SJ MOSFET is
increasingly crucial.
SJ MOSFET is a type of power MOSFET employing p-type To realize a deep trench SJ MOSFET above 600 V and
and n-type vertical pillars. Due to its low on-resistance and under 8.0 mohm·cm2, it needs deep trenches over 50 um. The
high avalanche breakdown voltage [1, 2], SJ MOSFET has trench should be filled with void-free epitaxial growth silicon
been a commercially attractive candidate for high-voltage [13]. For this reason, the design of a trench MOSFET must
applications. To date, major companies have been developing consider real variations of the process. Recently, some papers
two types of SJ MOSFETs, multi-step epitaxy [3–5] and deep describing a deep trench SJ MOSFET above 600 V were pre-
trench [6–11]. In particular, the deep trench SJ concept has sented [9–11]. However, these reports did not cover the spe-
the potential for optimizing specific resistance by the benefit cific design factors which have a significant impact on the
of a simple process compared to the multi-step epitaxial device’s BV and BV window. The BV window is one of the
process. Concretely, the multi-step epitaxial method requires most important values because it represents the feasibility of
money and a time-consuming repetitive process: epitaxial the device for industry and directly affects the yield of wafer if
growth–photolithography—ion implantation. Also, the struc- the process variations cannot be controlled within the window.
ture must suffer a high temperature pillar drive-in process to In this paper, we investigate how the trench angle affects the
form vertical p-n pillars by compensating a large amount of peak BV by employing a quantitative concept. Also, we
initial ions [12]. However, the deep trench process requires compared the windows of BV at high and low trench angle and
only one trench etch and epitaxial fill on the trench in an ideal find the results with physical calculations. Furthermore, the
case by minimizing the additional thermal process. Therefore, technological importance of trench angle will be discussed.
0268-1242/15/125008+05$33.00 1 © 2015 IOP Publishing Ltd Printed in the UK
Semicond. Sci. Technol. 30 (2015) 125008 H Kang et al
Figure 2. Simulation result of deep trench SJ MOSFET (a) Drain
voltage—drain current at 10 V of gate voltage (Turn-on); (b) Drain
voltage—drain current at 0 V of gate voltage (Turn-off).
determine intrinsic carrier density by bandgap narrowing of
silicon, a Slotboom model is employed. In the mobility
modeling, mobility degradation due to doping concentration
is considered. A Shockley–Read–Hall (SRH) and Quasi-
Fermi model are used to apply doping and temperature
dependency on recombination at the avalanche breakdown.
The number of the unit cell (area factor), figure 1(b), in the
simulation is set to 7E5. Rsp (Specific resistance) and BV are
measured at 10 A and 1 mA each.
Figure 1. The configuration of a deep trench SJ MOSFET (balance 3. Results and discussions
point fixed on H/2 at any angle).
3.1. Trade-off between the BV and BV window
After finishing the process simulations, the final remaining
2. Device simulation concentration of ion in both pillars is 5E15 cm−3. The thermal
quantity (1100 °C–120 min) used in the process simulation
The structure and device simulation of a deep trench SJ compensated half of the initial ions. The simulation result of
MOSFET is carried out by using a sentaurus work bench drain voltage–drain current at turn-on and turn-off is shown in
(SWB) provided by Synopsys Inc. After growing 55 um figure 2. The turn-on current has the same value for different
n-type epitaxial silicon on highly n-doped silicon substrate trench angles with specific resistance 7.4 mohm·cm2.
(100), trench etching is carried out. The depth of the trench However, as the trench angle decreases from 89.9° to 89.6°,
(length of pillar) is 50 um by changing the angles of the trench the peak voltage also decreased from 691 V to 627 V. The BV
from 89.9° to 89.6°. Cell pitch (CP) is fixed 8 um. The width variation due to charge imbalance is presented in the
of the positive (p) and negative (n) pillar is half of the CP at figure 3(a). The charge imbalance is given by following
H/2 (25 um) as shown in figure 1(a). Therefore, the charge equation (1)
balance point is fixed at the middle of pillar (25 um) at any
angle. The initial concentration of each pillar is the same, Np Np - Nn
Charge Imbalance (%) = ´ 100 (1 )
(positive ion concentration of p-pillar)=Nn (negative ion Np
concentration of n-pillar)= N=1E16 cm−3. The total ther-
mal budget, 1100 °C–120 min, is distributed to oxidation and
diffusion to form the top structure of the MOSFET. The The capability of the charge imbalance (BV window)
inclusion of the thermal amount is to simulate the condition as above 600 V is increased from ±2.4% (89.9°) to ±2.8%
an actual device. The gate structure is a trench gate that is (89.6°). If we simulate the structure for 89.5°, the curvature of
always feasible for a narrow cell pitch structure. BV variation is flatter compared to the higher trench angle,
The process simulation is carried out based on the but the peak value cannot exceed 600 V. To understand the
‘Advanced Calibration’, which has parameters of process that effect of the trench angle, we introduce a concept of
Synopsis selected as standard. On the device simulation, to ΔCharge. ΔCharge is the difference between the amount of
2
Semicond. Sci. Technol. 30 (2015) 125008 H Kang et al
length, L in figure 1(a), of the pillar, is 1 um and, therefore,
the term of length is removed in equation (2))
We replace W with a form of trench angle, the final
equation will be as follows: (equation (3))
N*W*H NH H
D Charge = = ´ (3 )
2 2 2 tan q
Since the balance point of the SJ is fixed at H/2 and the
trapezoidal volume of the upper part of the p-pillar is larger
than the n-pillar, the upper part will be positive rich and the
lower part negative rich. Also, the absolute amount of
ΔCharge in both the upper and lower part is the same.
According to equation (3), as the trench angle decreases,
ΔCharge will be increased. To put it another way, with a low
trench angle, the Vp of the upper part and Vn of the lower part
will be larger than the high angle. Therefore, higher ΔCharge
means that the charge imbalance is more severe both up and
down the pillar.
In order to understand the role of ΔCharge in more
depth, the vertical electric field profiles are presented in
figures 3(b) and (c). The extracted position of the electric field
is CP/2 as shown in the inset of figures 3(b) and (c). As the
trench angle decreases from 89.9° to 89.6° (increase of
ΔCharge), the bending of the electric field is increased at 0%.
Since the area under the electric field is the voltage of the SJ,
a more curved profile of electric field has a lower BV. In this
connection, the charge imbalance of the upper and lower part
of the pillar is larger, and larger with the increment of
ΔCharge, and finally has lower BV. (It should be noted that
Figure 3. Simulation result of a deep trench SJ MOSFET (a) the center point, H/2, is always balanced) Thus, ΔCharge,
relationship between the trench angle and BV, BV window; Profiles which is determined by the trench angle, decides the value
of electric field shift when the charge is imbalanced at (b) 89.9° and of BV.
(c) 89.6°. To explain relationship between the trench angle and BV
window, the imbalanced profiles of the electric field by
0∼6% at CP/2 are presented in figure 3. When we add 3%
ions in the p-pillar and the n-pillar. More specifically, the
of positive ions on p-pillars, the electric field moves down-
amount of positive ions from the middle (H/2) to the top of
wards of the pillar. In detail, 3% of the positive rich condition
the pillar will be the multiplication of Np (concentration of
needs an additional 3% of negative charge or has to reduce
positive ion) and Vp (volume of p-pillar). On the contrary to
3% of positive ions to meet the charge balance. In the trench
this, the amount of negative ions is the multiplication of Nn
SJ case, the lateral length of the p-pillar should be reduced if
(concentration of negative ion) and Vn (volume of n-pillar).
the concentration of the n-pillar is fixed. To meet this con-
Therefore, the ΔCharge can be represented by the following
dition, the charge balance point must move down from the
equation (2)
center. Therefore, the charge balance point will be the posi-
DCharge = N p ´ V p - N n ´ V n tion where the multiplications of concentration and lateral
length of the pillar are the same for both sides as shown in
= N (V p - V n )
equation (4).
{ H
= N (C P + W) - (C P - W)
4
H
4 } N p (1 imbalanced %) ´
⎛ CP
⎜
⎞
w⎟
N*W*H ⎝ 2 ⎠
= . (2 )
2 ⎛ CP ⎞
= Nn ´ ⎜ w⎟ (4 )
⎝ 2 ⎠
Where W is width change of the pillar at the top and bottom
due to the trench angle as expressed in figure 1(a). (If the Where w is the deviation of the lateral pillar length from CP/
trench angle is 90°, W will be zero). For example, if the trench 2. (In the case of the positive rich, n-pillar length will be CP/
angle is smaller than 90°, the width of the p-pillar will be CP/ 2+w and p-pillar CP/2–w at balance point). If we replace w
2+W and n-pillar CP/2 – W. (It should be noted that the as the trench angle form, equation (4) will become as follows:
3
Semicond. Sci. Technol. 30 (2015) 125008 H Kang et al
Figure 4. Trench angle deviation in a real case of a deep trench SJ
MOSFET: (a) lower angle; (b) higher angle.
(equation (5))
⎛ CP h ⎞⎟
N p (1 imbalanced %) ´ ⎜
⎝ 2 2 tan q ⎠
⎛ CP h ⎟⎞
= Nn ´ ⎜ (5 )
⎝ 2 2 tan q ⎠
Where h is the deviation of vertical pillar length from CP/2.
(In the case of positive rich, the balance position is H/2 – h.) Figure 5. (a) Simulation result of the BV and specific resistance and
From equation (5), we are able to calculate the depth of the (b) profiles of the electric field with a swing of trench angle.
peak electric field when the charge imbalance is generated. As
shown in figures 3(b) and (c), when the trench angle is
relatively high, the location of the peak field is more inclined specific resistances (mohm·cm2) are linearly decreased with
to bottom at the same % of charge imbalance. When the the decreasing trench angle, 7.67 (89.9°), 7.56 (89.8°), 7.43
electric field leans in the direction of bottom, the trapezoidal (89.7°), 7.33 (89.6°), and 7.24 (89.5°). If the trench angle is
area of the field becomes smaller. Decrement of the area of deviated to 89.6° from 89.7°, the colored area of figure 4(a) is
field means a drop of BV. For this reason, the high-angle added to the n-pillar. At the same time, the p-pillar is
trench SJ MOSFET is able to secure high voltage, but cannot diminished as the colored area shows. In other words, there is
sustain wide BV variation. It is a definite trade-off between a double effect of charge imbalance because the n-pillar gains
the BV and BV window. negative ions and the p-pillar loses positive ions simulta-
neously. With this principle, the lower trench angle, 89.6° and
89.5°, is imbalanced to a negative rich condition and the
3.2. Window of the trench angle
electric field is inclined to the top of SJ as shown in
When we realize a deep trench 600 V SJ MOSFET, we could figure 5(b). (The electric field is measured at CP/2 as shown
simply think the window of the trench angle is 0.4° in the inset of figure 5(b)). Inversely, a higher trench angle,
(89.9°∼89.6°) from the above data. However, it is the case 89.8° and 89.9°, has a positive rich condition and the peak of
of when we fixed the width of the pillar as CP/2 at the middle the electric field moves down to the bottom of SJ. By
of the trench. In a real case, we should fix the mesa width as extension, this double effect finally confines the available
(CP/2—W) of the top region before etching the trench. If window of the trench angle within ±0.1°. This tight angle
there is any trench angle deviation (θ±α), the final shape of margin is a reason why the trench SJ MOSFET is difficult to
SJ will be similar to figure 4. If we select the trench angle as be realized. The deviation of specific resistance on the con-
89.7° (BV: 662 V, BV window: ±2.7%), the mesa width will dition of the fixed mesa width is due to the change of the
be 3.869 um (CP/2—W). With a fixed mesa with 3.869 um, n-pillar’s area. A higher angle structure, 89.8° and 89.9°, will
the trench angle changed by ±0.2°. As shown in figure 5(a), lose the colored area of the n-pillar as shown in figure 4(b)
the BV of each trench angle has 496 V (89.9°), 619 V (89.8°), and the lower angle, 89.6° and 89.5°, is the opposite. The area
662 V (89.7°), 610 V (89.6°), and 514 V (89.5°). Also, of the n-pillar directly contributes to the resistance of the
4
Semicond. Sci. Technol. 30 (2015) 125008 H Kang et al
device and, therefore, the resistance to the trench angle stems superjunction MOSFET Proc. ISPSD’04. 16th Int. Symp.
from the area of the deviated n-pillar. 459–62
[5] Onishi Y, Iwamoto S, Nagaoka T and Ueno K 2002 24 mΩcm2
680 V Silicon Superjunction MOSFET Proc. Int. Symp.
Power Semicond. Devices 241–4
4. Conclusions [6] Hattori Y, Nakashima K, Kuwahara M, Yoshida T,
Yamauchi S and Yamaguchi H 2004 Design of a 200 V
This paper focuses on the deep trench SJ MOSFET behavior super junction MOSFET with n-buffer regions and its
when the trench angle is varied. With a fixed balance at the fabrication by trench filling Power Semicond. Devices ICs,
2004. Proc. ISPSD ’04. 16th Int. Symp. 189–92
middle of the pillar, as the trench angle decreases, the max- [7] Yamauchi S, Hattori Y and Yamaguchi H 2003 Electrical
imum BV decreased, but the BV window increased. The properties of super junction p-n diodes fabricated by trench
decrement BV is attributed to the large amount of ΔCharge. filling Power Semicond. Devices ICs, 2003. Proc. ISPSD’03.
A highly imbalanced condition of the upper and lower part of IEEE 15th Int. Symp. 207–10
the pillar, large ΔCharge, facilitates the electric field dis- [8] Strollo a G M and Napoli E 2001 Optimal ON-resistance
versus breakdown voltage tradeoff in superjunction power
tribution to be more uniform. As a result, a low trench angle is devices: a novel analytical model IEEE Trans. Electron
able to possess wider BV window. In real case, mesa width Devices 48 2161–7
should be fixed before the process of trench etching. On this, [9] Saito W, Omura I, Aida S, Koduki S, Izumisawa M,
deviation of trench angle produces a relative imbalance of Yoshioka H, Okumura H, Yamaguchi M and Ogura T 2006
both pillars. This deviation of trench angle finally results in A 15.5mΩcm2-680V superjunction MOSFET reduced on-
resistance by lateral pitch narrowing 2006 IEEE Int. Symp.
the margin of angle ±1° due to the double effect of charge Power Semicond. Devices IC’s 18–21
imbalance. Also, area deviation originating from trench [10] Zehong L, Min R, Bo Z, Jun M, Tao H, Shuai Z, Fei W and
angle variation is attributed to the change of specific Jian C 2010 Above 700 V superjunction MOSFETs
resistance. fabricated by deep trench etching and epitaxial growth
J. Semicond 31 084002
[11] Sakakibara J, Noda Y, Shibata T, Nogami S, Yamaoka T and
Yamaguchi H 2008 600V-class super junction MOSFET
References with high aspect ratio P/N columns structure Power
Semicond. Devices ICs, 2008. ISPSD’08. 20th Int. Symp.
299–302
[1] Fujihira T 1997 Theory of semiconductor superjunction [12] Rochefort C, Dalen R Van, Duhayon N and Vandervorst W
devices Japan. J. Appl. Phys. 36 6254–62 2002 Manufacturing of high aspect-ratio p-n junctions using
[2] Nassif-Khalil S G, Hou L Z and Salama C a T 2004 Sj/Resurf vapor phase doping for application in multi-resurf devices
Ldmost IEEE Trans. Electron Devices 51 1185–91 Proc. 14th Int. Symp. Power Semicond. Devices Ics 2
[3] Deboy G, Marz N, Stengl J-P, Strack H, Tihanyi J and 237–40
Weber H 1998 A new generation of high voltage MOSFETs [13] Sugi A, Takei M, Takahashi K, Yajima A, Tomizawa H and
breaks the limit line of silicon Int. Electron Devices Meeting Nakazawa H 2008 Super junction MOSFETs above 600V
Tech. Dig. 683–5 with parallel gate structure fabricated by deep trench etching
[4] Saito W, Omura I, Aida S, Koduki S, Izumisawa M, and epitaxial growth Proc. Int. Symp. Power Semicond.
Yoshioka H and Ogura T 2004 A 20 mΩcm 600 V-class Devices ICs 165–8