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Lab 1: Combinational Logic Design: A. Objectives

This lab manual summarizes experiments on combinational logic design. Students will analyze and implement combinational circuits using truth tables and canonical forms. They will reduce circuits to their minimal forms using AND, OR and NOT gates. Additionally, students will convert any logic gates to equivalent NAND gate circuits to learn about universal gates. The experiments aim to familiarize students with basic digital logic design and analysis techniques.

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97 views

Lab 1: Combinational Logic Design: A. Objectives

This lab manual summarizes experiments on combinational logic design. Students will analyze and implement combinational circuits using truth tables and canonical forms. They will reduce circuits to their minimal forms using AND, OR and NOT gates. Additionally, students will convert any logic gates to equivalent NAND gate circuits to learn about universal gates. The experiments aim to familiarize students with basic digital logic design and analysis techniques.

Uploaded by

Simon Elysium
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Department of Electrical & Computer Engineering ECE211L Lab Manual for EEE211 / ETE211 / CSE231

Lab 1: Combinational Logic Design


A. Objectives

 Familiarize with the analysis of combinational logic network.


 Learn the implementation of networks using the two canonical forms.
 Devise combinational circuits using universal logic.
 Acquaint with basic binary arithmetic circuits –the half and full adders.

B. Theory
Concise theory pertinent to lab experiments to go here to aid students in performing experiments with
minimal supervision
For example, topics for this lab should include definition and steps to:

Analysis of combinational logic design


Min terms and max terms
Canonical Forms
Universal gates – bubble pushing, De Morgan’s theorem

C. Experiment 1: Analysis of a Combinational Logic Circuit


C.1. Apparatus

 Trainer Board
 1 x IC 7411 Triple 3-input AND gates
 1 x IC 7432 Quadruple 2-input OR gates
 1 x IC 7404 Hex Inverters (NOT gates)

C.2. Procedure

Input
𝑨𝑩𝑪 𝑭 Min term Max term
Reference
0 000 0

1 001 1

2 010 1

3 011 0

4 100 0

5 101 0

6 110 1

7 111 0
Table C.1 Truth table to a combinational circuit

1. Write down all the min terms and max terms of three inputs 𝐴𝐵𝐶 in Table C.1.
st nd
2. Write down the function 𝐹 in 1 and 2 Canonical Forms in Table C.2.

Shorthand Notation Function


st
1 Canonical
𝐹=Σ 𝐹=
Form
nd
2 Canonical
𝐹=Π 𝐹=
Form
st nd
Table C.2 1 and 2 canonical forms of the combinational circuit of Table C.1

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Department of Electrical & Computer Engineering ECE211L Lab Manual for EEE211 / ETE211 / CSE231

3. Draw the circuits in the space provided below, clearly indicating the pin numbers corresponding to the
relevant ICs.
st
1 Canonical Form

nd
2 Canonical Form

st nd
Figure C.1 1 and 2 canonical circuit diagrams of the combinational circuit of Table C.1
st
4. Construct the 1 canonical form of the circuit and test it with the truth table.
i. Connect one min term at a time and check its output.
ii. Once all min terms have been connected and verified, OR the min terms for the function output.

C.3. Report

Additional report questions/simulations to go here

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Department of Electrical & Computer Engineering ECE211L Lab Manual for EEE211 / ETE211 / CSE231

D. Experiment 2: Universal Gates


D.1. Apparatus

 Trainer Board
 IC 7400 Quadruple 2-input NAND gates

D.2. Procedure

Figure 0.1 A combinational circuit

1. Complete the truth table for the circuit of Figure 0.1 in Table 0.1.

𝑿𝒀𝒁 𝑰𝟏 = 𝑨𝑪 𝑰𝟏 = 𝑩𝑪′ 𝑭
000

001

010

011

100

101

110

111
Table 0.1 Truth table of the combination circuit of Figure 0.1

2. Use the space provided below, showing the steps involved, to convert the circuit of Figure 0.1 to a
universal (NAND) gate circuit. Convert the inverter to a NAND equivalent as well.
3. Label the pin numbers of the appropriate ICs in step 2 of Figure 0.2.
4. Construct the universal gate circuit in Figure 0.2, checking the output of each NAND gate independently
before connecting the entire circuit together.
5. Validate the universal gate circuit using Table 0.1.

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Department of Electrical & Computer Engineering ECE211L Lab Manual for EEE211 / ETE211 / CSE231

Step 1

Step 2

Figure 0.2 Universal (NAND) gate implementation of the circuit of Figure 0.2

ECE.211L 11June 2015

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