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CS8382 Digital Lab 2017

The document provides a lecture plan for a Digital Systems Laboratory course. It includes objectives like understanding logic gates and designing combinational and sequential circuits. Assessment methods are internal tests, mini-projects, and end semester exams. The lecture plan lists 18 topics to be covered across the semester, including basic gates, adders, subtractors, MSI devices, registers, counters, and HDL coding. Students will learn to implement combinational and sequential circuits using gates and HDL and complete a mini temperature monitoring project. The outcomes are implementing circuits using gates and MSI devices, and simulating circuits using HDL.

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94 views3 pages

CS8382 Digital Lab 2017

The document provides a lecture plan for a Digital Systems Laboratory course. It includes objectives like understanding logic gates and designing combinational and sequential circuits. Assessment methods are internal tests, mini-projects, and end semester exams. The lecture plan lists 18 topics to be covered across the semester, including basic gates, adders, subtractors, MSI devices, registers, counters, and HDL coding. Students will learn to implement combinational and sequential circuits using gates and HDL and complete a mini temperature monitoring project. The outcomes are implementing circuits using gates and MSI devices, and simulating circuits using HDL.

Uploaded by

addssdfa
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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ANAND INSTITUTE OF HIGHER TECHNOLOGY

KAZHIPATTUR – 603 103

Department of Computer Science and Engineering

Academic Year: 2019-20 (Odd Semester)

Lecture Plan

Course Code & Title: CS8382 & Digital Systems Laboratory

Semester & Branch: III Semester B.E. Computer Science and Engineering/B Section

Name of the Faculty member: K. Rejini

Designation & Department: Assistant Professor & CSE

OBJECTIVES:

To understand the various basic logic gates

 To design and implement the various combinational circuits


 To design and implement combinational circuits using MSI devices
 To design and implement sequential circuits
 To understand and code with HDL programming

ASSESSMENT METHODS FOLLOWED:

 1.Internal Tests (Model Lab Exam) are conducted to assess continuous learning

 2.Mini project are given to improve the Experimental learning.

 3.End Semester Examination is conducted to assess overall learning by students.


Lecture Date Topic(s) to be covered Teaching aids
No. (Demo/ LCD)

Cycle 1

1 Introduction LCD
Verification of Boolean Theorems using Demo
2
basic gates.
Verification of Boolean Theorems using Demo
3
basic gates.
4 Design and implement Half/Full Adder Demo

Design and implement Half/Full Demo


5
Subtractor
Design and implementation of
6 combinational circuits using basic gates Demo
for arbitrary functions
Design and implementation of
7 combinational circuits using basic gates Demo
for arbitrary code converters
8 Model lab1
Design and implement combinational
circuits using MSI devices: 4 – bit binary Demo
9
adder

Design and implement combinational


circuits using MSI devices: 4 – bit binary Demo
10
subtractor

Parity generator / checker Demo

Magnitude Comparator Demo


11
Application using multiplexers
12 Demo

13 Design and implement shift-registers Demo

Design and implement synchronous


14 counters. Demo

Design and implement asynchronous


15 counters. Demo

Coding combinational circuits using


16 HDL. LCD

17 Coding sequential circuits using HDL. LCD

Design and implementation of a simple LCD


18
digital system (Mini Project).
Experiential
Mini project - TEMPERATURE
19 Learning
OUTCOMES:

Upon Completion of the course, the students will be able to:


 Implement simplified combinational circuits using basic logic gates
 Combinational circuits using MSI devices
 Implement sequential circuits like registers and counters
 Simulate combinational and sequential circuits using HDL

Prepared by: Approved by:

K. Rejini Dr.S.Roselin Mary

(Name & Signature of Faculty member) (Name & Signature of HOD)

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