Eastern Mediterranean University
27/10/2017
Department of Electrical and Electronic Engineering
HOMEWORK II DUE: 02 November 2017
1. Identify each of these logic gates by name, and complete their respective truth tables:
x F x F x F
y y y
Name: Name: Name:
x y F x y F x y F
x F x F x F
y y
Name: Name: Name:
x y F x y F x F
x F x F x F
y y y
Name: Name: Name:
x y F x y F x y F
(10 pts)
EENG/INFE115 1 |Page
Eastern Mediterranean University
27/10/2017
Department of Electrical and Electronic Engineering
2. Use algebraic manipulation to simplify the following expression:
F(A,B,C) = A’ + ABC + A(B⊕C) + AB’C’
(10 pts)
3. Convert the following logic gate circuit into a Boolean expression. Write Boolean sub-
expression next to each gate.
x
t1
t2 t4 F
z
t3
(10 pts)
4. Use DeMorgan’s Theorems to simplify the following expressions:
F = (B’D) (A’ + C’D) + (BC’+D’A)
(5 pts)
5. Without simplification, write the expressions for F(dual) and F’(complement) corresponding
to the Boolean function:
F = A + 0.B’(C’+1.D)
(5 pts)
6. A Boolean function F defined on the three input variables x, y and z is 1 if and only if number
of 1(one) input is even. (e.g., F is 1 if x = 1, y = 0, z = 1). Draw the truth table for the above
functions and express it in canonical sum-of-products and product-of-sums form.
(10 pts)
7. Draw the logic diagram for the following Boolean expression
F = x’z + x (y+z)
(10 pts)
8. Obtain the truth table of the following functions, and express each function in sum‐of‐
minterms and product‐of‐maxterms form:
bd’ + acd’ + ab’c + a’c’
(10 pts)
EENG/INFE115 2 |Page
Eastern Mediterranean University
27/10/2017
Department of Electrical and Electronic Engineering
9. For the Boolean function
F = xy’z + x’y’z + w’xy + wx’y + wxy
a. Obtain the truth table of F.
b. Draw the logic diagram, using the original Boolean expression.
c. Use Boolean algebra to simplify the function to a minimum number of literals.
d. Obtain the truth table of the function from the simplified expression and show that
it is the same as the one in part (a).
e. Draw the logic diagram from the simplified expression, and compare the total
number of gates with the diagram of part (b).
(25 pts)
10. Convert the following to the other canonical form:
a. F (x,y,z) = ∑ (2,3,5,6)
b. F (x,y,z) = ∏ (0,2,4,5,7)
(5 pts)
EENG/INFE115 3 |Page