Simple 8-bit RISC Microprocessor

 Objective and Specifications

— Design a Simple 8-bit RISC microprocessor

— Separate carry, zero and sign flag register

— Direct and memory data

— Two ports for data

— Clock frequency – 50 MHz

— Instruction sets on the next slide

— Create testing environment for the project and verify the behavior.

— Create test benches for the individual hierarchical modules to verify their behavior as
well.
  Instruction set for the microprocessor:

Opcode Mnemonics Operation

00 11dd dddd dddd mov Write to port

01 0000 dddd dddd or (rA) Logical OR (direct data)

01 0001 dddd dddd and (rA) Logical AND (direct data)

01 0010 dddd dddd inv (rA) Logical NOT (direct data)

01 0100 dddd dddd add (rA),(rB) Addition (direct data)

01 0110 dddd dddd sub (rA),(rB) Subtraction (direct data)

01 1100 dddd dddd ls (rA) Shift left (direct data)

01 1101 dddd dddd rs (rA) Shift Right (direct data)

11 0000 mmmm mmmm or (rA) Logical OR (memory data)

11 0001 mmmm mmmm and (rA) Logical AND (memory data)

11 0010 mmmm mmmm inv (rA) Logical NOT (memory data)

11 0100 mmmm mmmm add (rA),(rB) Addition (memory data)

11 0110 mmmm mmmm sub (rA),(rB) Subtraction (memory data)

11 1100 mmmm mmmm ls (rA) Shift left (memory data)

11 1101 mmmm mmmm rs (rA) Shift Right (memory data)

 Simple 8-bit RISC microprocessor

— A microprocessor comprises ‘timing and control’ , a datapath and memory.

data_out

data_in datapath control memory

status status

timing_control

microprocessor
microprocessor
memory 8 AL datapath
Instruc Data
tion registe U 8
8
memor rs
rs y Status
t registe
cl
rs
k
Instruct
Progra ion timing & control
m decode
counte FSM
r
r
  Instruction set for the microprocessor:

— Instruction set is the blue print of what operations the microprocessor can perform.

— The Data path design largely depends on these instruction set.

— Later, after the microprocessor has been implemented, the programmer can use this
instruction set to develop the program to carry out particular routines.

— The program is stored in the instruction memory from where the microprocessor can
read the instructions one by one.

 Datapath

— Datapath is the computational block.

— It generally comprises arithmetic and logic unit, data multiplexers and accumulator
registers.

— A microprocessor in general, has a data bus and an address bus

in order to minimize/share resources (sometimes, it can be just

a single bus time-multiplexed to carry data as well as address).

— Starting with a preliminary level, buses are not included in the project (project -3).

— Candidates who have completed Project -3 may be asked to upgrade their existing
design to include data and address buses.

— Shifter does the Shifting operation (this could be part of ALU).

— ‘direct’ is 8 bit direct data from the port.

— ‘mem’ is 8 bit data from the memory (RAM).

— ‘regA’ is the accumulator that acts as both, data latch for the operand 1 as well as for
storing the result (acc_out)

— ‘regB’ stores data for operand 2.

— ALU carries out all the arithmetic and logic operations depending on the control signal
‘opr’.

— The mux are the data multiplexers for the selection of appropriate data (either from the
port, memory or Shifter etc.)

— The select lines of MUX are controlled through the control FSM.

 Memory

— Though memory module could have variety of topologies, for our project, we will be
very specific.

— Memory comprises instruction memory, general purpose memory .

— Data registers and status register(s) constitute the general purpose memory.

— Instruction memory is implemented as a ROM.

— General purpose memory is the part of the datapath.

— Starting with a preliminary level design, buses are not included in the project (project
-3).
 — Candidates who have completed Project -3 may be asked to upgrade their existing
design to include data and address buses.

 Control FSM

Execute: