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A Hardware Description Language

Hardware description languages (HDLs) allow digital circuits to be described in a textual format resembling a programming language. HDLs can represent logic diagrams, truth tables, and complex hardware behaviors. The two main HDL standards are VHDL and Verilog. HDLs capture characteristics of digital circuits like entities, connectivity, concurrency, timing, and propagation delays. HDLs are used for formal documentation, simulation, and synthesis into integrated circuits.

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69 views

A Hardware Description Language

Hardware description languages (HDLs) allow digital circuits to be described in a textual format resembling a programming language. HDLs can represent logic diagrams, truth tables, and complex hardware behaviors. The two main HDL standards are VHDL and Verilog. HDLs capture characteristics of digital circuits like entities, connectivity, concurrency, timing, and propagation delays. HDLs are used for formal documentation, simulation, and synthesis into integrated circuits.

Uploaded by

sameer khan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Question No 1: You are required to discuss the basic concept of

hardware description language in your words.

Hardware description language


A hardware description language (HDL) is a computer-based language that describes
the hardware of digital systems in a textual form.

It resembles an ordinary computer programming language, such as C, but is specifically


oriented to describing hardware structures and the behavior of logic circuits. It can be
used to represent logic diagrams, truth tables, Boolean expressions, and complex
abstractions of the behavior of a digital system.

Design entry creates an HDL-based description of the functionality that is to be


implemented in hardware. Depending on the HDL, the description can be in a variety of
forms: Boolean logic equations, truth tables, a net list of interconnected gates, or an
abstract behavioral model.

In the public domain, there are two standard HDLs that are supported by the IEEE:
VHDL and Verilog.

VHDL and Verilog

Syntax and ``appearance'' of the two languages are very different

Capabilities and scopes are quite similar

Both are industrial standards and are supported by most software tools

VHDL:
VHDL is a Department of Defense–mandated language. (The V in VHDLstands for the
first letter in VHSIC, an acronym for very high-speed integrated circuit.)

Initially sponsored by Department of Defense as a hardware documentation standard in


early 80s

Transferred to IEEE and ratified it as IEEE standard 1176 in 1987 (known as VHDL-87)

Major modification in ’93 (known as VHDL-93)

Revised continuously

Verilog:
Verilog began as a proprietary HDL of Cadence Design Systems, but Cadence
transferred control of Verilog to a consortium of companies and universities known as
Open Verilog International (OVI) as a step leading to its adoption as an IEEE standard.

HDL is a
• Characteristics of digital hardware

Connections of parts
Concurrent operations
Concept of propagation delay and timing

• Characteristics cannot be captured by traditional PLs

• Require new languages: HDL

Use of an HDL program


• Formal documentation

• Input to a simulator

• Input to a synthesizer

Modern HDL
• Capture characteristics of a digital circuit:

– entity

– connectivity

– concurrency

– timing

• Cover description

– in Gate level and RT level

– In structural view and behavioral view

Highlights of modern HDL:


– Encapsulate the concepts of entity, connectivity, concurrency, and timing
– Incorporate propagation delay and timing information

– Consist of constructs for structural implementation

– Incorporate constructs for behavioral description (sequential execution of


traditional PL)

– Describe the operations and structures in gate level and RT level.

– Consist of constructs to support hierarchical design process

There are applications of HDL processing:


Logic simulation:

Logic simulation displays the behavior of a digital system through the use of a
computer. A simulator interprets the HDL description and either produces readable
output, such as a time-ordered sequence of input and output signal values, or displays
waveforms of the signals.

The stimulus (i.e., the logic values of the inputs to a circuit) that tests the functionality of
the design is called a test bench.

Logic synthesis:

Logic synthesis is the process of deriving a list of physical components and their
interconnections (called a net list) from the model of a digital system described in an
HDL. The netlist can be used to fabricate an integrated circuit or to lay out a printed
circuit board with the hardware counterparts of the gates in the list.

Timing verification confirms that the fabricated, integrated circuit will operate at a
specified speed. Because each logic gate in a circuit has a propagation delay, a signal
transition at the input of a circuit cannot immediately cause a change in the logic value
of the output of a circuit. Propagation delays ultimately limit the speed at which a circuit
can operate. Timing verification checks each signal path to verify that it is not
compromised by propagation delay. This step is done after logic synthesis specifies the
actual devices that will compose a circuit.

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