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Seven level asymmetric cascade inverter with

space vector PWM added PR control

Conference Paper · September 2016

DOI: 10.1109/EPEPEMC.2016.7751997

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 Seven Level Asymmetric Cascade Inverter with
Space Vector PWM Added PR Control
Ilhami COLAK Ersan KABALCI Gokhan KEVEN
Faculty of Engineering and Faculty of Engineering & Vocational College of Hacı Bektaş
Architecture, Department of Architecture, Department of Veli, Department of Biomedical
Electrical & Electronic Engineering Electrical & Electronic Engineering Equipment Technology
İstanbul Gelişim University Nevsehir Hacı Bektaş Veli Nevsehir Hacı Bektaş Veli
İstanbul, Turkey University University
[email protected] Nevsehir, Turkey Nevsehir, Turkey
[email protected] [email protected]

Abstract-Inverters are used to convert the DC energy to AC

energy for renewable energy conversation or high power
industrial applications. Asymmetric inverters are preferred
about their some advantages. Nowadays, control of inverters is
achieved lots of pals with modulation (PWM) techniques. Space
vector control is one of them. Seven level asymmetric cascade
inverter is achieved with space vector PWM (SVPWM) added
proportional resonant (PR) control in this study. The PR control
is used for reducing the lower number harmonics. General
SVPWM techniques use position of a vector in αβ frame.
Calculation of switching states becomes more complex when the
level of inverter is increased. In this study, switching states is
achieved with ceil and floor operations by using reference
signals in 600 degree coordinate system. Switching signal is
generated depends on output levels of inverter. This process is
mitigated calculations in SVPWM. Also adding PR control to
system decreases the total harmonic distortion (THD) of Fig. 1. Cascade MLIs categories (a) symmetric MLIs, (b) asymmetric MLIs
inverter.
I. INTRODUCTION Voltage control and current control are two different ways
of controlling the inverters. Common current control
In recent years, multilevel inverters (MLIs) are being used techniques are proportional integral, PR control, repetitive
more often in medium voltage and high power industrial controller, predictive control, dead beat and hysteresis control
applications. MLIs have some advantages about common as depicted in Fig. 2. [11-14]
mode voltage, dv/dt ratio and THD. There are three different
topologies of MLIs such as the diode-clamped, the flying
capacitor and the cascaded H-bridge. The cascaded MLIs are
classified into two categories that are symmetric and
asymmetric topologies depending on dc-link voltage ratio of
cells. The sources of symmetric MLIs are supplied at the
equal amplitudes while that of asymmetric cascade MLIs
(ACMLIs) are at different amplitudes as shown in Fig. 1.
Two types of ACMLIs are configured either in binary where
the ratio of cells is increasing the power of two as V, 2V, 4V
or in trinary that ratio of cells is increasing the power of three
as V, 3V, 9V. ACMLIs are needed less number of switching
components when compared other types of MLIs. [1-5]
There are many switching techniques improved for MLIs
such as SVPWM, multicarrier PWM, selective harmonic Fig. 2. Current control methods
elimination and hybrid PWM. [1, 5-7]. The most popular
technique is SVPWM for three phase MLIs [8]. SVPWM Seven-Level ACMLI (binary type) simulation is performed
technique can be implemented with digital signal processing, with SVPWM, adding PR control techniques in this paper.
and also implementation and optimization of switching SVPWM and PR control is explained in Section II while the
pattern is easy [9, 10]. simulation structures and results are given in Section III.
Discussion of results is mentioned in Section IV.

l-))) 
 II. SVPWM AND PR CONTROL In traditional SVPWM techniques the switching states is,
A. SVPWM produced in the following way for one phase. Positive peak
SVPWM technique is started to be used in the middle of value is during two sectors, negative peak value is during two
1980’s. It is digital modulation technique that generates sectors and passing from positive peak to negative peak and
switching states with sampling a reference vector. Reference passing from negative peak to positive peak is during two
vector is moving in αβ frame (900 coordinate system). This sectors.
coordinate system is divided into six parts, which are called
as sectors with 600 angle difference (15, 16).Input signals are
converted to αβ frame with Clarke transfer functions.
Traditional SVPWM uses αβ frame, but Wei et al. [17]
developed a new coordinate system using 600 degree
coordinate system. Equation (1), (2) and (3) show transfer
functions of Clarke transfer functions and Va, Vb, Vc are input
signals, Vα and Vβ are signals in αβ frame, Vref is amplitude of
reference signal and θ is angle of reference signal,
respectively.
⎛ 1 1 ⎞
1 − − ⎟ ⎛ Va ⎞
⎛ Vα ⎞ 2 ⎜ 2 2 ⎟ ⎜ ⎟
⎜ ⎟ = ×⎜ × Vb (1)
V
⎝ β ⎠ 3 ⎜0 3 3 ⎟ ⎜⎜ ⎟⎟
⎜ − V
⎟ ⎝ c⎠
⎝ 2 2 ⎠
Vref = V α 2 + V β 2 (2)
Vβ
θ = tan −1 (3)
Vα
Equation (4), (5) and (6) are used to transfer the reference
signals from αβ frame to 600 degree coordinate system. In
these equations, V is the normalization parameter of transfer
function, m is the modulation index, Vdc is total of input DC
sources and h is the level of inverter. Vx and Vy are the signals Fig. 4. Simulation diagram of degree coordinate system transfer block
in 600 degree coordinate system. Fig. 3 shows Vx and Vy in
600 degree coordinate system for first sector. Simulation
diagram and Vx and Vy signals are proposed in Fig. 4 and Fig
5, respectively.
Vref ⋅ m ⋅ ( h − 1)
V= (4)
Vdc
Vx = (V × cosθ ) − (V × sin θ / 3) (5)
V y = (V × cos(60 − θ )) − (V × sin(60 − θ ) / 3) (6)

Fig. 5. Vx and Vy signals and Sector numbers

Celanovic and Boroyevich [18] and Prats et al. [19]

performed SVPWM with ceil and floor operators. In this
paper, SVPWM performed with this suggestion and
additional to these switching states are generated with using
600 degree reference signals to calculating of inverters
outputs instead of calculating vector positions of reference
Fig. 3. Vx and Vy in 600 degree coordinate system signals. Calculations of SVPWM are reduced by this way.


 First of all, the output of inverter in each sector should be
known for the switching states of the calculation process.
Table 1 indicates the output of inverter sector by sector for
one phase. As shown in Table I, signals of phases trace a
sequence. The sequence is positive peak value at one sector,
passing from positive peak to negative peak at two sectors,
negative peak value at one sector and passing from negative
peak to positive peak at two sectors. For a seven level of
ACMLI the outputs are 3V, 2V, V, 0, -V, -2V and -3V while
input DC sources are V and 2V.
TABLE I
OUTPUTS OF INVERTER FOR EACH SECTOR
Phase A Phase B Phase C
Sector 1 3V -V, -2V -V, -2V
Sector 2 V, 2V V, 2V -3V
Sector 3 -V, -2V 3V -V, -2V
Sector 4 -3V V,2V V, 2V Fig. 7. Switching states of one phase
Sector 5 -V, -2V -V, -2V 3V
Sector 6 V, 2V -3V V, 2V TABLE II
CALCULATION OF SWITCHING STATES
The switching signals are generated with digital techniques Phase A Phase B Phase C
in SVPWM for driving the semi-conductors. Belong to this, Sector 1 Floor((xc+yc)/2) -Ceil(xc/3)-Ceil(yc/3)
we can operate normalized reference signals with ceil and Sector 2 -Floor((xf-yc)/3) Ceil(xc/3) -Ceil(yc/2)
Sector 3 -Ceil((xc-yc)/3) Ceil(xc/2) -Ceil(yc/3)
floor operators. Equation (7), (8), (9) and (10) shows ceil and Sector 4 -Floor((xc+yc)/2) Ceil(xc/3) Ceil(yc/3)
floor values of Vx and Vy signals. These are xc, xf, yc, yf, Sector 5 Floor((xf-yc)/3) -Ceil(xc/3) Ceil(yc/2)
respectively. Sector 6 Ceil((xc-yc)/3) -Ceil(xc/2) Ceil(yc/3)
Ceil operation rounds the number towards positive infinity
and floor operation rounds the number towards negative B. PR Control
infinity. Sector number and xc, yc, xf and yf signals are shown The PR control in this study is achieved in natural frame.
in Fig. 6. The value of xc and yc are integer numbers between The PR control transfer function is defined in (11) where ɷ is
1 and 6. The value of xf and yf are integer numbers between 0 the resonance frequency, Kp is the proportional gain, Ki is the
and 5. Calculations are indicated in Table II to realize integral gain of the PR controller and s is the integration term
switching states of inverter for each phase. Switching states in s domain. [20-22]
of one phase is shown in Fig 7. There are eight output of
SVPWM for one phase. s
GPR ( s ) = K p + K i (11)
xc = ceil ( x) (7) s 2 + w2

xf = floor ( x) (8) Main operating principle of PR control is that the system

yc = ceil ( y) (9) can adjusts gain only desired at a specific frequency. Low
order harmonics can be eliminated with PR control. It is
yf = floor ( y ) (10) capable to track the sinusoidal reference with zero steady-
state error. General structure of PR control is shown in Fig. 8
where the output current of the inverter is compared with a
reference signal and transfer function is implemented for each
phases. [20-22]

Fig. 6. xc, yc, xf and yf signals at sectors Fig. 8. General structure of PR control


 Fig. 10. SVPWM block

Fig. 9. Simulation diagram of Seven Level ACMLI

III. SIMULATION OF SEVEN LEVEL ACMLI

Main simulation diagram is shown in Fig. 9. There are
different blocks such as H-Bridges, SVPWM, PR Control,
filter and Load. H-Bridges is connected like Fig. 1(b). LC
filter parameters are 5mH and 500μF, respectively. Load is
star connected RL, 5Ω and 20 mH, respectively.
SVPWM block generates switching signals and there are
different sub-blocks as depicted in Fig. 10. Sub-blocks of
SVPWM convert three phase signals which connected to PR Fig. 11. PR control block
control outputs to αβ frame and gets Vref and θ parameters.
Then coordinate sub-block converts the αβ frame to 600
degree coordinate system. Switching states sub-block
performs calculations of switching states according to sector
numbers.
PR control block compares the output of ACMLI with
reference signal as shown in Fig. 11. Output current of
inverter is compared with reference signals. PR control gain
is implemented to phases separately. Kp parameter is 1 and Ki
parameter is 1.1 in PR control in this study. Output of PR
control block is connected to SVPWM block for input signals
for generation switching states. Fig. 12. Output voltages of inverter
Filtered three phase line voltages are illustrated in Fig. 12.
Output voltage levels are equal to each other as a value of
300V. Input voltage values of sources are 100V and 200V in
H-Bridges. Also filtered three phase line currents are shown
in Fig. 13, as can be seen here phase differences of the output
currents of inverter are 1200.
THD of output voltage (THDv) is 2.16%and THD of
output current (THDc) is 0.79%as given in Fig. 14 and Fig.
15, respectively. Harmonic orders are taken to the fiftieth
harmonic. Harmonic orders from 13-50 are nearly at zero
level and lower harmonics of THDv and THDc are mitigated.
Fig. 13. Output currents of inverter


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