Labsheet 1

1) Write VHDL program to model BASIC DIGITAL GATES and simulate the following using MODELSIM

Code:
library ieee;
use ieee.std_logic_1164.all;
entity myand is
port(l,m:in std_logic;
n:out std_logic);
end myand;
architecture archand of myand is
begin
n<= l and m;
end archand;

Testbench:
library ieee;
use ieee.std_logic_1164.all;
entity andtb is
end andtb;
architecture andtest of andtb is
component myand
port(a,b:in std_logic;
c:out std_logic);
end component;
signal at,bt,ct:std_logic;
begin
A1:
myand port map(a=>at,b=>bt,c=>ct);
at<='0','1' after 10 ns,'0' after 20 ns,'1' after 30 ns;
bt<='0','1'after 20 ns;
end andtest;

1
Behavioural:

Code:
library ieee;
use ieee.std_logic_1164.all;
entity myandb is
port(a,b:in std_logic;
c:out std_logic);
end myandb;
architecture archand of myandb is
begin
process(a,b)
begin
c<= a and b;
end process;
end archand;

2
Or:
Dataflow:
library ieee;
use ieee.std_logic_1164.all;
entity myor is
port(q,r:in std_logic;
s:out std_logic);
end myor;
architecture archor of myor is
begin
s<= q or r;
end archor;

testbench:
library ieee;
use ieee.std_logic_1164.all;
entity ortb is
end ortb;
architecture ortest of ortb is
component myor
port(q,r:in std_logic;
s:out std_logic);
end component;
signal at,bt,ct:std_logic;
begin
A1:myor port map(q=>at,r=>bt,s=>ct);
at<='0','1' after 10 ns,'0' after 20 ns,'1' after 30 ns;
bt<='0','1'after 20 ns;
end ortest;

3
Behavioural:
library ieee;
use ieee.std_logic_1164.all;
entity myorb is
port(a,b:in std_logic;
c:out std_logic);
end myorb;
architecture archor of myorb is
begin
process(a,b)
begin
c<= a or b;
end process;
end archor;

Not:

Dataflow:

library ieee;
use ieee.std_logic_1164.all;
entity mynot is

4
port(o:in std_logic;
p:out std_logic);
end mynot;
architecture archnot of mynot is
begin
p<= not o;
end archnot;

Testbench:
library ieee;
use ieee.std_logic_1164.all;
entity nottb is
end nottb;
architecture nottest of nottb is
component mynot
port(o:in std_logic;
p:out std_logic);
end component;
signal at,ct:std_logic;
begin
A1:mynot port map(o=>at,p=>ct);
at<='0','1' after 10 ns,'0' after 20 ns,'1' after 30 ns;
end nottest;

Behavioural:
library ieee;
use ieee.std_logic_1164.all;
entity mynotb is
port(a:in std_logic;
c:out std_logic);
end mynotb;
architecture archnot of mynotb is
begin
process(a)
c<= not a;
end process;
end archnot;

5
Nand:

Dataflow:
library ieee;
use ieee.std_logic_1164.all;
entity mynand is
port(a,b:in std_logic;
c:out std_logic);
end mynand;
architecture archnand of mynand is
begin
c<= a nand b;
end archnand;

Testbench:
library ieee;
use ieee.std_logic_1164.all;
entity nandtb is
end nandtb;
architecture nandtest of nandtb is

6
component mynand
port(a,b:in std_logic;
c:out std_logic);
end component;
signal at,bt,ct:std_logic;
begin
A1:
mynand port map(a=>at,b=>bt,c=>ct);
at<='0','1' after 10 ns,'0' after 20 ns,'1' after 30 ns;
bt<='0','1'after 20 ns;
end nandtest;

behavioural:
library ieee;
use ieee.std_logic_1164.all;
entity mynandb is
port(a,b:in std_logic;
c:out std_logic);
end mynandb;
architecture archnand of mynandb is
begin
process(a,b)
begin
c<= a nand b;
end process;
end archnand;

7
Nor:

Dataflow:
library ieee;
use ieee.std_logic_1164.all;
entity mynor is
port(a,b:in std_logic;
c:out std_logic);
end mynor;
architecture archnor of mynor is
begin
c<= a nor b;
end archnor;

8
Testbench:
library ieee;
use ieee.std_logic_1164.all;
entity nortb is
end nortb;
architecture nortest of nortb is
component mynor
port(a,b:in std_logic;
c:out std_logic);
end component;
signal at,bt,ct:std_logic;
begin
A1: mynor port map(a=>at,b=>bt,c=>ct);
at<='0','1' after 10 ns,'0' after 20 ns,'1' after 30 ns;
bt<='0','1'after 20 ns;
end nortest;

Behaviural:
library ieee;
use ieee.std_logic_1164.all;
entity mynorb is
port(a,b:in std_logic;
c:out std_logic);
end mynorb;
architecture archnor of mynorb is
begin
process(a,b)
begin
c<= a nor b;
end process;
end archnor;

9
Xor

Dataflow:
library ieee;
use ieee.std_logic_1164.all;
entity myxor is
port(a,b:in std_logic;
c:out std_logic);
end myxor;
architecture archxor of myxor is
begin
c<= a xor b;
end archxor;

Testbench:
library ieee;
use ieee.std_logic_1164.all;

10
entity xortb is
end xortb;
architecture xortest of xortb is
component myxor
port(a,b:in std_logic;
c:out std_logic);
end component;
signal at,bt,ct:std_logic;
begin
A1:
myxor port map(a=>at,b=>bt,c=>ct);

at<='0','1' after 10 ns,'0' after 20 ns,'1' after 30 ns;

Behavioural:
library ieee;
use ieee.std_logic_1164.all;
entity myxorb is
port(a,b:in std_logic;
c:out std_logic);
end myxorb;
architecture archxor of myxorb is
begin
process(a,b)
begin
c<= a xor b;
end process;
end archxor;

11
Xnor:

Dataflow:
library ieee;
use ieee.std_logic_1164.all;
entity myxnorb is
port(a,b:in std_logic;
c:out std_logic);
end myxnorb;
architecture archxnor of myxnorb is
begin
c<= a xnor b;
end archxnor;

Testbench:
library ieee;
use ieee.std_logic_1164.all;
entity xnortb is
end xnortb;
architecture xnortest of xnortb is
component myxnor

12
port(a,b:in std_logic;
c:out std_logic);
end component;
signal at,bt,ct:std_logic;
begin
A1:
myxnor port map(a=>at,b=>bt,c=>ct);

at<='0','1' after 10 ns,'0' after 20 ns,'1' after 30 ns;

Behavioural:
library ieee;
use ieee.std_logic_1164.all;
entity myxnorb is
port(a,b:in std_logic;
c:out std_logic);
end myxnorb;
architecture archxnor of myxnorb is
begin
process(a,b)
begin
c<= a xnor b;
end process;
end archxnor;

13
Structural modelling:
library ieee;
use ieee.std_logic_1164.all;
entity myand4 is
port(a,b,c,d:in std_logic;f:out std_logic);
end myand4;
architecture myandstr of myand4 is
component myand
port(l,m:in std_logic;n:out std_logic);
end component;
signal a1_t,c1_t:std_logic;
begin
x1:myand port map(a,b,a1_t);
x2:myand port map(c,d,c1_t);
x3:myand port map(a1_t,c1_t,f);
end myandstr;

14
Testbench:
library ieee;
use ieee.std_logic_1164.all;
entity tband4 is
end entity;
architecture archtb of tband4 is
component myand4
port(a,b,c,d:in std_logic;
f:out std_logic);
end component;
signal at,bt,ct,dt,ft:std_logic;
begin
h1:myand4 port map(a=>at,b=>bt,c=>ct,d=>dt,f=>ft);
at<='0','0' after 10 ns,'1' after 20 ns,'0' after 30 ns;
bt<='0','0' after 10 ns,'1' after 20 ns,'1' after 30 ns;
ct<='0','1' after 10 ns,'1' after 20 ns,'1' after 30 ns;
dt<='0','0' after 10 ns,'1' after 20 ns,'0' after 30 ns;
end archtb;

15
2) Write VHDL program to model the function f=(c’d’+cd+abd) using
(i)STRUCTURAL (ii)BEHAVIOR

(i)STRUCTURAL:
library ieee;
use ieee.std_logic_1164.all;
entity myquestion2 is
port ( a,b,c,d: in std_logic;
e: out std_logic);
end myquestion2;
architecture myquestion2arch of myquestion2 is
component myand
port( l,m :in std_logic;
n: out std_logic);
end component;

component myor
port( q,r :in std_logic;
s: out std_logic);
end component;

component mynot
port( o :in std_logic;
p: out std_logic);
end component;

signal i,j,k,l,m,n,o: std_logic;

16
Testbench:
library ieee;
use ieee.std_logic_1164.all;
entity que2tb is
end que2tb;
architecture archtest of que2tb is
component myquestion2
port ( a,b,c,d: in std_logic;
e: out std_logic);
end component;
signal at,bt,ct,dt,et: std_logic;
begin
a1:myquestion2 port map(a=>at,b=>bt,c=>ct,d=>dt,e=>et);
at<= '0','1' after 10ns, '0' after 20 ns;
bt<= '0','1' after 20ns, '0' after 40 ns;
ct<= '0','1' after 40ns, '0' after 80 ns;
dt<= '0','1' after 80ns, '0' after 110 ns;
end archtest;

(ii)BEHAVOIURAL:
library ieee;
use ieee.std_logic_1164.all;
entity myquestion2b is
port (a,b,c,d: in std_logic;
e: out std_logic);
end myquestion2b;
architecture que2arch of myquestion2b is
begin
process(a,b,c,d)
begin
e<=(not(c) and not(d)) or (c and d) or ((a and b)and c);
end process;
end que2arch;

17
3)Implement the function f=m(0,1,2,3,6) using STRUCTURAL modeling and simulate in
Modelsim.

CODE:
library ieee;
use ieee.std_logic_1164.all;
entity myque3 is
port (x,y,z : in std_logic;
f: out std_logic);
end myque3;
architecture que3arch of myque3 is
component myand
port( l,m :in std_logic;
n: out std_logic);
end component;
component myor
port( q,r :in std_logic;
18
s: out std_logic);
end component;
component mynot
port( o :in std_logic;
p: out std_logic);
end component;
signal i,j,k: std_logic;
begin
n1: component mynot port map( x,i);
n2: component mynot port map (z,j);
a1: component myand port map (y,j,k);
o1: component myor port map (i,k,f);
end que3arch;

Testbench:
library ieee;
use ieee.std_logic_1164.all;
entity que3tb is
end entity;
architecture que3tbarch of que3tb is
component myque3
port (x,y,z : in std_logic;
f: out std_logic);
end component;
signal xt,yt,zt,ft: std_logic;
begin
a1: component myque3 port map(x=>xt,y=>yt,z=>zt,f=>ft);
xt<= '0','1' after 10ns, '0' after 20 ns,'1' after 30 ns,'0' after 40 ns,'1' after 50 ns,'0' after 60 ns,'1' after 70
ns;
yt<= '0','1' after 20ns, '0' after 40 ns, '1' after 60 ns,'0' after 80 ns;
zt<= '0','1' after 40ns, '0' after 80 ns;
end architecture que3tbarch;

19
4)Implement the function F=M(4,5,7) using DATAFLOW modeling and simulate in modelsim.

Code:
library ieee;
use ieee.std_logic_1164.all;
entity myque4 is
port (x,y,z : in std_logic;
f: out std_logic);
end myque4;
architecture que4arch of myque4 is
begin
f<= ((not(x)) or (y and (not(z))));
end que4arch;

20
Testbench:

library ieee;
use ieee.std_logic_1164.all;
entity que4tb is
end entity;
architecture que4tbarch of que4tb is
component myque4
port (x,y,z : in std_logic;
f: out std_logic);
end component;
signal xt,yt,zt,ft: std_logic;
begin
a1: component myque4 port map(x=>xt,y=>yt,z=>zt,f=>ft);
xt<= '0','1' after 10ns, '0' after 20 ns,'1' after 30 ns,'0' after 40 ns,'1' after 50 ns,'0' after 60 ns,'1' after 70
ns;
yt<= '0','1' after 20ns, '0' after 40 ns, '1' after 60 ns,'0' after 80 ns;
zt<= '0','1' after 40ns, '0' after 80 ns;
end architecture que4tbarch;

21
5)Try simulating both the codes given below. What do you observe? Why is the difference?
a)
library ieee;
use IEEE.std_logic_1164.all;
entity var_assign is
port(a,clk:in std_logic;c:out std_logic);
end var_assign;
architecture behav of var_assign is
begin
process(clk)
variable b:std_logic;
begin
b:=a;
c<=b;
end process;
end behav;

Testbench:
library ieee;
use ieee.std_logic_1164.all;
entity vartb is
end entity;
architecture arch_tb of vartb is
component var_assign
port(a,clk:in std_logic;
c:out std_logic);
end component;
signal a_t,c_t:std_logic;
signal clk_t : std_logic := '1';
begin
h1:var_assign port map(a=>a_t,clk=>clk_t,c=>c_t);
a_t<='0','1' after 10 ns,'0' after 20 ns,'1' after 30 ns;
clk_t<=not(clk_t) after 5 ns;
end arch_tb;

22
b)
library ieee;
use IEEE.std_logic_1164.all;
entity sig_assign is
port(a,clk:in std_logic;c:out std_logic);
end sig_assign;
architecture behav of sig_assign is
signal b:std_logic;
begin
process(clk)
begin
b<=a;
c<=b;
end process;
end behav;

Testbench:
library ieee;
use ieee.std_logic_1164.all;
23
entity sigtb is
end sigtb;
architecture archtb of sigtb is
component sig_assign
port(a,clk:in std_logic;c:out std_logic);
end component;
signal a_t,c_t:std_logic;
signal clk_t : std_logic := '1';
begin
a1:sig_assign port map(a=>a_t,clk=>clk_t,c=>c_t);
a_t<='0','1' after 10 ns,'1' after 20 ns,'0' after 30 ns;
clk_t<=not clk_t after 5 ns;
end archtb;

Reason:
For variable assignment, the value is assigned immediately whereas for signal assignment it happens
after a delay in clock.
In the case of variable assignment, the value of b is the present value of a and is assigned to c
immediately. For signal assignment, it takes a change in clock for the first code to assign a to the value of
c; since the value of a is assigned to b, but however the value assigned to c is the previous value of b.
24