6.

012 DP: CMOS Integrated Differential Amplifier

Tony Hyun Kim

Contents
1 Introduction 1

2 Common-source gain stage with Lee load 2

3 Cascode current mirror gain stage 3

4 Push-pull output stage 5

4.1 Output resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.2 Output voltage swing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.3 Push-pull biasing circuitry Q24 , Q25 , Q26 , Q27 . . . . . . . . . . . . . . . . . . . . . . . 6
4.4 Small-signal attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5 Bias circuitry for voltages A, B, C, D 8

6 Remaining issues 8
6.1 Quiescent power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6.2 Differential input required to make VOU T = 0V . . . . . . . . . . . . . . . . . . . . . . . . 8

1 Introduction

This brief report accompanies my solution to the Spring 2008 6.012 project concerning the design of a
CMOS integrated differential amplifier. For an organized presentation of the results, please consult the
attached solution worksheet. Instead, the intent of this report is to informally describe the intuition
behind my approach.
The circuit is operated from ±1.5V supplies, and must meet the following performance criteria:

1. Small-signal gains:
(a) Differential-mode voltage gain, Avd ≥ 500, 000.
(b) Common-mode voltage gain, Avc ≤ 0.005.

2. Common-mode rejection ratio, Avd /Avc ≥ 108 .

3. Small-signal output resistance, rout ≤ 100 Ω.
4. Maximum output voltage swing into a 300 Ω load, |vOU T |max ≥ 0.6 V.
5. Minimum common-mode input voltage range, |vIC |min ≥ 0.8 V.

6. Total quiescent power dissipation not to exceed 1.5 mW.

1
 2 COMMON-SOURCE GAIN STAGE WITH LEE LOAD

7. Value of |VID | = |VIN 1 − VIN 2 | required to make VOU T = 0 V must be less than 5 microvolts.

Over the course of this document, I will verify that all of these conditions are met by my design.
My general approach was to take, for almost every transistor, the minimum gate-to-source voltage
of |VGS | = 0.6 V. This is motivated by two reasons. First, with the bias current fixed, many of the
performance characteristics are improved as we take the smallest possible bias. Secondly, the narrow
power supply rails do not offer much room for experimentation. In fact, in some cases the minimal
bias of 0.6 V is literally forced upon us by the performance requirements (in particular, the voltage
ranges (4) and (5) of the previous list) in conjuction with the power supply limitations.
In addition, I was able to halve the amount of work involved, by maximizing the symmetry of the
circuit. For instance, in the two vertical chains that constitute the current mirror stage (Figure 2), I
saw no reason to complicate the design by choosing a different set of device parameters for each chain.
The project document provided by 6.012 staff characterizes the overall circuit as consisting of several
stages: the Lee-load gain stage, the current-mirror cascode gain stage, and the output stage. I will
follow this framework in my discussion of the circuit. Brief comments regarding the biasing circuitry
are relegated to the end.

2 Common-source gain stage with Lee load

This gain stage involves transistors Q9 , Q10 , Q11 , Q12 , Q13 , Q14 , Q15 as shown in Figure 1.

Figure 1: Common-source gain stage with Lee load. The current through the bias transistor Q9 is
denoted IC . Note how this current splits among the branches downstream.

Let IC denote the bias current set up by Q9 . From our work in PS #10 on the small-signal gains
of the Lee load, we know the differential-mode and common-mode gains to be:
−2(IC /2)
gm10 |VGS −VT |10 −1
Avd = = = λ10 +λ12
(1)
go10 + 2go12 λ10 (IC /2) + 2λ12 (IC /4) 2 (VGS − VT )10

2
 3 CASCODE CURRENT MIRROR GAIN STAGE

−go9 −λ9 IC 1
Avc ≈ = 2·(I /4)
= − λ9 (VGS − VT )12 (2)
4gm12 4 · (VGS −VT )12
C 2

Hence, as indicated earlier, both characteristics are improved if we take the minimum allowed bias of
0.6V. Furthermore, Eqs. 1 and 2 show that we also should take Q9 , Q10 and Q12 (thereby all of the
transistors in this stage, by symmetry) to be double-length devices. This halves λ = V1A ∝ L1 as to
give the optimum characteristics.
By choosing (VGS − VT )12 = 0.6V , we are setting the quiescent output of this stage at -0.9V. This
output node is also the drain of Q10 and Q11 . It is then clear that Q10 and Q11 definitely will not go
out of saturation at the negative common mode input of -0.8V.
In addition, we must also make sure that all transistors are in saturation for a positive common-
mode input of 0.8V. For such inputs, the source tails of Q10 and Q11 are pushed up to 1.4V at the
least, since the very minimum allowed gate-to-source bias is 0.6V. This then forces node A to take
on 0.9V. If A were any higher, we would violate the necessary VSG bias for Q9 . If instead node A
were lower than 0.9V, Q9 would not be operating in saturation at the extreme common-mode input of
0.8V. With these voltage biases, the circuit successfully accomodates the common-mode input range
specified by (5).
Finally, to determine the device sizes, we minimize IC . In this task, we only need to recognize that
the n-channel transistors in the Lee load are the limiting devices, since they constitute the branch
carrying the smallest current. Absolute minimum K-factor for the n-channel device Q12 is K12 = 1
mA/V2 , yielding ID12 = IC /4 = 12 (1mA/V 2 )(0.1V )2 = 0.005mA.
In summary, the gains and the current consumption of this stage are Avd = 100, Avc = 0.005 and
IC = 0.02mA.

3 Cascode current mirror gain stage

In the analysis of this second gain stage, I have relied upon Prof. Fonstad’s results rather than
conducting the small-signal network analysis myself. On the other hand, I have decided to make the
two branches symmetric. Hence, they each carry a bias current of ID . (See Figure 2.) The small-signal
differential gain is:
2gm23
Avd =
go17 go19 /gm19 + go23 go21 /gm21
8
=
(VGS − VT )23 (λ17 λ19 (VSG − |VT |)19 + λ21 λ23 (VGS − VT )21 )
80V −1
= (3)
λ17 λ19 (VSG − |VT |)19 + λ21 λ23 (VGS − VT )21
where the last line follows after a little algebra, and also after recognizing that (VGS −VT )23 has already
been determined by our biasing of the previous Lee-load gain stage. Under quiescent conditions, the
outputs of the first stage sit at −0.9V , which gives (VGS − VT )23 = 0.1V .
We continue on with Eq. 3 by setting the remaining biases to 0.6V as well. This can be consistently
achieved by setting the voltage bias points C and D to the appropriate level. In particular, C: 0.8V
and D: -0.8V work nicely, without putting neighboring transistors out of saturation. These levels for
C and D also provide a large voltage range for the output node as illustrated in Figure 2. For the task
at hand, these choices yield:
800V −2
Avd = (4)
λ17 λ19 + λ21 λ23

3
 3 CASCODE CURRENT MIRROR GAIN STAGE

At first sight, Eq. 4 suggests that we choose all devices to be double-length, in order to maximize
the differential gain. However, it can easily be shown that the CMRR can be improved, if we let
λ17 = 0.2V −1 instead. With the remaining transistors (Q19 , Q21 , Q23 ) as double-length devices, we
obtain the following small-signal differential gain:

Avd = 2.67 × 104 (5)

We also have the expression for common-mode gain, courtesy Prof. Fonstad:
gm23 λ23 ID 1
Avc = − =− =− (6)
gm17 λ17 ID 2

Figure 2: The choice of C: 0.8V and D: -0.8V gives a large voltage range for the output node without
knocking any transistor out of saturation. The bias current ID is also indicated.

The current ID can be determined by recognizing the n-channel devices Q21 and Q23 as the devices
that limit the minimization of current. We conclude: ID = 0.005mA.
In this discussion, I have specified the sizes and biasing conditions of Q17 , Q19 , Q21 and Q23 . The
transistors of the opposite branch (Q16 , Q18 , Q20 and Q22 ) are determined by symmetry.
To conclude, the overall gains are (with an open load):

Aoverall,open
vd = ALL CM 4
vd × Avd = 100 × 2.67 × 10 = 2.67 × 10
6
(7)
Aoverall,open
vc = ALL
vc × ACM
vc = 0.005 × 0.5 = 0.0025 (8)
9
CM RR = 1.07 × 10 (9)

We have therefore satisfied the gain criteria.

4
 4 PUSH-PULL OUTPUT STAGE

4 Push-pull output stage

In this final stage, the output resistance and voltage swing requirements place somewhat stringent
restrictions on the device parameters. We begin by discussing the output resistance.

4.1 Output resistance

From the output port, the equivalent resistance looking into the circuit is that of two parallel source-
follower subcircuits. Furthermore, recall that the output conductance of a source-follower increases
when the large-signal current through the transistor is increased. It then follows that the worst-case,
maximum output resistance will occur when vOU T ≈ 0V . This is so, because when the output is
displaced from zero, either Q28 or Q29 will be very active, thereby providing at least one low resistance
path (of a source-follower with a high bias current).
Let IH denote the quiescent current through the push-pull (Q28 and Q29 ) when vOU T ≈ 0V . Then,
the output resistance is calculated to be:
1 1
rout = = 2IH
(10)
gm28 + gm29 (VGS −VT )28 + (VSG2I H
−|VT |)29

Again, I choose the two biases to be symmetric:

(VGS − VT )28
rout = ≤ 100 Ω (11)
4IH

We are free to choose (VGS − VT )28 = 0.1V , in order to limit quiescent power consumption. Then,
the inequality of Eq. 11 becomes:

1 |VGS − VT |
IH ≥ ·
4 100 Ω
≥ 0.25 mA (12)

which takes up half our current budget! Fortunately, because the other parts of the circuit are not so
current-hungry, we are able to satisfy this demand without further complications.
In this section, we have specified the gate-to-source bias and the current through Q28 . In turn, this
then specifies K28 = 50mA/V 2 .

4.2 Output voltage swing

The push-pull must be capable of delivering at least a 0.6V high-output when loaded by 300 Ω. By
design, at such a high-end swing, only Q28 is active (i.e. is “pushing” current) while Q29 is in cutoff.
This scenario is illustrated in Figure 3.
In Figure 3, the current into the resistor must be provided entirely by Q28 , which requires:
1 1
2mA = K28 (VGS − VT )2 = 50mA/V 2 (VGS − VT )2
2 s 2
4mA
VGS = VT + = 0.783V (13)
50mA/V 2

5
4.3 Push-pull biasing circuitry Q24 , Q25 , Q26 , Q27 4 PUSH-PULL OUTPUT STAGE

Figure 3: This circuit fragment illustrates the demands imposed on Q28 by the 0.6V voltage swing
requirement when loaded by 300 Ω.

Since VS = VOU T = 0.6V , we have:

VG28 = VGS + 0.6V = 1.383V (14)

which shows that we barely avoided kicking Q26 out of saturation. (It is precisely for this reason that
I did not conduct a more accurate calculation for the maximum VOU T . We are very close to the limit
already with 0.6V .) Here is a direct tradeoff between power consumption and output voltage swing
range. If we were to choose larger K-factors for Q28 and Q29 , we can extend the output range (in
addition to having smaller rout !) but we’ll have to settle for a larger quiescent current. My design
preference was to minimize power consumption.
A similar analysis can be performed on the negative swing, when Q29 is active.

4.3 Push-pull biasing circuitry Q24 , Q25 , Q26 , Q27

In this subsection, we regard the drain nodes of Q19 and Q21 (the output of the current mirror stage)
to be the input of the push-pull. The concern here is to communicate this input voltage to the output
of the push-pull, without incurring significant distortions.
It is well-known that directly driving the gates of a push-pull will result in the so-called “crossover
distortion,” as shown below in Figure 4. In the case of MOSFETs, this undesirable effect arises due
to the finite threshold voltage.
The design project circuit addresses this issue by biasing the push-pull (Q28 and Q29 ) by a proper
choice of Q24 , Q25 , Q26 , Q27 , selected to compensate for the threshold voltage. We note, however, that
the solution cannot be perfect, as we have seen previously that the gate-to-source voltages for Q28 and
Q29 are not constant over the operating range. On the other hand, Q26 and Q27 are configured in a
way to provide a constant gate-to-source bias throughout their operation. (This latter claim is only
approximately true. It is valid only because we are not taking into account the Early effect in this
large-signal analysis.)
Suppose VOU T > 0V so that Q28 is active. In other words VGS28 ≈ 0.6V . To compensate for
this “intrinsic” 0.6V drop, we bias Q27 in a way to provide a boost of 0.6V . Similarly, we provide
a gate-to-source bias of 0.6V on Q24 as to offset the VSG ≈ 0.6V on Q29 during a negative swing.

6
4.4 Small-signal attenuation 4 PUSH-PULL OUTPUT STAGE

Figure 4: Crossover distortion occurs when driving a push-pull stage directly. Image taken from the
Wikipedia article on “Crossover distortion.”

Altogether, we are reliably transferring the large-signal voltage from the output of the current mirror
to the final output port of the differential amplifer.
Finally, the sizes of transistors Q24 , Q25 , Q26 , Q27 are then determined by minimizing the current
consumption.

4.4 Small-signal attenuation

In a more detailed small-signal analysis of the push-pull, we find the transfer function to be:
RL
vout ≈ 1 · vin (15)
RL + 2gm28

where RL is the attached load. Using RL = 300Ω, we find:

300 3
AP
v
P
= (VGS −VT )28
= (16)
300 + 4
4IH

This gain is compounded on the open-load gains of Eqs. 7 and 8, which give:
3
Aoverall
vd = · Aoverall,open
vd = 2.00 × 106 (17)
4
3
Aoverall
vc = · Aoverall,open
vc = 0.00188 (18)
4
CM RR = 1.07 × 109 (19)

Hence, our device still satisfies the small-signal gain requirements. (Obviously, the CMRR remains
unchanged since the push-pull does not differentiate between differential-mode and common-mode
inputs.)

7
 6 REMAINING ISSUES

Circuit Description Current (mA)

Bias chain (A,B) 0.04
Bias chain (C,D) 0.01
Lee-load stage 0.02
Current-mirror stage 0.01 = 2 × 0.005
Push-pull biasing 0.0075 = 0.005 + 0.0025
Push-pull 0.25
Total 0.3375

Table 1: Current consumption in the differential amplifier circuit.

5 Bias circuitry for voltages A, B, C, D

So far, we have specified the following bias voltages: A = 0.9V , C = 0.8V , and D = −0.8V . It is
convenient to set B = −0.9V , given the role it plays as a counterpart to A in the output stage.
The determination of the necessary device sizes in the bias chains (Q1 through Q8 ) is a fairly
mechanical exercise that we encountered in PS # 10. Needless to say, my design attempts to minimize
the quiescent current consumption.

6 Remaining issues

6.1 Quiescent power dissipation

The differential amplifier can consume at most 1.5 mW under quiescent conditions. Because we are
operating from ±1.5V ideal supplies, this requirement can be reformulated in terms of a current. The
device cannot consume more than 0.5 mA at the quiescent point.
Table 1 enumerates the quiescent current consumption through the different branches of the circuit.
As can be seen, we are well within the power dissipation requirement.

6.2 Differential input required to make VOU T = 0V .

If we short both inputs VIN 1 = VIN 2 = 0V , the high-impedance node (output of the current-mirror)
can be shown to be 0.9V , upon considering the symmetric structure of the current-mirror subcircuit.
It is difficult to say exactly what the overall device’s output voltage VOU T will be, since under these
conditions, not all transistors are operating in saturation. The most obvious problem area involves
Q26 and Q27 . In any case, we can be certain that the zero-input output will not be zero.
However, a small differential input can be applied to bring the high-impedance node (and hence
VOU T ) to zero. Because of the large differential gain Aoverall
vd (Eq. 7), the necessary differential input
will be minor:
0.9V
|VID | = overall = 0.337µV (20)
Avd
This result exceeds requirement (7) by a significant margin.

8
REFERENCES REFERENCES

References

[1] 6.012 Staff. Special Problem on Circuit Design. Spring 2008.

[2] I discussed general design issues with 6.012 classmate Ilan Almog. The collaboration was as sanc-
tioned by the design project guidelines. In particular, final solutions were definitely not exchanged
nor discussed.