CO Slides Unit1 Part1
CO Slides Unit1 Part1
Module1
Introduction
• Basic structure
• Operational and operational concepts of computers
• Performance considerations
• Different architectures-Harvard Architecture, Von
Neumann Architecture, RISC and CISC
-Arithmetic Unit
Module4
-Processor Design
-Memory System
• Organization of memory
• Hierarchical memory system
• Cache memory and its operation
• Cache memory mapping
Text and Reference Books
Book Type Code Author and Title Publication Specification
Edition Publication Year
Text Book 1 Computer organization by 5th McGraw Hill 2011
Carl Hamacher, Z Vranesic and
Zaky
Text Book 2 ARM System Developer’s - Morgan 2004
Guide – Designing and Kaufmann
optimizing system software by
Andrew N SLOSS, Dominic SYMES,
Chris Wright
Primary Storage
• Fast and operates at electronic speeds
LOCA + R0 R0
Basic Operational Concepts
Alternate method
How addition performed when no direct access to memory?
• Ex: Load LOCA, R1
Add R1, R0
• R0 and R1 previous contents are overwritten
Interconnection between Processor and Memory
Basic Operational Concepts
Registers
• Instruction Register (IR) - holds the instruction that is currently
being executed (e.g., ADD LOCA, R0)
• [MDR]-> IR
Note: Computer can also accept data from input devices and
sends data to output devices
• Only 2 units can actively use bus at any given time as bus
supports one transfer at a time
Bus Structure
Single Bus Transfer
• Two forms
- System Software
- Application Software
Software
System Software
• Collection of programs that are executed as needed to
perform functions like
CISC RISC
• Complex instruction set • Reduced instruction set
computer computer
• It is prominent on • It is prominent on
hardware software
• Multiple instruction • Instructions of same size
sizes and formats with few formats
Instruction Set: CISC and RISC
CISC RISC
• Less registers • More registers
• More addressing modes • Less addressing modes
• Instructions take varying • Instructions take one
amount of cycle time cycle time
• Pipelining is difficult • Pipelining is efficient
Instruction Set: CISC and RISC