A B C D E

1 1

KSKAA
2 Bradford 10M/10MG 2

LA-4991P REV 1.0 Schematic

3

Intel Penryn/ Cantiga/ ICH9M 3

2008-05-07 Rev. 1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 1 of 48
A B C D E
 A B C D E

Compal Confidential
Model Name : KSKAA Fan Control Intel Penryn Processor Thermal Sensor Clock Generator
page 4
File Name : LA-4991P EMC1402 SLG8SP556VTR
uPGA-478 Package page 4 page 16
1
Display Port (Socket P) page 4,5,6
1

page 19

CRT FSB
H_A#(3..35) 667/800/1066MHz H_D#(0..63)
page 18
Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2
VGA MXM/B LCD Conn. Intel Cantiga Dual Channel
page 18 BANK 0, 1, 2, 3 page 14,15
ATI M92XT,64bit with 256M/512MB PCIE-Express 16X GM45/PM45/GL40 1.8V DDRII 667/800
ATI M96,128bit with 512M/1GB GM47/GM49
EC HDMI CEC Controller HDMI Conn. Level Shifter uFCBGA-1329
SMBUS R5F211A4SP USB/B Right USB Left FP conn
page 20 page 20 page 20 page 7,8,9,10,11,12,13 USB port 0,1 USB port 2 USB port 8
page 27 page 27 page 27
PCIeMini Card PCIeMini Card PCIeMini Card
2
3G/GPS/TV Tuner WiMax Reserve DMI x 4 C-Link BT conn Felica Int. Camera 2
USB port 6 USB port 7 PCIe port 11
USB port 5 USB port 9 USB port 11
page 28 page 28 page 28
USB page 27 page 27 page 27
5V 480MHz
USB
PCIeMini Card PCIeMini Card PCIeMini Card 5V 480MHz
PCIe 1x [2,4,5]
Reserve WLAN UWB/JET 1.5V 2.5GHz(250MB/s)
SATA port 1 SATA HDD0
PCIe port 5 PCIe port 4 PCIe port 2 5V 1.5GHz(150MB/s) page 25
page 28 page 28 page 28
Intel ICH9-M SATA port 0 SSD
Express Card 5V 1.5GHz(150MB/s) page 25
USB
BCAS USB port 4
5V 480MHz SATA port 4
page 26 Express Card PCIe 1x SATA ODD
5V 1.5GHz(150MB/s) page 25
PCIe port 1 page 26 1.5V 2.5GHz(250MB/s) BGA-676
SATA port 5
RTL8103EL 10/100M PCIe 1x 5V 1.5GHz(150MB/s)
RJ45 eSATA USB Left
page 29 RTL8111DL Giga 1.5V 2.5GHz(250MB/s) page 20,21,22,23 USB port 3 USB port 3
USB/B-1 page 26 page 26
page 25 PCIe port 3 page 29 5V 480MHz

3 PCIe 1x 3
JMB380 5IN1 1.5V 2.5GHz(250MB/s)
USB/B-2 PCIe port 6 page 32
page 27 HD Audio 3.3V 24.576MHz/48Mhz

I2C from SB
FM tuner Conn LPC BUS
Finger print/B 3.3V 33 MHz
HDA Codec
page 27 page 27 MDC 1.5 Conn
ALC272
Debug Port ENE KB926 D3 page 27 page 30
Power/B page 34 page 33
page 35

CAP SENSOR/B RTC CKT. AMP.

page 35 SPI ROM CIR GSENSOR Int. TPA6017
Int.KBD MIC CONN MIC CONN HP CONN
page 21 page 34 page 34 page 34 page 34 page 31 page 31 page 31 page 31

LIGTH PIPE/B
page 35
4
DC/DC Interface CKT. SPK CONN 4
page 31
page 35
LED/B
page 35
Power Circuit DC/DC Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

Touch Pad/B page 36,37,38,39 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
page 35 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
40,41,42 D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 2 of 48
A B C D E
 5 4 3 2 1

DESIGN CURRENT 0.1A +3VL

B+ DESIGN CURRENT 0.1A +5VL
DESIGN CURRENT 0.1A +VSB
TPS51125RGER DESIGN CURRENT 3A
+5VALW
D D
SUSP
N-CHANNEL DESIGN CURRENT 2A +5VS
SI4800 BCPWON
DESIGN CURRENT 0.5A +5VS_L_BCAS
P-CHANNEL
KSKAA/Bradford Intel AO-3413
FELICA_PWR
DESIGN CURRENT 0.5A +FLICA_VCC
P-CHANNEL
AO-3413
SUSP
DESIGN CURRENT 0.5A +HDMI_5V_OUT
N-CHANNEL
SBPWR_EN# SI3456
N-CHANNEL +5V_SB
DESIGN CURRENT 0.5A
2N7002

DESIGN CURRENT 0.5A

+3VALW

RUNON
C C
N-CHANNEL DESIGN CURRENT 0.5A
+3VS_DP
SI3456
SUSP
N-CHANNEL DESIGN CURRENT 2A +3VS
SI4800 ENVDD
P-CHANNEL DESIGN CURRENT 1A +LCD_VDD
AO-3413
WOL_EN#
P-CHANNEL DESIGN CURRENT 330mA +3V_LAN
AO-3413
BT_PWR#
P-CHANNEL DESIGN CURRENT 180mA +BT_VCC
AO-3413
DESIGN CURRENT 750mA +3V_SB
SBPWR_EN#
B B
P-CHANNEL
VR_ON
AO-3413
DESIGN CURRENT 35A +CPU_CORE
ISL6262
SYSON
DESIGN CURRENT 7A +1.8V
TPS51117RGYR SUSP
DESIGN CURRENT 1A +1.8VS
N-CHANNEL
SI4856 SUSP
DESIGN CURRENT 2A +0.9VS
SUSP# APL5331KAC
DESIGN CURRENT 2A +1.5VS
TPS51117RGYR
SUSP#
DESIGN CURRENT 10A +1.05VS
TPS51117RGYR
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 3 of 48
5 4 3 2 1
 A B C D E

Voltage Rails SIGNAL

STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5#

Power Plane Description S1 S3 S5 G3 Full ON HIGH HIGH HIGH HIGH

VIN Adapter power supply (19V) ON ON ON OFF S1(Power On Suspend) LOW HIGH HIGH HIGH
1 1
B+ AC or battery power rail for power circuit. ON ON ON ON
S3 (Suspend to RAM) LOW LOW HIGH HIGH
+CPU_CORE Core voltage for CPU ON OFF OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH
+1.05VS 1.05V switched power rail ON OFF OFF OFF
S5 (Soft OFF) LOW LOW LOW LOW
+1.5VS 1.5V switched power rail ON OFF OFF OFF
+1.8V 1.8V power rail for DDR ON ON OFF OFF G3 LOW LOW LOW LOW
+3VALW 3.3V always on power rail ON ON ON OFF
+3VL 3.3V always on power rail ON ON ON ON
+3V_SB 3.3V power rail for LAN ON ON OFF OFF
+3V_LAN 3.3V power rail for LAN ON ON OFF OFF
+3V_WLAN 3.3V power rail for LAN ON ON OFF OFF BTO Option Table
+3VS 3.3V switched power rail ON OFF OFF OFF
+5VALW 5V always on power rail ON ON ON OFF
Function HDMI CRT Display LAN
+5VL 5V always on power rail ON ON ON ON
2 +5V_SB 5V power rail for SB ON ON OFF OFF (Y) (Q) (Z) (E) (C) 2
description
+5VS 5V switched power rail ON OFF OFF OFF
explain Intel(UMA) ATI MXM/B COMMON 10/100M Giga
+VSB VSB always on power rail ON ON ON OFF
+RTCVCC RTC power ON ON ON ON BTO IHDMI@ NIHDMI@ HDMI@ H@ CRT@ DP@ 8103EL@ 8111DL@
+CPU_CORE Core voltage for VGA chip ON ON OFF OFF
+VGA_PCIE_1.1VS 1.1V switched power rail for VGA PCIE ON ON OFF OFF
Function 3G SIM slot Mini card Felica Finger printer CIR CAMERA & MIC BLUE TOOTH
+1.8VS 1.8V power rail for VRAM ON ON OFF OFF
description (3) (D2) (J) (F) (I) (X) (B)

explain Two Cards CAMERA MIC

External PCI Devices BTO 3G@ 3G@ FLICA@ FP@ CIR@ CAM@ MIC@ BT@

EC SM Bus1 address EC SM Bus2 address

3 3
Power Device Address Power Device Address
+3VL EC KB926 D3 +3VS EC KB926 D3
+5VL Smart Battery 0001 011X b CPU THM Sen
+3VS SMSC SMC1402 0100 110x b
+5VL HDMI-CEC 0011 010x b
+3VL FUN/B (CAP Sensor)

ICH9M SM Bus address

Power Device Address
+3V_SB ICH9M

Clock Generator 1101 001Xb

4 +3VS (SLG8SP556V) 4

+3VS DDR DIMM0 1001 000Xb

+3VS DDR DIMM1 1001 010Xb
+3VS Express
Security Classification Compal Secret Data Compal Electronics, Inc.
+3VS FM Module Issued Date 2008/10/06 2009/10/06 Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 4 of 48
A B C D E
 5 4 3 2 1

@
7 H_A#[3..16] +3VS
JCPUA
H_A#3 J4 H1
A[3]# ADS# H_ADS# 7

ADDR GROUP_0
H_A#4 L5 E2
A[4]# BNR# H_BNR# 7
H_A#5 L4 G5
A[5]# BPRI# H_BPRI# 7
H_A#6

0.1U_0402_16V4Z
K5 A[6]# 1
H_A#7 M3 H5
A[7]# DEFER# H_DEFER# 7 C1
H_A#8 N2 F21 C64 33P_0402_50V8K
A[8]# DRDY# H_DRDY# 7
H_A#9 J1 E1 U1 1 2
A[9]# DBSY# H_DBSY# 7 2
H_A#10 N3
H_A#11 A[10]#
P5 A[11]# BR0# F1 H_BR0# 7
H_A#12 P2 1 8
A[12]# VDD SMCLK EC_SMB_CK2 17,33,34,35

CONTROL
D H_A#13 L2 D20 H_IERR# R1 1 2 56_0402_5% +1.05VS D
H_A#14 A[13]# IERR# H_INIT# H_THERMDA
P4 A[14]# INIT# B3 H_INIT# 22 2 DP SMDATA 7 EC_SMB_DA2 17,33,34,35
H_A#15 P1 C2
H_A#16 A[15]# H_THERMDC
R1 A[16]# LOCK# H4 H_LOCK# 7 1 2 3 DN ALERT# 6 1 2 +3VS
M1 2200P_0402_50V7K R2 10K_0402_5%
7 H_ADSTB#0 ADSTB[0]#
C1 H_RESET# CPU_THERM# 4 5 @ Reserve for source control
RESET# H_RESET# 7 THERM# GND
7 H_REQ#0 K3 REQ[0]# RS[0]# F3 H_RS#0 7
H2 F4 R3
7 H_REQ#1 REQ[1]# RS[1]# H_RS#1 7 if use XDP,these resistor are 51ohm
7 H_REQ#2 K2 REQ[2]# RS[2]# G3 H_RS#2 7 +3VS 1 2
J3 G2 +1.05VS 10K_0402_5% EMC1402-1-ACZL-TR_MSOP8
7 H_REQ#3 REQ[3]# TRDY# H_TRDY# 7
7 H_REQ#4 L1 REQ[4]#
Address:0100_1100 EMC1402-1
G6 XDP_TDO 1 2 Address:0100_1101 EMC1402-2
7 H_A#[17..35] HIT# H_HIT# 7
H_A#17 Y2 E4 R14 54.9_0402_1%
A[17]# HITM# H_HITM# 7
H_A#18 U5 XDP_TMS 1 2
H_A#19 A[18]# R4 54.9_0402_1%
R3 A[19]# BPM[0]# AD4

ADDR GROUP_1
H_A#20 W6 AD3 XDP_TDI 1 2
H_A#21 A[20]# BPM[1]# R5 54.9_0402_1%
U4 AD1
H_A#22 Y5
A[21]#
A[22]#
BPM[2]#
BPM[3]# AC4
+5VS
FAN Control Circuit

XDP/ITP SIGNALS
H_A#23 U1 AC2 XDP_TCK 1 2
H_A#24 A[23]# PRDY# R6 54.9_0402_1%
R4 A[24]# PREQ# AC1
H_A#25 T5 AC5 XDP_TCK XDP_TRST# 1 2 1A
H_A#26 A[25]# TCK XDP_TDI R7 54.9_0402_1%
T3 A[26]# TDI AA6
H_A#27 W2 AB3 XDP_TDO
A[27]# TDO PAD T13

1
H_A#28 W5 AB5 XDP_TMS +1.05VS 1 2
H_A#29 A[28]# TMS XDP_TRST# R8 @ 56_0402_5%
Y4 A[29]# TRST# AB6 1SS355_SOD323-2
H_A#30 U2 C20 XDP_DBRESET# 1 2 2
A[30]# DBR# XDP_DBRESET# 23 D1
H_A#31 V4 R9 56_0402_5%
A[31]#

2
JFAN

B
H_A#32 W3 C3 @

2
H_A#33 AA4 A[32]# 10U_0805_10V4Z +FAN1
A[33]# THERMAL 1
1 1

E
C H_A#34 AB2 H_PROCHOT# 3 1 2 C
A[34]# OCP# 23 2

1
C
H_A#35 AA3 D21 H_PROCHOT# Q6 2 3
A[35]# PROCHOT# H_THERMDA @ MMBT3904_SOT23 U2 3
7 H_ADSTB#1 V1 ADSTB[1]# THERMDA A24
B25 H_THERMDC PROCHOT# PU: 68Ohm near CPU and MVP6. 1 8 D2 C4 4
H_A20M# THERMDC EN GND @ @ 1000P_0402_25V8J GND
22 H_A20M# A6 A20M# 56Ohm near CPU if no used. 2 VIN GND 7 5 GND
1
ICH

H_FERR# A5 C7 +FAN1 3 6
22 H_FERR# H_THERMTRIP# 8,22

2
H_IGNNE# FERR# THERMTRIP# VOUT GND
22 H_IGNNE# C4 IGNNE# 33 EN_DFAN1 4 VSET GND 5 ACES_85204-0300N
1 BAS16_SOT23-3 @
H_STPCLK# D5 10mil APL5607KI-TRG_SO8
22 H_STPCLK# STPCLK#
H_INTR C6 H CLK C5
22 H_INTR LINT0
H_NMI B4 A22 H_THERMDA, H_THERMDC routing together, 10U_0805_10V4Z R10 10K_0402_5%
22 H_NMI LINT1 BCLK[0] CLK_CPU_BCLK 16 2
H_SMI# A3 A21 2 1 +3VS
22 H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# 16 Trace width / Spacing = 10 / 10 mil
M4 RSVD[01] FAN_SPEED1 33
N5 RSVD[02] 1
T2 RSVD[03]
V3 C6 @
RSVD[04]
RESERVED

B2 0.01U_0402_25V7K
RSVD[05] 2
D2 RSVD[06]
D22 RSVD[07]
Reserve for D3 RSVD[08]
debug F6 RSVD[09]
close to South
Bridge
Penryn

H_FERR# 2 1
B C596 @ 180P_0402_50V8J B

H_SMI# 2 1
C597 @ 180P_0402_50V8J
H_INIT# 2 1
C598 @ 180P_0402_50V8J
H_NMI 2 1
C599 @ 180P_0402_50V8J
H_A20M# 2 1
C600 @ 180P_0402_50V8J
H_INTR 2 1
C601 @ 180P_0402_50V8J
H_IGNNE# 2 1
C602 @ 180P_0402_50V8J
H_STPCLK# 2 1
C603 @ 180P_0402_50V8J

Reserve for
debug
close to CPU
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 5 of 48
5 4 3 2 1
 5 4 3 2 1

@
JCPUD
A4 VSS[001] VSS[082] P6
A8 VSS[002] VSS[083] P21
A11 VSS[003] VSS[084] P24
A14 VSS[004] VSS[085] R2
7 H_D#[0..15] @ A16 R5
H_D#[32..47] 7 VSS[005] VSS[086]
JCPUB A19 R22
H_D#0 H_D#32 VSS[006] VSS[087]
E22 D[0]# D[32]# Y22 A23 VSS[007] VSS[088] R25
H_D#1 F24 AB24 H_D#33 AF2 T1
H_D#2 D[1]# D[33]# H_D#34 VSS[008] VSS[089]
E26 D[2]# D[34]# V24 B6 VSS[009] VSS[090] T4

DATA GRP 0
D H_D#3 G22 V26 H_D#35 B8 T23 D

DATA GRP 2
H_D#4 D[3]# D[35]# H_D#36 VSS[010] VSS[091]
F23 D[4]# D[36]# V23 B11 VSS[011] VSS[092] T26
H_D#5 G25 T22 H_D#37 B13 U3
H_D#6 D[5]# D[37]# H_D#38 VSS[012] VSS[093]
E25 D[6]# D[38]# U25 B16 VSS[013] VSS[094] U6
H_D#7 E23 U23 H_D#39 B19 U21
H_D#8 D[7]# D[39]# H_D#40 VSS[014] VSS[095]
K24 D[8]# D[40]# Y25 B21 VSS[015] VSS[096] U24
H_D#9 G24 W22 H_D#41 B24 V2
H_D#10 D[9]# D[41]# H_D#42 VSS[016] VSS[097]
J24 D[10]# D[42]# Y23 C5 VSS[017] VSS[098] V5
H_D#11 J23 W24 H_D#43 C8 V22
H_D#12 D[11]# D[43]# H_D#44 VSS[018] VSS[099]
H22 D[12]# D[44]# W25 C11 VSS[019] VSS[100] V25
H_D#13 F26 AA23 H_D#45 C14 W1
H_D#14 D[13]# D[45]# H_D#46 VSS[020] VSS[101]
K22 D[14]# D[46]# AA24 C16 VSS[021] VSS[102] W4
H_D#15 H23 AB25 H_D#47 C19 W23
D[15]# D[47]# VSS[022] VSS[103]
7 H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 7 C2 VSS[023] VSS[104] W26
7 H_DSTBP#0 H26 DSTBP[0]# DSTBP[2]# AA26 H_DSTBP#2 7 C22 VSS[024] VSS[105] Y3
7 H_DINV#0 H25 DINV[0]# DINV[2]# U22 H_DINV#2 7 C25 VSS[025] VSS[106] Y6
7 H_D#[16..31] H_D#[48..63] 7 D1 VSS[026] VSS[107] Y21
D4 VSS[027] VSS[108] Y24
H_D#16 N22 AE24 H_D#48 D8 AA2
H_D#17 D[16]# D[48]# H_D#49 VSS[028] VSS[109]
K25 D[17]# D[49]# AD24 D11 VSS[029] VSS[110] AA5
H_D#18 P26 AA21 H_D#50 D13 AA8
H_D#19 D[18]# D[50]# H_D#51 VSS[030] VSS[111]
R23 D[19]# D[51]# AB22 Resistor placed within D16 VSS[031] VSS[112] AA11
H_D#20 L23 AB21 H_D#52 D19 AA14
D[20]# D[52]# 0.5" of CPU pin.Trace VSS[032] VSS[113]

DATA GRP 1
H_D#21 M24 AC26 H_D#53 D23 AA16

DATA GRP 3
H_D#22 D[21]# D[53]# H_D#54 VSS[033] VSS[114]
L22 D[22]# D[54]# AD20 should be at least 25 D26 VSS[034] VSS[115] AA19
H_D#23 M23 AE22 H_D#55 E3 AA22
H_D#24 P25
D[23]# D[55]#
AF23 H_D#56 mils away from any other E6
VSS[035] VSS[116]
AA25
H_D#25 D[24]# D[56]# H_D#57 VSS[036] VSS[117]
P23 D[25]# D[57]# AC25 toggling signal. E8 VSS[037] VSS[118] AB1
H_D#26 P22 AE21 H_D#58 E11 AB4
C H_D#27 T24
D[26]# D[58]#
AD21 H_D#59 COMP[0,2] trace width is E14
VSS[038] VSS[119]
AB8 C
D[27]# D[59]# VSS[039] VSS[120]
+1.05VS Close to H_D#28 R24 D[28]# D[60]# AC22 H_D#60 18 mils. COMP[1,3] trace E16 VSS[040] VSS[121] AB11
CPU pin H_D#29 L25 AD23 H_D#61 E19 AB13
H_D#30 T25
D[29]# D[61]#
AF22 H_D#62 width is 4 mils. E21
VSS[041] VSS[122]
AB16
AD26 D[30]# D[62]# VSS[042] VSS[123]
1

H_D#31 N25 AC23 H_D#63 E24 AB19

within D[31]# D[63]# VSS[043] VSS[124]
7 H_DSTBN#1 L26 DSTBN[1]# DSTBN[3]# AE25 H_DSTBN#3 7 F5 VSS[044] VSS[125] AB23
R11 500mils. M26 AF24 COMP0 1 2 F8 AB26
7 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 7 VSS[045] VSS[126]
1K_0402_1% N24 AC20 R12 27.4_0402_1% F11 AC3
7 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 7 VSS[046] VSS[127]
COMP1 1 2 F13 AC6
2

+CPU_GTLREF +CPU_GTLREF COMP0 R13 54.9_0402_1% VSS[047] VSS[128]

AD26 GTLREF COMP[0] R26 F16 VSS[048] VSS[129] AC8
C23 MISC U26 COMP1 COMP2 1 2 F19 AC11
TEST1 COMP[1] VSS[049] VSS[130]
1

D25 AA1 COMP2 R15 27.4_0402_1% F2 AC14

TEST2 COMP[2] COMP3 COMP3 VSS[050] VSS[131]
C24 TEST3 COMP[3] Y1 1 2 F22 VSS[051] VSS[132] AC16
R17 AF26 R18 54.9_0402_1% F25 AC19
2K_0402_1% TEST4 H_DPRSTP# VSS[052] VSS[133]
AF1 TEST5 DPRSTP# E5 H_DPRSTP# 8,22,43 G4 VSS[053] VSS[134] AC21
A26 B5 H_DPSLP# G1 AC24
H_DPSLP# 22
2

TEST6 DPSLP# VSS[054] VSS[135]

C3 TEST7 DPWR# D24 H_DPWR# 7 G23 VSS[055] VSS[136] AD2
B22 D6 H_PWRGOOD G26 AD5
8,16 CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGOOD 22 VSS[056] VSS[137]
B23 D7 H_CPUSLP# H3 AD8
8,16 CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# 7 VSS[057] VSS[138]
8,16 CPU_BSEL2 C21 BSEL[2] PSI# AE6 H_PSI# 43 H6 VSS[058] VSS[139] AD11
layout note: Please use "Daisy Chain" H21 VSS[059] VSS[140] AD13
Penryn H24 AD16
to layout and the signal (H_DPRSTP#) J2
VSS[060] VSS[141]
AD19
VSS[061] VSS[142]
is routed from ICH9 to power IC, J5 VSS[062] VSS[143] AD22
J22 AD25
then to NB and CPU J25
VSS[063] VSS[144]
AE1
VSS[064] VSS[145]
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs K1 VSS[065] VSS[146] AE4
K4 VSS[066] VSS[147] AE8
K23 VSS[067] VSS[148] AE11
B B
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 K26 VSS[068] VSS[149] AE14
Reserve for L3 VSS[069] VSS[150] AE16
H_CPUSLP# 2 1 L6 AE19
C650 @ 180P_0402_50V8J debug L21
VSS[070] VSS[151]
AE23
H_PWRGOOD close to CPU VSS[071] VSS[152]
166 0 1 1 2 1 L24 VSS[072] VSS[153] AE26
C651 @ 180P_0402_50V8J M2 A2
H_DPRSTP# VSS[073] VSS[154]
2 1 M5 VSS[074] VSS[155] AF6
C652 180P_0402_50V8J M22 AF8
H_DPSLP# VSS[075] VSS[156]
200 0 1 0 2 1 M25 VSS[076] VSS[157] AF11
C653 @ 180P_0402_50V8J N1 AF13
VSS[077] VSS[158]
N4 VSS[078] VSS[159] AF16
N23 VSS[079] VSS[160] AF19
266 0 0 0 N26 VSS[080] VSS[161] AF21
P3 VSS[081] VSS[162] A25
VSS[163] AF25
Penryn
.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 6 of 48
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE
Near CPU CORE regulator
330U_D2_2VY_R7M 330U_D2_2VY_R7M +CPU_CORE
1 1 1 1

ESR <= 1.5m ohm C7

+
C8
+
C9
+
C10
+
1
C11
1
C12
1
C13
1
C14
1
C15
1
C16
1
C17
1
C18
Capacitor > 1980uF 2 2 2 2
Place these capacitors on L8
(North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
330U_D2_2VY_R7M 330U_D2_2VY_R7M 2 2 2 2 2 2 2 2

change highly to H1.9 for thermal type issue.

D D
+CPU_CORE +CPU_CORE +CPU_CORE
@
JCPUC
A7 AB20 330U_6.3V_M_R15 1 1 1 1 1 1 1 1
VCC[001] VCC[068] C19 C20 C21 C22 C23 C24 C25 C26
A9 VCC[002] VCC[069] AB7
A10 AC7 1 1 Place these capacitors on L8
VCC[003] VCC[070] (North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
A12 VCC[004] VCC[071] AC9
+ + 2 2 2 2 2 2 2 2
A13 VCC[005] VCC[072] AC12
A15 AC13 C79 C80
VCC[006] VCC[073] @ @
A17 VCC[007] VCC[074] AC15
2 2
A18 VCC[008] VCC[075] AC17
+CPU_CORE
A20 VCC[009] VCC[076] AC18
B7 AD7 330U_6.3V_M_R15
VCC[010] VCC[077]
B9 VCC[011] VCC[078] AD9
B10 VCC[012] VCC[079] AD10 1 1 1 1 1 1 1 1
B12 AD12 reserve for test C27 C28 C29 C30 C31 C32 C33 C34
VCC[013] VCC[080] Place these capacitors on L8
B14 VCC[014] VCC[081] AD14 please co-layout with C7~C10
B15 AD15 (Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VCC[015] VCC[082] 2 2 2 2 2 2 2 2
B17 VCC[016] VCC[083] AD17
B18 VCC[017] VCC[084] AD18
B20 VCC[018] VCC[085] AE9
C9 VCC[019] VCC[086] AE10
+CPU_CORE
C10 VCC[020] VCC[087] AE12
C12 VCC[021] VCC[088] AE13
C13 VCC[022] VCC[089] AE15
C15 VCC[023] VCC[090] AE17 1 1 1 1 1 1 1 1
C17 AE18 C35 C36 C37 C38 C39 C40 C41 C42
VCC[024] VCC[091] Place these capacitors on L8
C18 VCC[025] VCC[092] AE20
C D9 AF9 (Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M C
VCC[026] VCC[093] 2 2 2 2 2 2 2 2
D10 VCC[027] VCC[094] AF10
D12 VCC[028] VCC[095] AF12
D14 VCC[029] VCC[096] AF14
D15 VCC[030] VCC[097] AF15
D17 VCC[031] VCC[098] AF17 Mid Frequence Decoupling
D18 VCC[032] VCC[099] AF18
E7 AF20 +1.05VS
VCC[033] VCC[100]
E9 VCC[034]
E10 VCC[035] VCCP[01] G21
E12 VCC[036] VCCP[02] V6 1 Place these inside socket cavity on L8
E13 J6 +1.05VS (North side Secondary)
VCC[037] VCCP[03] + C43
E15 VCC[038] VCCP[04] K6
E17 M6 330U_D2_2VY_R7M
VCC[039] VCCP[05]
E18 VCC[040] VCCP[06] J21 1 1 1 1 1 1
2 C44 C45 C46 C47 C48 C49
E20 VCC[041] VCCP[07] K21
F7 VCC[042] VCCP[08] M21
F9 N21 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
VCC[043] VCCP[09] 2 2 2 2 2 2
F10 VCC[044] VCCP[10] N6
F12 VCC[045] VCCP[11] R21
F14 VCC[046] VCCP[12] R6
F15 VCC[047] VCCP[13] T21
F17 VCC[048] VCCP[14] T6
F18 VCC[049] VCCP[15] V21
F20 VCC[050] VCCP[16] W21
AA7 VCC[051] Near pin B26
AA9 VCC[052] VCCA[01] B26 +1.5VS
AA10 VCC[053] VCCA[02] C26 1 1
AA12 C51
B VCC[054] C50 B
AA13 VCC[055] VID[0] AD6 CPU_VID0 43
AA15 AF5 CPU_VID1 43 0.01U_0402_25V7K 10U_0805_6.3V6M
VCC[056] VID[1] 2 2
AA17 VCC[057] VID[2] AE5 CPU_VID2 43
AA18 VCC[058] VID[3] AF4 CPU_VID3 43
AA20 VCC[059] VID[4] AE3 CPU_VID4 43
AB9 VCC[060] VID[5] AF3 CPU_VID5 43
AC10 VCC[061] VID[6] AE2 CPU_VID6 43
AB10 VCC[062]
AB12 VCC[063]
AB14 AF7 VCCSENSE VCCSENSE 43
VCC[064] VCCSENSE
AB15 VCC[065]
AB17 VCC[066]
AB18 AE7 VSSSENSE VSSSENSE 43
VCC[067] VSSSENSE
Penryn
.

+CPU_CORE

VCCSENSE 100_0402_1% 2 1 R19

VSSSENSE 100_0402_1% 2 1 R20

A Close to CPU pin A

within 500mils.

Length match within 25 mils.

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
The trace width/space/other is SCHEMATIC,MB A4991
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
14/7/25. AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 7 of 48
5 4 3 2 1
 5 4 3 2 1

H_A#[3..35] 4
5 H_D#[0..63] U3A
A14 H_A#3
H_D#0 H_A#_3 H_A#4
F2 H_D#_0 H_A#_4 C15
H_D#1 G8 F16 H_A#5
H_D#2 H_D#_1 H_A#_5 H_A#6
F8 H_D#_2 H_A#_6 H13
H_D#3 E6 C18 H_A#7
H_D#4 H_D#_3 H_A#_7 H_A#8
G2 H_D#_4 H_A#_8 M16
H_D#5 H6 J13 H_A#9
H_D#6 H_D#_5 H_A#_9 H_A#10
H2 H_D#_6 H_A#_10 P16
D H_D#7 F6 R16 H_A#11 D
H_D#8 H_D#_7 H_A#_11 H_A#12
D4 H_D#_8 H_A#_12 N17
H_D#9 H3 M13 H_A#13
H_D#10 H_D#_9 H_A#_13 H_A#14
M9 H_D#_10 H_A#_14 E17
H_D#11 M11 P17 H_A#15
H_D#12 H_D#_11 H_A#_15 H_A#16
J1 H_D#_12 H_A#_16 F17
H_D#13 J2 G20 H_A#17
H_D#14 H_D#_13 H_A#_17 H_A#18
N12 H_D#_14 H_A#_18 B19
H_D#15 J6 J16 H_A#19
H_D#16 H_D#_15 H_A#_19 H_A#20
P2 H_D#_16 H_A#_20 E20
H_D#17 L2 H16 H_A#21
H_D#18 H_D#_17 H_A#_21 H_A#22
R2 H_D#_18 H_A#_22 J20
H_D#19 N9 L17 H_A#23
H_D#20 H_D#_19 H_A#_23 H_A#24
L6 H_D#_20 H_A#_24 A17
H_D#21 M5 B17 H_A#25
H_D#22 H_D#_21 H_A#_25 H_A#26
J3 H_D#_22 H_A#_26 L16
H_D#23 N2 C21 H_A#27
H_D#24 H_D#_23 H_A#_27 H_A#28
R1 H_D#_24 H_A#_28 J17
H_D#25 N5 H20 H_A#29
H_D#26 H_D#_25 H_A#_29 H_A#30
N6 H_D#_26 H_A#_30 B18
H_D#27 P13 K17 H_A#31
H_D#28 H_D#_27 H_A#_31 H_A#32
N8 H_D#_28 H_A#_32 B20
H_D#29 L7 F21 H_A#33
H_D#30 H_D#_29 H_A#_33 H_A#34
N10 H_D#_30 H_A#_34 K21
H_D#31 M3 L20 H_A#35
H_D#32 H_D#_31 H_A#_35
Y3 H_D#_32
H_D#33 AD14 H12
H_D#_33 H_ADS# H_ADS# 4
H_D#34 Y6 B16
H_D#_34 H_ADSTB#_0 H_ADSTB#0 4
H_D#35 Y10 G17
H_D#_35 H_ADSTB#_1 H_ADSTB#1 4
C H_D#36 Y12 A9 C
H_D#_36 H_BNR# H_BNR# 4

HOST
H_D#37 Y14 F11
H_D#_37 H_BPRI# H_BPRI# 4
H_D#38 Y7 G12
H_D#_38 H_BREQ# H_BR0# 4
H_D#39 W2 E9
H_D#_39 H_DEFER# H_DEFER# 4
H_D#40 AA8 B10
H_D#_40 H_DBSY# H_DBSY# 4
H_D#41 Y9 AH7
H_D#_41 HPLL_CLK CLK_MCH_BCLK 16
H_D#42 AA13 AH6
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# 16
H_D#43 AA9 J11
H_D#_43 H_DPWR# H_DPWR# 5
H_D#44 AA11 F9
H_D#_44 H_DRDY# H_DRDY# 4
H_D#45 AD11 H9
H_D#_45 H_HIT# H_HIT# 4
H_D#46 AD10 E12
H_D#_46 H_HITM# H_HITM# 4
H_D#47 AD13 H11
H_D#_47 H_LOCK# H_LOCK# 4
H_D#48 AE12 C9
H_D#_48 H_TRDY# H_TRDY# 4
H_D#49 AE9
H_D#50 H_D#_49
AA2 H_D#_50
H_D#51 AD8
H_D#52 H_D#_51
Layout Note: AA3 H_D#_52
H_D#53 AD3 J8
H_RCOMP / +H_VREF / H_SWNG H_D#_53 H_DINV#_0 H_DINV#0 5
H_D#54 AD7 L3
H_D#_54 H_DINV#_1 H_DINV#1 5
trace width and spacing is 10/20 H_D#55 AE14 Y13
H_D#_55 H_DINV#_2 H_DINV#2 5
H_D#56 AF3 Y1
H_D#_56 H_DINV#_3 H_DINV#3 5
within 100 mils from NB H_D#57 AC1
H_D#58 H_D#_57
AE3 H_D#_58 H_DSTBN#_0 L10 H_DSTBN#0 5
H_D#59 AC3 M7
+1.05VS +1.05VS H_D#_59 H_DSTBN#_1 H_DSTBN#1 5
H_D#60 AE11 AA5
H_D#_60 H_DSTBN#_2 H_DSTBN#2 5
H_D#61 AE8 AE6
H_D#_61 H_DSTBN#_3 H_DSTBN#3 5
H_D#62 AG2 H_D#_62
1

H_D#63 AD6 L9
H_D#_63 H_DSTBP#_0 H_DSTBP#0 5
R22 M8
B H_DSTBP#_1 H_DSTBP#1 5 B
R21 221_0402_1% AA6
H_DSTBP#_2 H_DSTBP#2 5
1K_0402_1% H_SWNG C5 AE5
H_SWING H_DSTBP#_3 H_DSTBP#3 5
H_SWING=0.3125*VCCP H_RCOMP E3
1 2

+H_VREF H_RCOMP H_SWNG H_RCOMP

H_REQ#_0 B15 H_REQ#0 4
H_REQ#_1 K13 H_REQ#1 4
1

1 1 H_REQ#_2 F13 H_REQ#2 4

R23 C52 R24 B13
H_REQ#_3 H_REQ#3 4
2K_0402_1% 0.1U_0402_16V4Z 24.9_0402_1% R25 C53 C12 B14
4 H_RESET# H_CPURST# H_REQ#_4 H_REQ#4 4
@ 100_0402_1% 0.1U_0402_16V4Z E11
5 H_CPUSLP#
2

2 2 H_CPUSLP#
B6 H_RS#0 4
2

H_RS#_0
H_RS#_1 F12 H_RS#1 4
Near B3 pin +H_VREF A11 C8
H_AVREF H_RS#_2 H_RS#2 4
B11 H_DVREF
CANTIGA ES_FCBGA1329
G7R3@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 8 of 48
5 4 3 2 1
 5 4 3 2 1

Strap Pin Table U3B +1.8V

011 = FSB667
CFG[2:0] 010 = FSB800 M36 RSVD1 SA_CK_0 AP24 DDRA_CLK0 14

1
000 = FSB1067 N36 RSVD2 SA_CK_1 AT21 DDRA_CLK1 14
R33 AV24 R26
RSVD3 SB_CK_0 DDRB_CLK0 15
0 = DMI x 2 T33 AU20 1K_0402_1%

COMPENSATION
RSVD4 SB_CK_1 DDRB_CLK1 15
CFG5 Internal pull-up 1 = DMI x 4 *(Default) AH9 RSVD5
AH10 AR24 DDRA_CLK0# 14

2
RSVD6 SA_CK#_0 +SM_RCOMP_VOH
0 = iTPM Host Interface is enabled can support disble by SW. AH12 RSVD7 SA_CK#_1 AR21 DDRA_CLK1# 14
CFG6 Internal pull-up 1 = iTPM Host Interface is Disabled *(Default) AH13 RSVD8 SB_CK#_0 AU24 DDRB_CLK0# 15
K12 RSVD9 SB_CK#_1 AV20 DDRB_CLK1# 15 1 1

1
0 = Intel Management Engine Crypto Transport Layer Security AL34 0.01U_0402_25V7K 2.2U_0603_6.3V6K
RSVD10 C54 C55
AK34 RSVD11 SA_CKE_0 BC28 DDRA_CKE0 14
(TLS) cipher suite with no confidentiality AN35 AY28 DDRA_CKE1 14
R27
D RSVD12 SA_CKE_1 2 2 3.01K_0402_1% D
CFG7 Internal pull-up AM35 RSVD13 SB_CKE_0 AY36 DDRB_CKE0 15 SM_DRAMRST# would be
1 = Intel Management Engine Crypto TLS cipher suite with T24 BB36 DDRB_CKE1 15 needed for DDR3 only

2
RSVD14 SB_CKE_1
confidentiality *(Default) BA17 DDRA_SCS0# 14
SA_CS#_0 +SM_RCOMP_VOL
SA_CS#_1 AY16 DDRA_SCS1# 14
0 = Lane Reversal Enable B31 RSVD15 SB_CS#_0 AV16 DDRB_SCS0# 15 For Cantiga 80 Ohm

1
CFG9 Internal pull-up 1 = Normal Operation *(Default) B2 RSVD16 SB_CS#_1 AR13 DDRB_SCS1# 15 1 1

DDR CLK/ CONTROL/

M1 0.01U_0402_25V7K 2.2U_0603_6.3V6K
RSVD17

RSVD
0 = PCIe Loopback Enable BD17 C56 C57 R28
SA_ODT_0 DDRA_ODT0 14
CFG10 Internal pull-up 1 = Disable*(Default) AY17 1K_0402_1%
SA_ODT_1 DDRA_ODT1 14 2 2
AY21 BF15 DDRB_ODT0 15

2
RSVD20 SB_ODT_O +1.8V +1.8V
01 = All Z Mode Enabled SB_ODT_1 AY13 DDRB_ODT1 15
CFG[13:12] 00 = Reserved
10 = XOR Mode Enabled BG22 SMRCOMP R29 1 2 80.6_0402_1%
SM_RCOMP

2
Internal pull-up 11 = Normal Operation*(Default) BG23 BH21 SMRCOMP# R30 1 2 80.6_0402_1%
RSVD22 SM_RCOMP# R31
BF23 RSVD23
0 = Dynamic ODT Disabled BH18 BF28 +SM_RCOMP_VOH 1K_0402_1%
RSVD24 SM_RCOMP_VOH +SM_RCOMP_VOL
CFG16 Internal pull-up 1 = Dynamic ODT Enabled *(Default) BF18 RSVD25 SM_RCOMP_VOL BH28
20mil

1
0 = Normal Operation AV42 +SM_VREF
SM_VREF SM_PWROK R32
CFG19 Internal pull-down 1 = DMI Lane Reversal Enable *(Default) SM_PWROK AR36 1 2 0_0402_5%

2
BF17 SM_REXT R33 1 2 499_0402_1% 1
SM_REXT R34
CFG20 0 = Only PCIE or [SDVO/DP/HDMI] is operational. * (Default) SM_DRAMRST# BC36
C58
Internal pull-down 1K_0402_1%
(PCIE/SDVO select) 1 = PCIE/[SDVO/DP/HDMI] are operating simu. 0.1U_0402_16V4Z
CLK_DREF_96M 2 @
B38 CLK_DREF_96M 16

1
DPLL_REF_CLK CLK_DREF_96M# CLK_DREF_96M PM@
DPLL_REF_CLK# A38 CLK_DREF_96M# 16 1 2
E41 CLK_DREF_SSC R575 0_0402_5%
DPLL_REF_SSCLK CLK_DREF_SSC 16
F41 CLK_DREF_SSC# CLK_DREF_96M# 1 PM@ 2
DPLL_REF_SSCLK# CLK_DREF_SSC# 16
R576 0_0402_5%

CLK
F43 CLK_DREF_SSC 1 PM@ 2
PEG_CLK CLK_MCH_3GPLL 16
E43 R577 0_0402_5%
C PEG_CLK# CLK_MCH_3GPLL# 16 C
CLK_DREF_SSC# 1 PM@ 2
R578 0_0402_5%

DMI_RXN_0 AE41 DMI_ITX_MRX_N0 21

DMI_RXN_1 AE37 DMI_ITX_MRX_N1 21 Please place these resistors close to related balls
DMI_RXN_2 AE47 DMI_ITX_MRX_N2 21
AH39 +1.05VS
DMI_RXN_3 DMI_ITX_MRX_N3 21

DMI_RXP_0 AE40 DMI_ITX_MRX_P0 21

R35 2 1 1K_0402_5% MCH_CLKSEL0 T25 AE38
5,16 CPU_BSEL0 CFG_0 DMI_RXP_1 DMI_ITX_MRX_P1 21

1
R36 2 1 1K_0402_5% MCH_CLKSEL1 R25 AE48 +3VS
5,16 CPU_BSEL1 CFG_1 DMI_RXP_2 DMI_ITX_MRX_P2 21
R37 2 1 1K_0402_5% MCH_CLKSEL2 P25 AH40 R38
5,16 CPU_BSEL2 CFG_2 DMI_RXP_3 DMI_ITX_MRX_P3 21
P20 Lane reversal 1K_0402_5%
T1 PAD CFG_3
T2 PAD P24 CFG_4 DMI_TXN_0 AE35 DMI_MTX_IRX_N0 21

1
R39 2@ 2.21K_0402_1% MCH_CFG_5

DMI
1 C25 AE43 DMI_MTX_IRX_N1 21

2
R40 MCH_CFG_6 CFG_5 DMI_TXN_1
1 2@ 2.21K_0402_1% N24 CFG_6 DMI_TXN_2 AE46 DMI_MTX_IRX_N2 21
R41 R42
R43 1 2@ 2.21K_0402_1% MCH_CFG_7 M24 AH42 54.9_0402_1% 1K_0402_5%
CFG_7 DMI_TXN_3 DMI_MTX_IRX_N3 21

2
CFG

B
E21 CFG_8
R44 1 2@ 2.21K_0402_1% MCH_CFG_9 C23 AD35 DMI_MTX_IRX_P0 21

2
CFG_9 DMI_TXP_0

E
R45 1 2@ 2.21K_0402_1% MCH_CFG_10 C24 AE44 MCH_TSATN# 3 1 MCH_TSATN_EC# 33
CFG_10 DMI_TXP_1 DMI_MTX_IRX_P1 21

C
N21 AF46 Q7
CFG_11 DMI_TXP_2 DMI_MTX_IRX_P2 21
R46 1 2@ 2.21K_0402_1% MCH_CFG_12 P21 AH43 MMBT3904_SOT23-3
CFG_12 DMI_TXP_3 DMI_MTX_IRX_P3 21
R47 1 2@ 2.21K_0402_1% MCH_CFG_13 T21 CFG_13
R20 CFG_14
M20 CFG_15
+3VS R48 1 2@ 2.21K_0402_1% MCH_CFG_16 L21 CFG_16
H21 CFG_17
P29

GRAPHICS VID
T12 PAD CFG_18
R49 1 2 4.02K_0402_1% MCH_CFG_19 R28
R50 1 2@ 4.02K_0402_1% MCH_CFG_20 T28
CFG_19
CFG_20 GFX_VID_0 B33 Strap Pin Table
GFX_VID_1 B32
B GFX_VID_2 G33 SDVO_CTRLDATA 0 = SDVO interface disabled *(Default) B
GFX_VID_3 F33 (Internal pull-down) 1 = SDVO interface enabled
23 PM_SYNC# R51 1 2 0_0402_5% PM_SYNC#_R R29 E33
PM_SYNC# GFX_VID_4
+3VS 1 2 PM_EXTTS#_R 5,22,43 H_DPRSTP# B7 PM_DPRSTP# DDPC_CTRLDATA 0 = Digital display (iHDMI/DP) interface disabled
R52 10K_0402_5% (Internal pull-down) 1 = Digital display (iHDMI/DP) interface enabled
N33 PM_EXT_TS#_0 *(Default)
PM

14,15 PM_EXTTS# R53 1 2 0_0402_5% PM_EXTTS#_R P32

GMCH_PWROK PM_EXT_TS#_1
AT40 PWROK GFX_VR_EN C34
17,21,26,28,29,32,33,34 PLT_RST# R54 1 2 100_0402_5% MCH_RSTIN# AT11 RSTIN#
R55 1 2 0_0402_5% NB_THERMTRIP# T20 +1.05VS
4,22 H_THERMTRIP# THERMTRIP#
R56 1 2 0_0402_5% DPRSLPVR R32
23,43 PM_DPRSLPVR DPRSLPVR

2
BG48 AH37 R57
NC_1 CL_CLK CL_CLK0 23
Use VGATE for GMCH_PWROK BF48 AH36 1K_0402_1%
NC_2 CL_DATA CL_DATA0 23
ME

BD48 AN36 ICH_PWROK Width:Spacing

GMCH_PWROK NC_3 CL_PWROK
23,33,43 VGATE 1 2 BC48 AJ35 CL_RST#0 23 12mil:12mil CL_VREF

1
R58 @ 0_0402_5% NC_4 CL_RST# +CL_VREF R61 PM@
BH47 NC_5 CL_VREF AH34 should be
1 2 BG47 +CL_VREF=0.355V 0_0402_5%
23 ICH_PWROK NC_6 0.35 V

2
R59 0_0402_5% BE47 1 R62 PM@
NC_7 DP_CLK C59 R60 0_0402_5%
BH46 NC_8 DDPC_CTRLCLK N28 DP_CLK 10
NC

BF46 M28 DP_DATA 0.1U_0402_16V4Z 499_0402_1%

NC_9 DDPC_CTRLDATA DP_DATA 10
BG45 G36 SDVO_SCLK
NC_10 SDVO_CTRLCLK SDVO_SCLK 20 2
BH44 E36 SDVO_SDATA
SDVO_SDATA 20

1
NC_11 SDVO_CTRLDATA +3VS
BH43 NC_12 CLKREQ# K36 CLKREQ_3GPLL# 16
MISC

BH6 NC_13 ICH_SYNC# H36 MCH_ICH_SYNC# 23

BH5 SDVO_SCLK 2 1 2.2K_0402_5% 1 GM@ 2
NC_14 R61 GM@ R579 0_0402_5%
BG4 NC_15
BH3 B12 MCH_TSATN# SDVO_SDATA 2 1 2.2K_0402_5% 1 PM@ 2
NC_16 TSATN# R62 IHDMI@ R580 0_0402_5%
BF3 NC_17
BH2 NC_18
BG2 NC_19
the strap pin will impact no IHDMI SKU if mount R62
BE2 NC_20 HDA_BCLK B28 AZ_BITCLK_MCH 22
BG1 NC_21 HDA_RST# B30 AZ_RST_MCH# 22
A AZ_SDIN2_MCH_R A
BF1 NC_22 HDA_SDI B29 1 2 AZ_SDIN2_MCH 22
BD1 C29 R63
AZ_SDOUT_MCH 22 33_0402_5%
NC_23 HDA_SDO IHDMI@ IHDMI@ RA35 C66 IHDMI@
BC1 A28
HDA

NC_24 HDA_SYNC AZ_SYNC_MCH 22

F1 AZ_BITCLK_MCH 1 2 2 1
NC_25 0_0402_5%
A47 NC_26 33P_0402_50V8K
CANTIGA ES_FCBGA1329
G7R3@ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 9 of 48
5 4 3 2 1
 5 4 3 2 1

D D
14 DDR_A_D[0..63] 15 DDR_B_D[0..63]
U3D U3E
DDR_A_D0 AJ38 BD21 DDR_B_D0 AK47 BC16
SA_DQ_0 SA_BS_0 DDR_A_BS0 14 SB_DQ_0 SB_BS_0 DDR_B_BS0 15
DDR_A_D1 AJ41 BG18 DDR_B_D1 AH46 BB17
SA_DQ_1 SA_BS_1 DDR_A_BS1 14 SB_DQ_1 SB_BS_1 DDR_B_BS1 15
DDR_A_D2 AN38 AT25 DDR_B_D2 AP47 BB33
SA_DQ_2 SA_BS_2 DDR_A_BS2 14 SB_DQ_2 SB_BS_2 DDR_B_BS2 15
DDR_A_D3 AM38 DDR_B_D3 AP46
DDR_A_D4 SA_DQ_3 DDR_B_D4 SB_DQ_3
AJ36 SA_DQ_4 SA_RAS# BB20 DDR_A_RAS# 14 AJ46 SB_DQ_4
DDR_A_D5 AJ40 BD20 DDR_B_D5 AJ48 AU17
SA_DQ_5 SA_CAS# DDR_A_CAS# 14 SB_DQ_5 SB_RAS# DDR_B_RAS# 15
DDR_A_D6 AM44 AY20 DDR_B_D6 AM48 BG16
SA_DQ_6 SA_WE# DDR_A_WE# 14 SB_DQ_6 SB_CAS# DDR_B_CAS# 15
DDR_A_D7 AM42 DDR_B_D7 AP48 BF14
SA_DQ_7 SB_DQ_7 SB_WE# DDR_B_WE# 15
DDR_A_D8 AN43 DDR_B_D8 AU47
DDR_A_D9 SA_DQ_8 DDR_B_D9 SB_DQ_8
AN44 SA_DQ_9 AU46 SB_DQ_9
DDR_A_D10 AU40 DDR_B_D10 BA48
DDR_A_D11 SA_DQ_10 DDR_B_D11 SB_DQ_10
AT38 SA_DQ_11 DDR_A_DM[0..7] 14 AY48 SB_DQ_11
DDR_A_D12 AN41 DDR_B_D12 AT47
DDR_A_D13 SA_DQ_12 DDR_A_DM0 DDR_B_D13 SB_DQ_12
AN39 SA_DQ_13 SA_DM_0 AM37 AR47 SB_DQ_13
DDR_A_D14 AU44 AT41 DDR_A_DM1 DDR_B_D14 BA47
SA_DQ_14 SA_DM_1 SB_DQ_14 DDR_B_DM[0..7] 15
DDR_A_D15 AU42 AY41 DDR_A_DM2 DDR_B_D15 BC47 AM47 DDR_B_DM0
DDR_A_D16 SA_DQ_15 SA_DM_2 DDR_A_DM3 DDR_B_D16 SB_DQ_15 SB_DM_0 DDR_B_DM1
AV39 SA_DQ_16 SA_DM_3 AU39 BC46 SB_DQ_16 SB_DM_1 AY47
DDR_A_D17 AY44 BB12 DDR_A_DM4 DDR_B_D17 BC44 BD40 DDR_B_DM2
DDR_A_D18 SA_DQ_17 SA_DM_4 DDR_A_DM5 DDR_B_D18 SB_DQ_17 SB_DM_2 DDR_B_DM3
BA40 SA_DQ_18 SA_DM_5 AY6 BG43 SB_DQ_18 SB_DM_3 BF35
DDR_A_D19 BD43 AT7 DDR_A_DM6 DDR_B_D19 BF43 BG11 DDR_B_DM4
DDR_A_D20 SA_DQ_19 SA_DM_6 DDR_A_DM7 DDR_B_D20 SB_DQ_19 SB_DM_4 DDR_B_DM5
AV41 SA_DQ_20 SA_DM_7 AJ5 BE45 SB_DQ_20 SB_DM_5 BA3
DDR_A_D21 AY43 DDR_B_D21 BC41 AP1 DDR_B_DM6

B
SA_DQ_21 SB_DQ_21 SB_DM_6

A
DDR_A_D22 BB41 DDR_B_D22 BF40 AK2 DDR_B_DM7
SA_DQ_22 DDR_A_DQS[0..7] 14 SB_DQ_22 SB_DM_7
DDR_A_D23 BC40 AJ44 DDR_A_DQS0 DDR_B_D23 BF41
DDR_A_D24 SA_DQ_23 SA_DQS_0 DDR_A_DQS1 DDR_B_D24 SB_DQ_23
AY37 SA_DQ_24 SA_DQS_1 AT44 BG38 SB_DQ_24 DDR_B_DQS[0..7] 15
DDR_A_D25 BD38 BA43 DDR_A_DQS2 DDR_B_D25 BF38 AL47 DDR_B_DQS0
SA_DQ_25 SA_DQS_2 SB_DQ_25 SB_DQS_0

MEMORY
C DDR_A_D26 DDR_A_DQS3 DDR_B_D26 DDR_B_DQS1 C
MEMORY
AV37 SA_DQ_26 SA_DQS_3 BC37 BH35 SB_DQ_26 SB_DQS_1 AV48
DDR_A_D27 AT36 AW12 DDR_A_DQS4 DDR_B_D27 BG35 BG41 DDR_B_DQS2
DDR_A_D28 SA_DQ_27 SA_DQS_4 DDR_A_DQS5 DDR_B_D28 SB_DQ_27 SB_DQS_2 DDR_B_DQS3
AY38 SA_DQ_28 SA_DQS_5 BC8 BH40 SB_DQ_28 SB_DQS_3 BG37
DDR_A_D29 BB38 AU8 DDR_A_DQS6 DDR_B_D29 BG39 BH9 DDR_B_DQS4
DDR_A_D30 SA_DQ_29 SA_DQS_6 DDR_A_DQS7 DDR_B_D30 SB_DQ_29 SB_DQS_4 DDR_B_DQS5
AV36 SA_DQ_30 SA_DQS_7 AM7 BG34 SB_DQ_30 SB_DQS_5 BB2
DDR_A_D31 AW36 DDR_B_D31 BH34 AU1 DDR_B_DQS6
DDR_A_D32 SA_DQ_31 DDR_B_D32 SB_DQ_31 SB_DQS_6 DDR_B_DQS7
BD13 SA_DQ_32 DDR_A_DQS#[0..7] 14 BH14 SB_DQ_32 SB_DQS_7 AN6
DDR_A_D33 AU11 AJ43 DDR_A_DQS#0 DDR_B_D33 BG12
DDR_A_D34 SA_DQ_33 SA_DQS#_0 SB_DQ_33
BC11 SA_DQ_34 SA_DQS#_1 AT43 DDR_A_DQS#1 DDR_B_D34 BH11 SB_DQ_34 DDR_B_DQS#[0..7] 15
DDR_A_D35 BA12 BA44 DDR_A_DQS#2 DDR_B_D35 BG8 AL46 DDR_B_DQS#0
SA_DQ_35 SA_DQS#_2 SB_DQ_35 SB_DQS#_0

SYSTEM
DDR_A_D36
SYSTEM

AU13 SA_DQ_36 SA_DQS#_3 BD37 DDR_A_DQS#3 DDR_B_D36 BH12 SB_DQ_36 SB_DQS#_1 AV47 DDR_B_DQS#1
DDR_A_D37 AV13 AY12 DDR_A_DQS#4 DDR_B_D37 BF11 BH41 DDR_B_DQS#2
DDR_A_D38 SA_DQ_37 SA_DQS#_4 SB_DQ_37 SB_DQS#_2
BD12 SA_DQ_38 SA_DQS#_5 BD8 DDR_A_DQS#5 DDR_B_D38 BF8 SB_DQ_38 SB_DQS#_3 BH37 DDR_B_DQS#3
DDR_A_D39 BC12 AU9 DDR_A_DQS#6 DDR_B_D39 BG7 BG9 DDR_B_DQS#4
DDR_A_D40 SA_DQ_39 SA_DQS#_6 SB_DQ_39 SB_DQS#_4
BB9 SA_DQ_40 SA_DQS#_7 AM8 DDR_A_DQS#7 DDR_B_D40 BC5 SB_DQ_40 SB_DQS#_5 BC2 DDR_B_DQS#5
DDR_A_D41 BA9 DDR_B_D41 BC6 AT2 DDR_B_DQS#6
DDR_A_D42 SA_DQ_41 DDR_B_D42 SB_DQ_41 SB_DQS#_6
AU10 SA_DQ_42 DDR_A_MA[0..14] 14 AY3 SB_DQ_42 SB_DQS#_7 AN5 DDR_B_DQS#7
DDR_A_D43 AV9 DDR_B_D43 AY1
DDR_A_D44 SA_DQ_43 DDR_A_MA0 DDR_B_D44 SB_DQ_43
BA11 SA_DQ_44 SA_MA_0 BA21 BF6 SB_DQ_44 DDR_B_MA[0..14] 15
DDR_A_D45 BD9 BC24 DDR_A_MA1 DDR_B_D45 BF5 AV17 DDR_B_MA0

DDR
SA_DQ_45 SA_MA_1 SB_DQ_45 SB_MA_0
DDR

DDR_A_D46 AY8 BG24 DDR_A_MA2 DDR_B_D46 BA1 BA25 DDR_B_MA1

DDR_A_D47 SA_DQ_46 SA_MA_2 DDR_A_MA3 DDR_B_D47 SB_DQ_46 SB_MA_1 DDR_B_MA2
BA6 SA_DQ_47 SA_MA_3 BH24 BD3 SB_DQ_47 SB_MA_2 BC25
DDR_A_D48 AV5 BG25 DDR_A_MA4 DDR_B_D48 AV2 AU25 DDR_B_MA3
DDR_A_D49 SA_DQ_48 SA_MA_4 DDR_A_MA5 DDR_B_D49 SB_DQ_48 SB_MA_3 DDR_B_MA4
AV7 SA_DQ_49 SA_MA_5 BA24 AU3 SB_DQ_49 SB_MA_4 AW25
DDR_A_D50 AT9 BD24 DDR_A_MA6 DDR_B_D50 AR3 BB28 DDR_B_MA5
DDR_A_D51 SA_DQ_50 SA_MA_6 DDR_A_MA7 DDR_B_D51 SB_DQ_50 SB_MA_5 DDR_B_MA6
AN8 SA_DQ_51 SA_MA_7 BG27 AN2 SB_DQ_51 SB_MA_6 AU28
DDR_A_D52 AU5 BF25 DDR_A_MA8 DDR_B_D52 AY2 AW28 DDR_B_MA7
DDR_A_D53 SA_DQ_52 SA_MA_8 DDR_A_MA9 DDR_B_D53 SB_DQ_52 SB_MA_7 DDR_B_MA8
AU6 SA_DQ_53 SA_MA_9 AW24 AV1 SB_DQ_53 SB_MA_8 AT33
DDR_A_D54 AT5 BC21 DDR_A_MA10 DDR_B_D54 AP3 BD33 DDR_B_MA9
B DDR_A_D55 SA_DQ_54 SA_MA_10 DDR_A_MA11 DDR_B_D55 SB_DQ_54 SB_MA_9 DDR_B_MA10 B
AN10 SA_DQ_55 SA_MA_11 BG26 AR1 SB_DQ_55 SB_MA_10 BB16
DDR_A_D56 AM11 BH26 DDR_A_MA12 DDR_B_D56 AL1 AW33 DDR_B_MA11
DDR_A_D57 SA_DQ_56 SA_MA_12 DDR_A_MA13 DDR_B_D57 SB_DQ_56 SB_MA_11 DDR_B_MA12
AM5 SA_DQ_57 SA_MA_13 BH17 AL2 SB_DQ_57 SB_MA_12 AY33
DDR_A_D58 AJ9 AY25 DDR_A_MA14 DDR_B_D58 AJ1 BH15 DDR_B_MA13
DDR_A_D59 SA_DQ_58 SA_MA_14 DDR_B_D59 SB_DQ_58 SB_MA_13 DDR_B_MA14
AJ8 SA_DQ_59 AH1 SB_DQ_59 SB_MA_14 AU33
DDR_A_D60 AN12 DDR_B_D60 AM2
DDR_A_D61 SA_DQ_60 DDR_B_D61 SB_DQ_60
AM13 SA_DQ_61 AM3 SB_DQ_61
DDR_A_D62 AJ11 DDR_B_D62 AH3
DDR_A_D63 SA_DQ_62 DDR_B_D63 SB_DQ_62
AJ12 SA_DQ_63 AJ3 SB_DQ_63
CANTIGA ES_FCBGA1329 CANTIGA ES_FCBGA1329
G7R3@ G7R3@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 10 of 48
5 4 3 2 1
 5 4 3 2 1

PCIE_GTX_C_MRX_N[0..15] PCIE_GTX_C_MRX_N[0..15] 17
+3VS U3C
within 500 mils PCIE_GTX_C_MRX_P[0..15] PCIE_GTX_C_MRX_P[0..15] 17
1 2 1 GM@ 2 LCTLA_CLK L32
R499GM@ 0_0402_5% R64 10K_0402_5% L_BKLT_CTRL PEG_COMP 1 PCIE_MTX_C_GRX_N[0..15]
33 UMA_ENBKL G32 L_BKLT_EN PEG_COMPI T37 2 +1.05VS PCIE_MTX_C_GRX_N[0..15] 17,20
1 GM@ 2 LCTLB_DATA LCTLA_CLK M32 T36 R65 49.9_0402_1%
R66 10K_0402_5% LCTLB_DATA L_CTRL_CLK PEG_COMPO PCIE_MTX_C_GRX_P[0..15]
GM@ UMA_LCD_EDID_CLK
M33
UMA_LCD_EDID_CLK K33 L_CTRL_DATA 10mils PCIE_MTX_C_GRX_P[0..15] 17,20
1 2 18 UMA_LCD_EDID_CLK L_DDC_CLK
R67 2.2K_0402_5% 18 UMA_LCD_EDID_DATA UMA_LCD_EDID_DATAJ33 H44 PCIE_GTX_C_MRX_N0
GM@ UMA_LCD_EDID_DATA UMA_ENVDD L_DDC_DATA PEG_RX#_0 PCIE_GTX_C_MRX_N1
1 2 1 2 18 UMA_ENVDD M29 L_VDD_EN PEG_RX#_1 J46
R500PM@ 0_0402_5% R68 2.2K_0402_5% L44 PCIE_GTX_C_MRX_N2
R69 1 GM@ PEG_RX#_2
2 LVDS_IBG C44 LVDS_IBG PEG_RX#_3 L40 PCIE_GTX_C_MRX_N3
D 2.37K_0402_1% Spacing=20mil B43 N41 PCIE_GTX_C_MRX_N4 D
R501 1 GM@ LVDS_VBG PEG_RX#_4
2 0_0402_5% E37 LVDS_VREFH PEG_RX#_5 P48 PCIE_GTX_C_MRX_N5
L_DDC_DATA R502 1 GM@ 2 0_0402_5% E38 N44 PCIE_GTX_C_MRX_N6
LVDS_VREFL PEG_RX#_6 PCIE_GTX_C_MRX_N7
PEG_RX#_7 T43
0 = LFP Disable PCIE_GTX_C_MRX_N8
*(Default) 18 UMA_LCD_TXCLK- C41 LVDSA_CLK# PEG_RX#_8 U43
PCIE_GTX_C_MRX_N9
1 = LFP Card Present; PCIE disable 18 UMA_LCD_TXCLK+ C40 LVDSA_CLK PEG_RX#_9 Y43
PCIE_GTX_C_MRX_N10
18 UMA_LCD_TZCLK- B37 LVDSB_CLK# PEG_RX#_10 Y48
A37 Y36 PCIE_GTX_C_MRX_N11
18 UMA_LCD_TZCLK+ LVDSB_CLK PEG_RX#_11

LVDS
AA43 PCIE_GTX_C_MRX_N12
R64 PM@ PEG_RX#_12 PCIE_GTX_C_MRX_N13
18 UMA_LCD_TXOUT0- H47 LVDSA_DATA#_0 PEG_RX#_13 AD37
0_0402_5% E46 AC47 PCIE_GTX_C_MRX_N14
18 UMA_LCD_TXOUT1- LVDSA_DATA#_1 PEG_RX#_14
R66 PM@ G40 AD39 PCIE_GTX_C_MRX_N15
18 UMA_LCD_TXOUT2- LVDSA_DATA#_2 PEG_RX#_15
0_0402_5% A40
R67 PM@ LVDSA_DATA#_3 PCIE_GTX_C_MRX_P0
PEG_RX_0 H43
0_0402_5% H48 J44 PCIE_GTX_C_MRX_P1 C612 IHDMI@ C611 IHDMI@
18 UMA_LCD_TXOUT0+ LVDSA_DATA_0 PEG_RX_1
R68 PM@ D45 L43 PCIE_GTX_C_MRX_P2 0_0402_5% 0_0402_5%
18 UMA_LCD_TXOUT1+ LVDSA_DATA_1 PEG_RX_2

GRAPHICS
0_0402_5% F40 L41 PCIE_GTX_C_MRX_P3
18 UMA_LCD_TXOUT2+ LVDSA_DATA_2 PEG_RX_3
B40 N40 PCIE_GTX_C_MRX_P4 C614 IHDMI@ C613 IHDMI@
LVDSA_DATA_3 PEG_RX_4 PCIE_GTX_C_MRX_P5 0_0402_5% 0_0402_5%
PEG_RX_5 P47
A41 N43 PCIE_GTX_C_MRX_P6
18 UMA_LCD_TZOUT0- LVDSB_DATA#_0 PEG_RX_6
H38 T42 PCIE_GTX_C_MRX_P7 C628 IHDMI@ C627 IHDMI@
18 UMA_LCD_TZOUT1- LVDSB_DATA#_1 PEG_RX_7
G37 U42 PCIE_GTX_C_MRX_P8 0_0402_5% 0_0402_5%
18 UMA_LCD_TZOUT2- LVDSB_DATA#_2 PEG_RX_8
J37 Y42 PCIE_GTX_C_MRX_P9
LVDSB_DATA#_3 PEG_RX_9 PCIE_GTX_C_MRX_P10 C630 IHDMI@ C629 IHDMI@
PEG_RX_10 W47
B42 Y37 PCIE_GTX_C_MRX_P11 0_0402_5% 0_0402_5%
18 UMA_LCD_TZOUT0+ LVDSB_DATA_0 PEG_RX_11
G38 AA42 PCIE_GTX_C_MRX_P12
18 UMA_LCD_TZOUT1+ LVDSB_DATA_1 PEG_RX_12
F37 AD36 PCIE_GTX_C_MRX_P13
18 UMA_LCD_TZOUT2+ LVDSB_DATA_2 PEG_RX_13
K37 AC48 PCIE_GTX_C_MRX_P14
LVDSB_DATA_3 PEG_RX_14

PCI-EXPRESS
AD40 PCIE_GTX_C_MRX_P15
C
PEG_RX_15 C
J41 PCIE_MTX_GRX_N0 C611 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N0
R70 PM@ PEG_TX#_0
1 GM@ 2 TV_COMPS PEG_TX#_1 M46 PCIE_MTX_GRX_N1 C612 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N1
0_0402_5% R70 75_0402_1% TV_COMPS F25 M47 PCIE_MTX_GRX_N2 C613 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N2
R71 PM@ TVA_DAC PEG_TX#_2
1 GM@ 2 TV_LUMA TV_LUMA H25 TVB_DAC PEG_TX#_3 M40 PCIE_MTX_GRX_N3 C614 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N3
0_0402_5% R71 75_0402_1% TV_CRMA K25 M42 PCIE_MTX_GRX_N4 C615 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N4
R72 PM@ TVC_DAC PEG_TX#_4
1 GM@ 2 TV_CRMA PEG_TX#_5 R48 PCIE_MTX_GRX_N5 C616 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N5

TV
0_0402_5% R72 75_0402_1% H24 N38 PCIE_MTX_GRX_N6 C617 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6
TV_RTN PEG_TX#_6 PCIE_MTX_GRX_N7 C618 1
PEG_TX#_7 T40 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N7
U37 PCIE_MTX_GRX_N8 C619 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N8
PEG_TX#_8 PCIE_MTX_GRX_N9 C620 1
PEG_TX#_9 U40 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N9
C31 Y40 PCIE_MTX_GRX_N10 C621 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N10
TV_DCONSEL_0 PEG_TX#_10 PCIE_MTX_GRX_N11 C622 1
E32 TV_DCONSEL_1 PEG_TX#_11 AA46 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N11
AA37 PCIE_MTX_GRX_N12 C623 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N12
PEG_TX#_12 PCIE_MTX_GRX_N13 C624 1
PEG_TX#_13 AA40 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N13
R73 PM@ 1 GM@ 2 UMA_CRT_B AD43 PCIE_MTX_GRX_N14 C625 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N14
0_0402_5% R73 75_0402_1% PEG_TX#_14 PCIE_MTX_GRX_N15 C626 1
PEG_TX#_15 AC46 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N15
R74 PM@ 1 GM@ 2 UMA_CRT_G
0_0402_5% R74 75_0402_1% UMA_CRT_B E28 J42 PCIE_MTX_GRX_P0 C627 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0
18 UMA_CRT_B CRT_BLUE PEG_TX_0
R75 PM@ 1 GM@ 2 UMA_CRT_R L46 PCIE_MTX_GRX_P1 C628 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P1
0_0402_5% R75 75_0402_1% UMA_CRT_G PEG_TX_1 PCIE_MTX_GRX_P2 C629
18 UMA_CRT_G G28 CRT_GREEN PEG_TX_2 M48 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2
M39 PCIE_MTX_GRX_P3 C630 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P3
PEG_TX_3

VGA
UMA_CRT_R J28 M43 PCIE_MTX_GRX_P4 C631 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4
18 UMA_CRT_R CRT_RED PEG_TX_4
R47 PCIE_MTX_GRX_P5 C632 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P5
+3VS PEG_TX_5 PCIE_MTX_GRX_P6 C633
G29 CRT_IRTN PEG_TX_6 N37 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6
T39 PCIE_MTX_GRX_P7 C634 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P7
UMA_CRT_CLK UMA_CRT_CLK PEG_TX_7 PCIE_MTX_GRX_P8 C635
1 2 18 UMA_CRT_CLK H32 CRT_DDC_CLK PEG_TX_8 U36 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P8
R76 GM@ 4.7K_0402_5% UMA_CRT_DATA J32 U39 PCIE_MTX_GRX_P9 C636 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P9
18 UMA_CRT_DATA CRT_DDC_DATA PEG_TX_9
R78 PM@ 1 2 UMA_CRT_DATA UMA_CRT_HSYNC J29 Y39 PCIE_MTX_GRX_P10 C637 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10
B 18 UMA_CRT_HSYNC CRT_HSYNC PEG_TX_10 B
0_0402_5% R77 GM@ 4.7K_0402_5% 2 1UMA_CRT_IREF E29 Y46 PCIE_MTX_GRX_P11 C638 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P11
R78 GM@ 1.02K_0402_1% CRT_TVO_IREF PEG_TX_11 PCIE_MTX_GRX_P12 C639
PEG_TX_12 AA36 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12
1 2 UMA_CRT_HSYNC AA39 PCIE_MTX_GRX_P13 C640 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P13
R503 PM@ 0_0402_5% UMA_CRT_VSYNC L29 PEG_TX_13 PCIE_MTX_GRX_P14 C641
18 UMA_CRT_VSYNC CRT_VSYNC PEG_TX_14 AD42 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14
1 2 UMA_CRT_VSYNC AD46 PCIE_MTX_GRX_P15 C642 1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P15
R504 PM@ 0_0402_5% PEG_TX_15

CANTIGA ES_FCBGA1329
G7R3@

+3VS
+5VS
PCIE_GTX_MRX_P6 1 @ 2
R135 100K_0402_1% PCIE_GTX_C_MRX_P3 1 2 PCIE_GTX_C_MRX_HDMI_P3 20
PCIE_GTX_MRX_N6 1 IDP@ 2 R505 IHDMI@ 0_0402_5%
2

R188 100K_0402_1%
+5VS PCIE_GTX_MRX_P6 1 IDP@ 2 R97
DP/DVI Switch Circuit (1) R218 100K_0402_1% 4.7K_0402_5%
U13 IDP@ IDP@
2 8 C644 IDP@
17,19 DP_AUX
1

1A VCC PCIE_GTX_MRX_P6 1
17,19 DP_AUX# 5 2A 1B 3 20.1U_0402_16V7KPCIE_GTX_C_MRX_P6 DP_DDC_EN# PCIE_GTX_C_MRX_P7 R7971 IDP@ 2 0_0402_5%
DP_HPD 17,19
19 DP_AUX_EN# 1 6 PCIE_GTX_MRX_N6 1 2 PCIE_GTX_C_MRX_N6
1OE# 2B
1

0.1U_0402_16V7K D PCIE_MTX_GRX_N4 R1391 IDP@ 0_0402_5%

7 2OE# GND 4 2 DP_L0-_NB 17
C649 IDP@ DP_AUX_EN#2 Q27 PCIE_MTX_GRX_N5 R1581 IDP@ 2 0_0402_5%
DP_L1-_NB 17
SN74CBTD3306CPWR_TSSOP8 G 2N7002_SOT23-3 PCIE_MTX_GRX_N6 R1811 IDP@ 2 0_0402_5%
DP_L2-_NB 17
+3VS S IDP@ PCIE_MTX_GRX_N7 R1821 IDP@ 2 0_0402_5%
DP_L3-_NB 17
3

PCIE_MTX_GRX_P4 R1841 IDP@ 2 0_0402_5%

DP_L0+_NB 17
PCIE_MTX_GRX_P5 R1041 IDP@ 2 0_0402_5%
DP_L1+_NB 17
+5VS R204 2.2K_0402_5% PCIE_MTX_GRX_P6 R1401 IDP@ 2 0_0402_5%
A DP_L2+_NB 17 A
DP_CLK 1 IDP@ 2 PCIE_MTX_GRX_P7 R1461 IDP@ 2 0_0402_5%
DP_L3+_NB 17
U14 IDP@ DP_DATA 1 IDP@ 2
DP_AUX 2 8 R217 2.2K_0402_5%
DP_AUX# 1A VCC DP_CLK
5 2A 1B 3 DP_CLK 8
DP_DDC_EN# 1 6 DP_DATA
1OE# 2B DP_DATA 8
7 4
2OE# GND Security Classification Compal Secret Data Compal Electronics, Inc.
SN74CBTD3306CPWR_TSSOP8 2008/10/06 2009/10/06 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 11 of 48
5 4 3 2 1
 5 4 3 2 1

U3F
DDR2,667MHz,2600mA +NB_VCCAXG Extnal Graphic: 1210.34mA
DDR2,800MHz,3000mA Int. Graphic integrated Graphic: 1930.4mA
VCC_AXG_NTCF_1 W28 Intel Management Engine Link:508.12mA
+1.8V AP33 V28
VCC_SM_1 VCC_AXG_NCTF_2
DDR PWR AN33 VCC_SM_2 VCC_AXG_NCTF_3 W26
10U_0805_10V4Z BH32 V26
VCC_SM_3 VCC_AXG_NCTF_4
BG32 VCC_SM_4 VCC_AXG_NCTF_5 W25
BF32 VCC_SM_5 VCC_AXG_NCTF_6 V25
1 BD32 VCC_SM_6 VCC_AXG_NCTF_7 W24
1 1 1 BC32 VCC_SM_7 VCC_AXG_NCTF_8 V24
D + BB32 W23 +1.05VS NB Core,Intel Management Engine Link U3G D
VCC_SM_8 VCC_AXG_NCTF_9

VCC
C68 C69 C70 C71 BA32 V23
220U_D2_4VM_R15 VCC_SM_9 VCC_AXG_NCTF_10 220U_6.3V_M 0.22U_0402_10V4Z 0.1U_0402_16V4Z
AY32 VCC_SM_10 VCC_AXG_NCTF_11 AM21 AG34 VCC_1
2 2 2 2
AW32 VCC_SM_11 VCC_AXG_NCTF_12 AL21 1 1 AC34 VCC_2
AV32 VCC_SM_12 VCC_AXG_NCTF_13 AK21 1 1 1 1 AB34 VCC_3
AU32 W21 + + AA34
10U_0805_10V4Z 0.1U_0402_16V4Z VCC_SM_13 VCC_AXG_NCTF_14 C72 C73 C74 C75 C76 C77 VCC_4
AT32 V21 Y34

SM
VCC_SM_14 VCC_AXG_NCTF_15 220U_D2_4VM_R15 VCC_5
AR32 U21 V34

VCC CORE
VCC_SM_15 VCC_AXG_NCTF_16 2 2 2 2 2 2 VCC_6
AP32 VCC_SM_16 VCC_AXG_NCTF_17 AM20 U34 VCC_7
AN32 AK20 10U_0805_10V4Z 0.22U_0402_10V4Z AM33
VCC_SM_17 VCC_AXG_NCTF_18 VCC_8
BH31 VCC_SM_18 VCC_AXG_NCTF_19 W20 Intel: VCC -- 220U*2, ESR 12mOhm AK33 VCC_9
BG31 VCC_SM_19 VCC_AXG_NCTF_20 U20 AJ33 VCC_10
BF31 VCC_SM_20 VCC_AXG_NCTF_21 AM19 AG33 VCC_11
BG30 VCC_SM_21 VCC_AXG_NCTF_22 AL19 AF33 VCC_12
BH29 VCC_SM_22 VCC_AXG_NCTF_23 AK19
BG29 VCC_SM_23 VCC_AXG_NCTF_24 AJ19
BF29 VCC_SM_24 VCC_AXG_NCTF_25 AH19
BD29 VCC_SM_25 VCC_AXG_NCTF_26 AG19 AE33 VCC_13
BC29 VCC_SM_26 VCC_AXG_NCTF_27 AF19 AC33 VCC_14
BB29 VCC_SM_27 VCC_AXG_NCTF_28 AE19 AA33 VCC_15
BA29 VCC_SM_28 VCC_AXG_NCTF_29 AB19 Y33 VCC_16
AY29 VCC_SM_29 VCC_AXG_NCTF_30 AA19 W33 VCC_17

GFX NCTF

POWER
AW29 VCC_SM_30 VCC_AXG_NCTF_31 Y19 V33 VCC_18
AV29 VCC_SM_31 VCC_AXG_NCTF_32 W19 U33 VCC_19
AU29 VCC_SM_32 VCC_AXG_NCTF_33 V19 AH28 VCC_20
AT29 VCC_SM_33 VCC_AXG_NCTF_34 U19 AF28 VCC_21
AR29 VCC_SM_34 VCC_AXG_NCTF_35 AM17 AC28 VCC_22
AP29 VCC_SM_35 VCC_AXG_NCTF_36 AK17 AA28 VCC_23
VCC_AXG_NCTF_37 AH17 AJ26 VCC_24
VCC_AXG_NCTF_38 AG17 AG26 VCC_25
VCC_AXG_NCTF_39 AF17 AE26 VCC_26
BA36 VCC_SM_36/NC VCC_AXG_NCTF_40 AE17 AC26 VCC_27
C
BB24 AC17 AH25 +1.05VS C
VCC_SM_37/NC VCC_AXG_NCTF_41 VCC_28

VCC
Could be NC for DDR2 Board.BD16 VCC_SM_38/NC VCC_AXG_NCTF_42 AB17 AG25 VCC_29
BB21 VCC_SM_39/NC VCC_AXG_NCTF_43 Y17 AF25 VCC_30
AW16 VCC_SM_40/NC VCC_AXG_NCTF_44 W17 AG24 VCC_31 VCC_NCTF_1 AM32
AW13 VCC_SM_41/NC VCC_AXG_NCTF_45 V17 AJ23 VCC_32 VCC_NCTF_2 AL32
AT13 VCC_SM_42/NC VCC_AXG_NCTF_46 AM16 AH23 VCC_33 VCC_NCTF_3 AK32
VCC_AXG_NCTF_47 AL16 AF23 VCC_34 VCC_NCTF_4 AJ32
AK16 T32 AH32

POWER
VCC_AXG_NCTF_48 VCC_35 VCC_NCTF_5
VCC_AXG_NCTF_49 AJ16 VCC_NCTF_6 AG32
VCC_AXG_NCTF_50 AH16 VCC_NCTF_7 AE32
8700mA VCC_AXG_NCTF_51 AG16 VCC_NCTF_8 AC32
VCC_AXG_NCTF_52 AF16 VCC_NCTF_9 AA32
Y26 VCC_AXG_1 VCC_AXG_NCTF_53 AE16 VCC_NCTF_10 Y32
AE25 VCC_AXG_2 VCC_AXG_NCTF_54 AC16 VCC_NCTF_11 W32
For layout placement un-mound C123 and mound C84 AB25 VCC_AXG_3 VCC_AXG_NCTF_55 AB16 VCC_NCTF_12 U32
AA25 VCC_AXG_4 VCC_AXG_NCTF_56 AA16 VCC_NCTF_13 AM30
Int. Graphic AE24 VCC_AXG_5 VCC_AXG_NCTF_57 Y16 VCC_NCTF_14 AL30
AC24 VCC_AXG_6 VCC_AXG_NCTF_58 W16 VCC_NCTF_15 AK30
+1.05VS +NB_VCCAXG AA24 V16 AH30
VCC_AXG_7 VCC_AXG_NCTF_59 VCC_NCTF_16
Y24 VCC_AXG_8 VCC_AXG_NCTF_60 U16 VCC_NCTF_17 AG30
220U_D2_4VM_R15 10U_0805_10V4Z 0.47U_0603_10V7K 0.1U_0402_16V4Z AE23 AF30
VCC_AXG_9 VCC_NCTF_18
1 AC23 VCC_AXG_10 VCC_NCTF_19 AE30
1 1 1 1 1 1 AB23 AC30

NCTF
+ VCC_AXG_11 VCC_NCTF_20
AA23 VCC_AXG_12 VCC_NCTF_21 AB30
C84 C85 C86 C87 C88 C89 C90 AJ21 AA30
GM@ GM@ GM@ GM@ GM@ GM@ GM@ VCC_AXG_13 VCC_NCTF_22
AG21 VCC_AXG_14 VCC_NCTF_23 Y30
2 2 2 2 2 2 2
AE21 VCC_AXG_15 VCC_NCTF_24 W30
10U_0805_10V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z AC21 V30
VCC_AXG_16 VCC_NCTF_25
AA21 VCC_AXG_17 VCC_NCTF_26 U30

VCC
Intel:AXG and AXG_NCTF -- 220U*2, ESR 15mOhm Y21 VCC_AXG_18 VCC_NCTF_27 AL29
VCC

AH20 VCC_AXG_19 VCC_NCTF_28 AK29

For layout issue to separate 220u*2 to +1.05VS AF20 AJ29
B C86 PM@ VCC_AXG_20 VCC_NCTF_29 B
AE20 VCC_AXG_21 VCC_NCTF_30 AH29
0_0805_5% AC20 AG29
VCC_AXG_22 VCC_NCTF_31
AB20 VCC_AXG_23 VCC_NCTF_32 AE29
AA20 AC29
GFX

+1.05VS +NB_VCCAXG VCC_AXG_24 VCC_NCTF_33

T17 VCC_AXG_25 VCC_NCTF_34 AA29
T16 VCC_AXG_26 VCC_NCTF_35 Y29
PJ27 AM15 VCC_AXG_27 VCC_NCTF_36 W29
AL15 VCC_AXG_28 VCC_NCTF_37 V29
1 1 2 2 AE15 VCC_AXG_29 VCC_NCTF_38 AL28
AJ15 VCC_AXG_30 VCC_NCTF_39 AK28
JUMP_43X39 @ AH15 AL26
VCC_AXG_31 VCC_NCTF_40
PJ28 AG15 VCC_AXG_32 VCC_NCTF_41 AK26
AF15 VCC_AXG_33 VCC_NCTF_42 AK25
1 1 2 2 AB15 VCC_AXG_34 VCC_NCTF_43 AK24
AA15 VCC_AXG_35 VCC_NCTF_44 AK23
JUMP_43X39 @ Y15 VCC_AXG_36
PJ29 V15 VCC_AXG_37
U15 VCC_AXG_38
1 1 2 2 AN14 VCC_AXG_39
AM14 VCC_AXG_40
JUMP_43X39 @ U14 AV44 VCCSM_LF1
VCC SM LF

VCC_AXG_41 VCC_SM_LF1
PJ30 T14 VCC_AXG_42 VCC_SM_LF2 BA37 VCCSM_LF2
VCC_SM_LF3 AM40 VCCSM_LF3
1 1 2 2 VCC_SM_LF4 AV21 VCCSM_LF4
VCC_SM_LF5 AY5 VCCSM_LF5 CANTIGA ES_FCBGA1329
JUMP_43X39 @ PAD T3 AJ14 AM10 VCCSM_LF6 G7R3@
VCC_AXG_SENSE VCC_SM_LF6
PJ31 PAD T4 AH14 VSS_AXG_SENSE VCC_SM_LF7 BB13 VCCSM_LF7
1 1 C93 1 1 C95 1 1 C96 1
1 2 0.22U_0603_10V7K 0.47U_0603_10V7K 1U_0402_6.3V4Z
1 2
JUMP_43X39 @ C91 C92 C94 C97
0.1U_0402_16V4Z 2 2 0.1U_0402_16V4Z 2 2 0.22U_0603_10V7K 2 2 1U_0402_6.3V4Z 2
A PJ32 A
1 2 CANTIGA ES_FCBGA1329
1 2 G7R3@
JUMP_43X39 @

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 12 of 48
5 4 3 2 1
 5 4 3 2 1

+3VS_TVCRT_DACBG +3VS_TVCRT_DAC +3VS_TVCRT_DACBG

CRT TV +3VS_TVCRT_DACBG
+3VS
2 R80 1 0.01U_0402_25V7K C100 PM@ 0.01U_0402_25V7K
1 0_0603_5% 1 1 0_0402_5% 1 1 2 R79 1
GM@ C101 PM@ Pin A25 2_0603_5% 1 U3H
C225 C99 C100 0_0402_5% C101 C102 GM@ FSB=1067Mhz,852mA +1.05VS
GM@ GM@ Pin B27 GM@ GM@ GNDtoB25 C98 AGTL+
2
0.1U_0402_16V4Z 2 2 2 2 10U_0805_10V4Z 73mA VTT_1 U13
0.1U_0402_16V4Z 0.1U_0402_16V4Z GM@ 2 +3VS_TVCRT_DAC B27 T13 1
VCCA_CRT_DAC_1 VTT_2
A26 VCCA_CRT_DAC_2 VTT_3 U12 1 1 1 1
T12 + C103
+1.05VS +1.05VS_DPLLA +1.05VS +1.05VS_DPLLB VTT_4 C104 C105 C106 C107 220U_D2_4VM_R15
VTT_5 U11
R81GM@ R82 GM@ 5mA T11 0.47U_0603_10V7K 2.2U_0603_6.3V6K 4.7U_0805_10V4Z 4.7U_0805_10V4Z
VTT_6 2 2 2 2 2

CRT
D 10U_0805_10V4Z 10U_0805_10V4Z D
2 1 2 1 +3VS_TVCRT_DACBG A25 VCCA_DAC_BG VTT_7 U10
10U_FLC-453232-100K_0.25A_10%
1 10U_FLC-453232-100K_0.25A_10%
1 T10 Intel: VTT 270U*1 ESR 12mOhm
C110 PM@ C112 PM@ VTT_8
1 1 1 1 B25 VSSA_DAC_BG VTT_9 U9
C108 + 0_0805_5% C109 + 0_0805_5% T9
220U_B2_2.5VM C110 C111 220U_B2_2.5VM C112 C113 VTT_10
VTT_11 U8
@ GM@ GM@ Pin F47 @ GM@ GM@ Pin L48 T8
2 2 2 2 2 2 VTT_12

VTT
0.1U_0402_16V4Z 0.1U_0402_16V4Z
+1.05VS_DPLLA F47 VCCA_DPLLA64.8mA VTT_13 U7
VTT_14 T7
+1.05VS_DPLLB L48 VCCA_DPLLB64.8mA VTT_15 U6
VTT_16 T6

PLL
+1.05VS +1.05VS_AHPLL +1.05VS +1.05VS_MPLL +1.05VS_AHPLL AD1 VCCA_HPLL 24mA VTT_17 U5
VTT_18 T5
R83 R84 +1.8V_TXLVDS
+1.05VS_MPLL AE1 VCCA_MPLL 139.2mA VTT_19 V3
2 1 2 1 LVDS VTT_20 U3
KC FBM-L11-160808-121LMT
1 0603 1 MBK2012121YZF_0805 1 1 13.2mA V2
VTT_21

A PEG A LVDS
1 2 C117 +1.8V_TXLVDS J48 U2
C115 C116 C114 R85 0.5_0805_1% C118 C118 PM@ VCCA_LVDS VTT_22
VTT_23 T2
4.7U_0805_10V4Z 10U_0805_10V4Z Pin AE12 1000P_0402_50V7K 0_0402_5% J47 V1
2 0.1U_0402_16V4Z
2 2 GM@ VSSA_LVDS VTT_24
Pin J48 VTT_25 U1
+1.05VS
Pin AD1 0.1U_0402_16V4Z GND to J47 414uA +1.05VS_AXF
+1.5VS_PEG_BG AD48 NB I/O R86
VCCA_PEG_BG
1 2
2 1 0_0603_5%
+1.5VS_PEG_BG +1.05VS_PEGPLL
50mA C119
PCIe&DMI +1.05VS_PEGPLL AA48 C120
VCCA_PEG_PLL 1U_0402_6.3V4Z 10U_0805_10V4Z
1 2 @
+1.5VS 1 2 1
R87 0_0603_5% 1 667MTs,480mA
C121 Pin B22
C122 0.1U_0402_16V4Z 800MTs,720mA
0.1U_0402_16V4Z
2
2
PCIe&DMI AR20 VCCA_SM_1
POWER
Pin AD48 Pin AA48 DDR2 +1.05VS_A_SM AP20 VCCA_SM_2 +1.8V_SM_CK
C +1.05VS AN20 DDR2 +1.8V C
R88 VCCA_SM_3 R89
AR17 VCCA_SM_4 Host Interface I/O and HSIO

A SM
1 2 4.7U_0805_10V4Z AP17 321.35mA 1 2
VCCA_SM_5
1 0_0805_5% 1 1 1 AN17 VCCA_SM_6 VCC_AXF_1 B22 +1.05VS_AXF 1 1 0_0805_5%

AXF
AT16 VCCA_SM_7 VCC_AXF_2 B21
C123 + C124 C125 C126 AR16 A21 C127 R90 C128
220U_D2_4VM_R15 VCCA_SM_8 VCC_AXF_3 0.1U_0402_16V4Z 1_0805_1% 10U_0805_10V4Z
AP16 VCCA_SM_9
@ 2 2 2 2 2 @
2
DDR2,667MHz,119.85mA C129
10U_0805_10V4Z 1U_0402_6.3V4Z Pin BF21
Pin AR20 DDR2,800MHz,124mA 1 2
VCC_SM_CK_1 BF21 +1.8V_SM_CK

SM CK
667MTs,24mA BH20 10U_0805_10V4Z
VCC_SM_CK_2
BG20
DDR2 800MTs,26mA VCC_SM_CK_3
BF20 +1.8V_TXLVDS +1.8V
+1.05VS +1.05VS_A_SM_CK VCC_SM_CK_4 R91 GM@
AP28 VCCA_SM_CK_1 LVDS
R92 AN28 1 2
0.1U_0402_16V4Z VCCA_SM_CK_2
1 2 AP25 VCCA_SM_CK_3 1 1 0_0603_5%
0_0603_5% 1 1 1 AN25 118.8mA
@ VCCA_SM_CK_4 C130 PM@ C130 C131
AN24 VCCA_SM_CK_5 VCC_TX_LVDS K47 +1.8V_TXLVDS

A CK
C132 C133 C134 AM28 0_0402_5% 1000P_0402_50V7K 10U_0805_10V4Z
10U_0805_10V4Z VCCA_SM_CK_NCTF_1 2 GM@ 2 GM@
AM26 VCCA_SM_CK_NCTF_2
2 2 2
AM25 VCCA_SM_CK_NCTF_3 105.3mA Pin K47
2.2U_0603_6.3V6K AL25 C35 +3VS
+3VS_TVCRT_DAC +1.5VS +1.5VS_HDA VCCA_SM_CK_NCTF_4 VCC_HV_1
TV Pin AP28 AM24 VCCA_SM_CK_NCTF_5 VCC_HV_2 B35

HV
R94 HDMI's HDA AL24 A35
0.01U_0402_25V7K VCCA_SM_CK_NCTF_6 VCC_HV_3 D3
1 2 AM23 VCCA_SM_CK_NCTF_7
1 1 0_0402_5% 1 AL23 +3VS 2 R93 1 1 2 +1.05VS
IHDMI@ VCCA_SM_CK_NCTF_8 10_0603_5%
1782mA 1
C135 C136 C138 V48 +1.05VS C137 CH751H-40PT_SOD323-2
0.1U_0402_16V4Z 0.1U_0402_16V4Z VCC_PEG_1 0.1U_0402_16V4Z
2 2
Pin B24 Pin A32 VCC_PEG_2 U48
IHDMI@ 2

PEG
VCC_PEG_3 V47
2
Pin C35
B
79mA VCC_PEG_4 U47
B
B24 VCCA_TV_DAC_1 VCC_PEG_5 U46
+3VS_TVCRT_DAC A24 VCCA_TV_DAC_2

TV
+1.5VS +1.5VS_TVDAC +1.5VS +1.5VS_QDAC
50mA 456mA
R95 TV R96 TV +1.5VS_HDA A32 AH48 +1.05VS +1.05VS
VCC_HDA VCC_DMI_1

HDA
2 1 0.1U_0402_16V4Z 2 1 0.01U_0402_25V7K AF48 PCIe&DMI
VCC_DMI_2

DMI
0_0603_5% 1 1 1 0_0603_5% 1 1 AH47
VCC_DMI_3 10U_0805_10V4Z
VCC_DMI_4 AG47 1
C139 C140 C141 C142 C143 35mA 1 1
@ 10U_0805_10V4Z Pin M252 0.1U_0402_16V4Z Pin L282 M25 +
2 2 2 +1.5VS_TVDAC VCCD_TVDAC

D TV/CRT
C144 C145 C146
0.01U_0402_25V7K +1.5VS_QDAC L28 VCCD_QDAC500uA 2
10U_0805_10V4Z 2 2
157.2mA Pin V48 220U_6.3V_M
+1.05VS_DHPLL AF1 VCCD_HPLL
50mA A8 VTTLF1
+1.05VS +1.05VS_DHPLL VTTLF1 VTTLF2
+1.05VS_PEGPLL AA47 VCCD_PEG_PLL VTTLF2 L1 +1.05VS
VTTLF
R98
VTTLF3 AB2 VTTLF3 PCIe&DMI
1 2 60.31mA 1 1 1
0_0402_5% 2 M38 VCCD_LVDS_1
LVDS

+1.8V_LVDS L37 C147 C148 C149 1

C150 VCCD_LVDS_2 0.47U_0603_10V7K 0.47U_0603_10V7K 0.47U_0603_10V7K C151
2 2 2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
Pin AF1
CANTIGA ES_FCBGA1329 2
Pin AH48
G7R3@

+1.05VS PCIe&DMI +1.05VS_PEGPLL

A L1 +1.8V_LVDS A
2 1 0.1U_0402_16V4Z R99 LVDS
BLM18PG121SN1D_0603 1 +1.8V 2 1
0_0603_5% 1
R100 C152
1_0805_1% C153
2 1U_0402_6.3V4Z
2
2 1 C154
10U_0805_10V4Z Pin AA47 Pin M38
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 13 of 48
5 4 3 2 1
 5 4 3 2 1

U3I U3J

AU48 VSS_1 VSS_100 AM36 BG21 VSS_199 VSS_297 AH8

AR48 VSS_2 VSS_101 AE36 L12 VSS_200 VSS_298 Y8
AL48 VSS_3 VSS_102 P36 AW21 VSS_201 VSS_299 L8
BB47 VSS_4 VSS_103 L36 AU21 VSS_202 VSS_300 E8
AW47 VSS_5 VSS_104 J36 AP21 VSS_203 VSS_301 B8
AN47 VSS_6 VSS_105 F36 AN21 VSS_204 VSS_302 AY7
AJ47 VSS_7 VSS_106 B36 AH21 VSS_205 VSS_303 AU7
AF47 VSS_8 VSS_107 AH35 AF21 VSS_206 VSS_304 AN7
AD47 VSS_9 VSS_108 AA35 AB21 VSS_207 VSS_305 AJ7
AB47 VSS_10 VSS_109 Y35 R21 VSS_208 VSS_306 AE7
Y47 VSS_11 VSS_110 U35 M21 VSS_209 VSS_307 AA7
T47 VSS_12 VSS_111 T35 J21 VSS_210 VSS_308 N7
D D
N47 VSS_13 VSS_112 BF34 G21 VSS_211 VSS_309 J7
L47 VSS_14 VSS_113 AM34 BC20 VSS_212 VSS_310 BG6
G47 VSS_15 VSS_114 AJ34 BA20 VSS_213 VSS_311 BD6
BD46 VSS_16 VSS_115 AF34 AW20 VSS_214 VSS_312 AV6
BA46 VSS_17 VSS_116 AE34 AT20 VSS_215 VSS_313 AT6
AY46 VSS_18 VSS_117 W34 AJ20 VSS_216 VSS_314 AM6
AV46 VSS_19 VSS_118 B34 AG20 VSS_217 VSS_315 M6
AR46 VSS_20 VSS_119 A34 Y20 VSS_218 VSS_316 C6
AM46 VSS_21 VSS_120 BG33 N20 VSS_219 VSS_317 BA5
V46 VSS_22 VSS_121 BC33 K20 VSS_220 VSS_318 AH5
R46 VSS_23 VSS_122 BA33 F20 VSS_221 VSS_319 AD5
P46 VSS_24 VSS_123 AV33 C20 VSS_222 VSS_320 Y5
H46 VSS_25 VSS_124 AR33 A20 VSS_223 VSS_321 L5
F46 VSS_26 VSS_125 AL33 BG19 VSS_224 VSS_322 J5
BF44 VSS_27 VSS_126 AH33 A18 VSS_225 VSS_323 H5
AH44 VSS_28 VSS_127 AB33 BG17 VSS_226 VSS_324 F5
AD44 VSS_29 VSS_128 P33 BC17 VSS_227 VSS_325 BE4
AA44 VSS_30 VSS_129 L33 AW17 VSS_228
Y44 VSS_31 VSS_130 H33 AT17 VSS_229 VSS_327 BC3
U44 VSS_32 VSS_131 N32 R17 VSS_230 VSS_328 AV3
T44 VSS_33 VSS_132 K32 M17 VSS_231 VSS_329 AL3
M44 VSS_34 VSS_133 F32 H17 VSS_232 VSS_330 R3
F44
BC43
VSS_35
VSS_36
VSS_134
VSS_135
C32
A31
C17 VSS_233 VSS VSS_331
VSS_332
P3
F3
AV43 VSS_37 VSS_136 AN29 BA16 VSS_235 VSS_333 BA2
AU43 VSS_38 VSS_137 T29 VSS_334 AW2
AM43 VSS_39 VSS_138 N29 AU16 VSS_237 VSS_335 AU2
J43 VSS_40 VSS_139 K29 AN16 VSS_238 VSS_336 AR2
C43 VSS_41 VSS_140 H29 N16 VSS_239 VSS_337 AP2
BG42
AY42
VSS_42
VSS_43
VSS VSS_141
VSS_142
F29
A29
K16
G16
VSS_240
VSS_241
VSS_338
VSS_339
AJ2
AH2
AT42 VSS_44 VSS_143 BG28 E16 VSS_242 VSS_340 AF2
C C
AN42 VSS_45 VSS_144 BD28 BG15 VSS_243 VSS_341 AE2
AJ42 VSS_46 VSS_145 BA28 AC15 VSS_244 VSS_342 AD2
AE42 VSS_47 VSS_146 AV28 W15 VSS_245 VSS_343 AC2
N42 VSS_48 VSS_147 AT28 A15 VSS_246 VSS_344 Y2
L42 VSS_49 VSS_148 AR28 BG14 VSS_247 VSS_345 M2
BD41 VSS_50 VSS_149 AJ28 AA14 VSS_248 VSS_346 K2
AU41 VSS_51 VSS_150 AG28 C14 VSS_249 VSS_347 AM1
AM41 VSS_52 VSS_151 AE28 BG13 VSS_250 VSS_348 AA1
AH41 VSS_53 VSS_152 AB28 BC13 VSS_251 VSS_349 P1
AD41 VSS_54 VSS_153 Y28 BA13 VSS_252 VSS_350 H1
AA41 VSS_55 VSS_154 P28
Y41 VSS_56 VSS_155 K28 VSS_351 U24
U41 VSS_57 VSS_156 H28 AN13 VSS_255 VSS_352 U28
T41 VSS_58 VSS_157 F28 AJ13 VSS_256 VSS_353 U25
M41 VSS_59 VSS_158 C28 AE13 VSS_257 VSS_354 U29
G41 VSS_60 VSS_159 BF26 N13 VSS_258
B41 VSS_61 VSS_160 AH26 L13 VSS_259 VSS_NCTF_1 AF32
BG40 VSS_62 VSS_161 AF26 G13 VSS_260 VSS_NCTF_2 AB32
BB40 VSS_63 VSS_162 AB26 E13 VSS_261 VSS_NCTF_3 V32
AV40 VSS_64 VSS_163 AA26 BF12 VSS_262 VSS_NCTF_4 AJ30
AN40 VSS_65 VSS_164 C26 AV12 VSS_263 VSS_NCTF_5 AM29
H40 VSS_66 VSS_165 B26 AT12 VSS_264 VSS_NCTF_6 AF29
E40 VSS_67 VSS_166 BH25 AM12 VSS_265 VSS_NCTF_7 AB29
AT39 BD25 AA12 U26

VSS NCTF
VSS_68 VSS_167 VSS_266 VSS_NCTF_8
AM39 VSS_69 VSS_168 BB25 J12 VSS_267 VSS_NCTF_9 U23
AJ39 VSS_70 VSS_169 AV25 A12 VSS_268 VSS_NCTF_10 AL20
AE39 VSS_71 VSS_170 AR25 BD11 VSS_269 VSS_NCTF_11 V20
N39 VSS_72 VSS_171 AJ25 BB11 VSS_270 VSS_NCTF_12 AC19
L39 VSS_73 VSS_172 AC25 AY11 VSS_271 VSS_NCTF_13 AL17
B39 VSS_74 VSS_173 Y25 AN11 VSS_272 VSS_NCTF_14 AJ17
BH38 VSS_75 VSS_174 N25 AH11 VSS_273 VSS_NCTF_15 AA17
BC38 VSS_76 VSS_175 L25 VSS_NCTF_16 U17
B B
BA38 VSS_77 VSS_176 J25 Y11 VSS_275
AU38 VSS_78 VSS_177 G25 N11 VSS_276
AH38 VSS_79 VSS_178 E25 G11 VSS_277 VSS_SCB_1 BH48
AD38 VSS_80 VSS_179 BF24 C11 VSS_278 VSS_SCB_2 BH1
AA38 VSS_81 VSS_180 AD12 BG10 VSS_279 VSS_SCB_3 A48
Y38 AY24 AV10 C1

VSS SCB
VSS_82 VSS_181 VSS_280 VSS_SCB_4
U38 VSS_83 VSS_182 AT24 AT10 VSS_281 VSS_SCB_5 A3
T38 VSS_84 VSS_183 AJ24 AJ10 VSS_282
J38 VSS_85 VSS_184 AH24 AE10 VSS_283
F38 VSS_86 VSS_185 AF24 AA10 VSS_284
C38 VSS_87 VSS_186 AB24 M10 VSS_285
BF37 VSS_88 VSS_187 R24 BF9 VSS_286 NC_26 E1
BB37 VSS_89 VSS_188 L24 BC9 VSS_287 NC_27 D2
AW37 VSS_90 VSS_189 K24 AN9 VSS_288 NC_28 C3
AT37 VSS_91 VSS_190 J24 AM9 VSS_289 NC_29 B4
AN37 VSS_92 VSS_191 G24 AD9 VSS_290 NC_30 A5
AJ37 VSS_93 VSS_192 F24 G9 VSS_291 NC_31 A6
H37 VSS_94 VSS_193 E24 B9 VSS_292 NC_32 A43
C37 VSS_95 VSS_194 BH23 BH8 VSS_293 NC_33 A44
BG36 VSS_96 VSS_195 AG23 BB8 VSS_294 NC_34 B45
BD36 Y23 AV8 C46

NC
VSS_97 VSS_196 VSS_295 NC_35
AK15 VSS_98 VSS_197 B23 AT8 VSS_296 NC_36 D47
AU36 VSS_99 VSS_198 A23 NC_37 B47
VSS_199 AJ6 NC_38 A46
NC_39 F48
CANTIGA ES_FCBGA1329 E48
G7R3@ NC_40
NC_41 C48
NC_42 B48

CANTIGA ES_FCBGA1329
G7R3@
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 14 of 48
5 4 3 2 1
 5 4 3 2 1

JDDRL @
+DIMM_VREF 1 VREF VSS 2 DDR_A_DQS#[0..7] 9
1 1 3 4 DDR_A_D5
DDR_A_D4 VSS DQ4 DDR_A_D0
5 DQ0 DQ5 6 DDR_A_D[0..63] 9
C155 C156 DDR_A_D1 7 8
2.2U_0603_6.3V6K 0.1U_0402_16V4Z DQ1 VSS DDR_A_DM0
9 VSS DM0 10 DDR_A_DM[0..7] 9
2 2 DDR_A_DQS#0 11 DQS0# VSS 12
DDR_A_DQS0 13 14 DDR_A_D6
DQS0 DQ6 DDR_A_DQS[0..7] 9
15 16 DDR_A_D7
DDR_A_D2 VSS DQ7
17 DQ2 VSS 18 DDR_A_MA[0..14] 9
DDR_A_D3 19 20 DDR_A_D13
+1.8V DQ3 DQ12 DDR_A_D12
21 VSS DQ13 22
DDR_A_D8 23 24
DDR_A_D14 DQ8 VSS DDR_A_DM1
D 25 DQ9 DM1 26 Layout Note: D
1

27 28 +1.8V
R101 DDR_A_DQS#1 VSS VSS Place near JP3
29 DQS1# CK0 30 DDRA_CLK0 8
DDR_A_DQS1 31 32
DQS1 CK0# DDRA_CLK0# 8
1K_0402_1% 20mils 33 34
VSS VSS

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_A_D9 35 36 DDR_A_D11 1
2

DDR_A_D15 DQ10 DQ14 DDR_A_D10

+DIMM_VREF 37 DQ11 DQ15 38 1 1 1 1 1 1 1 1 1

C158

C159

C160

C161

C162

C163

C164

C165

C166
39 40 + C157
VSS VSS
1

220U_Y_4VM
R102 @
2 2 2 2 2 2 2 2 2 2
41 VSS VSS 42
1K_0402_1% DDR_A_D16 43 44 DDR_A_D20
DDR_A_D17 DQ16 DQ20 DDR_A_D21 4.4
45 46
2

DQ17 DQ21
47 VSS VSS 48
DDR_A_DQS#2 49 50
DQS2# NC PM_EXTTS# 8,15
DDR_A_DQS2 51 52 DDR_A_DM2
DQS2 DM2
53 VSS VSS 54
DDR_A_D18 55 56 DDR_A_D23
DDR_A_D19 DQ18 DQ22 DDR_A_D22
57 DQ19 DQ23 58
59 VSS VSS 60
DDR_A_D29 61 62 DDR_A_D28 Layout Note: Place one cap close to every 2 pullup
DDR_A_D24 DQ24 DQ28 DDR_A_D25 +0.9VS
63 DQ25 DQ29 64
65 66 resistors terminated to +0.9VS
DDR_A_DM3 VSS VSS DDR_A_DQS#3
67 DM3 DQS3# 68
69 70 DDR_A_DQS3
NC DQS3

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
71 VSS VSS 72
DDR_A_D26 73 74 DDR_A_D31
DDR_A_D27 DQ26 DQ30 DDR_A_D30
75 DQ27 DQ31 76 1 1 1 1 1 1 1 1 1 1 1 1 1
77 VSS VSS 78
C DDRA_CKE0 79 80 DDRA_CKE1 C
8 DDRA_CKE0 CKE0 NC/CKE1 DDRA_CKE1 8
+1.8V 81 VDD VDD 82 +1.8V 2 2 2 2 2 2 2 2 2 2 2 2 2
83 NC NC/A15 84

C167

C168

C169

C170

C171

C172

C173

C174

C175

C176

C177

C178

C179
DDR_A_BS2 85 86 DDR_A_MA14
9 DDR_A_BS2 BA2 NC/A14
87 VDD VDD 88
DDR_A_MA12 89 90 DDR_A_MA11
DDR_A_MA9 A12 A11 DDR_A_MA7
91 A9 A7 92
DDR_A_MA8 93 94 DDR_A_MA6
A8 A6
95 VDD VDD 96
DDR_A_MA5 97 98 DDR_A_MA4
DDR_A_MA3 A5 A4 DDR_A_MA2
99 A3 A2 100
DDR_A_MA1 101 102 DDR_A_MA0
A1 A0
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS1 Layout Note:
A10/AP BA1 DDR_A_BS1 9
DDR_A_BS0 107 108 DDR_A_RAS#
9 DDR_A_BS0
DDR_A_WE# BA0 RAS# DDRA_SCS0#
DDR_A_RAS# 9 Place these resistor
9 DDR_A_WE# 109 WE# S0# 110 DDRA_SCS0# 8
111 112 closely JP3,all
DDR_A_CAS# VDD VDD DDRA_ODT0
9 DDR_A_CAS# 113 CAS# ODT0 114 DDRA_ODT0 8 trace length Max=1.5"
DDRA_SCS1# 115 116 DDR_A_MA13
8 DDRA_SCS1# NC/S1# NC/A13 +0.9VS
117 VDD VDD 118
8 DDRA_ODT1 DDRA_ODT1 119 120
NC/ODT1 NC RP1 RP2
121 VSS VSS 122
DDR_A_D37 123 124 DDR_A_D39 DDR_A_MA8 8 1 8 1 DDR_A_MA13
DDR_A_D36 DQ32 DQ36 DDR_A_D38 DDR_A_BS2 DDRA_ODT0
125 DQ33 DQ37 126 7 2 7 2
127 128 DDR_A_MA12 6 3 6 3 DDR_A_RAS#
DDR_A_DQS#4 VSS VSS DDR_A_DM4 DDR_A_MA1 DDRA_SCS0#
129 DQS4# DM4 130 5 4 5 4
DDR_A_DQS4 131 132
DQS4 VSS DDR_A_D34 56_0804_8P4R_5% 56_0804_8P4R_5%
133 VSS DQ38 134
DDR_A_D35 135 136 DDR_A_D33
B DDR_A_D32 DQ34 DQ39 RP3 RP4 B
137 DQ35 VSS 138
139 140 DDR_A_D45 DDR_A_MA14 8 1 8 1 DDR_A_MA5
DDR_A_D40 VSS DQ44 DDR_A_D43 DDR_A_MA11 DDR_A_MA3
141 DQ40 DQ45 142 7 2 7 2
DDR_A_D44 143 144 DDR_A_MA6 6 3 6 3 DDR_A_MA9
DQ41 VSS DDR_A_DQS#5 DDR_A_MA7 DDR_A_MA10
145 VSS DQS5# 146 5 4 5 4
DDR_A_DM5 147 148 DDR_A_DQS5
DM5 DQS5 56_0804_8P4R_5% 56_0804_8P4R_5%
149 VSS VSS 150
DDR_A_D41 151 152 DDR_A_D47
DDR_A_D46 DQ42 DQ46 DDR_A_D42 RP5 RP12
153 DQ43 DQ47 154
155 156 DDRA_ODT1 8 1 1 8 DDR_A_MA4
DDR_A_D49 VSS VSS DDR_A_D52 DDR_A_CAS# DDR_A_MA2
157 DQ48 DQ52 158 7 2 2 7
DDR_A_D48 159 160 DDR_A_D53 DDR_A_WE# 6 3 3 6 DDR_A_BS1
DQ49 DQ53 DDR_A_BS0 DDR_A_MA0
161 VSS VSS 162 5 4 4 5
163 NC,TEST CK1 164 DDRA_CLK1 8
165 166 56_0804_8P4R_5% 56_0804_8P4R_5%
VSS CK1# DDRA_CLK1# 8
DDR_A_DQS#6 167 168
DDR_A_DQS6 DQS6# VSS DDR_A_DM6
169 DQS6 DM6 170
171 172 DDRA_SCS1#R480 1 2 56_0402_5%
DDR_A_D54 VSS VSS DDR_A_D51 DDRA_CKE0 R481 1 56_0402_5%
173 DQ50 DQ54 174 2
DDR_A_D50 175 176 DDR_A_D55 DDRA_CKE1 R482 1 2 56_0402_5%
DQ51 DQ55
177 VSS VSS 178
DDR_A_D61 179 180 DDR_A_D57
DDR_A_D60 DQ56 DQ60 DDR_A_D56
181 DQ57 DQ61 182
183 VSS VSS 184
DDR_A_DM7 185 186 DDR_A_DQS#7
DM7 DQS7# DDR_A_DQS7
187 VSS DQS7 188
DDR_A_D59 189 190
SUPPORT_PAD
SUPPORT_PAD

DDR_A_D58 DQ58 VSS DDR_A_D62

191 DQ59 DQ62 192
193 194 DDR_A_D63
A VSS DQ63 A
15,16,23,26,28 PM_SMBDATA 195 SDA VSS 196
15,16,23,26,28 PM_SMBCLK 197 SCL SAO 198
+3VS 199 VDDSPD SA1 200

1
C180 FOX_AS0A426-M2RN-7F
0.1U_0402_16V4Z

SO-DIMM A Security Classification Compal Secret Data Compal Electronics, Inc.

203
204

2008/10/06 2009/10/06 Title

REVERSE 2 Issued Date Deciphered Date
SCHEMATIC,MB A4991
Top side THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 15 of 48
5 4 3 2 1
 A B C D E

JDDRH @
DDR_B_DQS#[0..7] 9
+DIMM_VREF 1 VREF VSS 2
1 1 3 4 DDR_B_D5 DDR_B_D[0..63] 9
DDR_B_D0 VSS DQ4 DDR_B_D4
5 DQ0 DQ5 6
C181 C182 DDR_B_D1 7 8
DQ1 VSS DDR_B_DM[0..7] 9
2.2U_0603_6.3V6K 0.1U_0402_16V4Z 9 10 DDR_B_DM0
@ 2 2 DDR_B_DQS#0 VSS DM0
11 DQS0# VSS 12 DDR_B_DQS[0..7] 9
DDR_B_DQS0 13 14 DDR_B_D6
DQS0 DQ6 DDR_B_D7
15 VSS DQ7 16 DDR_B_MA[0..14] 9
DDR_B_D2 17 18
DDR_B_D3 DQ2 VSS DDR_B_D12
19 DQ3 DQ12 20
21 22 DDR_B_D13 Layout Note:
DDR_B_D8 VSS DQ13 +1.8V
23 DQ8 VSS 24
1 DDR_B_D9 25 26 DDR_B_DM1 Place near JP4 1
DQ9 DM1
27 VSS VSS 28
DDR_B_DQS#1 29 30
DQS1# CK0 DDRB_CLK0 8

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_B_DQS1 31 32
DQS1 CK0# DDRB_CLK0# 8
33 VSS VSS 34 1 1 1 1 1 1 1 1 1

C183

C184

C185

C186

C187

C188

C189

C190

C191
DDR_B_D10 35 36 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
37 DQ11 DQ15 38
39 VSS VSS 40
2 2 2 2 2 2 2 2 2

41 VSS VSS 42
DDR_B_D17 43 44 DDR_B_D21
DDR_B_D20 DQ16 DQ20 DDR_B_D16
45 DQ17 DQ21 46
47 VSS VSS 48
DDR_B_DQS#2 49 50
DQS2# NC PM_EXTTS# 8,14
DDR_B_DQS2 51 52 DDR_B_DM2
DQS2 DM2
53 VSS VSS 54
DDR_B_D18 55 56 DDR_B_D22
DDR_B_D19 DQ18 DQ22 DDR_B_D23
57 DQ19 DQ23 58
+0.9VS Layout Note: Place one cap close to every 2 pullup
59 VSS VSS 60
DDR_B_D28 61 62 DDR_B_D26 Resistors terminated to +0.9VS
DDR_B_D25 DQ24 DQ28 DDR_B_D24
63 DQ25 DQ29 64
65 VSS VSS 66

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_B_DM3 67 68 DDR_B_DQS#3
DM3 DQS3# DDR_B_DQS3
69 NC DQS3 70
71 VSS VSS 72 1 1 1 1 1 1 1 1 1 1 1 1 1
DDR_B_D30 73 74 DDR_B_D29
DDR_B_D31 DQ26 DQ30 DDR_B_D27
75 DQ27 DQ31 76
77 VSS VSS 78
2 DDRB_CKE0 DDRB_CKE1 2 2 2 2 2 2 2 2 2 2 2 2 2 2
8 DDRB_CKE0 79 CKE0 NC/CKE1 80 DDRB_CKE1 8

C192

C193

C60

C61

C62

C63

C198

C199

C200

C201

C202

C203

C204
+1.8V 81 VDD VDD 82 +1.8V
83 NC NC/A15 84
DDR_B_BS2 85 86 DDR_B_MA14
9 DDR_B_BS2 BA2 NC/A14
87 VDD VDD 88
DDR_B_MA12 89 90 DDR_B_MA11
DDR_B_MA9 A12 A11 DDR_B_MA7
91 A9 A7 92
DDR_B_MA8 93 94 DDR_B_MA6
A8 A6
95 VDD VDD 96
DDR_B_MA5 97 98 DDR_B_MA4
DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100 Layout Note:
DDR_B_MA1 101 102 DDR_B_MA0
A1 A0 Place these resistor
103 VDD VDD 104
DDR_B_MA10 105 106 DDR_B_BS1 closely JP4,all
A10/AP BA1 DDR_B_BS1 9
DDR_B_BS0 107 108 DDR_B_RAS# trace length Max=1.5"
9 DDR_B_BS0 BA0 RAS# DDR_B_RAS# 9
DDR_B_WE# 109 110 DDRB_SCS0#
9 DDR_B_WE# WE# S0# DDRB_SCS0# 8
111 VDD VDD 112
DDR_B_CAS# 113 114 DDRB_ODT0
9 DDR_B_CAS# CAS# ODT0 DDRB_ODT0 8 +0.9VS
DDRB_SCS1# 115 116 DDR_B_MA13
8 DDRB_SCS1# NC/S1# NC/A13
117 VDD VDD 118
DDRB_ODT1 119 120 RP8 RP9
8 DDRB_ODT1 NC/ODT1 NC
121 122 DDR_B_CAS# 8 1 8 1 DDR_B_MA7
DDR_B_D32 VSS VSS DDR_B_D36 DDR_B_WE# DDR_B_MA6
123 DQ32 DQ36 124 7 2 7 2
DDR_B_D33 125 126 DDR_B_D37 DDR_B_MA10 6 3 6 3 DDR_B_MA14
DQ33 DQ37 DDR_B_BS0 DDR_B_MA11
127 VSS VSS 128 5 4 5 4
DDR_B_DQS#4 129 130 DDR_B_DM4
DDR_B_DQS4 DQS4# DM4 56_0804_8P4R_5% 56_0804_8P4R_5%
131 DQS4 VSS 132
133 134 DDR_B_D39
DDR_B_D34 VSS DQ38 DDR_B_D38 RP10 RP11
135 DQ34 DQ39 136
3 DDR_B_D35 DDR_B_RAS# DDR_B_MA8 3
137 DQ35 VSS 138 8 1 8 1
139 140 DDR_B_D44 DDRB_SCS0# 7 2 7 2 DDR_B_MA5
DDR_B_D40 VSS DQ44 DDR_B_D45 DDRB_ODT0 DDR_B_MA1
141 DQ40 DQ45 142 6 3 6 3
DDR_B_D41 143 144 DDR_B_MA13 5 4 5 4 DDR_B_MA3
DQ41 VSS DDR_B_DQS#5
145 VSS DQS5# 146
DDR_B_DM5 147 148 DDR_B_DQS5 56_0804_8P4R_5% 56_0804_8P4R_5%
DM5 DQS5
149 VSS VSS 150
DDR_B_D42 151 152 DDR_B_D46 RP6 RP13
DDR_B_D43 DQ42 DQ46 DDR_B_D47 DDR_B_MA12 DDR_B_BS1
153 DQ43 DQ47 154 8 1 8 1
155 156 DDR_B_BS2 7 2 7 2 DDR_B_MA0
DDR_B_D48 VSS VSS DDR_B_D52 DDRB_CKE0 DDR_B_MA4
157 DQ48 DQ52 158 6 3 6 3
DDR_B_D49 159 160 DDR_B_D53 DDR_B_MA9 5 4 5 4 DDR_B_MA2
DQ49 DQ53
161 VSS VSS 162
163 164 56_0804_8P4R_5% 56_0804_8P4R_5%
NC,TEST CK1 DDRB_CLK1 8
165 VSS CK1# 166 DDRB_CLK1# 8
DDR_B_DQS#6 167 168
DDR_B_DQS6 DQS6# VSS DDR_B_DM6 DDRB_ODT1 R4831 56_0402_5%
169 DQS6 DM6 170 2
171 172 DDRB_SCS1# R4841 2 56_0402_5%
DDR_B_D51 VSS VSS DDR_B_D54 DDRB_CKE1 R4851 56_0402_5%
173 DQ50 DQ54 174 2
DDR_B_D50 175 176 DDR_B_D55
DQ51 DQ55
177 VSS VSS 178
DDR_B_D56 179 180 DDR_B_D60
DDR_B_D61 DQ56 DQ60 DDR_B_D57
181 DQ57 DQ61 182
183 VSS VSS 184
DDR_B_DM7 185 186 DDR_B_DQS#7
DM7 DQS7# DDR_B_DQS7
187 VSS DQS7 188
DDR_B_D59 189 190
SUPPORT_PAD
SUPPORT_PAD

DDR_B_D58 DQ58 VSS DDR_B_D62

191 DQ59 DQ62 192
193 194 DDR_B_D63
4 VSS DQ63 4
14,16,23,26,28 PM_SMBDATA 195 SDA VSS 196
14,16,23,26,28 PM_SMBCLK 197 SCL SAO 198
+3VS 199 VDDSPD SA1 200 +3VS

1
FOX_AS0A426-MARG-7F
Security Classification Compal Secret Data Compal Electronics, Inc.
201
202

C205
SO-DIMM B 2
0.1U_0402_16V4Z
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

STANDARD THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
Size Document Number Rev
Bottom side AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 16 of 48
A B C D E
 A B C D E F G H

+1.05VS_CK505 +3VS_CK505
R108 R107
FSC FSB FSA CPU SRC PCI REF DOT_96 USB 80mA 250mA
+1.05VS 1 2 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z +3VS 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz MHz MHz MHz FBMH1608HM601-T_0603~D
1 1 1 1 1 1 FBMH1608HM601-T_0603~D
1 1 1 1 1 1

1
C213 C214 C215 C216 C217 C218 C219 C206 C207 C208 C209 C210 C211 C212
For SED request For SED request
0 0 0 266 100 33.3 14.318 96.0 48.0 47P_0402_50V8J

2
2 2 2 2 2 2 2 2 2 2 2 2
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 47P_0402_50V8J 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0 0 1 133 100 33.3 14.318 96.0 48.0
For SED request
+3VS_CK505 SED
0 1 0 200 100 33.3 14.318 96.0 48.0 U4
1
SDA 9 PM_SMBDATA 14,15,23,26,28 1
55 VDD_SRC
0 1 1 166 100 33.3 14.318 96.0 48.0 SCL 10 PM_SMBCLK 14,15,23,26,28
6 VDD_REF
1 0 0 333 100 33.3 14.318 96.0 48.0 12 VDD_PCI CPU_0 71 CLK_CPU_BCLK 4
CPU
72 VDD_CPU CPU_0# 70 CLK_CPU_BCLK# 4
1 0 1 100 100 33.3 14.318 96.0 48.0
19 VDD_48 CPU_1 68 CLK_MCH_BCLK 7
+1.05VS_CK505 CLK_MCH_BCLK# 7 NB
1 1 0 400 100 33.3 14.318 96.0 48.0 27 VDD_PLL3 CPU_1# 67
R513 1 2 CLK_DREF_96M 8
1 GM@ 2 0_0402_5% NB (96MHz)
CLK_DREF_96M# 8
1 1 1 CLK_96M R515 GM@ 0_0402_5%
Reserved 66 VDD_CPU_IO SRC_0/DOT_96 24
1 2 CLK_PCIE_VGA 17
31 25 CLK_96M# R511 1 PM@ 2 0_0402_5% VGA (100MHz)
VDD_PLL3_IO SRC_0#/DOT_96# CLK_PCIE_VGA# 17
R512 PM@ 0_0402_5%
62 VDD_SRC_IO
28 CLK_DREF_SSC
LCDCLK/27M CLK_DREF_SSC 8
+/-30ppm 52 VDD_SRC_IO NB_SSC (100MHz)
CLK_XTAL_OUT Routing the 29 CLK_DREF_SSC#
LCDCLK#/27M_SS CLK_DREF_SSC# 8
Y1 23 VDD_IO
trace at
2 1 CLK_XTAL_IN
least 10mil 38 VDD_SRC_IO SRC_2 32 CLK_PCIE_ICH 21
2 2 ICH-DMI
14.31818MHZ_16P 33
SRC_2# CLK_PCIE_ICH# 21
C220 C221
18P_0402_50V8J 18P_0402_50V8J 1 R117 2 33_0402_5% CLK_FSA 20
2 1 1 23 CLK_48M_ICH USB_0/FS_A 2
SRC_3 35 CLK_PCIE_SATA 22
FSB CPU_BSEL1 2 SATA
FS_B/TEST_MODE
SRC_3# 36 CLK_PCIE_SATA# 22
CLK_FSC 7 REF_0/FS_C/TEST_
23 CLK_14M_ICH R114 1 2 33_0402_5%CLK_14ICH 8 39
REF_1 SRC_4 CLK_WLAN 28
WLAN
SRC_4# 40 CLK_WLAN# 28
2 1 CLK_FSA 1
5,8 CPU_BSEL0 23 CK_PWRGD CKPWRGD/PD#
R116 2.2K_0402_5%
11 NC SRC_6 57 CLK_NEW 26
CPU_BSEL1 ExpressCard
5,8 CPU_BSEL1
SRC_6# 56 CLK_NEW# 26
2 1 CLK_FSC 53
5,8 CPU_BSEL2 23 H_STP_CPU# CPU_STOP#
R109 10K_0402_5% 61
SRC_7 CLK_MCH_3GPLL 8
23 H_STP_PCI# 54 PCI_STOP# 3G_PLL
SRC_7# 60 CLK_MCH_3GPLL# 8
C228 1 @ 2 0.1U_0402_16V4Z CLK_48M_ICH CLK_XTAL_IN 5 XTAL_IN CLK_LAN
SRC_8/CPU_ITP 64 CLK_LAN 29
C229 1 @ 2 0.1U_0402_16V4Z CLK_14M_ICH CLK_XTAL_OUT 4 LOM
XTAL_OUT CLK_LAN#
SRC_8#/CPU_ITP# 63 CLK_LAN# 29
C230 1 @ 2 0.1U_0402_16V4Z CLK_PCI_EC

13 PCI_1 SRC_9 44 CLK_UWB 28

For SED request
R115 1
UWB
2 33_0402_5% CLK_DDR 14 PCI_2 SRC_9# 45 CLK_UWB# 28
34 CLK_PCI_DDR
3 3
15 PCI_3
SRC_10 50 CLK_5IN1 32
R113 1 2 33_0402_5% CLK_EC 16 5IN1
33 CLK_PCI_EC PCI_4/SEL_LCDCL
SRC_10# 51 CLK_5IN1# 32
21 CLK_PCI_ICH R112 1 2 33_0402_5% CLK_ICH 17 PCIF_5/ITP_EN

SRC_11 48 CLK_TV 28
TV
18 VSS_PCI SRC_11# 47 CLK_TV# 28 +3VS
3 VSS_REF
CLKREQ_SATA# CLKREQ_SATA#
0 = SRC8/SRC8# (100MHz) 22 VSS_48 CLKREQ_3# 37 CLKREQ_SATA# 23 2
R125
1
10K_0402_5%
CLK_ICH CLKREQ_WLAN# CLKREQ_WLAN#
1 = ITP/ITP# (266MHz) 26 VSS_IO CLKREQ_4# 41 CLKREQ_WLAN# 28 2
R124
1
10K_0402_5%
CLKREQ_NEW# CLKREQ_NEW#
0 = Enable DOT96 & SRC1(UMA) 69 VSS_CPU CLKREQ_6# 58 CLKREQ_NEW# 26 2
R286
1
10K_0402_5%
CLK_EC CLKREQ_3GPLL# CLKREQ_3GPLL#
1 = Enable SRC0 & 27MHz(DIS) 30 VSS_PLL3 CLKREQ_7# 65 CLKREQ_3GPLL# 8 2
R287
1
10K_0402_5%
34 43 CLKREQ_UWB# CLKREQ_UWB# 2 1
VSS_SRC CLKREQ_9# CLKREQ_UWB# 28
R123 10K_0402_5%
59 49 CLKREQ_5IN1# CLKREQ_5IN1# 2 1
+3VS +3VS VSS_SRC SLKREQ_10# R126 10K_0402_5%
42 46 CLKREQ_TV# CLKREQ_TV# 2 1
VSS_SRC CLKREQ_11# CLKREQ_TV# 28
R120 10K_0402_5%
1

73 THERMAL_PAD USB_1/CLKREQ_A# 21
R121 R122
@ 10K_0402_5% 10K_0402_5%
4 4
PM@ SLG8SP556VTR_QFN72_10X10
2

CLK_ICH CLK_EC
1

R127 R128
10K_0402_5% 10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
GM@ 2008/10/06 2009/10/06 Title
Issued Date Deciphered Date
SCHEMATIC,MB A4991
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 17 of 48
A B C D E F G H
 5 4 3 2 1

PCIE_MTX_C_GRX_N[0..15] PCIE_GTX_C_MRX_N[0..15]
10,20 PCIE_MTX_C_GRX_N[0..15] 10 PCIE_GTX_C_MRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15] PCIE_GTX_C_MRX_P[0..15]
10,20 PCIE_MTX_C_GRX_P[0..15] 10 PCIE_GTX_C_MRX_P[0..15]

JMXMB
JMXMA
PCIE_GTX_C_MRX_N1 109 110
PCIE_GTX_C_MRX_P1 PEX_RX1# GND PCIE_MTX_C_GRX_N1
+MXM_B+ 1 PWR_SRC 1V8RUN 2 +1.8VS 111 PEX_RX1 PEX_TX1# 112
3 4 113 114 PCIE_MTX_C_GRX_P1
PWR_SRC 1V8RUN PCIE_GTX_C_MRX_N0 GND PEX_TX1
D 5 PWR_SRC 1V8RUN 6 140mil(3.5A) PCIE_GTX_C_MRX_P0
115 PEX_RX0# GND 116
PCIE_MTX_C_GRX_N0
D
7 PWR_SRC 1V8RUN 8 117 PEX_RX0 PEX_TX0# 118
9 10 119 120 PCIE_MTX_C_GRX_P0
PWR_SRC 1V8RUN GND PEX_TX0
11 PWR_SRC 1V8RUN 12 16 CLK_PCIE_VGA# 121 PEX_REFCLK# PRSNT1# 122
13 PWR_SRC 1V8RUN 14 16 CLK_PCIE_VGA 123 PEX_REFCLK TV_C/HDTV_Pr 124
15 PWR_SRC RUNPWROK 16 SUSP# 26,30,33,36,39,41 125 CLK_REQ# GND 126
17 GND 5VRUN 18 +5VALW 8,21,26,28,29,32,33,34 PLT_RST# 127 PEX_RST# TV_Y/HDTV_Y 128
19 GND GND 20 129 RSVD GND 130
21 GND GND 22 131 RSVD TV_CVBS/HDTV_Pb 132
23 GND GND 24 4,33,34,35 EC_SMB_DA2 133 SMB_DAT GND 134
4,33,34,35 EC_SMB_CK2 135 SMB_CLK VGA_RED 136 VGA_CRT_R 18
137 THERM# GND 138
18 VGA_CRT_HSYNC 139 VGA_HSYNC VGA_GRN 140 VGA_CRT_G 18
18 VGA_CRT_VSYNC 141 VGA_VSYNC GND 142
18 VGA_CRT_CLK 143 DDCA_CLK VGA_BLU 144 VGA_CRT_B 18
18 VGA_CRT_DATA 145 DDCA_DAT GND 146
PCIE_GTX_C_MRX_N15 25 26 147 148
PEX_RX15# PRSNT2# IGP_UCLK# LVDS_UCLK# LCD_TZCLK- 18
PCIE_GTX_C_MRX_P15 27 28 PCIE_MTX_C_GRX_N15 149 150
PEX_RX15 PEX_TX15# IGP_UCLK LVDS_UCLK LCD_TZCLK+ 18
29 30 PCIE_MTX_C_GRX_P15 151 152
PCIE_GTX_C_MRX_N14 GND PEX_TX15 GND GND
31 PEX_RX14# GND 32 153 RSVD LVDS_UTX3# 154
PCIE_GTX_C_MRX_P14 33 34 PCIE_MTX_C_GRX_N14 155 156
PEX_RX14 PEX_TX14# PCIE_MTX_C_GRX_P14 RSVD LVDS_UTX3
35 GND PEX_TX14 36 157 RSVD GND 158 SPDIF_MXM 30
PCIE_GTX_C_MRX_N13 37 38 159 160
PEX_RX13# GND 10,19 DP_AUX# IGP_UTX2# LVDS_UTX2# LCD_TZOUT2- 18
PCIE_GTX_C_MRX_P13 39 40 PCIE_MTX_C_GRX_N13 161 162
PEX_RX13 PEX_TX13# 10,19 DP_AUX IGP_UTX2 LVDS_UTX2 LCD_TZOUT2+ 18
41 42 PCIE_MTX_C_GRX_P13 163 164
PCIE_GTX_C_MRX_N12 GND PEX_TX13 GND GND
43 PEX_RX12# GND 44 165 IGP_UTX1# LVDS_UTX1# 166 LCD_TZOUT1- 18
PCIE_GTX_C_MRX_P12 45 46 PCIE_MTX_C_GRX_N12 167 168
PEX_RX12 PEX_TX12# IGP_UTX1 LVDS_UTX1 LCD_TZOUT1+ 18
47 48 PCIE_MTX_C_GRX_P12 169 170
PCIE_GTX_C_MRX_N11 GND PEX_TX12 GND GND
49 PEX_RX11# GND 50 171 IGP_UTX0# LVDS_UTX0# 172 LCD_TZOUT0- 18
C PCIE_GTX_C_MRX_P11 51 52 PCIE_MTX_C_GRX_N11 173 174 C
PEX_RX11 PEX_TX11# IGP_UTX0 LVDS_UTX0 LCD_TZOUT0+ 18
53 54 PCIE_MTX_C_GRX_P11 175 176
PCIE_GTX_C_MRX_N10 GND PEX_TX11 GND GND
55 PEX_RX10# GND 56 19 DP_L3- 177 IGP_LCLK#/DVI_B_CLK# LVDS_LCLK# 178 LCD_TXCLK- 18
PCIE_GTX_C_MRX_P10 57 58 PCIE_MTX_C_GRX_N10 179 180
PEX_RX10 PEX_TX10# 19 DP_L3+ IGP_LCLK/DVI_B_CLK LVDS_LCLK LCD_TXCLK+ 18
59 60 PCIE_MTX_C_GRX_P10 181 182
GND PEX_TX10 10,19 DP_HPD DVI_B_HPD/GND GND
PCIE_GTX_C_MRX_N9 61 62 183 184
PCIE_GTX_C_MRX_P9 PEX_RX9# GND PCIE_MTX_C_GRX_N9 RSVD LVDS_LTX3#
63 PEX_RX9 PEX_TX9# 64 185 RSVD LVDS_LTX3 186
65 66 PCIE_MTX_C_GRX_P9 187 188
PCIE_GTX_C_MRX_N8 GND PEX_TX9 GND GND
67 PEX_RX8# GND 68 19 DP_L0- 189 IGP_LTX2#/DVI_B_TX2# LVDS_LTX2# 190 LCD_TXOUT2- 18
PCIE_GTX_C_MRX_P8 69 70 PCIE_MTX_C_GRX_N8 191 192
PEX_RX8 PEX_TX8# 19 DP_L0+ IGP_LTX2/DVI_B_TX2 LVDS_LTX2 LCD_TXOUT2+ 18
71 72 PCIE_MTX_C_GRX_P8 193 194
PCIE_GTX_C_MRX_N7 GND PEX_TX8 GND GND
73 PEX_RX7# GND 74 19 DP_L1- 195 IGP_LTX1#/DVI_B_TX1# LVDS_LTX1# 196 LCD_TXOUT1- 18
PCIE_GTX_C_MRX_P7 75 76 PCIE_MTX_C_GRX_N7 197 198
PEX_RX7 PEX_TX7# 19 DP_L1+ IGP_LTX1/DVI_B_TX1 LVDS_LTX1 LCD_TXOUT1+ 18
77 78 PCIE_MTX_C_GRX_P7 199 200
PCIE_GTX_C_MRX_N6 GND PEX_TX7 GND GND
79 PEX_RX6# GND 80 19 DP_L2- 201 IGP_LTX0#/DVI_B_TX0# LVDS_LTX0# 202 LCD_TXOUT0- 18
PCIE_GTX_C_MRX_P6 81 82 PCIE_MTX_C_GRX_N6 203 204
PEX_RX6 PEX_TX6# 19 DP_L2+ IGP_LTX0/DVI_B_TX0 LVDS_LTX0 LCD_TXOUT0+ 18
83 84 PCIE_MTX_C_GRX_P6 205 206
GND PEX_TX6 20,23 VGA_HDMI_HPD DVI_A_HPD GND
PCIE_GTX_C_MRX_N5 85 86 207 208
PEX_RX5# GND 20 PCIE_MTX_C_GRX_HDMI_N3 DVI_A_CLK# DDCC_DAT LCD_EDID_DATA 18
PCIE_GTX_C_MRX_P5 87 88 PCIE_MTX_C_GRX_N5 209 210
PEX_RX5 PEX_TX5# 20 PCIE_MTX_C_GRX_HDMI_P3 DVI_A_CLK DDCC_CLK LCD_EDID_CLK 18
89 90 PCIE_MTX_C_GRX_P5 211 212
GND PEX_TX5 GND LVDS_PPEN VGA_ENVDD 18
PCIE_GTX_C_MRX_N4 91 92 213 214
PEX_RX4# GND 20 PCIE_MTX_C_GRX_HDMI_N2 DVI_A_TX2# LVDS_BL_BRGHT
PCIE_GTX_C_MRX_P4 93 94 PCIE_MTX_C_GRX_N4 215 216
PEX_RX4 PEX_TX4# 20 PCIE_MTX_C_GRX_HDMI_P2 DVI_A_TX2 LVDS_BLEN VGA_ENBKL 33
95 96 PCIE_MTX_C_GRX_P4 217 218 VGA_HDMI_DATA 20
PCIE_GTX_C_MRX_N3 GND PEX_TX4 GND DDCB_DAT
97 PEX_RX3# GND 98 20 PCIE_MTX_C_GRX_HDMI_N1 219 DVI_A_TX1# DDCB_CLK 220 VGA_HDMI_CLK 20
PCIE_GTX_C_MRX_P3 99 100 PCIE_MTX_C_GRX_N3 221 222
PEX_RX3 PEX_TX3# 20 PCIE_MTX_C_GRX_HDMI_P1 DVI_A_TX1 2V5RUN
101 102 PCIE_MTX_C_GRX_P3 223 224
PCIE_GTX_C_MRX_N2 GND PEX_TX3 GND GND
103 PEX_RX2# GND 104 20 PCIE_MTX_C_GRX_HDMI_N0 225 DVI_A_TX0# 3V3RUN 226 +3VS
PCIE_GTX_C_MRX_P2 105 106 PCIE_MTX_C_GRX_N2 227 228
PEX_RX2 PEX_TX2# 20 PCIE_MTX_C_GRX_HDMI_P0 DVI_A_TX0 3V3RUN
107 108 PCIE_MTX_C_GRX_P2 229 230
B GND PEX_TX2 GND 3V3RUN B
231 FIX PIN FIX PIN 232
QUASA_CA0330-230N20
QUASA_CA0330-230N20
@
@

+5VALW +1.8VS

+MXM_B+
1 1
160mil(4A) L28 2 1 C484 C485 CV62 1 20.1U_0402_16V7K DP_L0-
B+ 10 DP_L0-_NB
KC FBM-L11-201209-221LMAT_0805 PM@ PM@ IDP@
PM@ 2 160mil(4A) 0.1U_0402_16V4Z 0.1U_0402_16V4Z CV63 1 20.1U_0402_16V7K DP_L1-
2 2 10 DP_L1-_NB
L27 2 1 C222 IDP@
KC FBM-L11-201209-221LMAT_0805 PM@ CV64 1 20.1U_0402_16V7K DP_L2-
10 DP_L2-_NB
1 1 PM@ IDP@
C224 C223 1
0.1U_0603_25V7K CV65 1
10 DP_L3-_NB 20.1U_0402_16V7K DP_L3-
PM@ PM@ IDP@
680P_0402_50V7K 68P_0402_50V8J CV66 1 20.1U_0402_16V7K DP_L0+
2 2 10 DP_L0+_NB
IDP@
CV67 1 20.1U_0402_16V7K DP_L1+
10 DP_L1+_NB
IDP@
CV68 1 20.1U_0402_16V7K DP_L2+
10 DP_L2+_NB
IDP@
CV69 1 2 0.1U_0402_16V7K DP_L3+
10 DP_L3+_NB
IDP@
A A

Close to MXM Connector

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 18 of 48
5 4 3 2 1
 5 4 3 2 1

W=60mils C693 1500P_0402_16V4Z

1 2 1 2 For EMI request
+5VS
R431 0_0603_5%
JLVDS +LCDVDD_R 2 L16 1
1.5A LCD/PANEL BD. Conn.
+LCD_VDD
+5VALW 1 @ 2+LCDCAM_VDD2 1 0_0805_5%
R429 0_0603_5% 2 1 LCD_TXCLK+ please link to VGA Conn. then link to LVDS Conn.
27 CAMERA_P 4 4 3 3 1 1
6 5 LCD_TXCLK- VGA side LVDS conn. NB side
27 CAMERA_N 6 5
8 7 C674 C675
8 7 DAC_BRIG 0.1U_0402_16V4Z 4.7U_0805_10V4Z
31 INT_MIC 10 10 9 9 DAC_BRIG 33
LCD_TXOUT0+ INVT_PWM 2 2 LCD_TXOUT0+ 0_0402_5%
12 12 11 11 INVT_PWM 33 17 LCD_TXOUT0+ 2 GM@ 1 R629 UMA_LCD_TXOUT0+ 10
LCD_TXOUT0- 14 13 LCD_TXOUT0- 0_0402_5% 2 GM@ 1 R631
14 13 17 LCD_TXOUT0- UMA_LCD_TXOUT0- 10
LCD_TXOUT1+ 16 15 LCD_TZCLK+
LCD_TXOUT1- 16 15 LCD_TZCLK- LCD_TXOUT1+ 0_0402_5%
18 18 17 17 17 LCD_TXOUT1+ 2 GM@ 1 R633 UMA_LCD_TXOUT1+ 10
D LCD_TXOUT2+ 20 19 LCD_TXOUT1- 0_0402_5% 2 GM@ 1 R635 D
20 19 17 LCD_TXOUT1- UMA_LCD_TXOUT1- 10
LCD_TXOUT2- 22 21 LCD_EDID_CLK
22 21 LCD_EDID_DATA LCD_TXOUT2+ 0_0402_5%
24 24 23 23 17 LCD_TXOUT2+ 2 GM@ 1 R637 UMA_LCD_TXOUT2+ 10
LCD_TZOUT0+ 26 25 +3VS LCD_TXOUT2- 0_0402_5% 2 GM@ 1 R639
26 25 17 LCD_TXOUT2- UMA_LCD_TXOUT2- 10
LCD_TZOUT0- 28 27 +LCDVDD_R
LCD_TZOUT1+ 28 27 LCD_TXCLK+ 0_0402_5%
30 30 29 29 17 LCD_TXCLK+ 2 GM@ 1 R641 UMA_LCD_TXCLK+ 10
LCD_TZOUT1- 32 31 LVDS_SEL 1 1 LCD_TXCLK- 0_0402_5% 2 GM@ 1 R643
32 31 LVDS_SEL 23 17 LCD_TXCLK- UMA_LCD_TXCLK- 10
LCD_TZOUT2+ 34 33 +LCD_INV @
LCD_TZOUT2- 34 33 C391 C676
36 36 35 35
38 37 B+ 0.1U_0402_16V4Z 0.1U_0402_16V4Z LCD_TZOUT0+ 0_0402_5% 2 GM@ 1 R645
38 37 2 2 17 LCD_TZOUT0+ UMA_LCD_TZOUT0+ 10
BKOFF# 40 39 L17 LCD_TZOUT0- 0_0402_5% 2 GM@ 1 R647
33 BKOFF# 40 39 17 LCD_TZOUT0- UMA_LCD_TZOUT0- 10
42 GND GND 41 2 1
FBMA-L11-201209-221LMA30T_0805 LCD_TZOUT1+ 0_0402_5% 2 GM@ 1 R649
17 LCD_TZOUT1+ UMA_LCD_TZOUT1+ 10
1

ACES_88242-4001 1 1 Rated Current 1MAX:3000mA LCD_TZOUT1- 0_0402_5% 2 GM@ 1 R651

17 LCD_TZOUT1- UMA_LCD_TZOUT1- 10
R103 @ C392
10K_0402_5% C677 C275 @ LCD_TZOUT2+ 0_0402_5% 2 GM@ 1 R653
17 LCD_TZOUT2+ UMA_LCD_TZOUT2+ 10
68P_0402_50V8J 0.1U_0402_25V4K
680P_0402_50V7K LCD_TZOUT2- 0_0402_5% 2 GM@ 1 R655
2 2 2 17 LCD_TZOUT2- UMA_LCD_TZOUT2- 10
2

LCD_TZCLK+ 0_0402_5% 2 GM@ 1 R657

17 LCD_TZCLK+ UMA_LCD_TZCLK+ 10
LCD_TZCLK- 0_0402_5% 2 GM@ 1 R659
17 LCD_TZCLK- UMA_LCD_TZCLK- 10

LCD_EDID_CLK 0_0402_5% 2 GM@ 1 R661 UMA_LCD_EDID_CLK 10

+LCD_VDD +3VS 17 LCD_EDID_CLK
LCD_EDID_DATA 0_0402_5% 2 GM@ 1 R663 UMA_LCD_EDID_DATA 10
17 LCD_EDID_DATA
1

R621 +3VS
150_0603_5% 100K_0402_5%
C R627 W=60mils C
2 Inrush current = 0A
6 2

C267
0.1U_0402_16V7K

3
1
S
Q17A G
2N7002DW-T/R7_SOT363-6 2 1 R623 2 2 Q18
CRT CONNECTOR

1
AO3413_SOT23 D55 D56 D57
3

47K_0402_5% 2
D
1

1
+LCD_VDD
C671
UMA_ENVDD 1 2 ENVDD 5 0.01U_0402_25V7K +3VS
10 UMA_ENVDD 1
R624 GM@ 0_0402_5% Q17B DAN217_SC59 DAN217_SC59 DAN217_SC59

3
VGA_ENVDD 1 2 2N7002DW-T/R7_SOT363-6 @ @ @
17 VGA_ENVDD
4
1

R625 PM@ 0_0402_5% 1 1

R626 C672 C673
100K_0402_5% 4.7U_0805_10V4Z 0.1U_0402_16V4Z L18 CRT@ 1
@ 2 2
1 2 CRT_R 1 2 CRT_R_L
10 UMA_CRT_R
2

R664 GM@ 0_0402_5% NBQ100505T-800Y_0402 C691

1 2 0.1U_0402_16V4Z
17 VGA_CRT_R 2
R665 PM@ 0_0402_5% L19 CRT@
1 2 CRT_G 1 2 CRT_G_L
10 UMA_CRT_G
R666 GM@ 0_0402_5% NBQ100505T-800Y_0402
17 VGA_CRT_G 1 2
R667 PM@ 0_0402_5% L20 CRT@ For EMI request
1 2 CRT_B 1 2 CRT_B_L
+3VS 10 UMA_CRT_B

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C
R668 GM@ 0_0402_5% NBQ100505T-800Y_0402
17 VGA_CRT_B 1 2
B B

150_0402_1%

150_0402_1%

150_0402_1%
R669 PM@ 0_0402_5% 1 1 1 1 1 1

1
R670 R671 R672 C680 C681 C682 C683 C684 C685
1

+CRT_VCC PM@ PM@ PM@ CRT@ CRT@ CRT@ CRT@ CRT@ CRT@
R685 R674 2 2 2 2 2 2
0_0402_5% 0_0402_5%

2
CRT@ CRT@
2

2
2

R677 R678
4.7K_0402_5% 4.7K_0402_5% +CRT_VCC CRT@
2

Q157A CRT@ CRT@ CRT@ CRT@ R673 10K_0402_5%

1 2 2 1
1

10 UMA_CRT_DATA 1 2 CRT_DATA 1 6 CRT_DDC_DAT C686 0.1U_0402_16V4Z

5
1
R679 GM@ 0_0402_5%
5

17 VGA_CRT_DATA 1 2 Q157B 2N7002DW-T/R7_SOT363-6 CRT@

P
OE#
R680 PM@ 0_0402_5% 1 2 CRT_HSYNC 2 4 D_CRT_HSYNC 1 2 HSYNC
10 UMA_CRT_HSYNC A Y
10 UMA_CRT_CLK 1 2 CRT_CLK 4 3 CRT@ CRT_DDC_CLK R675 GM@ 0_0402_5% L21 10_0402_5%

G
R682 GM@ 0_0402_5% 1 1 U38 CRT@
17 VGA_CRT_CLK 1 2 1 1 2N7002DW-T/R7_SOT363-6 1 2 SN74AHCT1G125GW_SOT353-5 D_CRT_VSYNC 1 2 VSYNC
17 VGA_CRT_HSYNC

3
R684 PM@ 0_0402_5% C689 C690 R676 PM@ 0_0402_5% CRT@ L22 10_0402_5%

10P_0402_50V8J

10P_0402_50V8J
C850 C849 470P_0402_50V8J 470P_0402_50V8J
33P_0402_50V8K 33P_0402_50V8K @ 2 2 @ +CRT_VCC
2 2 @ 1 1
@
JCRT C687 C688

5
1
6 @ @
6 2 2
11

P
OE#
CRT_R_L 11 CRT_VSYNC
1 1 10 UMA_CRT_VSYNC 1 2 2 A Y 4
7 R681 GM@ 0_0402_5%
7

G
CRT_DDC_DAT 12 U39
A 12 +5VS A
CRT_G_L 2 1 2 SN74AHCT1G125GW_SOT353-5
17 VGA_CRT_VSYNC

3
2 D58 +CRT_VCC_R +CRT_VCC R683 PM@ 0_0402_5% CRT@
8 8
HSYNC 13 2 F3 CRT@ 30mil
CRT_B_L 13
3 3 1 1 2
+CRT_VCC 9 3 RB491D_SOT23-3 1
VSYNC 9 1.1A_6V_MINISMDC110F-2
14 16
4
14
4
G1
G2 17 If=1A C679
@ 0.1U_0402_16V4Z
Security Classification Compal Secret Data Compal Electronics, Inc.
10 10 2 Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
CRT_DDC_CLK 15
5
15
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
5 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
SUYIN_070546FR015S267ZR D
@
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 19 of 48
5 4 3 2 1
 A B C D E

1 1

Display Port DP@

RB161M-20_SOD123-2 D23 1A_6VDC_MINISMDC110
KC FBM-L11-201209-221LMAT_0805
LV14
+3VS 2 1 DP@ 2 FV3 1 1 2 +3VS_DP
DP@
2 2

0.1U_0402_16V7K

0.1U_0402_16V7K
CV2 CV1

DP@ DP@
1 1

HHPD CV26 IDP@ CV28 IDP@ CV30 IDP@ CV32 IDP@

0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%
1

D CV27 IDP@ CV29 IDP@ CV31 IDP@ CV33 IDP@

1

HPD 2 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% JDP

IDP@ G RV107
Q52 S 7.5K_0402_1%
3

2N7002_SOT23-3 IDP@
DP_L0+ DDP@1 2 DP_TXD0+ DPP_TXD0+ 1
17 DP_L0+
2

LANE0_P
DP_L0- 0.1U_0402_16V7K CV26 DDP@1 2 DP_TXD0- 2
17 DP_L0- GND
0.1U_0402_16V7K CV27 DPN_TXD0- 3 LANE0_N
+3VS DP_L1+ DDP@1 2 DP_TXD1+ DPP_TXD1+ 4
17 DP_L1+ LANE1_P
DP_L1- 0.1U_0402_16V7K CV28 DDP@1 2 DP_TXD1- 5
17 DP_L1- GND
0.1U_0402_16V7K CV29 DPN_TXD1- 6

2
LANE1_N
@ DP_L2+ DDP@1 2 DP_TXD2+ DPP_TXD2+ 7
17 DP_L2+ LANE2_P
2 DP_L2- 0.1U_0402_16V7K CV30 DDP@1 2 DP_TXD2- 8 2
+3VS_DP 4.7K_0402_5% 17 DP_L2- GND
0.1U_0402_16V7K CV31 DPN_TXD2- 9 LANE2_N
IDP@ RV89 DP_L3+ DDP@1 2 DP_TXC+ DPP_TXC+ 10
17 DP_L3+ LANE3_P
RV105 DP_L3- 0.1U_0402_16V7K CV32 DDP@1 2 DP_TXC- 11
17 DP_L3-

1
+3VS GND
20K_0402_5% 0.1U_0402_16V7K CV33 DPN_TXC- 12 LANE3_N
DP_AUX_EN# 13 GND
10 DP_AUX_EN#
14 GND
1

DP_AUXP 15 AUXCH_P
DDP@ DP_AUXN 16 GND
RV105 LV13 17 AUXCH_N
2.2K_0402_5% HPD 1 RV40 2 1 2 MBK1608121YZF_0603 18 HPD
1K_0402_5% DP@ 19
2

1
5

1
RETURN
RV106 DP@ DDP@ 1 CV34 DP@ 1 20

1
DP_PWR
1 2 HHPD DDP@ RV41
P
OE#

10,17 DP_HPD

100P_0402_50V8J
0_0402_5% 4 2 DP@ DP@ CV35 21
Y A

100K_0402_5%
RV81 180P_0402_50V8J 22
G

2 2

GROUND
UV12 SN74AHCT1G125GW_SOT353-5 1M_0402_5% DDP@ 23
2

24
3

2
@ MOLEX_SD-105019-001

1
CV57 IDP@ CV58 IDP@ DP@
0_0402_5% 0_0402_5% RV44
5.1M_0402_5%
1 DP@ 2 R284 1 DP@ 2 R136 1 DP@ 2 R132
DDP@ 0_0402_5% 0_0402_5% 0_0402_5%

2
1 2 DP_AUXP L23 @ L7 @ L5 @ PIN 14
10,17 DP_AUX
0.1U_0402_16V7K CV57 1 2 1 2 1 2
3 DP_TXD0- 1 2 DPN_TXD0- DP_TXD1- 1 2 DPN_TXD1- DP_TXD2- 1 2 DPN_TXD2- PULLED UP (26K) 3
DDP@ DP_TXD0+ DPP_TXD0+ DP_TXD1+ DPP_TXD1+ DP_TXD2+ DPP_TXD2+
1 2 DP_AUXN 4 3 4 3 4 3 INSIDE DONGLE
10,17 DP_AUX# 4 3 4 3 4 3
0.1U_0402_16V7K CV58
WCM2012F2SF-900T04_0805_0805 WCM2012F2SF-900T04_0805_0805 WCM2012F2SF-900T04_0805_0805
1 2 R285 1 DP@ 2 R137 1 2 R133
DP@ 0_0402_5% 0_0402_5% DP@ 0_0402_5%

1 DP@ 2 R138
0_0402_5%
B+ B+ L8 @
1 1 2 2
DP_TXC- DPN_TXC-
Q160B Q160A DP_TXC+ DPP_TXC+
1

2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 RV42 RV38 4 3

DP_AUX DP_AUXP DDP@ DDP@ 4 3
3 4 1 6
DDP@ DDP@ WCM2012F2SF-900T04_0805_0805
100K_0402_5% 100K_0402_5% 1 2 R283
EN DP@0_0402_5%
5

Q158B Q158A EN
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
DP_AUX# 3 4 1 6 DP_AUXN
3

DDP@ DDP@ DDP@

Q159A
EN DDP@ 2N7002DW-T/R7_SOT363-6
5

Q159B 5 2 DP_AUX_EN#
2N7002DW-T/R7_SOT363-6
4

4 4

DDP@
1 2 EN
0.1U_0402_16V7K CV59
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
SCHEMATIC,MB A4991
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 20 of 48
A B C D E
 5 4 3 2 1

+3VS +3VS OE 2 R144 1 +3VS

2
10K_0402_5%

2
1 1 1 1 1 1 1 1 IHDMI@ RV67
C242 C243 C244 C245 C246 C247 C248 C249 0_0402_5% RV68

1
IHDMI@ IHDMI@ IHDMI@ IHDMI@ IHDMI@ IHDMI@ IHDMI@ IHDMI@ U7 HDMI@ 0_0402_5%
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z R141 HDMI@

2 1
2 2 2 2 2 2 2 2 20K_0402_5%

1
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z IHDMI@ +3VS 25 OE
OE* VGA_HDMI_CLK 17

G
2
PCIE_GTX_C_MRX_HDMI_P3 2
RB161M-20_SOD123-2 D17 H@ +5VS_HDMI VCC3V HDMI_SCLK
11 VCC3V SCL_SINK 28 1 3

2
+5VL 2 1 Inrush current = 0A 15 Q48
R145 VCC3V Q47 BSH111_SOT23-3

G
21 VCC3V SDA_SINK 29
D RB161M-20_SOD123-2 D53 H@ F2 H@ 7.5K_0402_1% 26 BSH111_SOT23-3 HDMI@ D
IHDMI@ VCC3V HDMI_SDATA HDMI@
+5VS 2 1 2 1 +HDMI_5V_OUT 33 VCC3V 1 3 VGA_HDMI_DATA 17
1.1A_6V_MINISMDC110F-21 40 30

2
C250 VCC3V HPD_SINK HDMI_HPD_R

S
46 VCC3V
H@ 32 R147 2 1 4.7K_0402_5% +3VS
0.1U_0402_16V4Z DDC_EN IHDMI@
2
+3VS R148 1 @
0_0402_5%
2 3 34 R149 2 @ 1 0_0402_5%
R150 @
0_0402_5% FUNCTION1 FUNCTION3 R151
1 2 4 FUCNTION2 FUNCTION4 35 2 IHDMI@ 1 2.2K_0402_5% +3VS
R152 1 IHDMI@ 2
2.2K_0402_5% R153 1 IHDMI@ 2 2.2K_0402_5%
R154 1 IHDMI@ 2
2.2K_0402_5% R155 1 @ 2 0_0402_5%
2 R156 1 6
VGA_DVI_TXC+ @ ANALOG1(REXT)
1 2 R164 HDMI_R_CK+ 3.3K_0402_1% IHDMI@
0_0402_5% 7
10 PCIE_GTX_C_MRX_HDMI_P3 HPD_SOURCE
L9 H@ R570 10K_0402_5%
1 2 8 +3VL 2 H@ 1 2 1 +3VS
1 2 8 SDVO_SDATA SDA_SOURCE R571 H@
9 2.2K_0402_5%
8 SDVO_SCLK SCL_SOURCE
4 3 HDMI_HPD_R 1 2
4 3 VGA_HDMI_HPD 17,23
D54
WCM-2012-121T_0805 +3VS 1 @ 2 10 CH751H-40PT_SOD323-2 R958 100K_0402_5%
VGA_DVI_TXC- @ ANALOG2
1 2 R166 HDMI_R_CK- R220 0_0402_5% H@ 1 H@ 2
0_0402_5% 1 IHDMI@ 2
Vendor suggest un-mound for these. R689 2.2K_0402_5%
VGA_DVI_TXC+ 13 48 PCIE_HDMI_P3 R2761 @ 2 0_0402_5%
OUT_D4+ IN_D4+ PCIE_MTX_C_GRX_P3 10,17
VGA_DVI_TXD0+ 1 @ 2 R167 HDMI_R_D0+ VGA_DVI_TXC- 14 47 PCIE_HDMI_N3 R2801 @ 2 0_0402_5%
OUT_D4- IN_D4- PCIE_MTX_C_GRX_N3 10,17
0_0402_5% VGA_DVI_TXC- R159 1 2 1 2 VGA_DVI_TXC+
L10 H@ 200_0402_5% C251 0.5P_0402_50V8B VGA_DVI_TXD2+ 16 45 PCIE_HDMI_P0 R2821 @ 2 0_0402_5%
OUT_D3+ IN_D3+ PCIE_MTX_C_GRX_P0 10,17
1 2 @ @ VGA_DVI_TXD2- 17 44 PCIE_HDMI_N0 R2791 @ 2 0_0402_5%
1 2 OUT_D3- IN_D3- PCIE_MTX_C_GRX_N0 10,17
C VGA_DVI_TXD2- R160 1 2 1 2 VGA_DVI_TXD2+ VGA_DVI_TXD1+ 19 42 PCIE_HDMI_P1 R2811 @ 2 0_0402_5% C
OUT_D2+ IN_D2+ PCIE_MTX_C_GRX_P1 10,17
4 3 200_0402_5% C252 0.5P_0402_50V8B VGA_DVI_TXD1- 20 41 PCIE_HDMI_N1 R1061 @ 2 0_0402_5%
4 3 OUT_D2- IN_D2- PCIE_MTX_C_GRX_N1 10,17
@ @
WCM-2012-121T_0805 VGA_DVI_TXD0+ 22 39 PCIE_HDMI_P2 R2771 @ 2 0_0402_5%
OUT_D1+ IN_D1+ PCIE_MTX_C_GRX_P2 10,17
VGA_DVI_TXD0- 1 @ 2 R172 HDMI_R_D0- VGA_DVI_TXD1- R161 1 2 1 2 VGA_DVI_TXD1+ VGA_DVI_TXD0- 23 38 PCIE_HDMI_N2 R2781 @ 2 0_0402_5%
OUT_D1- IN_D1- PCIE_MTX_C_GRX_N2 10,17
0_0402_5% 200_0402_5% C253 0.5P_0402_50V8B
@ @ R276 IHDMI@ R282 IHDMI@ R281 IHDMI@ R277 IHDMI@
0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K
VGA_DVI_TXD1+ 1 @ 2 R173 HDMI_R_D1+ VGA_DVI_TXD0- R162 1 2 1 2 VGA_DVI_TXD0+ 1 R280 IHDMI@ R279 IHDMI@ R106 IHDMI@ R278 IHDMI@
0_0402_5% 200_0402_5% C254 0.5P_0402_50V8B GND 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K
5 GND
L11 H@ @ 12 +5VL
@ GND
1 1 2 2 18 GND
+3VL 24 HDMI_HPD
GND
27 GND THERMAL_PAD 49 2
4 3 31 C658 2
4 3 GND

2
+3VL +HDMI_5V_OUT 36 H@ R572 C659
GND

1
WCM-2012-121T_0805 37 0.1U_0402_16V4Z U37 100K_0402_5% H@
GND
1

1
VGA_DVI_TXD1- @ 1
1 2 R176 HDMI_R_D1- 43 H@

OE#
0_0402_5% R185 R187 R290 R262 GND HDMI_HPD_R 1
2 A Y 4
2

10K_0402_5% 10K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 0.1U_0402_16V4Z

1
G
G

H@ H@ H@ H@ ASM1442T QFN 48P HDMI SHIFTER_QFN48_7X7 74AHCT1G125GW_SOT353-5

VGA_DVI_TXD2+ 1 @ 2 R177 HDMI_R_D2+ IHDMI@ H@
2

3
0_0402_5% HDMI_CLK 3 1 HDMI_SCLK
L12 H@ Q39
2

1 2 BSH111_SOT23-3
1 2
G

H@

4 4 3 3 HDMI_DATA 3 1
Q13
HDMI_SDATA
C65
2
33P_0402_50V8K
1
HDMI CEC Controller
U8
B
S

WCM-2012-121T_0805 BSH111_SOT23-3 B
VGA_DVI_TXD2- 1 @ 2 R178 HDMI_R_D2- H@ 1 11
+3VL +3VL 33,38 EC_SMB_CK1 P3_5/SSCK/SCL/CMP1_2 P1_6/CLK0/SSI01 CEC_INT# 33 +3VL
0_0402_5%
CV164 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXC-
17 PCIE_MTX_C_GRX_HDMI_N3 +3VL
CV165 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD0- 2 12 CEC_TEST 1 H@ 2
17 PCIE_MTX_C_GRX_HDMI_N0 P3_7/CNTR0#/SSO/TXD1 P1_5/RXD0/CNTR01/INT11#
CV166 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD1- R168 4.7K_0402_5%
17 PCIE_MTX_C_GRX_HDMI_N1
1

2
CV167 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD2-
17 PCIE_MTX_C_GRX_HDMI_N2
R157 D9 2 1CEC_RST# 3 13 CEC_FSHUPD 1 H@ 2
R169 4.7K_0402_5% RESET# P1_4/TXD0 R170 4.7K_0402_5%
10K_0402_5% CH751H-40PT_SOD323-2
CV168 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXC+ H@ H@ H@ CEC_FSHUPD (Pin13)
17 PCIE_MTX_C_GRX_HDMI_P3
CV169 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD0+ 2 1CEC_XOUT 4 14 Low= Force to update flash.
17 PCIE_MTX_C_GRX_HDMI_P0
2

1 1

CV170 1 XOUT/P4_7 P1_3/KI3#/AN11/TZOUT

17 PCIE_MTX_C_GRX_HDMI_P1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD1+ HDMI_CECIN R171 47K_0402_5%
CV171 1 2 0.1U_0402_16V7K HDMI@ VGA_DVI_TXD2+ H@ C848 1 2
17 PCIE_MTX_C_GRX_HDMI_P2
R581 5 15 H@ 1U_0402_6.3V4Z
27K_0402_5% VSS/AVSS P1_2/KI2#/AN10/CMP0_2 C255 1 2
HDMI Connector
1

D H@ H@ 0.1U_0402_16V4Z
HDMI_R_CK+ 1 HDMI@ 2 Q49 2 2 1CEC_XIN 6 16 +3VL
2

R690 499_0402_1% 2N7002_SOT23-3 G HDMI_CEC R174 47K_0402_5% XIN/P4_6 P4_2/VREF

HDMI_R_CK- 1 HDMI@ 2 JHDMI H@ S H@
3

R691 499_0402_1% HDMI_HPD 19 7 17 HDMI_CLK

HDMI_R_D1- 1 HDMI@ 2 HP_DET VCC/AVCC P1_1/KI1#/AN9/CMP0_1
+HDMI_5V_OUT 18 +5V
1

R692 499_0402_1% D
17 DDC/CEC_GND
HDMI_R_D1+ 1 HDMI@ 2 HDMI_SDATA 16 HDMI_CECOUT 1 R163 2 2 Q50 2 1 8 18 HDMI_DATA
R693 499_0402_1% HDMI_SCLK SDA 27K_0402_5% G 2N7002_SOT23-3 R175 4.7K_0402_5% MODE P1_0/KI0#/AN8/CMP0_0
15 SCL
HDMI_R_D0- 1 HDMI@ 2 14 H@ S H@ C256 1 H@
3

Reserved
1

R694 499_0402_1% HDMI_CEC 13 0.1U_0402_16V4Z HDMI_CECIN 9 19 HDMI_HPD_R

HDMI_R_D0+ 1 HDMI@ 2 HDMI_R_CK- CEC R165 H@ P4_5/INT0#/RXD1 P3_3/TCIN/INT3#/SSI00/CMP1_0
12 CK- GND 20
R695 499_0402_1% 11 21 100K_0402_5%
HDMI_R_D2+ 1 HDMI@ 2 HDMI_R_CK+ CK_shield GND H@ 2 HDMI_CECOUT
A 10 CK+ GND 22 10 P1_7/CNTR00/INT10# P3_4/SCS#/SDA/CMP1_1 20 EC_SMB_DA1 33,38 A
R696 499_0402_1% HDMI_R_D0- 9 23
2

HDMI_R_D2- 1 HDMI@ 2 D0- GND

8 D0_shield
R697 499_0402_1% HDMI_R_D0+ 7 R5F211B4D33SP_LSSOP20
D0+
1

D HDMI_R_D1- 6 D1- H@
+5VS 2 Q2 5
G 2N7002_SOT23-3 HDMI_R_D1+ D1_shield
4
S HDMI@ HDMI_R_D2- 3
D1+ Security Classification Compal Secret Data Compal Electronics, Inc.
3

D2-
1 @ 2 2 D2_shield Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
1 R698 100K_0402_5% HDMI_R_D2+ 1 D2+ SCHEMATIC,MB A4991
C266
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H@ @ TYCO_1939864-1_19P AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1U_0402_16V4Z D
2 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 21 of 48
5 4 3 2 1
 5 4 3 2 1

+3VS

U9B
D11 F1 PCI_REQ#0 RP15
AD0 REQ0# PCI_REQ#0
C8 AD1 GNT0# G4 PCI_GNT#0 23 1 8
PCI_REQ#1 PCI_REQ#1
D9
E12
AD2 PCI REQ1#/GPIO50 B6
A7 PCI_REQ#2
2
3
7
6
AD3 GNT1#/GPIO51 PCI_REQ#2 PCI_REQ#3
E9 AD4 REQ2#/GPIO52 F13 4 5
C9 AD5 GNT2#/GPIO53 F12
E10 E6 PCI_REQ#3 8.2K_0804_8P4R_5%
AD6 REQ3#/GPIO54 RP16
B7 AD7 GNT3#/GPIO55 F6 STRAP_A16 23
C7 PCI_IRDY# 1 8
AD8 PCI_DEVSEL#
D C5 AD9 C/BE0# D8 2 7 D
G11 B4 PCI_PERR# 3 6
AD10 C/BE1# PCI_PLOCK#
F8 AD11 C/BE2# D6 4 5
F11 AD12 C/BE3# A5
E7 8.2K_0804_8P4R_5%
AD13 PCI_IRDY# RP17
A3 AD14 IRDY# D3
D2 E3 PCI_SERR# 1 8
AD15 PAR PCI_STOP#
F10 AD16 PCIRST# R1 2 7
D5 C6 PCI_DEVSEL# PCI_TRDY# 3 6
AD17 DEVSEL# PCI_PERR# PCI_FRAME#
D10 AD18 PERR# E4 4 5
B3 C2 PCI_PLOCK#
AD19 PLOCK# PCI_SERR# 8.2K_0804_8P4R_5%
F7 AD20 SERR# J4
C3 A4 PCI_STOP#
AD21 STOP# PCI_TRDY#
F3 AD22 TRDY# F5
F4 D7 PCI_FRAME#
AD23 FRAME#
C1 AD24
G7 AD25 PLTRST# C14 PLT_RST# 8,17,26,28,29,32,33,34 C257
H7 D4 CLK_PCI_ICH R179
AD26 PCICLK CLK_PCI_ICH 16
D1 R2 CLK_PCI_ICH 2 1 1 2
AD27 PME# @ 10_0402_5%
G5 AD28
H6 @ 10P_0402_50V8J
AD29
G1 AD30
H3 AD31
+3VS +3VS
RP18 RP19
1 8 PCI_PIRQA# PCI_PIRQA# J5
Interrupt I/F H4 PCI_PIRQE# PCI_PIRQE# 1 8
PCI_PIRQB# PCI_PIRQB# PIRQA# PIRQE#/GPIO2 PCI_PIRQF# PCI_PIRQF#
2 7 E1 PIRQB# PIRQF#/GPIO3 K6 2 7
3 6 PCI_PIRQC# PCI_PIRQC# J6 F2 PCI_PIRQG# PCI_PIRQG# 3 6
C PCI_PIRQD# PCI_PIRQD# PIRQC# PIRQG#/GPIO4 PCI_PIRQH# PCI_PIRQH# C
4 5 C4 PIRQD# PIRQH#/GPIO5 G2 4 5

8.2K_0804_8P4R_5% ICH9-M ES_FCBGA676 8.2K_0804_8P4R_5%

ICH9R3@

U9D
26 PCIE_IRX_C_NEWTX_N1 N29 PERN1 DMI0RXN V27 DMI_MTX_IRX_N3 8
For Express 26 PCIE_IRX_C_NEWTX_P1 N28 PERP1 DMI0RXP V26 DMI_MTX_IRX_P3 8
26 PCIE_ITX_C_NEWRX_N1 2 1 0.1U_0402_16V7K PCIE_ITX_NEWRX_N1 P27 PETN1 DMI0TXN U29 DMI_ITX_MRX_N3 8
Card C258 2 1 0.1U_0402_16V7K PCIE_ITX_NEWRX_P1 P26 U28

Direct Media Interface

26 PCIE_ITX_C_NEWRX_P1 PETP1 DMI0TXP DMI_ITX_MRX_P3 8
C259
28 PCIE_IRX_C_NANDTX_N2 L29 PERN2 DMI1RXN Y27 DMI_MTX_IRX_N2 8
For UWB 28 PCIE_IRX_C_NANDTX_P2
C260 2
L28 PERP2 DMI1RXP Y26 DMI_MTX_IRX_P2 8
28 PCIE_ITX_C_NANDRX_N2 1 0.1U_0402_16V7K PCIE_ITX_NANDRX_N2 M27 PETN2 DMI1TXN W29 DMI_ITX_MRX_N2 8
C261 2 1 0.1U_0402_16V7K PCIE_ITX_NANDRX_P2 M26 W28
28 PCIE_ITX_C_NANDRX_P2 PETP2 DMI1TXP DMI_ITX_MRX_P2 8
Lane reversal

PCI - Express
29 PCIE_IRX_C_LANTX_N3 J29 PERN3 DMI2RXN AB27 DMI_MTX_IRX_N1 8
For LAN 29 PCIE_IRX_C_LANTX_P3
C262 2
J28 PERP3 DMI2RXP AB26 DMI_MTX_IRX_P1 8
29 PCIE_ITX_C_LANRX_N3 1 0.1U_0402_16V7K PCIE_ITX_LANRX_N3 K27 PETN3 DMI2TXN AA29 DMI_ITX_MRX_N1 8
29 PCIE_ITX_C_LANRX_P3 C263 2 1 0.1U_0402_16V7K PCIE_ITX_LANRX_P3 K26 AA28
PETP3 DMI2TXP DMI_ITX_MRX_P1 8

28 PCIE_IRX_C_WLANTX_N4 G29 PERN4 DMI3RXN AD27 DMI_MTX_IRX_N0 8

For WLAN 28 PCIE_IRX_C_WLANTX_P4
C264 2
G28 PERP4 DMI3RXP AD26 DMI_MTX_IRX_P0 8
28 PCIE_ITX_C_WLANRX_N4 1 0.1U_0402_16V7K PCIE_ITX_WLANRX_N4 H27 PETN4 DMI3TXN AC29 DMI_ITX_MRX_N0 8
28 PCIE_ITX_C_WLANRX_P4 C265 2 1 0.1U_0402_16V7K PCIE_ITX_WLANRX_P4 H26 AC28
PETP4 DMI3TXP DMI_ITX_MRX_P0 8

28 PCIE_IRX_C_TVTX_N5 E29 PERN5 DMI_CLKN T26 CLK_PCIE_ICH# 16

For 3G/GPS/TV Tuner 28 PCIE_IRX_C_TVTX_P5
C846 2
E28 PERP5 DMI_CLKP T25 CLK_PCIE_ICH 16
28 PCIE_ITX_C_TVRX_N5 1 0.1U_0402_16V7K PCIE_ITX_TVRX_N5 F27 PETN5
B C847 2 B
28 PCIE_ITX_C_TVRX_P5 1 0.1U_0402_16V7K PCIE_ITX_TVRX_P5 F26 PETP5 DMI_ZCOMP AF29 Within 500 mils
AF28 DMI_IRCOMP 1 2 +1.5VS
DMI_IRCOMP R180 24.9_0402_1%
32 PCIE_IRX_C_5IN1TX_N6 C29 PERN6/GLAN_RXN
For 5 IN 1 32 PCIE_IRX_C_5IN1TX_P6
C268 2
C28 PERP6/GLAN_RXP USBP0N AC5 USB20_N0 27
32 PCIE_ITX_C_5IN1RX_N6 1 0.1U_0402_16V7K PCIE_ITX_5IN1RX_N6 D27 PETN6/GLAN_TXN USBP0P AC4 USB20_P0 27 USB/B-Right
32 PCIE_ITX_C_5IN1RX_P6 C269 2 1 0.1U_0402_16V7K PCIE_ITX_5IN1RX_P6 D26 AD3
PETP6/GLAN_TXP USBP1N USB20_N1 27
USBP1P AD2 USB20_P1 27 USB/B-Right
D23 SPI_CLK USBP2N AC1 USB20_N2 25
+3V_SB
RP21
D24 SPI_CS0# USBP2P AC2 USB20_P2 25 USB Left
23 SPI_CS#1 F23 SPI_CS1#GPIO58/CLGPIO6 USBP3N AA5 USB20_N3 25
5 4 SLP_CHG# USBP3P AA4 USB20_P3 25 eSATA-USB
6 3 SLP_CHG_M4 23 ICH_SPI_MOSI D25 SPI_MOSI SPI USBP4N AB2 USB20_N4 26
7 2 USB_OC#11 E23 SPI_MISO USBP4P AB3 USB20_P4 26 ExpressCard
8 1 USB_OC#10 USBP5N AA1 USB20_N5 27
10K_0804_8P4R_5% USB_OC#0 N4 AA2 BT
27,33 USB_OC#0 OC0#/GPIO59 USBP5P USB20_P5 27
N5 OC1#/GPIO40 USBP6N W5 USB20_N6 28
RP22 USB_OC#2_D
5 4 SLP_CHG_M3
N6
P6
OC2#/GPIO41 USB USBP6P W4
Y3
USB20_P6 28 GPS
OC3#/GPIO42 USBP7N USB20_N7 28
6 3 USB_OC#0 25 SLP_CHG#
SLP_CHG# M1 OC4#/GPIO43 USBP7P Y2 USB20_P7 28 WiMax(WLAN)
7 2 USB_OC#8 25 SLP_CHG_M3
SLP_CHG_M3 N2 OC5#/GPIO29 USBP8N W1 USB20_N8 27
8 1 USB_OC#2_D 25 SLP_CHG_M4
SLP_CHG_M4 M4 OC6#/GPIO30 USBP8P W2 USB20_P8 27 FP
10K_0804_8P4R_5% M3 V2
26 EXP_CPPE# OC7#/GPIO31 USBP9N USB20_N9 27
USB_OC#8 N3 V3 Felica
OC8#/GPIO44 USBP9P USB20_P9 27
1 2 USB_OC#9 USB_OC#9 N1 OC9#/GPIO45 USBP10N U5 USB20_N10 28
R183 10K_0402_5% USB_OC#10 P5 U4 TV Tuner
OC10#/GPIO46 USBP10P USB20_P10 28
USB_OC#11 P3 U1
OC11#/GPIO47 USBP11N USB20_N11 27
+3VL USBBIAS USBP11P U2 USB20_P11 27 Int. Camera
Within 500 mils AG2 USBRBIAS
A 1 2 AG1 USBRBIAS# A
1

R186
R794 22.6_0402_1% ICH9-M ES_FCBGA676
330K_0402_5% ICH9R3@
2

D16
25,33 USB_OC#2
USB_OC#2 1 2 USB_OC#2_D
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
CH751H-40PT_SOD323-2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 22 of 48
5 4 3 2 1
 5 4 3 2 1

D D
+RTCBATT C270
12P_0402_50V8J
1

2 1

10M_0402_5%
D10 32.768KHZ_12.5P_MC-306 X1

1
BAS40-04_SOT23-3 3 NC 4
OUT

R189
+RTCVCC
2 1
3

NC IN
+CHGRTC
1 C272 U9A

2
12P_0402_50V8J ICH_RTCX1 C23 K5
RTCX1 FWH0/LAD0 LPC_AD0 33,34
C271 2 1 ICH_RTCX2 C24 K4
RTCX2 FWH1/LAD1 LPC_AD1 33,34
0.1U_0402_16V4Z L6
2 FWH2/LAD2 LPC_AD2 33,34
ICH_RTCRST# A25 K2
RTCRST# FWH3/LAD3 LPC_AD3 33,34
ICH_SRTCRST# F20
SM_INTRUDER# SRTCRST#
CMOS Setting, near DDR Door J1 @
C22 INTRUDER# FWH4/LFRAME# K3 LPC_FRAME# 33,34

RTC

LPC
+RTCVCC R190 1 2 ICH_RTCRST# 1 2 B22 J3
23 ICH_INTVRMEN INTVRMEN LDRQ0#
20K_0402_5% SHORT PADS A22 J1
23 LAN100_SLP LAN100_SLP LDRQ1#/GPIO23 FELICA_PWR 27
C273 1 2 GATEA20 1 2 +3VS
1U_0402_6.3V4Z E25 N7 GATEA20 R191 @ 10K_0402_5%
GLAN_CLK A20GATE GATEA20 33
AJ27 H_DPRSTP# 2 1 +1.05VS
A20M# H_A20M# 4
C13 R192 @ 56_0402_5%
LAN_RSTSYNC H_FERR#
ITPM Setting, near DDR Door J2 @ DPRSTP# AJ25 H_DPRSTP# 5,8,43 2
R193
1
56_0402_5%
F14 LAN_RXD0 DPSLP# AE23 H_DPSLP# 5
R194 1 2ICH_SRTCRST# 1 2 G13
20K_0402_5% SHORT PADS LAN_RXD1 FERR# R195 1
D14 LAN_RXD2 FERR# AJ26 2 56_0402_5%H_FERR# H_FERR# 4

LAN / GLAN
C274 1 2
C 1U_0402_6.3V4Z D13 AD22 C
LAN_TXD_0 CPUPWRGD H_PWRGOOD 5
D12 LAN_TXD_1
E13 LAN_TXD_2 IGNNE# AF25 H_IGNNE# 4
R196 1 2 SM_INTRUDER# KB_RST# R197 2 @ 1 10K_0402_5% +3VS
1M_0402_5% 32 CR_CPPE# CR_CPPE# B10 AE22
GPIO56 INIT# H_INIT# 4
AG25

CPU
INTR H_INTR 4
+1.5VS 1 R198 2 GLAN_COMP B28 GLAN_COMPI RCIN# L3 KB_RST#
KB_RST# 33 2 @ 1 +1.05VS
30 AZ_BITCLK_HD R200 1 2 33_0402_5% 24.9_0402_1% B27 +1.05VS 1 2 R199
R202 1 GLAN_COMPO
27 AZ_BITCLK_MD 2 33_0402_5%MDC@ NMI AF23 H_NMI 4
R201 330_0402_5%

2
B
8 AZ_BITCLK_MCH R203 1 2 33_0402_5%IHDMI@ AZ_BITCLK AF6 AF24 56_0402_5%
HDA_BIT_CLK SMI# H_SMI# 4
AZ_SYNC AH4 HDA_SYNC

C
AH27 H_THERMTRIP# 3 1 2SC2411K_SOT23
STPCLK# H_STPCLK# 4
30 AZ_SYNC_HD R205 1 2 33_0402_5% AZ_RST# AE7 @ Q10
R206 1 HDA_RST#
27 AZ_SYNC_MD 2 33_0402_5%MDC@ THRMTRIP# AG26 THRMTRIP_ICH# 1 2 H_THERMTRIP#
H_THERMTRIP# 4,8
8 AZ_SYNC_MCH R207 1 2 33_0402_5%IHDMI@ AZ_SYNC 30 AZ_SDIN0_HD AF4 R208 54.9_0402_1%
HDA_SDIN0 TP12
27 AZ_SDIN1_MD AG4 HDA_SDIN1 TP12 AG27 PAD T5

1
8 AZ_SDIN2_MCH AH3 HDA_SDIN2
R209 1 2 33_0402_5% AE5 D50

IHDA
30 AZ_RST_HD# HDA_SDIN3
27 AZ_RST_MD# R210 1 2 33_0402_5%MDC@ AH11 DAN202UT106_SC70-3
SATA4RXN SATA_IRX_C_DTX_N4 25
8 AZ_RST_MCH# R211 1 2 33_0402_5%IHDMI@ AZ_RST# AZ_SDOUT AG5 AJ11
23 AZ_SDOUT HDA_SDOUT SATA4RXP SATA_IRX_C_DTX_P4 25
AG12 ODD @
SATA4TXN SATA_ITX_DRX_N4 25
AG7 AF12 SATA_ITX_DRX_P4 25

3
R212 1 HDA_DOCK_EN#/GPIO33 SATA4TXP
30 AZ_SDOUT_HD 2 33_0402_5% 32 CR_WAKE#
CR_WAKE# AE8 HDA_DOCK_RST#/GPIO34
27 AZ_SDOUT_MD R213 1 2 33_0402_5%MDC@
8 AZ_SDOUT_MCH R214 1 2 33_0402_5%IHDMI@ AZ_SDOUT SATA_LED# AG8 ENTRIP1 38,40
35 SATA_LED# SATALED#
SATA5RXN AH9 SATA_IRX_C_DTX_N5 25
25 SATA_IRX_C_DTX_N0 AJ16 SATA0RXN SATA5RXP AJ9 SATA_IRX_C_DTX_P5 25 eSATA
25 SATA_IRX_C_DTX_P0 AH16 SATA0RXP SATA5TXN AE10 SATA_ITX_DRX_N5 25 ENTRIP2 38,40
B HDD 25 SATA_ITX_DRX_N0 AF17 SATA0TXN SATA5TXP AF10 SATA_ITX_DRX_P5 25 B
25 SATA_ITX_DRX_P0 AG17 SATA0TXP
+3VS 1 2 SATA_LED# AH18
SATA_CLKN CLK_PCIE_SATA# 16

SATA
R215 10K_0402_5% 25 SATA_IRX_C_DTX_N1 AH13 AJ18
SATA1RXN SATA_CLKP CLK_PCIE_SATA 16
25 SATA_IRX_C_DTX_P1 AJ13 SATA1RXP SATARBIAS# AJ7
SSD AG14 AH7 SATARBIAS
25 SATA_ITX_DRX_N1 SATA1TXN SATARBIAS
25 SATA_ITX_DRX_P1 AF14 SATA1TXP

2
R216
10mils width
ICH9-M ES_FCBGA676 24.9_0402_1% less than
ICH9R3@
500mils

1
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 23 of 48
5 4 3 2 1
 5 4 3 2 1

0_0402_5% 1 2 R225 +3VS

+3VS
0_0402_5% 1 2 R219 1 2
R221 1 2 4.7K_0402_5% +3V_SB LVDS_SEL 2 1 +3VS C234 0.1U_0402_16V4Z

5
4.7K_0402_5% 2 1 R223 R224 1 2 4.7K_0402_5%

2
4.7K_0402_5% 2 1 R811 10K_0402_5% VGATE 2

P
R226 B ICH_PWROK
Y 4
1 6 ICH_SMBDATA EC_PWROK 1
14,15,16,26,28 PM_SMBDATA 33 EC_PWROK A

G
5
U9C NC7SZ08P5X_NL_SC70-5 U47

3
Q4A ICH_SMBCLK G16 SMBCLK SATA0GP/GPIO21 AH23 SPK_SEL 30
2N7002DW-T/R7_SOT363-6 4 ICH_SMBCLK ICH_SMBDATA BIOS need to
14,15,16,26,28 PM_SMBCLK 3
LINKALERT#
A13 SMBDATA SMB SATA1GP/GPIO19 AF19 LVDS_SEL 18
@

SATA
GPIO
E17 LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36 AE21 BT_PWR# 27 set GPIO 1 2
D 2N7002DW-T/R7_SOT363-6 ME_EC_CLK1 C17 AD20 R227 0_0402_5% D
Q4B SMLINK0 SATA5GP/GPIO37 BT_RST# 27
+3V_SB R230 1 2 10K_0402_5% LINKALERT# ME_EC_DATA1 B18
R232 10K_0402_5% ME_EC_CLK1 SMLINK1
1 2 CLK14 H1 CLK_14M_ICH CLK_14M_ICH 16
R239 0_0402_5%
R233 10K_0402_5% ME_EC_DATA1 ICH_RI# AF3 CLK_48M_ICH @
R234
1
1
2
2 10K_0402_5% ICH_RI#
F19 RI# clocks CLK48 CLK_48M_ICH 16 2 1 1
R291
2 +3V_SB
1K_0402_5%
R236 1 2 10K_0402_5% XDP_DBRESET# R4 P1 SB_RSMRST# 1 Q11 3

C
SUS_STAT#/LPCPD# SUSCLK EC_RSMRST# 33
XDP_DBRESET# G19 1 2

E
4 XDP_DBRESET# SYS_RESET#
+3V_SB R238 1 2 10K_0402_5% EC_LID_OUT# C16 R241 MMBT3906_SOT23-3
SLP_S3# PM_SLP_S3# 33
M6 E16 10K_0402_5%

B
8 PM_SYNC# PM_SLP_S4# 33

2
R240 1 8.2K_0402_5% PM_CLKRUN# PMSYNC#/GPIO0 SLP_S4#
+3VS 2 G17 1 2 +3V_SB

SYS / GPIO
SLP_S5# PM_SLP_S5# 33
33 EC_LID_OUT# EC_LID_OUT# A17 R243
SMBALERT#/GPIO11

1
C10 S4_STATE# 4.7K_0402_5%
R242 1 1K_0402_5% SB_WAKE# S4_STATE#/GPIO26 D11B D11A
+3V_SB 2 16 H_STP_PCI# A14 STP_PCI#
16 H_STP_CPU# E19 STP_CPU# PWROK G20 ICH_PWROK ICH_PWROK 8
BAV99DW-7_SOT363 BAV99DW-7_SOT363
+3VS R244 1 2 10K_0402_5% SERIRQ
R245 1 2 @ 8.2K_0402_5% EC_THERM# PM_CLKRUN# L4 M2

Power MGT
CLKRUN# DPRSLPVR/GPIO16 PM_DPRSLPVR 8,43
THRM# not

6
R246 1 2 10K_0402_5% OCP# SB_WAKE# E20 B13 ICH_LOW_BAT# 2 1
+3VS
ICH_ACIN
used, 8.2K to
10K PU to
26,33 SB_WAKE#
33,34 SERIRQ
SERIRQ
EC_THERM#
M5
WAKE#
SERIRQ
BATLOW# R249
2.2K_0402_5%
RSMRST# circuit
+3VS 1 2 33 EC_THERM# AJ23 THRM# PWRBTN# R3 PBTN_OUT# 33
R248 330K_0402_5% +3VS.
1 2 VGATE D21 D20 1 2 CLK_14M_ICH 1 2 1 2
33,35,37 ACIN 8,33,43 VGATE VRMPWRGD LAN_RST#
D12 CH751H-40PT_SOD323-2 R247 0_0402_5% R228 C276
PAD TP11 A20 D22 SB_RSMRST# @ 10_0402_5% @ 4.7P_0402_50V8C
T6 TP11 RSMRST#
+3V_SB R250 1 2 8.2K_0402_5% EC_SMI# CLK_48M_ICH 1 2 1 2
R251 1 2 10K_0402_5% EC_SCI# 4 OCP# OCP# AG19 R5 R229 C277
GPIO1 CK_PWRGD CK_PWRGD 16
ICH_ACIN AH21 @ 10_0402_5% @ 4.7P_0402_50V8C
GPIO6
+3VS 1 R807 2 100K_0402_5% HDD_DET#
27 FM_I2CCLK AG21 GPIO7 CLPWROK R6 ICH_PWROK ICH_PWROK 1 2
33 EC_SMI# EC_SMI# A21 R231 10K_0402_5%
C EC_SCI# GPIO8 +3VS C
1 2 33 EC_SCI# C12 GPIO12 SLP_M# B16
R808 SSD@ 1K_0402_5% VGA_HDMI_HPD C21 EC_PWROK 1 2
17,20 VGA_HDMI_HPD GPIO13
AE18 F24 R275 10K_0402_5%
GPIO17 CL_CLK0 CL_CLK0 8

1
R253 1 2 8.2K_0402_5% BT_DET# K1 B19

GPIO
+3VS

Controller Link
HDD_DET# GPIO18 CL_CLK1 R252 S4_STATE#
AF8 GPIO20 1 2 +3V_SB
BT_DET# AJ22 F22 3.24K_0402_1% R235 @ 10K_0402_5%
27 BT_DET# SCLOCK/GPIO22 CL_DATA0 CL_DATA0 8
+3V_SB R255 2 1 @ 10K_0402_5% GPIO57 A9 C19 ICH_LOW_BAT# 2 1
27 FM_I2CDAT GPIO27 CL_DATA1
R257 2 1 100K_0402_5% D19 R237 8.2K_0402_5%
27 FM_I2CINT

2
GPIO28
16 CLKREQ_SATA# L1 SATACLKREQ#/GPIO35 CL_VREF0 C25 +CL_VREF0_ICH
LAN_DSM# AE19 A19 Width:Spacing
29 LAN_DSM# SLOAD/GPIO38 CL_VREF1

1
+3VS 1 R809 2 100K_0402_5% CIR_EN# CIR_EN# AG22 12mil:12mil 2
ISDBT_DET SDATAOUT0/GPIO39 R254
1 2 28 ISDBT_DET AF21 SDATAOUT1/GPIO48 CL_RST0# F21 CL_RST#0 8
R810 CIR@ 1K_0402_5% AH24 D18 453_0402_1% C278
29 LAN_ISOLATE# GPIO49 CL_RST1#
GPIO57 A8 0.1U_0402_16V4Z
GPIO57/CLGPIO5 1
+3VS 1 R264@ 2 10K_0402_5% LAN_DSM# A16

2
SB_SPKR MEM_LED/GPIO24 SUS_PWR_ACK 1
30 SB_SPKR M7 SPKR GPIO10/SUS_PWR_ACK C18 2 +3V_SB
iTPM Physical Presence AJ24 C11 R256 10K_0402_5%

MISC
8 MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT
ICH_TP3 B21 C20
TP8 TP3 WOL_EN/GPIO9
Assert = iTPM Physical Presence Enable T7 PAD AH20 TP8
CLGPIO5 TP9 AJ20 SUS_PWR_ACK Mobile Platform used only
De-assert = iTPM disable T8 PAD
TP10 TP9
Mobil Platform T9 PAD AJ21 TP10
**Only used in iAMT w/ME Firmware
GPIO57 Desktop Platform used only ICH9-M ES_FCBGA676 GPIO10 Desktop Platform used only
ICH9R3@

B
ICH9M Strap Pin Internal TPM Strap(Internal pull-down) Internal VR Enable Strap B
(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5) Flash Descriptor Security Override Strap
+3VS 1 2 ICH_SPI_MOSI 21 SPI_MOSI Low= Disable
R258 @ 1K_0402_5% Low= Descriptor Security override
High= iTPM enable by MCH strap*
Low = Internal VR Disabled GPIO33 High= Default* (Internal pull-up)
ICH_INTVRMEN High = Internal VR Enabled(Default)
No Reboot Strap (Internal pull-up)
+RTCVCC 1 2 ICH_INTVRMEN 22
+3VS 1 2 SB_SPKR SB_SPKR Low= *Default R259 330K_0402_5%
R261 @ 1K_0402_5% 1 2 ICH8M LAN100 SLP Strap
High= "No Reboot" R260 @ 0_0402_5%
LAN100_SLP 22
DMI Termination Voltage
(Internal VR for VccLAN1.05 and VccCL1.05) GPIO49 Low= Desktop used
High= Mobile* (Internal pull-up)
Boot BIOS Strap (Internal pull-up) Low = Internal VR Disabled
ICH_LAN100_SLP High = Internal VR Enabled(Default)
PCI_GNT#0 SPI_CS#1 Boot BIOS Loaction
1 2 PCI_GNT#0 21
R263 @ 1K_0402_5%
0 0 RESERVED
1
R265
2
@ 1K_0402_5%
SPI_CS#1 21 0 1 SPI
1 0 PCI XOR Chain Entrance Strap
1 1 LPC* (Default) ICH_TP3 HDA_SDOUT Description
(Internal pull-up) (Internal pull-down)
0 0 RSVD
A16 Swap Override Strap +3VS
R266 @ 1K_0402_5%
AZ_SDOUT 22 0 1 Enter XOR Chain
A 1 2 STRAP_A16 21 A
R267 @ 1K_0402_5% Low= A16 swap override Enable 1 0 Normal Operation (Default)
PCI_GNT#3 ICH_TP3
High= Default* (Internal pull-up) R268 @ 1K_0402_5% 1 1 Set PCIE port config bit 1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 24 of 48
5 4 3 2 1
 5 4 3 2 1

U9F
U9E
+RTCVCC A23 VCCRTC6uA at G3 state VCC1_05[01] A15 +1.05VS
1 1 1 VCC1_05[02] B15 1 1 AA26 VSS[001] VSS[107] H5
+ICH_V5REF A6 2mA C15 AA27 J23
C279 C280 C281 V5REF VCC1_05[03] C282 C283 VSS[002] VSS[108]
VCC1_05[04] D15 AA3 VSS[003] VSS[109] J26
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z E15 0.1U_0402_16V4Z 0.1U_0402_16V4Z AA6 J27
2 2 2 +ICH_V5REF_SUS VCC1_05[05] 2 2 VSS[004] VSS[110]
AE1 V5REF_SUS 2mA VCC1_05[06] F15 AB1 VSS[005] VSS[111] AC22
VCC1_05[07] L11 AA23 VSS[006] VSS[112] K28
AA24 VCC1_5_B[01] 646mA 1634mA VCC1_05[08] L12 AB28 VSS[007] VSS[113] K29
AA25 VCC1_5_B[02] VCC1_05[09] L14 AB29 VSS[008] VSS[114] L13
D13 AB24 L16 AB4 L15
CH751H-40PT_SOD323-2 VCC1_5_B[03] VCC1_05[10] VSS[009] VSS[115]
AB25 VCC1_5_B[04] VCC1_05[11] L17 AB5 VSS[010] VSS[116] L2
PJ37 +3VS 2 1 AC24 L18 AC17 L26
VCC1_5_B[05] VCC1_05[12] +1.5VS_DMIPLL_ICH +1.5VS VSS[011] VSS[117]
2 2 1 1 AC25 VCC1_5_B[06] VCC1_05[13] M11 AC26 VSS[012] VSS[118] L27
+5VS 2 1 +ICH_V5REF AD24 M18 AC27 L5
JUMP_43X39 @ R269 1 VCC1_5_B[07] VCC1_05[14] 0.01U_0402_25V7K L13 1 VSS[013] VSS[119]

CORE
D AD25 VCC1_5_B[08] VCC1_05[15] P11 2 AC3 VSS[014] VSS[120] L7 D
100_0402_5% AE25 P18 1 1 MBK1608121YZF_0603 AD1 M12
2N7002DW-T/R7_SOT363-6 C284 VCC1_5_B[09] VCC1_05[16] VSS[015] VSS[121]
AE26 VCC1_5_B[10] VCC1_05[17] T11 AD10 VSS[016] VSS[122] M13
+5V_SB 1 6 +5VALW 1U_0402_6.3V4Z AE27 T18 C285 C286 AD12 M14
Q16A 2 VCC1_5_B[11] VCC1_05[18] 10U_0805_10V4Z VSS[017] VSS[123]
AE28 VCC1_5_B[12] VCC1_05[19] U11 AD13 VSS[018] VSS[124] M15
STAR@ 2 2
33,36 SBPWR_EN# AE29 VCC1_5_B[13] VCC1_05[20] U18 AD14 VSS[019] VSS[125] M16
Q16B F25 V11 AD17 M17
2

VCC1_5_B[14] VCC1_05[21] VSS[020] VSS[126]

5

STAR@ G25 V12 AD18 M23

2N7002DW-T/R7_SOT363-6 D14 VCC1_5_B[15] VCC1_05[22] +1.05VS VSS[021] VSS[127]
H24 VCC1_5_B[16] VCC1_05[23] V14 AD21 VSS[022] VSS[128] M28
4 3 1 R593 2 +VSB CH751H-40PT_SOD323-2 H25 VCC1_5_B[17] VCC1_05[24] V16 AD28 VSS[023] VSS[129] M29
47K_0402_5% +3V_SB 2 1 J24 V17 AD29 N11
VCC1_5_B[18] VCC1_05[25] VSS[024] VSS[130]

VCCA3GP
1 R594 2 STAR@ J25 VCC1_5_B[19] VCC1_05[26] V18 1 AD4 VSS[025] VSS[131] N12
200K_0402_5% +5V_SB 2 1 +ICH_V5REF_SUS K24 AD5 N13
@ R270 VCC1_5_B[20] C287 VSS[026] VSS[132]
2 K25 VCC1_5_B[21] AD6 VSS[027] VSS[133] N14
C851 STAR@ 100_0402_5% L23 4.7U_0805_10V4Z AD7 N15
C289 VCC1_5_B[22] 2 VSS[028] VSS[134]
1 2 L24 VCC1_5_B[23] 23mA VCCDMIPLL R29 AD9 VSS[029] VSS[135] N16
1U_0402_6.3V4Z L25 AE12 N17
0.1U_0603_25V7K 1 VCC1_5_B[24] VSS[030] VSS[136]
M24 VCC1_5_B[25] W23 AE13 N18
M25 VCC1_5_B[26] 48mA VCC_DMI[1]
VCC_DMI[2] Y23 +1.05VS AE14
VSS[031]
VSS[032]
VSS[137]
VSS[138] N26
SBPWR_EN# 1 R597 2 +5VALW N23 AE16 N27
47K_0402_5% VCC1_5_B[27] VSS[033] VSS[139]
N24 VCC1_5_B[28] V_CPU_IO[1] AB23 AE17 VSS[034] VSS[140] P12
STAR@ N25 2mA AC23 1 1 1 AE2 P13
VCC1_5_B[29] V_CPU_IO[2] VSS[035] VSS[141]
P24 VCC1_5_B[30] AE20 VSS[036] VSS[142] P14
+1.5VS_PCIE_ICH P25 AG29 C290 C291 C292 AE24 P15
VCC1_5_B[31]
R24 VCC1_5_B[32] 308mAVCC3_3[01]
VCC3_3[02] AJ6 0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2 2
4.7U_0805_10V4Z AE3
VSS[037]
VSS[038]
VSS[143]
VSS[144] P16
+1.5VS L14 2 1 10U_0805_10V4Z 2.2U_0603_6.3V6K R25 AC10 AE4 P17
KC FBM-L11-201209-221LMAT_0805 VCC1_5_B[33] VCC3_3[07] VSS[039] VSS[145]
1 R26 VCC1_5_B[34] AE6 VSS[040] VSS[146] P2
1 1 1 R27 VCC1_5_B[35] VCC3_3[03] AD19 AE9 VSS[041] VSS[147] P23

VCCP_CORE
+ T24 AF20 +3VS AF13 P28
C293 C294 C295 C296 VCC1_5_B[36] VCC3_3[04] VSS[042] VSS[148]
T27 VCC1_5_B[37] VCC3_3[05] AG24 AF16 VSS[043] VSS[149] P29
220U_D2_4VM_R15 T28 AC20 close to AG29 close to AG24 AF18 P4
2 2 10U_0805_10V4Z
2 2 VCC1_5_B[38] VCC3_3[06] 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z VSS[044] VSS[150]
T29 VCC1_5_B[39] AF22 VSS[045] VSS[151] P7
C
U24 VCC1_5_B[40] 1 1 1 1 1 1 1 AH26 VSS[046] VSS[152] R11 C
U25 B9 C297 AF26 R12
VCC1_5_B[41] VCC3_3[08] C298 C299 C300 C301 C302 C303 VSS[047] VSS[153]
V24 VCC1_5_B[42] VCC3_3[09] F9 AF27 VSS[048] VSS[154] R13
V25 G3 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z AF5 R14
+1.5VS +1.5VS_SATAPLL_ICH VCC1_5_B[43] VCC3_3[10] 2 2 2 2 2 2 2 VSS[049] VSS[155]
U23 VCC1_5_B[44] VCC3_3[11] G6 AF7 VSS[050] VSS[156] R15

PCI
W24 VCC1_5_B[45] VCC3_3[12] J2 AF9 VSS[051] VSS[157] R16
L15 1 2 W25 J7 close to AD19 close to B9, G6, K7 close to AJ6 AG13 R17
MBK1608121YZF_0603 VCC1_5_B[46] VCC3_3[13] VSS[052] VSS[158]
1 1 K23 VCC1_5_B[47] VCC3_3[14] K7 AG16 VSS[053] VSS[159] R18
Y24 +ICH_HDA AG18 R28
C304 C305 VCC1_5_B[48] NIHDMI@ VSS[054] VSS[160]
Y25 VCC1_5_B[49] AG20 VSS[055] VSS[161] T12
10U_0805_10V4Z 1U_0402_6.3V4Z 11mA AJ4 R271 0_0603_5% +3VS AG23 T13
2 2 VCCHDA VSS[056] VSS[162]
1 +1.5VS AG3 VSS[057] VSS[163] T14
47mA 11mA AJ3 R272 0_0603_5% AG6 T15
VCCSUSHDA C306 IHDMI@ VSS[058] VSS[164]
AJ19 VCCSATAPLL AG9 VSS[059] VSS[165] T16
0.1U_0402_16V4Z AH12 T17
2 VSS[060] VSS[166]
1342mA VCCSUS1_05[1] AC8 TP_VCCSUS1_05_ICH_1 @ PAD T10 AH14 VSS[061] VSS[167] T23
+1.5VS AC16 VCC1_5_A[01] VCCSUS1_05[2] F17 TP_VCCSUS1_05_ICH_2 @ PAD T11 AH17 VSS[062] VSS[168] B26
1 1 AD15 VCC1_5_A[02] AH19 VSS[063] VSS[169] U12
AD16 +ICH_SUSHDA AH2 U13
C307 C308 VCC1_5_A[03] NIHDMI@ VSS[064] VSS[170]
AE15 VCC1_5_A[04] VCCSUS1_5[1] AD8 AH22 VSS[065] VSS[171] U14

ARX
1U_0402_6.3V4Z 1U_0402_6.3V4Z AF15 R273 0_0603_5% +3V_SB AH25 U15
2 2 VCC1_5_A[05] VSS[066] VSS[172]
AG15 VCC1_5_A[06] VCCSUS1_5[2] F18 +VCCSUS1_5_ICH_INT 1 +VCCSUS1_5_ICH_INT AH28 VSS[067] VSS[173] U16
close to AE15 close to AF11 AH15 1 R274 0_0603_5% AH5 U17
VCC1_5_A[07] C310 C309 IHDMI@ VSS[068] VSS[174]
AJ15 VCC1_5_A[08] 212mA AH8 VSS[069] VSS[175] AD23
A18 0.1U_0402_16V4Z AJ12 U26
VCCSUS3_3[01] 0.1U_0402_16V4Z 2 VSS[070] VSS[176]
AC11 VCC1_5_A[09]
VCCPSUS VCCSUS3_3[02] D16 AJ14 VSS[071] VSS[177] U27
2
Symbol S0 S3 S4/S5 AD11 VCC1_5_A[10] VCCSUS3_3[03] D17 AJ17 VSS[072] VSS[178] U3
AE11 VCC1_5_A[11] VCCSUS3_3[04] E22 AJ8 VSS[073] VSS[179] V1
AF11 VCC1_5_A[12] B11 VSS[074] VSS[180] V13
ATX

VCCLAN1_05 VCC_1_05 VCCLAN3_3 VCCLAN3_3 AG10 VCC1_5_A[13] B14 VSS[075] VSS[181] V15
AG11 VCC1_5_A[14] B17 VSS[076] VSS[182] V23
AH10 VCC1_5_A[15] B2 VSS[077] VSS[183] V28
VCCCL1_5 VCC_1_5_A VCCCL3_3 VCCCL3_3 close to AC9 AJ10 VCC1_5_A[16] VCCSUS3_3[05] AF1 +3V_SB B20 VSS[078] VSS[184] V29
B B23 VSS[079] VSS[185] V4 B
+1.5VS AC9 VCC1_5_A[17] 1 1 1 B5 VSS[080] VSS[186] V5
VCCCL1_05 VCC_1_05 VCCCL3_3 VCCCL3_3 B8 VSS[081] VSS[187] W26
1 1 AC18 C311 C312 C313 C26 W27
C314 C315 VCC1_5_A[18] 0.022U_0402_16V7K 0.022U_0402_16V7K 0.1U_0402_16V4Z VSS[082] VSS[188]
AC19 VCC1_5_A[19] C27 VSS[083] VSS[189] W3
2 2
VCCSUS1_5 VCC_1_5_A VCCSUS3_3 VCCSUS3_3 VCCSUS3_3[06] T1 close to T1 close to AF1 2 E11 VSS[084] VSS[190] Y1
0.1U_0402_16V4Z AC21 T2 E14 Y28
2 2 VCC1_5_A[20] VCCSUS3_3[07] VSS[085] VSS[191]
VCCSUS3_3[08] T3 E18 VSS[086] VSS[192] Y29
VCCSUS1_05 VCC_1_05 VCCSUS3_3 VCCSUS3_3 0.1U_0402_16V4Z G10 T4 E2 Y4
VCC1_5_A[21] VCCSUS3_3[09] VSS[087] VSS[193]
G9 VCC1_5_A[22] VCCSUS3_3[10] T5 E21 VSS[088] VSS[194] Y5
Internal voltage regulators power these wells inside the ICH9 VCCSUS3_3[11] T6 E24 VSS[089] VSS[195] AG28
close to AC14 AC12 U6 E5 AH6
VCCPUSB

and current for this rail is accounted for in the sourcing voltage VCC1_5_A[23] VCCSUS3_3[12] VSS[090] VSS[196]
AC13 VCC1_5_A[24] VCCSUS3_3[13] U7 E8 VSS[091] VSS[197] AF2
rail current requirements. AC14 V6 F16 B25
VCC1_5_A[25] VCCSUS3_3[14] VSS[092] VSS[198]
close to AC7 close to AJ5 VCCSUS3_3[15] V7 F28 VSS[093]
+1.5VS AJ5 VCCUSBPLL 11mA VCCSUS3_3[16] W6 F29 VSS[094]
1 1 VCCSUS3_3[17] W7 G12 VSS[095]
USB CORE

AA7 VCC1_5_A[26] VCCSUS3_3[18] Y6 G14 VSS[096] VSS_NCTF[01] A1

C316 C317 AB6 Y7 G18 A2
0.1U_0402_16V4Z 0.1U_0402_16V4Z VCC1_5_A[27] VCCSUS3_3[19] VSS[097] VSS_NCTF[02]
AB7 VCC1_5_A[28] VCCSUS3_3[20] T7 G21 VSS[098] VSS_NCTF[03] A28
2 2
AC6 VCC1_5_A[29] G24 VSS[099] VSS_NCTF[04] A29
AC7 VCC1_5_A[30] G26 VSS[100] VSS_NCTF[05] AH1
G27 VSS[101] VSS_NCTF[06] AH29
VCCLAN1_05_INT_ICH A10 G8 AJ1
VCCLAN1_05[1] VCCCL1_05_INT_ICH VSS[102] VSS_NCTF[07]
1 A11 VCCLAN1_05[2] VCCCL1_05 G22 H2 VSS[103] VSS_NCTF[08] AJ2
G23 VCCCL1_5_INT_ICH 1 H23 AJ28
C318 VCCCL1_5 VSS[104] VSS_NCTF[09]
+3VS A12 VCCLAN3_3[1] 1 1 H28 VSS[105] VSS_NCTF[10] AJ29
0.1U_0402_16V4Z C319
2 1
+1.5VS
B12 VCCLAN3_3[2] 78mA C320 C321 0.1U_0402_16V4Z
H29 VSS[106] VSS_NCTF[11] B1
VCCCL3_3[1] A24 +3VS VSS_NCTF[12] B29
C322 1U_0402_6.3V4Z 0.1U_0402_16V4Z 2
VCCCL3_3[2] B24
2 2
close to G22
GLAN POWER

0.1U_0402_16V4Z A27 23mA

2 VCCGLANPLL ICH9-M ES_FCBGA676
1 close to G23
D28 ICH9R3@
A
C323 VCCGLAN1_5[1] A
D29 VCCGLAN1_5[2] 80mA
0.1U_0402_16V4Z E26
2 VCCGLAN1_5[3]
E27 VCCGLAN1_5[4]
+1.5VS
A26 VCCGLAN3_3 1mA
1 ICH9-M ES_FCBGA676
ICH9R3@
C324
+3VS Security Classification Compal Secret Data Compal Electronics, Inc.
0.1U_0402_16V4Z 2008/10/06 2009/10/06 Title
2 Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 25 of 48
5 4 3 2 1
 5 4 3 2 1

SATA HDD Conn. SSD Conn. SATA ODD Conn

+5VS +5VS
Place closely JP25 SATA CONN.
1.2A SSD HDD need 400mA for 3V(PHISON) 1.1A
+3VS
1
C387
1
C388
1
C389
1
C390
+3VS rail reserve for SSD
1 1 1 1 1
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 1 1 C414 C415 C416
C194 C195 C196 C197 @ C417 C418
2 2 2 2 10U_0805_10V4Z 10U_0805_10V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 2
2 SSD@ 2 2 2
D SSD@ SSD@ SSD@ D

SSD HDD need 400mA for 3V(PHISON) Place component's closely ODD CONN.
+3VS
+3VS rail reserve for SSD
1 1 1
C336 C337 1 C338 C339
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z JSSD @
@ @ @ @ 1 SSD@
2 2 2 GND SATA_ITX_C_DRX_P0 C514 1
A+ 2 2 0.01U_0402_25V7K SATA_ITX_DRX_P0 22
2 SATA_ITX_C_DRX_N0 C515 1
A- 3 2 0.01U_0402_25V7K SATA_ITX_DRX_N0 22
4 SSD@ SSD@
GND SATA_IRX_DTX_N0 C411 1
B- 5 2 0.01U_0402_25V7K SATA_IRX_C_DTX_N0 22
6 SATA_IRX_DTX_P0 C413 1 2 0.01U_0402_25V7K
B+ SATA_IRX_C_DTX_P0 22
7 SSD@
GND JODD @

JHDD0 @ 8 1
V33 +3VS GND
1 9 2 SATA_ITX_C_DRX_P4 C518 1 2 0.01U_0402_25V7K
GND V33 A+ SATA_ITX_DRX_P4 22
2 SATA_ITX_C_DRX_P1 C512 1 2 0.01U_0402_25V7K 10 3 SATA_ITX_C_DRX_N4 C519 1 2 0.01U_0402_25V7K
A+ SATA_ITX_DRX_P1 22 GND A- SATA_ITX_DRX_N4 22
3 SATA_ITX_C_DRX_N1 C513 1 2 0.01U_0402_25V7K 11 4
A- SATA_ITX_DRX_N1 22 GND GND
4 12 5 SATA_IRX_DTX_N4 C424 1 2 0.01U_0402_25V7K
GND V5 B- SATA_IRX_C_DTX_N4 22
5 SATA_IRX_DTX_N1 C410 1 2 0.01U_0402_25V7K 13 6 SATA_IRX_DTX_P4 C425 1 2 0.01U_0402_25V7K
B- SATA_IRX_C_DTX_N1 22 V5 B+ SATA_IRX_C_DTX_P4 22
6 SATA_IRX_DTX_P1 C412 1 2 0.01U_0402_25V7K 14 7
B+ SATA_IRX_C_DTX_P1 22 R GND
GND 7 17 GND Rsv1 15
18 GND Rsv2 16
V33 8 DP 8
9 SANTA_285002-1_RV 9 +5VS
V33 +3VS +5V
C 10 10 C
V33 +5V
MD 11
GND 11 15 GND GND 12
GND 12 14 GND GND 13
GND 13
V5 14 +5VS
15 SANTA_206401-1_RV
V5
V5 16
GND 17
LED 18
GND 19
V12 20
23 GND V12 21
24 GND V12 22

SANTA_195601-1_RV

Q8
USB Conn. +3VALW
AO3413_SOT23

+USB_VCCB +USB_VCCB

S
+USB_VCCC 1 3 +USB_VCCB
1

U52 +USB_VCCB
R949 R952 C353 0.1U_0402_16V4Z W=60mils

G
2
75K_0402_1% 43K_0402_1% USB20_P3_S 1 10 1 @ 2
B 1D+ VCC 0.1U_0402_16V4Z B
+USB_VCCC 27,33 USB_EN#
USB20_N3_S 2 9 SLP_CHG#
SLP_CHG# 21
2

1D- S
W=60mils USB20_P3_S_O USB20_P3 USB20_P3_R
1 1 1
21 USB20_P3 3 2D+ D+ 8
JUSBB1 USB20_N3_S_O +USB_VCCB C350 +
1 USB20_N3 4 7 USB20_N3_R C352 C351
1 21 USB20_N3 2D- D- D15
1

2 2
2 2 R951 R950 USB20_N3_R 2
21 USB20_N2 3 3 5 GND OE# 6 4 VIN IO1 2
21 USB20_P2 4 51K_0402_1% 51K_0402_1% 150U_D_6.3VM 1000P_0402_50V7K
4 USB20_P3_R
5 5 3 IO2 GND 1
6
2

6 CM1293A-02SR SOT143-4
ACES_85202-0605L TS3USB221RSER_QFN10_2x1P5~D eSATA/USB Conn
+5VALW JESATA
@ U53
1 USB
eSATA/USB 21 SLP_CHG_M3 1 1OE# USB_EN#
USB20_N3_R
USB20_P3_R
2
VBUS
D-
W=60mils 4 2OE# 1
R568
2
100K_0402_5%
3 D+
10 4
+5VALW 1.4A
U19
+USB_VCCB 21 SLP_CHG_M4
13
3OE#
4OE#
GND
5 GND
1 8 USB20_P3_S 2 3 USB20_P3_S_O C520 1 2 0.01U_0402_25V7K SATA_ITX_C_DRX_P5 6
GND OUT 1A 1B 22 SATA_ITX_DRX_P5 A+ ESATA
2 7 USB20_N3_S 5 6 USB20_N3_S_O C521 1 2 0.01U_0402_25V7K SATA_ITX_C_DRX_N5 7
IN OUT 2A 2B 22 SATA_ITX_DRX_N5 A-
3 IN OUT 6 9 3A 3B 8 R111 1 2 100_0402_5% 8 GND SHIELD 12
33 USB_CHG_EN# 4 5 12 11 C361 1 2 0.01U_0402_25V7K SATA_IRX_DTX_N5 9 13
EN# FLG USB_OC#2 21,33 4A 4B 22 SATA_IRX_C_DTX_N5 B- SHIELD
C357 1 2 0.01U_0402_25V7K SATA_IRX_DTX_P5 10 14
22 SATA_IRX_C_DTX_P5 B+ SHIELD
G528_SO8 1 +USB_VCCB 14 7 11 15
C367 VCC GND GND SHIELD
2
4.7U_0805_10V4Z SN74CBT3125PWRG4_TSSOP14 TYCO_1909574-1
A A
@ C354 @
2
0.1U_0402_16V4Z
1

SLP_CHG_M3 SLP_CHG_M4 SLP_CHG FUNCTION Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
Mode 3 HIGH LOW LOW D=1D SCHEMATIC,MB A4991
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Mode 4 D
LOW HIGH HIGH D=2D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 26 of 48
5 4 3 2 1
 5 4 3 2 1

B-CAS Circuit
+5VS
+5VALW

1
TV@ 2 Inrush current = 0A
TV@RB2
TV@RB2 C486
0.1U_0402_16V7K
100K_0402_5% 1

3
TV@ RB5 1 S
CB1 TV@

2
G
D 1 2 2 QB1 TV@ 4.7U_0603_6.3V6K D
47K_0402_5% AO3413_SOT23-3

1
D D 2
2

1
BCPWON 2 QB3 TV@
28 BCPWON +5VS_L_BCAS
G 2N7002_SOT23-3 CB2

1
S TV@ 0.01U_0402_25V7K

3
1
TV@ RB7

1
10K_0402_5% 1
+5VS_BCAS +5VS_L_BCAS
2

TV@ RB8 CB3 TV@ LB1 TV@

2.2K_0402_5% 4.7U_0603_6.3V6K 1 2
2
1 1 FBMA-L11-201209-221LMA30T_0805

2
CB4
TV@ CB5 TV@
+5VS_L_BCAS 0.1U_0402_16V4Z 1U_0402_6.3V4Z
2 2
5

UB1 TV@
1 JBCAS1 @
P

A B_R_BCRST B_BCRST
O 4 1 2 12 GND 10 10
BCRSTM 2 RB9 100_0402_5% 11 9 B_XBCCLK
28 BCRSTM B GND 9
G

TV@ 8 B_BCRST
NC7ST08P5X_NL _SC70 8
7 +5VS_BCAS
3

7
6 6 2 1 BCCDET BCCDET 28
5 RB10 TV@470_0402_5%
5
4 4
3 3
5

C UB2 TV@ 2 BCIO C

2
1 1
P

A B_R_XBCCLK 1 B_XBCCLK 1
O 4 2
XBCLKM 2 RB11 100_0402_5% ACES_85201-10051
28 XBCLKM B
G

TV@
NC7ST08P5X_NL _SC70
3

+5VS_L_BCAS

1 2
RB12 TV@
3

RB1 TV@ E 10K_0402_5%

+5VS_L_BCAS 1 2 2 1 2 QB4 TV@ BCIO
B BCIO 28
RB13 TV@ 2SB1197K_SOT23-3
10K_0402_5% 10K_0402_5% C
1

1 2
1

D RB14 TV@
CPLGP1 2 QB2 1.5K_0402_5%
28 CPLGP1
G 2N7002_SOT23-3
S TV@
3

+3VALW_CARD +3VS_CARD +1.5VS_CARD

Imax = 0.275A Imax = 1.35A Imax = 0.75A
1 1 1 1 1 1 JEXP
B B
CN1 CN2 CN3 CN4 CN5 CN6 1
10U_0805_10V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z GND
21 USB20_N4 2 USB_D-
2 2 2 2 2 2
21 USB20_P4 3 USB_D+
CP_USB# 4 CPUSB#
UN1 5 RSV
+3V_SB
60mils 6 RSV
+1.5VS 12 11 +1.5VS_CARD PM_SMBCLK 7
1.5Vin 1.5Vout 14,15,16,23,28 PM_SMBCLK SMB_CLK
1 2 CP_USB# 14 1.5Vin 1.5Vout 13 14,15,16,23,28 PM_SMBDATA
PM_SMBDATA 8 SMB_DATA
RN1 100K_0402_5% +1.5VS_CARD 9 +1.5V
share with USB OC PIN 40mils 10 +1.5V
+3VS 2 3 +3VS_CARD SB_WAKE# 11
3.3Vin 3.3Vout 23,33 SB_WAKE# WAKE#
RN2
1 2EXP_CPPE#
100K_0402_5%
need always pull high 4 3.3Vin 3.3Vout 5 +3VALW_CARD
PERST#
12 +3.3VAUX
40mils 13 PERST#
+3V_SB 17 AUX_IN AUX_OUT 15 +3VALW_CARD +3VS_CARD 14 +3.3V
1 2 PLT_RST# 15 +3.3V
RN3 100K_0402_5% PLT_RST# 6 19 CLKREQ# 16
8,17,21,28,29,32,33,34 PLT_RST# SYSRST# OC# CLKREQ#
EXP_CPPE# 17
21 EXP_CPPE# CPPE#
20 8 PERST# 18
33,42 SYSON SHDN# PERST# 16 CLK_NEW# REFCLK-
16 CLK_NEW 19 REFCLK+
+3VS +3VS 1 16 20
17,30,33,36,39,41 SUSP# STBY# NC GND
21 PCIE_IRX_C_NEWTX_N1 21 PERn0
+3VS EXP_CPPE# 10 7 22
CPPE# GND 21 PCIE_IRX_C_NEWTX_P1 PERp0
1

RN4 1 23
CN7 CP_USB# GND
9 CPUSB# Thermal_Pad 21 21 PCIE_ITX_C_NEWRX_N1 24 PETn0
1

10K_0402_5% @ @ 21 PCIE_ITX_C_NEWRX_P1 25
RN5 @ 0.1U_0402_16V4Z RCLKEN PETp0
18 RCLKEN 26 GND GND 29
5

UN2 2
30
2

10K_0402_5% CLKREQ# GND

2 27
G Vcc

A B G577NSR91U_TQFN20_4x4 GND A
4 CLKREQ_NEW# 28
CLKREQ_NEW# 16
2

Y GND
1 A SANTA_130801-5_RT
1

@ D NC7SZ32P5X_NL_SC70-5 @
3

RCLKEN 2 Q21 @
G 2N7002_SOT23-3
S RN6 0_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
3

another at page35 CLKREQ# 1 2 CLKREQ_NEW# 2008/10/06 2009/10/06 Title

Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 27 of 48
5 4 3 2 1
 5 4 3 2 1

BlueTooth Interface +3VS

+3VS
Right USB Board
Inrush current = 0A

W=60mils

2
R432
100K_0402_5%
C481
0.1U_0402_16V7K
2
BT@
C482 BT@
0.1U_0402_16V4Z
+5VALW 1.4A
U25
+USB_VCCA +USB_VCCA

BT@ 1 8 W=60mils JUSBB2

GND OUT

3
1
S
R441 BT@ 2 7 1

1
G IN OUT 1
23 BT_PWR# 1 2 2 3 IN OUT 6 2 2
47K_0402_5% 2 JBT 25,33 USB_EN# 4 5 1 2 USB_OC#0 21,33 3
BT@ Q25 BT@ EN# FLG 3
12 1 R422 0_0402_5% 4
D
D D

1
C232 AO3413_SOT23 GND2 G528_SO8 4
11 GND1 5 5
0.01U_0402_25V7K C438 6
1 4.7U_0805_10V4Z 6
21 USB20_N0 7 7
2 @
+BT_VCC 21 USB20_P0 8 8
10 10 9 9
21 USB20_P5 9 9 21 USB20_N1 10 10
21 USB20_N5 8 8 21 USB20_P1 11 11
28 WLAN_BT_CLK 7 7 12 12
BT@ 23 BT_DET# 1 BT@ 2 6 13
6 GND
23 BT_RST# 2 1BT_RESET# R437 0_0402_5% 5 5 14 GND
R722 0_0402_5% 4
28 WLAN_BT_DATA 4
3 E&T_6905-E12N-00R
3
+3VS 1 2 2 2 @
R438 @ 1
4.7K_0402_5% 1
+BT_VCC
ACES_87213-1000G

2
C754 (MAX=200mA)
1 @
0.1U_0402_16V4Z
@ C483 C479 BT@R439
BT@R439
4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7K_0402_5%
BT@ 2 BT@

1
FM tuner +3VS

FM_I2CCLK 1 2
R725 FM@ 4.7K_0402_5%
JFM FM_I2CDAT 1 2
C 1 +3VS R726 FM@ 4.7K_0402_5% C
1 FM_I2CINT
2 2 1 2
3 FM_I2CCLK R727 @ 100K_0402_5%
Finger printer 3
4 4
5
FM_I2CDAT
FM_I2CINT_R
FM_I2CCLK 23
FM_I2CDAT 23
1 2FM_I2CINT
5 FM_I2CINT 23
6 6 FM_LINE_R 30 R728 @ 0_0402_5%
D21 7 7 FM_LINE_L 30
JFP @ 8
8
+3VS 1 R119 2 +3VS_FP 1 1
+3VS_FP 4 VIN IO1 2 USB20_P8
9 9
0_0603_5% 1 2 10
21 USB20_N8 2 10
FP@ C468 USB20_N8
21 USB20_P8 3
4
3 GND 5
6
3 IO2 GND 1 GND 11
12
Change at PVT-3
0.1U_0402_16V4Z FP@ 4 GND PRTR5V0U2X_SOT143-4 GND
1

2 ACES_85201-04051 ACES_85201-1005N
R118 @ @
0_0603_5% For EMI request
FP@
2

+FLICA_VCC
Felica
1
+5VS
C758 FLICA@ +5VS Inrush current = 0A
JFEL 0.1U_0402_16V4Z
2
1 1 2

2
2 USB20_N9 C397 C403 FLICA@
2 USB20_N9 21
3 USB20_P9 R414 0.1U_0402_16V7K FLICA@ 0.1U_0402_16V4Z
3 USB20_P9 21
4 100K_0402_5%
MDC 1.5 Conn. 4
5 5 FLICA@ 1

3
S
B R391 FLICA@ B
6

1
6 G
Q20
G1 7 1 2 2

1
+3V_SB 8 47K_0402_5% AO3413_SOT23
G2

1
R131 D D FLICA@
2

1
ACES_87151-06051 0_0603_5% 2 FLICA@
22 FELICA_PWR
1 1 1 @ FLICA@ G C233
FLICA@ Q28 S 0.01U_0402_25V7K

3
C778 C779 C780 2N7002_SOT23-3 1
+FLICA_VCC
1000P_0402_50V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z
2 MDC@ 2 MDC@ 2 MDC@
1 2 +3V_SB
R731 NIHDMI@ 0_0603_5%
1 2
1 R733 IHDMI@
+VCCSUS1_5_ICH_INT
0_0603_5% Int. Camera
R428 R293 0_0603_5%
JMDC @ C761 @
W=20mils
+5VALW 1 2+CAM_VDD USB20_N11 1 CAM@ 2 CAMERA_N 18
0.1U_0402_16V4Z 0_0603_5% USB20_P11 1 CAM@ 2
2 MDC@ CAMERA_P 18
1 2 +MDC R430 CAM@ R294 0_0603_5%
GND1 RES0
22 AZ_SDOUT_MD 3 IAC_SDATA_OUT RES1 4 +5VS 1 2 1 2 reserve for test, close to JCAM
5 6 +3V_SB CAM@ 0_0603_5% C744
GND2 3.3V 0.1U_0402_16V4Z
22 AZ_SYNC_MD 7 IAC_SYNC GND3 8
AZ_SDIN1_MD_R 9 10 JCAM
IAC_SDATA_IN GND4 R288 0_0603_5%
22 AZ_RST_MD# 11 IAC_RESET# IAC_BITCLK 12 AZ_BITCLK_MD 22 1 1
2 USB20_N11_R 1 @ 2
2 USB20_N11 21
2

3 USB20_P11_R 1 @ 2
3 USB20_P11 21
R496 4 R289 0_0603_5%
GND
GND
GND
GND
GND
GND

10_0402_5% 4
5 5
@ 6
GND1
2 1 AZ_SDIN1_MD_R ACES_88018-124G 7
13
14
15
16
17
18

A 22 AZ_SDIN1_MD GND2 A
R495 33_0402_5% MDC@ 1
C777 ACES_88266-05001
Connector for MDC Rev1.5 10P_0402_50V8J @
@
2

Security Classification Compal Secret Data Compal Electronics, Inc.

For EMI request 2008/10/06 2009/10/06 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 28 of 48
5 4 3 2 1
 UWB/JET (Slot3)
PCIe Mini Card-3G/GPS/TV Tuner (Slot2) +3VS +1.5VS
+3VS +1.5VS
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1
1 1 1 1 1 1
CM1 CM2 CM3 CM4 CM5 CM6
CM7 CM8 CM9 CM10 CM11 CM12

2
+1.5VS +3VS 2 2 2 2
47P_0402_50V8J 4.7U_0805_10V4Z 47P_0402_50V8J 4.7U_0805_10V4Z 2 2 2 2 2 2
JGPS For SED request For SED request 0.01U_0402_25V7K 4.7U_0805_10V4Z 0.01U_0402_25V7K 4.7U_0805_10V4Z
1 1 2 2
26 XBCLKM 3 3 4 4
26 BCCDET 5 5 6 6
7 8 +UIM_PWR RM2 0_0402_5%
16 CLKREQ_TV# 7 8
9 10 UIM_DATA Common 1 3G@ 2 UIM_VPP
9 10 UIM_CLK RM7 0_0402_5% +1.5VS +3VS
16 CLK_TV# 11 11 12 12
16 CLK_TV 13 14 UIM_RESET Common 1 TV@ 2 BCIO
13 14 BCIO 26
15 16 Common JNAND
15 16 ISDBT_DET
26 BCRSTM 17 17 18 18 ISDBT_DET 23 1 1 2 2
19 20 3G_OFF# 3 4
26 BCPWON 19 20 3G_OFF# 33 3 4
21 22 PLT_RST# 5 6
21 22 5 6
21 PCIE_IRX_C_TVTX_N5 23 23 24 24 16 CLKREQ_UWB# 7 7 8 8
25 26 R767 47K_0402_5% 9 10
21 PCIE_IRX_C_TVTX_P5 25 26 9 10
27 28 ISDBT_DET 1 TV@ 2 16 CLK_UWB# 11 12
27 28 11 12
29 29 30 30 USB20_P10 21 16 CLK_UWB 13 13 14 14
21 PCIE_ITX_C_TVRX_N5 31 31 32 32 USB20_N10 21 15 15 16 16
21 PCIE_ITX_C_TVRX_P5 33 33 34 34 17 17 18 18
35 36 USB20_N6 21 19 20 UWB_OFF#
35 36 19 20 UWB_OFF# 33
TV 37 38 USB20_P6 21 21 22 PLT_RST#
37 38 21 22
+3VS 39 39 40 40 21 PCIE_IRX_C_NANDTX_N2 23 23 24 24
41 42 LED_WIMAX# 25 26
41 42 21 PCIE_IRX_C_NANDTX_P2 25 26
43 43 44 44 CPLGP1 26 27 27 28 28
45 45 46 46 TMPTU1_SXP 33 29 29 30 30
33 TMPTU2_SXP 47 47 48 48 21 PCIE_ITX_C_NANDRX_N2 31 31 32 32
49 49 50 50 3G/GPS +UIM_PWR 21 PCIE_ITX_C_NANDRX_P2 33 33 34 34
51 51 52 52 35 35 36 36
UWB 37 37 38 38
53 GND1 GND2 54 +3VS 39 39 40 40
41 42 LED_WIMAX#
41 42

1
RM1 43 44
FOX_AS0B226-S40N-7F 4.7K_0402_5% 43 44
45 45 46 46
@ @ 47 48
47 48
J3GSIM 49 49 50 50
51 52

2
+UIM_PWR 51 52
+UIM_PWR 1 VCC GND 4
UIM_RESET 2 5 UIM_VPP 53 54
RST VPP GND1 GND2
1

1 UIM_CLK 3 6 UIM_DATA
DM1 CLK I/O
CM13 RLZ20A_LL34 7 8 1 FOX_AS0B226-S40N-7F
NC NC
1

1
0.1U_0402_16V4Z 3G@ 1 1 @
3G@ 2 MOLEX_47273-0001 CM14
2

CM15 CM16 @ 22P_0402_50V8J

10P_0402_50V8J 10P_0402_50V8J DM2 DM3 DM4 2 @
3G@ 2 2 3G@ DAN217_SC59 DAN217_SC59 DAN217_SC59
@ @ @
3

2
+UIM_PWR

PCIe Mini Card-WLAN/WiMax (Slot1) +3V_WLAN +1.5VS

Kill SWITCH
+3V_WLAN
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1
1

2
+3V_WLAN
+1.5VS CM17 CM18 CM19 CM20 CM21 CM22 SW1 DM5
5 DAN217_SC59
2

JWLAN 2 2 2 2 G2 @
G1 4
1 2 47P_0402_50V8J 4.7U_0805_10V4Z 47P_0402_50V8J 4.7U_0805_10V4Z RM5
1 2 For SED request For SED request
27 WLAN_BT_DATA 3 4 1 2 +3V_WLAN

1
3 4 100K_0402_5%
27 WLAN_BT_CLK 5 5 6 6 3 3
16 CLKREQ_WLAN# 7 7 8 8 2 2 KILL_SW# 33
9 9 10 10 1 1
16 CLK_WLAN# 11 11 12 12
13 14 1BS003-1210L_3P
16 CLK_WLAN 13 14 Default Setting
15 15 16 16
17 18 PJ18
17 18 XMIT_OFF#
19 19 20 20 +3V_WLAN 2 2 1 1 +3VS
21 22 PLT_RST# +3V_WLAN
21 22 PLT_RST# 8,17,21,26,29,32,33,34
23 24 @ JUMP_43X79 CM23 0.1U_0402_16V4Z
21 PCIE_IRX_C_WLANTX_N4 23 24
21 PCIE_IRX_C_WLANTX_P4 25 25 26 26 1 2
27 28 PJ19
27 28

5
29 30 PM_SMBCLK 2 1 +3V_SB
29 30 PM_SMBCLK 14,15,16,23,26 2 1
31 32 PM_SMBDATA 2 0_0402_5% RM3

P
21 PCIE_ITX_C_WLANRX_N4 31 32 PM_SMBDATA 14,15,16,23,26 33 WL_OFF# B
33 34 @ JUMP_43X79 4 XMIT_OFF# 2 @ 1 3G_OFF#
21 PCIE_ITX_C_WLANRX_P4 33 34 Y
35 36 USB20_N7 21 KILL_SW# 1
35 36 A

G
WLAN/ WiFi 37 37 38 38 USB20_P7 21
UM1
+3V_WLAN 39 40

3
39 40 LED_WIMAX# NC7SZ08P5X_NL_SC70-5
41 41 42 42 LED_WIMAX# 35
Debug card using 43 43 44 44
R823 0_0402_5%
45 45 46 46
RM6
WiMax
47 47 48 48
33 E51_TXD 1 2 49 49 50 50 1 2 +3VS
1 2 51 52 100K_0402_5%
33 E51_RXD 51 52
R824 0_0402_5% WIMAX@
53 GND1 GND2 54
Security Classification Compal Secret Data Compal Electronics, Inc.
1

ACES_88911-5204 2008/10/06 2009/10/06 Title

R825
Issued Date Deciphered Date
100K_0402_5%
@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
2

D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 29 of 48
 5 4 3 2 1

1 2 +3V_LAN
+3V_LAN
UL1 RL1 3.6K_0402_5%
UL2 @ Close to Pin1,29,37,40
21 PCIE_IRX_C_LANTX_P3 CL1 1 2 0.1U_0402_16V7K PCIE_IRX_LANTX_P3 20 33 LAN_DO 4 5 2
HSOP LED3/EEDO LAN_DI DO GND CL3
LED2/EEDI 34 3 DI ORG 6
21 PCIE_IRX_C_LANTX_N3 CL2 1 2 0.1U_0402_16V7K PCIE_IRX_LANTX_N3 21 35 LAN_SK 2 7 @ 1 2
HSON LED1/EESK LAN_CS SK NC 0.1U_0402_16V4Z CL4
EECS 32 1 CS VCC 8 +3V_LAN
1
0.1U_0402_16V4Z
21 PCIE_ITX_C_LANRX_P3 15 HSIP 1 2
CAT93C46VI-GT3_SO8 0.1U_0402_16V4Z CL5
D 21 PCIE_ITX_C_LANRX_N3 16 HSIN 1 2 D
38 LAN_ACTIVITY# 1 2 0.1U_0402_16V4Z CL6
+3V_LAN LED0 RL2 1K_0402_5% 1 2
25 2 LAN_MDI0+ 8103EL@ 0.1U_0402_16V4Z CL7
@ LAN_WAKE# CLKREQB MDIP0 LAN_MDI0-
1 2 MDIN0 3 8111DL@
RL3 100K_0402_5% 17 5 LAN_MDI1+
16 CLK_LAN REFCLK_P MDIP1
6 LAN_MDI1-
MDIN1 LAN_MDI2+
16 CLK_LAN# 18 REFCLK_N NC/MDIP2 8
9 LAN_MDI2-
NC/MDIN2 LAN_MDI3+
8,17,21,26,28,32,33,34 PLT_RST# 27 PERSTB NC/MDIP3 11
12 LAN_MDI3- RL16 8103EL@ Close to Pin10,13,30,36,39
NC/MDIN3
1 2
+LAN_CTRL12A 48 13 0_0603_5% +LAN_DVDD12
VCTRL12A/SROUT12 DVDD12 +LAN_DVDD12 +LAN_AVDD12
DVDD12 30
+LAN_DVDD12 4 NC/FB12 DVDD12 36
LL1 8111DL@ 1 2
+3VS RL4 43 19 +LAN_CTRL12A 1 2 0.1U_0402_16V4Z CL19
+3V_LAN NC/ENSWREG VDDTX/EVDD12 +LAN_EVDD12
0_0402_5% 8111DL@ 4.7UH_1008HC-472EJFS-A_5%_1008 1 2
1 2 46 29 +3V_LAN 1 2 0.1U_0402_16V4Z CL20
RSET VDD33
1

RL5 2.49K_0402_1% 37 Layout Note: LL1 must be 1 2

RL6 VDD33 within 500mil to Pin1 CL8 CL9 0.1U_0402_16V4Z CL21
1K_0402_1% LAN_WAKE# 26 44 +LAN_CTRL12VDD CL8,CL9 must be within 22U_0805_6.3V6M 0.1U_0402_16V4Z 1 2
33 LAN_WAKE# LANWAKEB NC/VDDSR 500mil to LL1 8111DL@2 1 0.1U_0402_16V4Z CL22
ISOLATEB 28 1 +3V_LAN 1 2
2

ISOLATEB AVDD33
23 LAN_ISOLATE# 2 R398 1 ISOLATEB
NC/AVDD33 40 [email protected]_0402_16V4Z CL23
1K_0402_1%
@ LAN_X1 41 10 +LAN_DVDD12
CKTAL1 DVDD12/AVDD12
RL7 LAN_X2 42 +LAN_AVDD12
C 15K_0402_5% CKTAL2 +LAN_EVDD12 C
NC/AVDD12 39
+LAN_CTRL12VDD 45 1 2 Close to Pin 44,45
VCTRL12D/VDDSR DSM# LL2 0_0603_5%
NC/GPO 23 2 1 LAN_DSM# 23 1 1
YL1 7 24 R399 8111DL@ +LAN_DVDD12
LAN_X1 2 GND NC
1LAN_X2 14 GND
0_0402_5% CL17 CL18 1 2
31 22 @ 1U_0402_6.3V4Z 1U_0402_6.3V4Z RL8 0_0603_5% +3V_LAN
GND EGND 2 2 8103EL@
25MHz_20pF_6X25000017 47 GND
1 1 Pin23 is GPO pin for 8111DL to +LAN_CTRL12VDD 1 2
1 1 LL4 0_0603_5%
CL24 CL25
be used DSM function 8111DL@
Close to Pin19
27P_0402_50V8J 27P_0402_50V8J 8111DL@ CL28 CL29
2 2 RTL8111DL-GR_LQFP48_7X7 0.1U_0402_16V4Z 22U_0805_6.3V6M
2 2 8111DL@
<BOM Structure> <BOM Structure>

+LAN_DVDD12 +LAN_AVDD12

1 2
RL9 0_0603_5%
pin assignments table for difference 8111DL@ LAN Conn.
Pin 8111DL 8103EL
4 FB12 NC JLAN
8 MDIP2 NC LAN_ACTIVITY# 2 1 RL10 12
150_0402_5% Yellow LED-
9 MDIN2 NC 1
10 AVDD12 DVDD12 +3V_LAN 2 1 11
11 MDIP3 NC UL3 CL43 RL17 150_0402_5% Yellow LED+
B CL39 1000P_0402_50V7K 68P_0402_50V8J RJ45_MIDI3- B
12 MDIN3 NC 8 PR4-
2
19 EVDD12 VDDTX 1 TCT1 MCT1 24 2 1 1 8111DL@2
23 GPO NC LAN_MDI3- 2 23 RL11 75_0402_1% RJ45_MIDI3- RJ45_MIDI3+ 7
LAN_MDI3+ TD1+ MX1+ RJ45_MIDI3+ PR4+
33 EEDO LED3 3 TD1- MX1- 22
34 EEDI LED2 CL40 1000P_0402_50V7K RJ45_MIDI1- 6 PR2-
35 EESK LED1 4 TCT2 MCT2 21 2 1 1 8111DL@2
39 AVDD12 NC LAN_MDI2- 5 20 RL12 75_0402_1% RJ45_MIDI2- RJ45_MIDI2- 5
LAN_MDI2+ TD2+ MX2+ RJ45_MIDI2+ PR3-
40 AVDD33 NC 6 TD2- MX2- 19
43 ENSR NC CL41 1000P_0402_50V7K RJ45_MIDI2+ 4 PR3+
44 VDDSR NC 7 TCT3 MCT3 18 2 1 1 2
45 VDDSR VCTRL12D LAN_MDI1- 8 17 RL13 75_0402_1% RJ45_MIDI1- RJ45_MIDI1+ 3
LAN_MDI1+ TD3+ MX3+ RJ45_MIDI1+ PR2+
48 SROUT12 VCTRL12A 9 TD3- MX3- 16
CL42 1000P_0402_50V7K RJ45_MIDI0- 2 PR1-
10 TCT4 MCT4 15 2 1 1 2 SHLD2 14
LAN_MDI0- 11 14 RL15 75_0402_1% RJ45_MIDI0- RJ45_MIDI0+ 1
LAN_MDI0+ TD4+ MX4+ RJ45_MIDI0+ PR1+
12 TD4- MX4- 13 SHLD1 13
LAN_SK 2 1 RL14 10
150_0402_5% Green LED-
1
1 1 1 1 +3V_LAN 2 1 9 Green LED+
SUPERWORLD_SWG150401 CL44
CL32 CL33 8111DL@ 8111DL@
8111DL@ 68P_0402_50V8J RL18 150_0402_5% SUYIN_100073FR012G101ZL
0.01U_0402_25V7K 0.01U_0402_25V7K CL34 CL35 RJ45_GND 2
8111DL@ 2 2 8111DL@ 0.01U_0402_25V7K 2 2 0.01U_0402_25V7K
@

Place these components RJ45_GND 1 2 1000P_1808_3KV7K LANGND

CL36 1 1
colsed to LAN chip CL37 CL38
A A
0.1U_0402_16V4Z 4.7U_0603_6.3V6K
2 2

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 30 of 48
5 4 3 2 1
 5 4 3 2 1

+3VS_DVDD 1500P_0402_50V7K RA1

Codec For EMI request 10U_0805_10V4Z 30mil 2 1
1 1 1 1 0_0603_5%
+3VS
Audio regulator
CA1 CA2 CA57 1

1
C694
+AVDD 0.1U_0402_16V4Z RA2 C692
2 2 2 2 0.1U_0402_16V4Z
For EMI request RA3 40mil 0.1U_0402_16V4Z
0_0603_5%
2 +5VALW +5VS +VDDA
+1.5VS_DVDIO NIHDMI@
+VDDA 2 1 10U_0805_10V4Z 0.1U_0402_16V4Z For EMI request J3

2
0_0603_5% LA1 For EMI request @
1
CA3
1
CA4
1
CA5
1
CA6
1
10U_0805_10V4Z 20mil
1 2 2 1
+1.5VS 2 1
CA56 1 CA58 1 1 FBMA-L11-160808-800LMT_0603 4.75V
1500P_0402_50V7K IHDMI@ JUMP_43X39 2
2 2 2 2 2 CA7 CA8
D 2 D
10U_0805_10V4Z 0.1U_0402_16V4Z 1500P_0402_50V7K CA9 UA1 CA10
2 2 2 @ 1U_0402_6.3V4Z
0.1U_0402_16V4Z 1U_0402_6.3V4Z 1 @

25

38
1 VIN VOUT 5

9
U49 For EMI request 1
2 @ 1 LINE1_L 2

AVDD1

AVDD2

DVDD_IO
DVDD
100P_0402_25V8K CA52 GND CA11 @
2 @ 1 LINE1_R
17,26,33,36,39,41 SUSP# 3 SHDN# BP 4 2 1
100P_0402_25V8K CA53
14 35 0.22U_0402_10V4Z
LINE2-L LOUT1_L AMP_SPK_L 31
2 @ 1 15 LINE2-R LOUT1_R 36 AMP_SPK_R 31
APL5151-475BC-TRL_SOT23-5
100P_0402_25V8K CA43 @
MIC2_L 16 39 LA2 1 2
31 MIC2_L MIC2_L LOUT2_L SPDIF 31
2 @ 1 MBK1608121YZF_0603
100P_0402_25V8K CA44 MIC2_R 17 41 1 2
31 MIC2_R MIC2_R LOUT2_R CA39 @ 33P_0402_50V8K
1 2 LINE1_L 23 48
27 FM_LINE_L LINE1_L SPDIFO1
CA12 2.2U_0603_6.3V6K @ LA11 For EMI request
1 2 LINE1_R 24 45 1 2
27 FM_LINE_R LINE1_R SPDIFO2 SPDIF_MXM 17
CA13 2.2U_0603_6.3V6K MBK1608121YZF_0603
MIC1_C_L 21 33 1 RA5 2
31 MIC1_C_L MIC1_L HPOUT_L HP_L 31
2 1 63.4_0402_1%
100P_0402_25V8K CA45 MIC1_C_R 22 32 1 RA6 2
31 MIC1_C_R MIC1_R HPOUT_R HP_R 31
2 1 63.4_0402_1%
100P_0402_25V8K CA46
1 2 MONO_IN 12 37
CA14 100P_0402_25V8K BEEP_IN MONO_OUT
+MIC2_VREFO Beep sound
C 6 46 C
22 AZ_BITCLK_HD BITCLK DMIC_CLK1/2
5 44
22 AZ_SDOUT_HD SDATA_OUT DMIC_CLK3/4 CA42
1
EC Beep RA8
22 AZ_SDIN0_HD 2 1 AZ_SDIN0_HD_R 8 SDATA_IN LINE2_VREFO 20 1U_0402_6.3V4Z
33 EC_BEEP# 1 2
33_0402_5% RA7 47K_0402_5%
2
22 AZ_RST_HD# 11 RESET# LINE1_VREFO 18

10 28 10mil
22 AZ_SYNC_HD SYNC MIC1_VREFO
10mil
+MIC1_VREFO
PCI Beep RA9
CA15
19 +MIC2_VREFO 1 2 1 2 MONO_IN
MIC2_VREFO 23 SB_SPKR
23 SPK_SEL 2 GPIO0/DMIC_DATA1/2 47K_0402_5%
31 1 2 0.1U_0402_16V4Z
CPVEE CA16 2.2U_0603_6.3V6K
3 GPIO1/DMIC_DATA3/4
27 AC_VREF CA18 CA19 CA47
VREF

100P_0402_25V8K
10U_0805_10V4Z
SENSE_A

0.1U_0402_16V4Z
13 SENSE A
40 AC_JDREF 1 1 1
SENSE_B JDREF RA10 CA55
34 SENSE B

1
100P_0402_25V8K
CBN 30 1 2 1 1

20K_0402_1%
31 MUTE# 1 2 EAPD 47 EAPD
CA17 2.2U_0603_6.3V6K
RA32 0_0603_5% 2 2 2 RA11 CA20
CBP 29
43 10K_0402_5% 0.1U_0402_16V4Z
CA36 RA33 NC 2 2

2
1 2 2 1 AZ_BITCLK_HD 4 26
DVSS AVSS1
7 DVSS AVSS2 42
10P_0402_50V8J 10_0402_5% For EMI request
CA51 1 2 0.1U_0603_50V7K
ALC272-GR_LQFP48_7X7
CA48 1 2 0.1U_0603_50V7K
B DGND AGND B
CA49 1 2 0.1U_0603_50V7K

GPIO0-->SPK_SEL HIGH:HARMAN CA50 1 2 0.1U_0603_50V7K

LOW:NO-BRAND
RA12 1 2
0_0603_5%
RA13 1 2
0_0603_5%

Sense Pin Impedance Codec Signals Function place close to chip

39.2K PORT-A (PIN 39, 41)
31 MIC_SENSE 1 RA18 2 SENSE_A
20K_0402_1%
20K PORT-B (PIN 21, 22) Ext. MIC
SENSE A 1 RA19 2
10K_0402_1%
10K PORT-C (PIN 23, 24) FM@
FM tuner
5.1K PORT-D (PIN 35, 36) SPK out SENSE_B
31 NBA_PLUG 1 2
RA16 5.1K_0402_1%
39.2K PORT-E (PIN 14, 15)
A 1 RA17 2 A
20K_0402_1%
20K PORT-F (PIN 16, 17) MIC@
Int. MIC
SENSE B
10K PORT-H (PIN 37)
Security Classification Compal Secret Data Compal Electronics, Inc.
5.1K PORT-I (PIN 32, 33) Headphone out Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 31 of 48
5 4 3 2 1
 +5VS CH751H-40PT_SOD323-2
TPA6017 Medium Range Amplifier 0.1U_0402_16V4Z Ext. Mic CA21
RA21 2 RA20
1K_0402_5% 4.7K_0402_5%
1 1
DA1
2 +MIC1_VREFO
4.7U_0805_10V4Z 2 1 2 1 MIC1_L
30 MIC1_C_L
1 1 1
4.7U_0805_10V4Z 2 1 2 1 MIC1_R
30 MIC1_C_R
CA23 CA24 CA25 1K_0402_5%
10U_0805_10V4Z CA22 RA22 2 RA23 1 1 2 +MIC1_VREFO
2 2 2 4.7K_0402_5% DA2
CH751H-40PT_SOD323-2
0.1U_0402_16V4Z 10 dB
+5VS
Int. Mic RA24 2
4.7K_0402_5%
MIC@ 1
1
+MIC2_VREFO
CA35 1 @ 2 INT_MIC 18

1
1U_0402_6.3V4Z RA34 0_0402_5%

16
15
6
UA3 RA28 RA27 MIC@ RA25 MIC@ MIC@
100K_0402_5% 100K_0402_5% CA26 1K_0402_5% 2 JMIC
Put on close U49
Rin =70Kohm

VDD
PVDD1
PVDD2
@ 1U_0402_6.3V4Z 2 1 2 1 MIC MICOUT 1 1 NC1 3
30 MIC2_L
1 2 2 2 NC2 4

2
1U_0402_6.3V4Z 2 1 2 1 MIC@ CA27
30 MIC2_R
1 2 7 2 1K_0402_5% 220P_0402_50V7K ACES_85204-0200N
CA29 0.033U_0402_16V7K RIN+ GAIN0 CA28 RA26 MIC@ @
Put on close U49

3
3 MIC@
GAIN1 DA3
Put on close U49

1
30 AMP_SPK_R 1 2 LINE_C_OUTR 17 PACDN042Y3R_SOT23-3
CA30 0.033U_0402_16V7K RIN- SPKR+ RA30 RA29 MIC MIC1R MICOUT
ROUT+ 18 1 2 1 2
100K_0402_5% 100K_0402_5% RA36 0_0603_5% RA38 0_0603_5%
@ 1 @ 2 MIC2R 1 @ 2

1
14 SPKR- RA37 0_0603_5% RA39 0_0603_5%

2
ROUT-
1 2 9 LIN+
CA31 0.033U_0402_16V7K
4 SPKL+
LOUT+
30 AMP_SPK_L 1 2 LINE_C_OUTL 5
CA32 0.033U_0402_16V7K LIN-
LOUT- 8 SPKL- GAIN0 GAIN1 Av(db)Rin(ohm) Left Connector DA4 PACDN042Y3R_SOT23-3
2
0 0 6 90K 1
setting 68Hz 3
0 1 10 70K JSPKL
F=1/2πRC --> -3db 12 Keep 10 mil width SPKL+ LA3 1 2 FBMA-L11-160808-800LMT_0603 SPK_L1 1 3
NC SPKL- LA4 1 1 NC1
1 0 15.6 45K 2 FBMA-L11-160808-800LMT_0603 SPK_L2 2 2 NC2 4
C=0.033U,R=70K,F=68Hz 10 AMP_BYPASS
BYPASS ACES_85204-0200N
30 MUTE# 19 SHUTDOWN 1 1 21.6 25K
2 @
Right Connector
GND5
GND1
GND2
GND3
GND4 CA33 DA5 PACDN042Y3R_SOT23-3
0.47U_0603_10V7K 2
1
1
TPA6017A2_TSSOP20 3
21
20
13
11
1

JSPKR
SPKR+ LA5 1 2 FBMA-L11-160808-800LMT_0603 SPK_R1 1 3
SPKR- LA6 1 1 NC1
2 FBMA-L11-160808-800LMT_0603 SPK_R2 2 2 NC2 4
ACES_85204-0200N
@
KSO10 1 @ 2
C803 100P_0402_25V8K
KSO11 1 @ 2 HeadPhone/LINE Out JACK
KSO12
C804
1
100P_0402_25V8K
@ 2
KEYBOARD CONN. JBLG
1 1 +5VS_LED 30 NBA_PLUG 1
JLINE
1
C805 100P_0402_25V8K 2 LA7 1 2 HP_R_L 2
2 30 HP_R 2
KSO15 1 @ 2 3 1 KC FBM-L11-160808-121LMT 0603
C807 100P_0402_25V8K 3 C860 LA8 1
4 4 30 HP_L 2 HP_L_L 3 3
KSI7 1 @ 2 5 @ 0.1U_0402_16V4Z KC FBM-L11-160808-121LMT 0603
C808 100P_0402_25V8K KSI[0..7] GND
KSI[0..7] 33,35 GND 6 4 4
KSI2 @ 2 2 DA6
1 AGND
C810 100P_0402_25V8K KSO[0..17] ACES_85201-0405N 2 5
KSO[0..17] 33,35 5
KSI3 1 @ 2 @ 1
C811 100P_0402_25V8K 3 SPDIF_R 8
KSI4 @ 2 8
1 DRIVE
C812 100P_0402_25V8K 9
KSI0 1
C813
@ 2
100P_0402_25V8K
@
ACES_88170-3400 Keyboard LED PACDN042Y3R_SOT23-3
+5VS
1
CA37 10
9

10
IC

GND 6
KSI5 1 @ 2 NUM_LED# 1 2 SPDIF_R 0.1U_0402_16V4Z 7
1 NUM_LED# 33 +5VS_LED 30 SPDIF GND
C814 100P_0402_25V8K RA31 1
KSI6 @ 2 2 CAPS_LED# Q38 0_0603_5% 2
1 CAPS_LED# 33 SINGA_2SJ-A373-H01
C815 100P_0402_25V8K 3 AO3413_SOT23-3 CA34
4 2 1 +3VS @
KSI1 1 @ 2 KSI1 R509 300_0402_5% 100P_0402_25V8K
5 2
S

C816 100P_0402_25V8K KSI6 3 D

1
6 +5VS
CAPS_LED# 1 @ 2 KSI5
C817 100P_0402_25V8K 7 KSI0
8 1
1

NUM_LED# @ 2 KSI4
G

1
2

C819 100P_0402_25V8K 9 KSI3 R587 C836

KSO16 1
C809
@ 2
100P_0402_25V8K
10
11
KSI2
KSI7
+3VS 10K_0402_5% 0.1U_0402_16V4Z
2
Ext.MIC/LINE IN JACK AGND 5
JEXMIC @

KSO17 @ 2 12 KSO15
1
2

C806 100P_0402_25V8K 13 KSO12

14 30 MIC_SENSE 4
1

KSO2 1 @ 2 KSO11 @
C793 100P_0402_25V8K 15 KSO10 R588 MIC1_R LA9 1
16 2 MIC1_L_R 3
KSO1 1 @ 2 KSO9 100K_0402_5% KC FBM-L11-160808-121LMT 0603 6
C790 100P_0402_25V8K 17 KSO8 MIC1_L LA101
18 2 MIC1_L_L 2
1

KSO0 @ 2 KSO13 D KC FBM-L11-160808-121LMT 0603

1 1
2

19

100P_0402_25V8K

100P_0402_25V8K
C791 100P_0402_25V8K KSO7 Q51

0.1U_0402_16V4Z
20 33 KB_LED 2

CA38

CA40

CA41
KSO4 1 @ 2 KSO6 G 2N7002_SOT23-3 DA7 SINGA_2SJ-S351-015
21
1

C792 100P_0402_25V8K KSO14 S 2 1 1 1

3

KSO3 @ 2 22 KSO5 R589

1 23 1
C795 100P_0402_25V8K KSO3 100K_0402_5% 3
24

@
KSO5 1 @ 2 KSO4
C796 100P_0402_25V8K 25 KSO0 2 2 2
2

KSO14 @ 2 26 KSO1 PACDN042Y3R_SOT23-3

1 27
C797 100P_0402_25V8K KSO2
KSO6 @ 2 28 For EMI request
1 29
C798 100P_0402_25V8K
KSO7 @ 2 30 KSO17
1
C799 100P_0402_25V8K 31
32
Security Classification Compal Secret Data Compal Electronics, Inc.
KSO13 1 @ 2 KSO16 2008/10/06 2009/10/06 Title
C800 100P_0402_25V8K 33 Issued Date Deciphered Date
KSO8 1 @ 2 34 2 1
R510 300_0402_5%
+3VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
C801 100P_0402_25V8K JKB Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
KSO9 @ 2 D
1
C802 100P_0402_25V8K
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 32 of 48
 A B C D E

+1.8VS_OUT
40mil
0.1U_0402_16V4Z 1000P_0402_50V7K +3VALW
1 1 1 1 D3E mode
Power Circuit

1
CC1 CC2 CC3 CC4
R129
UC1 2 2 2 2 10K_0402_5%
1 10U_0805_10V4Z 0.1U_0402_16V4Z @ 1
3 5 +3VS

2
16 CLK_5IN1# APCLKN APVDD
16 CLK_5IN1 4 APCLKP APV18 10
1 2
9 CC5 0.1U_0402_16V4Z
21 PCIE_ITX_C_5IN1RX_N6 APRXN CPPE
21 PCIE_ITX_C_5IN1RX_P6 8 APRXP DV33 19 1 2 22 CR_CPPE# 1 2
20 CC6 0.1U_0402_16V4Z R400 0_0603_5%
CC7 0.1U_0402_16V7K PCIE_IRX_5IN1TX_N6 DV33
21 PCIE_IRX_C_5IN1TX_N6 1 2 11 APTXN DV33 44 +1.8VS_OUT
21 PCIE_IRX_C_5IN1TX_P6 CC8 1 2 0.1U_0402_16V7K PCIE_IRX_5IN1TX_P6 12 18
APTXP DV18
DV18 37 1 1
2 1 7 APREXT
8.2K_0402_5% RC1 48 XD_SD_MS_D0 CC9 CC10
MDIO0 XD_SD_MS_D1 0.1U_0402_16V4Z +VCC_OUT
MDIO1 47
XIN XD_SD_MS_D2 2 2
38 TXIN MDIO2 46 22 CR_WAKE# 1 2 XDCD0#_SDCD#
39 45 XD_SD_MS_D3 0.1U_0402_16V4Z R397 0_0603_5%
+3VS TXOUT JMB380 MDIO3
MDIO4 43 SDCMD_MSBS_XDWE# XDWP#_SDWP# 2 1
42 SDCLK_MSCLK_XDCE# RC3 10K_0402_5%
MDIO5 XDWP#_SDWP# XD_RB#
1 2 30 TAV33 MDIO6 41 2 1
CC12 0.1U_0402_16V4Z 40 XD_CLE RC4 10K_0402_5%
MDIO7 XD_SD_D4 SDCMD_MSBS_XDWE#
MDIO8 29 2 1
1 28 XD_SD_D5 RC2 10K_0402_5%
8,17,21,26,28,29,33,34 PLT_RST# XRSTN MDIO9 XD_SD_D6
2 XTEST MDIO10 27
26 XD_SD_D7
MDIO11 XD_RE#
MDIO12 25
+3VS CPPE 13 23 XD_RB#
TC2 PAD SEEDAT MDIO13 XD_ALE
14 SEECLK MDIO14 22 Strapping setting
1 2XDCD0#_SDCD# TPA1P 34 Description
RC5 4.7K_0402_5% XDCD1#_MSCD# 15 35 +3VS Pin name
XDCD0#_SDCD# CR1_CD1N TPBIAS_1
2 16 CR1_CD0N TREXT 36 1 2 High low 2
1 2 XDCD1#_MSCD# RC6 12K_0402_1%
RC7 4.7K_0402_5% 6 XD_CLE 1 2
APGND RC8 10K_0402_5%
+VCC_OUT 17 CR1_PCTLN MDIO7 on-board★ add-in card
1 2 XIN 24 1 2
RC11 10K_0402_5% TCPS RC9 10K_0402_5%
TPB1N 31
CR_LED 21 32 +VCC_OUT +VCC_OUT
CR1_LEDN TPB1P XD_RE#
TPA1N 33 1 2 MDIO12 high active low active★
RC10 200K_0402_5%
GND 49

JMB380-QGAZ0A_QFN48_7X7 MDIO14 CR_LED CR_LED

XD_ALE 1 2
RC12 10K_0402_5% high active★ low active

P.S CR1_PCTLN aslo can out 3V with 250mA for

5IN1 using.(MDIO12 can't be seted after MP IC)
CR_LEDCON CR_LEDCON 35

SDCLK_MSCLK_XDCE# 2 1 SDCLK
QC1 22_0402_5% 2 1 RC13 MSCLK
1

2N7002_SOT23-3 D 22_0402_5% 2 1 RC14 XDCE#

2 CR_LED 22_0402_5% RC15
G
2

S
3

RC17 SDCLK 1 2 1 2
3 4.7K_0402_5% 3
RC16 CC14
@ 100_0402_5% @ 100P_0402_25V8K
1

MSCLK 1 2 1 2
Card Reader Connector RC18 CC15
+VCC_OUT @ 100_0402_5% @ 100P_0402_25V8K
20 mils JREAD
3 XD-VCC SD-VCC 21 +VCC_OUT
MS-VCC 28
1 1 XD_SD_MS_D0 32
XD_SD_MS_D1 XD-D0 SDCLK
10 XD-D1 SD_CLK 20
CC17 CC18 XD_SD_MS_D2 9 14 XD_SD_MS_D0
10U_0805_10V4Z 0.1U_0402_16V4Z XD_SD_MS_D3 XD-D2 SD-DAT0 XD_SD_MS_D1
2 2
8 XD-D3 7 IN 1 CONN SD-DAT1 12
XD_SD_D4 7 30 XD_SD_MS_D2
XD_SD_D5 XD-D4 SD-DAT2 XD_SD_MS_D3
6 XD-D5 SD-DAT3 29
XD_SD_D6 5 27 XD_SD_D4
XD_SD_D7 XD-D6 SD-DAT4 XD_SD_D5
4 XD-D7 SD-DAT5 23
CC19@ 18 XD_SD_D6
@ XDCE# SDCMD_MSBS_XDWE# 34 SD-DAT6 XD_SD_D7
2 1 2 1 XD-WE SD-DAT7 16
RC24 100_0402_5% XDWP#_SDWP# 33 1 XDCD0#_SDCD#
100P_0402_25V8K XD_ALE XD-WP SD-CD XDWP#_SDWP#
35 XD-ALE SD-WP 2
XD_CD# 40 25 SDCMD_MSBS_XDWE#
XD_RB# XD-CD SD-CMD
39 XD-R/B
XD_RE# 38 26 MSCLK
XDCE# XD-RE MS-SCLK XD_SD_MS_D0
37 XD-CE MS-DATA0 17
DC2 XD_CLE 36 15 XD_SD_MS_D1
XDCD1#_MSCD# XD-CLE MS-DATA1 XD_SD_MS_D2
4 2 MS-DATA2 19 4
1 XD_CD# 31 24 XD_SD_MS_D3
XDCD0#_SDCD# 7IN1-GND MS-DATA3 XDCD1#_MSCD#
3 1 11 7IN1-GND MS-INS 22
41 13 SDCMD_MSBS_XDWE#
DAN202UT106_SC70-3 CC21 7IN1-GND MS-BS
42 7IN1-GND
270P_0402_50V7K
2
TAITW_R015-D10-LM_NR
@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 33 of 48
A B C D E
 5 4 3 2 1

+3VL
+3VL
0.1U_0402_16V4Z 0.1U_0402_16V4Z BATT_TEMPA 1 2
1 1 C771 1 1 2 2 C769 0.1U_0402_16V4Z C776 100P_0402_25V8K
C770 1 2
C772 C773 C774 C775
1000P_0402_50V7K1000P_0402_50V7K C794 0.1U_0402_16V4Z ACIN_D 1 2
2 2 2 2 1 1 C788 100P_0402_25V8K
1 2

111
125
0.1U_0402_16V4Z 0.1U_0402_16V4Z

22
33
96

67
9
U43 For EMI request

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
+5VS
D R740 4.7K_0402_5% D
TP_CLK 1 2
CLK_PCI_EC GATEA20 1 21 INVT_PWM
22 GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PWM 18
KB_RST# 2 23 EC_BEEP# R741 4.7K_0402_5%
1 22 KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 EC_BEEP# 30
SERIRQ 3 26 UWB_OFF# TP_DATA 1 2
23,34 SERIRQ SERIRQ# FANPWM1/GPIO12 UWB_OFF# 28
R738 LPC_FRAME# 4 27 ACOFF
22,34 LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF 39
@ 10_0402_5% LPC_AD3 5
22,34 LPC_AD3 LAD3 +3VL
LPC_AD2 7 PWM Output
22,34 LPC_AD2 LAD2
LPC_AD1 8 63 BATT_TEMPA
22,34 LPC_AD1 BATT_TEMPA 38
2

LPC_AD0 LAD1 BATT_TEMP/AD0/GPIO38 TMPTU1_SXP R760 4.7K_0402_5%

1 22,34 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I
TMPTU1_SXP 28
CAP_INT#
ADP_I/AD2/GPIO3A 65 ADP_I 39 1 2
C787 CLK_PCI_EC 12 AD Input 66 ADP_V
16 CLK_PCI_EC PCICLK AD3/GPIO3B ADP_V 39
@ 22P_0402_50V8J PLT_RST# 13 75 TMPTU2_SXP 100K_0402_5% R751
2 8,17,21,26,28,29,32,34 PLT_RST# PCIRST#/GPIO05 AD4/GPIO42 TMPTU2_SXP 28
ECRST# 37 76 HDPACT CEC_INT# 2 1
ECRST# SELIO2#/AD5/GPIO43 HDPACT 34
EC_SCI# 20
23 EC_SCI# SCI#/GPIO0E
WL_BT_LED# 38
35 WL_BT_LED# CLKRUN#/GPIO1D +5VL
For EMI request 68 DAC_BRIG
DAC_BRIG/DA0/GPIO3C DAC_BRIG 18
70 EN_DFAN1
+3VL EN_DFAN1/DA1/GPIO3D EN_DFAN1 4
DA Output 71 IREF
IREF/DA2/GPIO3E IREF 39
R739 47K_0402_5% KSI0 55 72 CHGVADJ R748 10K_0402_5%
KSI0/GPIO30 DA3/GPIO3F CHGVADJ 39
2 1 ECRST# KSI1 56 CIR_IN 1 2
KSI2 KSI1/GPIO31
57 KSI2/GPIO32
2 1 KSI3 58 83 USB_CHG_EN#
+3VL KSI3/GPIO33 PSCLK1/GPIO4A USB_CHG_EN# 25
C789 0.1U_0402_16V4Z KSI4 59 84 USB_EN#
KSI4/GPIO34 PSDAT1/GPIO4B USB_EN# 25,27
KSI5 60 85 CAP_INT#
KSI5/GPIO35 PSCLK2/GPIO4C CAP_INT# 35 +3VS
1 2 KSO1 KSI6 61 PS2 Interface 86 CAP_RST#
KSI6/GPIO36 PSDAT2/GPIO4D CAP_RST# 35
R595 47K_0402_5% KSI7 62 87 TP_CLK
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK 35
1 2 KSO2 KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA 35
R596 47K_0402_5% KSO1 40 R753 4.7K_0402_5%
C KSO2 KSO1/GPIO21 HDPLOCK @ C
41 KSO2/GPIO22 1 2
KSO3 42 97 VGATE
KSO3/GPIO23 SDICS#/GPXOA00 VGATE 8,23,43
to avoid EC entry ENE test mode KSO4 43 98 WOL_EN# R754 10K_0402_5%
KSO4/GPIO24 SDICLK/GPXOA01 WOL_EN# 36
KSO5 SBPWR_EN# TMPTU1_SXP
KSI[0..7] KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
LID_SW#
SBPWR_EN# 24,36 1 2
31,35 KSI[0..7] 45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 LID_SW# 34
KSO7 46 SPI Device Interface R757 10K_0402_5%
KSO[0..17] KSO8 KSO7/GPIO27 TMPTU2_SXP
31,35 KSO[0..17] 47 KSO8/GPIO28 1 2
KSO9 48 119 EC_SI_SPI_SO
KSO9/GPIO29 SPIDI/RD# EC_SI_SPI_SO 34
KSO10 49 120 EC_SO_SPI_SI
KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI 34 +3VALW
KSO11 50 SPI Flash ROM 126 SPI_CLK
KSO11/GPIO2B SPICLK/GPIO58 SPI_CLK 34
KSO12 51 128 SPI_CS# R766 47K_0402_5%
KSO12/GPIO2C SPICS# SPI_CS# 34
R755 2.2K_0402_5% KSO13 52 LID_SW# 1 2
KSO13/GPIO2D
+3VL 1 2 EC_SMB_CK1 KSO14 53 KSO14/GPIO2E
R756 2.2K_0402_5% KSO15 54 73 CIR_IN
KSO15/GPIO2F CIR_RX/GPIO40
1 2 EC_SMB_DA1 KSO16 81 KSO16/GPIO48 CIR_RLC_TX/GPIO41 74 TP_LED
TP_LED 35
KSO17 82 89 FSTCHG
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG 39
90 BATT_FULL_LED#
BATT_CHGI_LED#/GPIO52 BATT_FULL_LED# 35
91 CAPS_LED#
CAPS_LED#/GPIO53 CAPS_LED# 31 +3VALW
EC_SMB_CK1 77 GPIO 92 BATT_CHG_LOW_LED#
20,38 EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 BATT_CHG_LOW_LED# 35
EC_SMB_DA1 78 93 PWR_ON_LED#
20,38 EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 PWR_ON_LED# 35
R758 4.7K_0402_5% EC_SMB_CK2 79 SM Bus 95 SYSON 1 2
4,17,34,35 EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON 26,42
+3VS 1 2 EC_SMB_CK2 4,17,34,35 EC_SMB_DA2
EC_SMB_DA2 80 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 121 VR_ON
VR_ON 43
100K_0402_5% R742
R759 4.7K_0402_5% 127 ACIN_D D64
AC_IN/GPIO59
1 2 EC_SMB_DA2 ACIN_D 2 1 ACIN 23,35,37
PM_SLP_S3# 6 100 EC_RSMRST# CH751H-40PT_SOD323-2
23 PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# 23
SLP_S5# 14 101 EC_LID_OUT#
PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# 23
EC_SMI# 15 102 EC_ON
23 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON 35
CEC_INT# 16 103 EC_SWI#
B +3VALW 20 CEC_INT# LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_SWI# B
ESB_CK 17 104 EC_PWROK
35 ESB_CK SUSP#/GPIO0B ICH_PWROK/GPXO06 EC_PWROK 23
C781 ESB_DAT 18 GPO 105 BKOFF#
35 ESB_DAT PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# 18
1 2 MCH_TSATN_EC# 19 GPIO 106 WL_OFF#
8 MCH_TSATN_EC# EC_PME#/GPIO0D WL_OFF#/GPXO09 WL_OFF# 28
0.1U_0402_16V4Z KB_LED 25 107 KILL_SW#
31 KB_LED EC_THERM#/GPIO11 GPXO10 KILL_SW# 28
5

FAN_SPEED1 28 108 LOGO_LED

4 FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11 LOGO_LED 35
2 HDPLOCK 29
P

23 PM_SLP_S5# B 34 HDPLOCK FANFB2/GPIO15

4 SLP_S5# E51_TXD 30
Y 28 E51_TXD EC_TX/GPIO16
1 E51_RXD 31 110 HDPINT 1 2
23 PM_SLP_S4# A 28 E51_RXD EC_RX/GPIO17 PM_SLP_S4#/GPXID1 HDPINT 34 UMA_ENBKL 10
G

ON/OFFBTN# 32 112 ENBKL R745GM@ 0_0402_5%

35 ON/OFFBTN# ON_OFF/GPIO18 ENBKL/GPXID2
NC7SZ08P5X_NL_SC70-5 U44 PWR_SUSP_LED 34 114 USB_OC#2 ENBKL 1 2
35 PWR_SUSP_LED USB_OC#2 21,25 VGA_ENBKL 17
3

NUM_LED# PWR_LED#/GPIO19 GPXID3 EC_THERM# R746PM@ 0_0402_5%

31 NUM_LED# 36 NUMLED#/GPIO1A GPI GPXID4 115 EC_THERM# 23
116 SUSP# 1 2
GPXID5 SUSP# 17,26,30,36,39,41
117 PBTN_OUT# R747 100K_0402_5%
GPXID6 PBTN_OUT# 23
118 USB_OC#0_R
CRY1 GPXID7
reserve for ENE_CS board 122 XCLK1
CRY2 123 124 +EC_V18R
XCLK0 V18R
AGND

R749
GND
GND
GND
GND
GND

CRY1 1 2CRY2 C782

4.7U_0805_10V4Z U45
@ 20M_0603_5% KB926QFD3_LQFP128_14X14 CIR_IN 1
11
24
35
94
113

69

R750 100_0805_5% Vout

+5VL 1 2 2 VCC
1 2 CIR@
28 3G_OFF#
R768@ 0_0402_5% 1 1 3
EC_SWI# C784 C785 C783 GND
23,26 SB_WAKE# 1 2
1

R761@ 0_0402_5% 4.7U_0805_10V4Z 4 GND

15P_0402_50V8J

15P_0402_50V8J

1 2 Y5 CIR@
OUT
IN

LAN_WAKE# 29 2 2
R762 0_0402_5% IRM-V536/TR1_3P
A A
USB_OC#0_R 1 2
R763@ 0_0402_5% CIR@
NC

NC

1 2 USB_OC#0 21,27
R764 0_0402_5%
2

The circuit is reserve for new design for pre-MP Security Classification Compal Secret Data Compal Electronics, Inc.
32.768KHZ_12.5P_1TJS125BJ4A421P 2008/10/06 2009/10/06 Title
Issued Date Deciphered Date
SCHEMATIC,MB A4991
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 34 of 48
5 4 3 2 1
 SPI Flash (16Mb*1)
Lid SW LPC Debug Port
Please place the PAD under DDR DIMM.
+3VL H1
+3VALW U34 +3VS
APX9132ATI-TRL_SOT23-3
6 5
1 20mils
C786 U46 2 3

GND
VDD VOUT LID_SW# 33
8 4 SERIRQ 1 2 7 4 PLT_RST#
VCC VSS 23,33 SERIRQ PLT_RST# 8,17,21,26,28,29,32,33
0.1U_0402_16V4Z R622 0_0402_5%
2
3 1 1

1
W LPC_AD3 LPC_AD2
22,33 LPC_AD3 8 3 LPC_AD2 22,33
7 C645 C647
HOLD 0.1U_0402_16V4Z 10P_0402_50V8J
2 2 LPC_AD1 LPC_AD0
33 SPI_CS# 1 S 22,33 LPC_AD1 9 2 LPC_AD0 22,33

33 SPI_CLK 6 C LPC_FRAME# 10 1
22,33 LPC_FRAME# CLK_PCI_DDR 16
33 EC_SO_SPI_SI 5 D Q 2 EC_SI_SPI_SO 33

2
SST25LF080A_SO8-200mil 4.75V
@ DEBUG_PAD R636
22_0402_5%

1
2
C643
22P_0402_50V8J
1

G-Sensor +5VS GSENSOR@ +3VS_HDP

DG1 CH751H-40PT_SOD323-2
1 2
2 2
CG12 UG3 GSENSOR@
RG2 1U_0402_6.3V4Z CG13 UG1 1ST@
+3VS 2 1 +3VS_HDP GSENSOR@ 1 5 1U_0402_6.3V4Z +3VS_HDP 2 3 VOUTX CG1 1 2 1ST@ 0.033U_0402_16V7K
@ 1 VIN VOUT 1 Vdd1 Voutx VOUTY CG2
12 Vdd2 Vouty 5 1 2 1ST@ 0.033U_0402_16V7K
0_0603_5% 2 7 VOUTZ CG3 1 2 1ST@ 0.033U_0402_16V7K
GND CG14 0.22U_0402_10V4Z Voutz
3 SHDN# BP 4 2 @ 1 SELF_TEST 4 ST NC1 10
6 PD NC2 11
8 FS NC3 14
G9191-330T1U_SOT23-5 15
NC4
NC5 16
+3VS_HDP
9 Rev GND1 1
GND2 13
TSH35TR_LGA16

UG2

4,17,33,35 EC_SMB_CK2 1 P3_5/SSCK/SCL/CMP1_2 P1_6/CLK0/SSI01 11 HDPACT 33

2
SELF_TEST 2 12
P3_7/CNTR0#/SSO/TXD1 P1_5/RXD0/CNTR01/INT11# RG9
GSENSOR@ 47K_0402_5%
+3VS_HDP RG3 2 1 4.7K_0402_5% 3 13 GSENSOR@
RESET# P1_4/TXD0 +3VS_HDP

1
GSENSOR@ CG9 0.1U_0402_16V4Z UG4 2ND@
RG4 2 1 4.7K_0402_5% GXOUT 4 14 2ND@ 2 1VOUTX2 6
XOUT/P4_7 P1_3/KI3#/AN11/TZOUT HDPLOCK 33
CG10 0.1U_0402_16V4Z XOUT VDD
RG10 47K_0402_5% 2ND@ 2 1VOUTY3
5 15 VOUTZ 2 1 CG11 0.1U_0402_16V4Z YOUT 1
VSS/AVSS P1_2/KI2#/AN10/CMP0_2 GSENSOR@ 2ND@ 2 NC
1VOUTZ4 ZOUT NC 8
GSENSOR@ 11
RG5 NC
2 1 4.7K_0402_5% GXIN 6 XIN/P4_6 P4_2/VREF 16 +3VS_HDP 9 0G-DET NC 12
NC 14
1 +3VS_HDP 7 SLEEP#
7 17 VOUTX CG6 10
VCC/AVCC P1_1/KI1#/AN9/CMP0_1 0.1U_0402_16V4Z SELF_TEST G-SELECT
13 ST VSS 5
GSENSOR@ GSENSOR@
RG6 2
2 1 4.7K_0402_5% 8 MODE P1_0/KI0#/AN8/CMP0_0 18 VOUTY MMA7360LR2_LGA14

GSENSOR@
HDPINT RG7 2 1 1K_0402_5% 9 19
33 HDPINT P4_5/INT0#/RXD1 P3_3/TCIN/INT3#/SSI00/CMP1_0

10 P1_7/CNTR00/INT10# P3_4/SCS#/SDA/CMP1_1 20 EC_SMB_DA2 4,17,33,35

1 1 R5F211B4D31SP_LSSOP20
1ST-GSENSOR@
CG7 CG8
0.1U_0402_16V4Z
GSENSOR@ 2 2 0.1U_0402_16V4Z UG2 2ND-GSENSOR@
GSENSOR@ R5F211B4D34SP
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 35 of 48
 5 4 3 2 1

JPOWER
Power Button/ PWR/B 1 1
2 2
POWER_ON_LED
+3VS
Touch/B Connector Caps Sensor Connector
ON/OFFBTN# JCS
3 3 JTOUCH
4 4 +3VL 1 1
5 5 EC_SMB_CK2 4,17,33,34 +5VS 1 1 +5VALW 2 2 ESB_DAZ
+3VL 6 6 EC_SMB_DA2 4,17,33,34 33 TP_CLK 2 2 3 3 1 2 1 2
GND 7 33 TP_DATA 3 3 4 4 R401 C226
GND 8 D20
@
4 4 5 5 @ 100_0402_5% @ 100P_0402_25V8K
33 CAP_INT# 6 6

2
ACES_85201-06051 +5VS 4 2 TP_CLK ACES_85201-04051 L2 1 FBMA-11-100505-301T_0402
2 ESB_DAZ 7
VIN IO1 33 ESB_DAT 7
R765 @ @ L3 1 FBMA-11-100505-301T_0402
2 ESB_CKZ 8 ESB_CKZ 1 2 1 2
33 ESB_CK 8
D TP_DATA 3 1 9 D
IO2 GND 33 CAP_RST# 9
100K_0402_5% 10 R402 C227
SW5 @ CM1293A-02SR SOT143-4 10 @ 100_0402_5% @ 100P_0402_25V8K
51_ON# 37 11

1
ON/OFFBTN# GND
1 3 ON/OFFBTN# 33 12 GND
TOP side
2 4 1 @ ACES_85201-1005N

SMT1-05-A_4P
C646
0.1U_0402_16V4Z
Light Pipe Connector @
6
5

1
D C648 0.1U_0402_16V4Z
2 Q19
33 EC_ON 2 1 @ 2
SW6 @ G 2N7002_SOT23-3 JLIGHT

2
1 3 S 1
+5VS
LED/B Connector

3
R514 L_LED# 1
2 2
BTM side 2 4 10K_0402_5% KSI6 3 JLED
31,33 KSI6 3
KSO0 4 +5VALW 1
31,33 KSO0 4 1
SMT1-05-A_4P 5 +5VS 2
6
5

1
G1 2

1
D DC_IN DC-IN LED
2N7002_SOT23-3 6 G2 3 3
2 POWER_LED 4 POWER LED
33 TP_LED Q57 ACES_85201-0405N SUSPEND_LED 4 SUSPEND LED
debug phase using G 5 5
S @ HDD_LED 6 HDD LED

3
CR_LEDCON 6 CARD READER LED
D22 32 CR_LEDCON 7 7
@ BATT_FULL_LED# 8 BATT CHARGE/FULL LED
33 BATT_FULL_LED# 8 BATT CHARGE/LOW LED
+3VS 4 2 ON/OFFBTN# BATT_CHG_LOW_LED# 9
VIN IO1 33 BATT_CHG_LOW_LED# 9
10 10
ON/OFFBTN# 3 1 11
IO2 GND GND
12 GND
CM1293A-02SR SOT143-4
ACES_85201-1005N
@
C C

DC-IN LED ACIN 23,33,37

Satellite LED Screw Hole

2
G

LOGO_LED 33
DC_IN 1 3

2
D18

G
D

HT-SV116BP_WHITE H2 H3 H4 H5 H6 H7 H8 H9 H10
2N7002_SOT23-3 +5VS 1 2 2 1 LOGO_LED# 1 3
Q56 R774 120_0402_5%

S
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0

1
2N7002_SOT23-3 @ @ @ @ @ @ @ @ @
Q30
WL&BT LED Vf=1.9V(typ),2.4V(max)
D74
1
R776
2
120_0402_5%
2 1
H13 H14 H15 H19 H24 H25 H26 H27 H34
+5VS 1 2 2 1 WL_BT_LED# 33
R777 300_0402_5% D19
HT-110UD_1204 HT-SV116BP_WHITE H_3P0 H_3P0 H_3P0 H_3P8 H_4P8X3P8
H_4P8X3P8
H_1P2 H_1P2 H_3P8

1
@ @ @ @ @ @ @ @ @

WiMAX LED WIMAX_LED_GND1 R506

0_0402_5%
2 LED_WIMAX# 28
H18 H11 H16
2

@
B H_3P0N H_4P0X3P0N H_2P7N B

1
2 R819 1 6 1 @ @ @
+5VS
10K_0402_5% POWER LED
5

Q156A
D75 2N7002DW-T/R7_SOT363-6 +5VALW
+5VS 1
R778
2
300_0402_5%
2 1WIMAX_LED_GND3 4 JNAND H45 H44 JWLAN H41 H40 SSD H36 H38 H39
3

WIMAX@ HT-110NB5 1204 BLUE Q156B 2N7002DW-T/R7_SOT363-6 47K

WIMAX@ Q42 H_1P2 H_1P2 H_3P3 H_3P3 H_1P2 H_1P2 H_1P2

1
@ @ @ @ @ @ @
10K 2 PWR_ON_LED# 33
SATA_LED# 22
JGPS H43 H42 VGA H21 H20 MDC H22 H23
2

HDD LED DTA114YKAT146_SOT23-3

+5VS 2 R779 1 6 1 H_3P7 H_1P2 H_3P7 H_3P7 H_1P2 H_1P2
1

1
10K_0402_5% @ @ @ @ @ @
5

Q31A 1 2 POWER_LED
2N7002DW-T/R7_SOT363-6 R516 120_0402_5%
HDD_LED 3 4
1 2 POWER_ON_LED
Q31B 2N7002DW-T/R7_SOT363-6 R544 120_0402_5%

PCB Fedical Mark PAD

SUSPEND LED
+3VALW FD1 FD2 FD3 FD4
A A
@ @ @ @
3

47K

1
Q29

10K 2 PWR_SUSP_LED 33
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
DTA114YKAT146_SOT23-3
SCHEMATIC,MB A4991
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2 1 SUSPEND_LED AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
R770 300_0402_5% D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 36 of 48
5 4 3 2 1
 A B C D E

+3VALW TO +3VS Inrush current = 0A +5VALW TO +5VS +1.8V to +1.8VS

Inrush current = 0A
+3VALW +3VS Vgs=-0V,Id=9A,Rds=18.5mohm +5VALW +5VS Inrush current = 0A
4.7U_0805_10V4Z +1.8V +1.8VS
4.7U_0805_10V4Z
1 1 1 1 Vgs=10V,Id=14.5A,Rds=6mohm
Q32 C824 C825 4.7U_0805_10V4Z Q33 C826 C827 1 1

470_0805_5%

470_0805_5%
8 1 8 1 Q34 C828 C829
D S D S

470_0805_5%
7 2 7 2 8 1 PM@ PM@
D S D S D S

2
2 2 R781 2 2 R782
6 D S 3 6 D S 3 7 D S 2
2 2 R783
1 5 D G 4 5 D G 4 6 D S 3 1
1U_0402_6.3V4Z 1U_0402_6.3V4Z 5 4 PM@
SI4800BDY_SO8 D G
1 R784 2 +VSB SI4800BDY_SO8 RUNON 1 R785 2 +VSB 1U_0402_6.3V4Z

3 1

3 1
0.022U_0402_25V7K

0.01U_0402_25V7K
47K_0402_5% 47K_0402_5% SI4856ADY_SO8 1 R786
4.7U_0805_10V4Z

4.7U_0805_10V4Z
1 1 1 1 2 +VSB

3 1
1

0.1U_0603_25V7K
C831 PM@ 220K_0402_5%

4.7U_0805_10V4Z
1

6
C830 R787 Q35A C832 C833 R788 Q36A FDS6676AS 1 PM@
330K_0402_5% Q35B @ 200K_0402_5% Q36B C834 R789 Q37A
2 2 SUSP 2 2 SUSP 5 PM@ C835 820K_0402_5% Q37B
2 5 2
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2 PM@ PM@ SUSP 5 PM@
2

2
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2 2N7002DW-T/R7_SOT363-6

2
2N7002DW-T/R7_SOT363-6

4
PM@

+3VALW TO +3V_LAN
+3VALW TO +3V_SB
+3VALW +3VALW Inrush current = 0A
0.1U_0402_16V7K Vgs=-4.5V,Id=3A,Rds<97mohm +3VALW +3V_SB
2

PJ36
R793 2 2 1
100K_0402_5% 2 1
2 STAR@ STAR@ Q44 @ JUMP_43X79 Inrush current = 0A 2

2
C231 AO3413_SOT23 Vgs=10V,Id=6A,Rds=35mohm
1

D
1
S
R795 47K_0402_5% STAR@ PJ35 6

S
G
WOL_EN# 1 2 2 Q41 JUMP_43X79 1 5 4 1U_0402_6.3V4Z
33 WOL_EN#
@ C842 2 1 1

2
1
STAR@ 2 STAR@ 1 D 10U_0805_10V4Z 1 C843
STAR@ 4.7U_0805_10V4Z C844 R803

G
1
C837 +3V_LAN 2 STAR@ STAR@ STAR@ 470_0805_5%

3
0.01U_0402_25V7K SI3456BDV-T1-E3_TSOP6 2 2 STAR@
1
+VSB 2 1

6 1
R804 20K_0402_5%

1
STAR@ 1
1 1 R805 C845 Q46A
Q46B 200K_0402_5% 0.1U_0603_25V7K STAR@
C840 C841 1U_0402_6.3V4Z SBPWR_EN# 5 STAR@ STAR@ STAR@ 2 SBPWR_EN#
2 SBPWR_EN# 24,33
4.7U_0805_10V4Z STAR@

2
@ 2 2 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6

1
3 3
+5VALW

+1.5VS +0.9VS
2

R796

2
100K_0402_5%
R801 R802
470_0805_5% 470_0805_5%
1

SUSP
42 SUSP

1
Q24
1

D 2N7002_SOT23-3
2 Q22 Q23
17,26,30,33,39,41 SUSP#

1
G 2N7002_SOT23-3 D 2N7002_SOT23-3 D
2

S 2 SUSP 2 SUSP
3

G G
R799 S S

3
10K_0402_5%
1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 37 of 48
A B C D E
 A B C D

VIN VS
PL1 PR1
PF1 SMB3025500YA_2P VIN 1M_0402_1%
DC301001M80 DC_IN_S1 1 2 DC_IN_S2 1 2 1 2

1
PJP1

1
1 10A_125V_451010MRL N1 PR3
+ PR2 5.6K_0402_5% PR4

1
2 84.5K_0402_1% 10K_0402_1%
+ PC1 PC2 PC3 PC4 1 2 ACIN 23,33,35

2
3 1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K 100P_0402_50V8J PR5

2
-

8
1 1

22K_0402_1% PU1A
4 1 2 3

P
- + PACIN
O 1 PACIN 39
@ SINGA_2DW-0005-B03 2 -

G
1

1
PR6 LM393DG_SO8

4
PC5 20K_0402_1% PC6 PD1 PR7
0.068U_0402_10V6K .1U_0402_16V7K GLZ4.3B_LL34-2 10K_0402_1%

2
2

2
2 1 RTCVREF
VIN PR8
10K_0402_1%
3.3V Vin Detector

2
PD2
RLS4148_LL34-2
High 18.384 17.901 17.430
Low 17.728 17.257 16.976

1
BATT+ 2 1

1
PD3 PR9 PR10
RLS4148_LL34-2 PQ1 68_1206_5% 68_1206_5%
N1 TP0610K-T1-E3_SOT23-3
PR11

2
200_0603_5%
CHGRTCP 1 2 N1 3 1 VS
1 2
1

2
PR12 2
1

1
PC8 1K_1206_5%
PR13 PC7 0.1U_0603_25V7K PD4
100K_0402_1% 0.22U_1206_25V7K 2 1 N3 1 2
VIN B+
2

2
RTC Battery
2

0.1U_0402_25V6
RLS4148_LL34-2 PR14

2
1 2 1K_1206_5%
35 51_ON#

PC135
PR15
22K_0402_1% 1 2

1
- PBJ1 + PR16
1K_1206_5%
RTCVREF 2 1 +RTCBATT +RTCBATT
1

1
PR17 PR19 PR20
200_0603_5% 100K_0402_1% 2.2M_0402_5% PR18
PR21 PR22 PU2 G920AT24U_SOT89-3 @ MAXEL_ML1220T10 1 2 2 1 499K_0402_1%
560_0603_5% 560_0603_5% 3.3V VL
2

2
1 2 1 2 3 2 N2
+CHGRTC OUT IN LM393DG_SO8
PD5 PU1B
SP093MX0000
1

8
GND RB715F_SOT323-3
PC9 PC10 2 5

P
10U_0805_10V4Z 1 40 EN0 +
1 7
2

1U_0805_25V4Z O
39 ACON 3 - 6 2 1 RTCVREF

1
G

1
PR23 PR24 PC12

1
10K_0402_1% 499K_0402_1% 1000P_0402_50V7K

1
PR26

2
PC11 PC13 @ PR25
@PR25 191K_0402_1%

2
1000P_0402_50V7K 1000P_0402_50V7K 66.5K_0402_1%
PJ3

2
PJ1 PJ2

2
3 3

+3VALWP 2 2 1 1 +3VALW +1.8VP 2 2 1 1 +1.8V VL 2 2 1 1 +5VL

@ JUMP_43X118 @ JUMP_43X118 @ JUMP_43X39
(5A,200mils ,Via NO.= 10) PJ4 (100mA,40mils ,Via NO.= 2)
2 2 PR27
1 1

1
D 47K_0402_1%
OCP(min)=7.7A
@ JUMP_43X118 2 2 1 PACIN
(8A,320mils ,Via NO.= 16) PJ6
G
S PQ2

3
PJ5 OCP(min)=10.28A +3VLP 2 1 +3VL SSM3K7002FU_SC70-3
2 1
+5VALWP 2 2 1 1 +5VALW

1
@ JUMP_43X39
@ JUMP_43X118 PJ7 (100mA,40mils ,Via NO.= 2)
(5A,200mils ,Via NO.= 10) 2 2 1 1

OCP(min)=7.9A @ JUMP_43X118 2 +5VALWP

PJ9
PJ8
PQ3
+VSBP 2 1 +VSB
+1.05VSP 2 2 1 1 +1.05VS Precharge detector DTC115EUA_SC70-3

3
2 1 @ JUMP_43X118
@ JUMP_43X39 (10A,400mils ,Via NO.=20)
15.97V/14.84V FOR
ADAPTOR
(120mA,40mils ,Via NO.= 1) OCP(min)=12.32A

PJ11
PJ10 +1.5VSP 2 1 +1.5VS
2 1
+0.9VSP 2 2 1 1 +0.9VS
@ JUMP_43X79
4
@ JUMP_43X79 (6.0A,240mils ,Via NO.=12) 4

(2A,80mils ,Via NO.= 4)

OCP(min)=7.96A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401662
Date: Thursday, May 21, 2009 Sheet 38 of 48
A B C D
 A B C D

PH1 under CPU botten side :

CPU thermal protection at 92 degree C
Recovery at 56 degree C
1 1
VMB VL
PF2 PL2 VL ENTRIP1 22,40
PJP2 15A_65V_451015MRL SMB3025500YA_2P VL
1 BATT_S1 1 2 1 2
1 BATT+
2 2

2
3 3 1 2 1 2 +3VLP
4 PR28 PR29 PR30
4

1
1K_0402_1% 47K_0402_1% 47K_0402_1% D
5 5
10 6 EC_SMDA PC14 PC15 PH1 PC16 2 PQ4
GND 6 EC_SMCA 1000P_0402_50V7K 0.01U_0402_25V7K 100K_0603_1%_TH11-4H104FT 0.1U_0603_25V7K PR32 G SSM3K7002FU_SC70-3
11 7

1
GND 7 47K_0402_1%
12 8 S

3
GND 8

1
13 9 1 2

2
GND 9 PR31 PR33

8
@ OCTEK_BTJ-09HA1G 1K_0402_1% 13.7K_0402_1% PU3A
1 2 3

P
+
1 2 1

2
O
2

TM_REF1 2 ENTRIP2 22,40

-

G
PR34 PR35 PD6
100_0402_1% 100_0402_1% LM393DG_SO8 RLS4148_LL34-2

4
0.22U_0805_16V7K
1

1
D

15.4K_0402_1%
1

1
PC17
PR36 2 PQ5

1000P_0402_50V7K
PR37
6.49K_0402_1% G SSM3K7002FU_SC70-3
2 1 +3VLP 2 1 VL S

3
1

PC18
PR38

2
100K_0402_1%

2
1

1
PR39
2
1K_0402_1% 2

PR40
100K_0402_1%
2

2
BATT_TEMPA 33

EC_SMB_DA1 20,33

EC_SMB_CK1 20,33
PH2 near main Battery CONN :
BAT. thermal protection at 90 degree C
Recovery at 53 degree C

VL VL

PQ6

2
TP0610K-T1-E3_SOT23-3

1
PR41
47K_0402_1%
B+ 3 1 +VSBP PH2 PR42
100K_0603_1%_TH11-4H104FT 47K_0402_1%

1
3 3
100K_0402_1%

0.22U_1206_25V7K

0.1U_0603_25V7K

1 2

2
1

1
PR43

PC19

PC20

PR44

8
13.7K_0402_1% PU3B
1 2 5

P
2

+
7 2 1
2

TM_REF1 O
6 -

G
VL PR45 PD7

1
22K_0402_1% @ LM393DG_SO8 RLS4148_LL34-2

4
1 2 @ PC21 PR46
2

0.22U_0805_16V7K 16.9K_0402_1%

2
PR47

2
100K_0402_1%

PR48
1

0_0402_5% D
1 2 2 PQ7
40 POK
G SSM3K7002FU_SC70-3
.1U_0402_16V7K

S
3
1

PC22
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 39 of 48
A B C D
 A B C D

B+
PQ40
@ FDS4435BZ_SO8

PQ8
FDS4435BZ_SO8 P2
PQ9
FDS4435BZ_SO8 P3
PR49
0.02_2512_1%
B+ PL19
HCB4532KF-800T90_1812 CHG_B+
1
2
S D 8
7
S D
1 3 S D 6 1

VIN 8 D S 1 1 S D 8 1 4 2 1 4 G D 5
7 D S 2 2 S D 7
6 3 3 6 2 3 CSIN
D S S D PQ10
5 D G 4 4 G D 5
FDS4435BZ_SO8

2200P_0402_50V7K
0.1U_0402_25V6

4.7U_1206_25V6K

4.7U_1206_25V6K

4.7U_1206_25V6K
CSIP

1
1 S D 8

1
PC139

PC144
PQ12 TP0610K-T1-E3_SOT23-3 2 7
3 PR150 S D

PC23

PC24

PC25
PQ11 PR50 3 6
S D

2
DTA144EUA_SC70-3 200K_0402_1% 3 1 1 2 DCIN 4 5

2
PC26 P3 @
G D

2
1

1
2 5600P_0402_25V7K 10_0603_5%

1
PC27 PR54 PQ13 PR51

1
PR53 0.1U_0603_25V7K 100K_0402_1% DTC115EUA_SC70-3 47K_0402_1%
2

47K_0402_1% 1 2
PR55 PD9 VIN
2

2
100K_0402_1% 2 FSTCHG
1

2
1

PD10 2 1 2 1 PR52 PD8

1SS355_SOD323-2 3 10K_0402_1% 1 2 ACOFF
1 2 6251VDD SUSP# 17,26,30,33,36,41

2.2U_0603_6.3V6K
RB715F_SOT323-3 1SS355_SOD323-2

1
PC28
2 PR57 PR56

3
1
PQ14 10K_0402_1% 200K_0402_1%

1
DTC115EUA_SC70-3 2 1 PU5 PC30 1 2 VIN
33 FSTCHG 0.1U_0603_25V7K

2
1

100K_0402_1%
1 2 1 24 DCIN 2 1
3

VDD DCIN
1

1
2 PQ16 PQ15 PD11

PR59
G SSM3K7002FU_SC70-3 PC29 DTC115EUA_SC70-3 2 1 2
S PR58 .1U_0402_16V7K 2 23
3

150K_0402_1% ACSET ACPRN PR60 1SS355_SOD323-2

20_0603_5%
2

2
2
6251_EN 3 22 1 2 CSON 2

3
EN CSON

1
PC32 PC33 D

5
6
7
8

1
@ 680P_0402_50V7K 0.047U_0603_16V7K PC31 2 PACIN
CSON 1 2 4 21 1 2 CSOP 0.1U_0603_25V7K G

1
CELLS CSOP PR61 PQ18 PQ17
S

3
PC34 6800P_0402_25V7K 20_0603_5% AO4466_SO8 SSM3K7002FU_SC70-3
1 2 5 ICOMP CSIN 20 2 1
1

2
D PR62 4
2 PQ19 PC35 PR63 6.81K_0402_1% PC36 20_0603_5%
G SSM3K7002FU_SC70-3 1 2 1 2 6 19 0.1U_0603_25V7K
1 2

1
PR65 VCOMP CSIP PL3 PR67
S
3

0.01U_0402_25V7K 21 100_0402_1% PR64 10U_LF919AS-100M-P3_4.5A_20% 0.02_2512_1% BATT+

3
2
1
PR66 PC37 1 2 7 18 LX_CHG 2.2_0603_5% 1 2 CHG 1 4
22K_0402_5% @ 100P_0402_50V8J ICM PHASE

5
6
7
8

4.7_1206_5%
PACIN 1 2 1 2 2 3
37 PACIN

10U_1206_25V6M

10U_1206_25V6M
PR166
6251VREF 8 17 DH_CHG
VREF UGATE
37 ACON 33 PR68 ADP_I .1U_0402_16V7K PC38 PR69 PC39

AO4466_SO8
154K_0402_1% 2.2_0603_5% 0.1U_0603_25V7K

1
PQ20

PC40

PC41
2 1 9 16 BST_CHG 1 2 BST_CHGA 2 1

2
33 IREF CHLIM BOOT
1

1
PQ21 PR70 4
0.01U_0402_25V7K

DTC115EUA_SC70-3 24K_0402_1% PD12

2
1

680P_0603_50V8J
6251VREF 1 2 6251aclim 10 15 6251VDDP RB751V-40TE17_SOD323-2
ACLIM VDDP
1

PC140
1

1
PC42

ACOFF 2 PR71 1 26251VDD

33 ACOFF

3
2
1

2
120K_0402_1% PR72 11 14 DL_CHG
VADJ LGATE

2
20K_0402_1% PR73
2

4.7_0603_5%
2

12 13 PC43
3

1
GND PGND 4.7U_0805_6.3V6K

ISL6251AHAZ-T_QSOP24
3 3

PR74
15.4K_0402_1%
1 2
33 CHGVADJ
1

PR75
Iada=0~3.947A(75W) CP= 92%*Iada; CP=3.65A 31.6K_0402_1%
2

CP mode VIN
Vaclim=2.39*(20K//152K/(20K//152K+24K//152K))=1.09986V
Iinput=(1/0.02)((0.05*Vaclm)/2.39+0.05)
where Vaclm=1.09986V, Iinput=3.65A
1

PR216
309K_0402_1%

CC=0.25A~3A CHGVADJ=(Vcell-4)/0.10627 PR167

2

IREF=1.016*Icharge Vcell CHGVADJ 1 2 ADP_V 33

IREF=0.254V~3.048V 4V 0V 10K_0402_1%
1

VCHLIM need over 95mV 4.2V 1.882V @PD14

@ PD14 PR217
GLZ4.3B_LL34-2 47K_0402_1% PC162
4.35V 3.2935V .1U_0402_16V7K
2
2

4 4

CELLS VDD GND Float

CELL number 4 3 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 40 of 48
A B C D
 5 4 3 2 1

2VREF_51125

0.22U_0603_10V7K
D D

1
PC44

2
PR76 PR77
13K_0402_1% 30K_0402_1%
1 2 1 2

PR78 PR79
B++
20K_0402_1% 19.6K_0402_1%
B++
1 2 1 2
PL20
HCB4532KF-800T90_1812
B+ 2 1 +3VLP
680P_0402_50V7K

ENTRIP2

ENTRIP1
330P_0402_25V8K~D

2200P_0402_50V7K
1000P_0402_25V8J

PR80 PR81
1

10U_1206_25V6M

10U_1206_25V6M
PC136

PC137

PC138

0.1U_0402_25V6
150K_0402_1% 150K_0402_1%
1

2200P_0402_50V7K
PC45

1 2 1 2

2
PC46

PC48

PC148
2

PC47
4.7U_0805_10V6K
2

1
6

5
6
7
8
PC49
PU6 @

8
7
6
5

1
C C

VREF
ENTRIP2

VFB2

VFB1

ENTRIP1
TONSEL
25 PQ23
PQ22 P PAD AO4466_SO8

2
AO4466_SO8
7 VO2 VO1 24 POK 38 4
4
8 23 PR83 PC51
PR82 VREG3 PGOOD 2.2_0603_1% .1U_0402_16V7K
1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2

3
2
1
2.2_0603_1% VBST2 VBST1
1
2
3

PL4 PC50 UG_3V 10 21 UG_5V PL5

4.7U_LF919AS-4R7M-P3_5.2A_20% .1U_0402_16V7K DRVH2 DRVH1 4.7U_LF919AS-4R7M-P3_5.2A_20% +5VALWP
1 2 LX_3V 11 20 LX_5V 1 2
+3VALWP LL2 LL1
1

8
7
6
5

5
6
7
8

1
4.7_1206_5%

4.7_1206_5%
LG_3V 12 19 LG_5V
DRVL2 DRVL1
PR84

PR85
.1U_0402_16V7K

SKIPSEL

150U_V_6.3VM_R18
PQ24 PQ25

VREG5
2

37 EN0
PC125

VCLK

.1U_0402_16V7K
150U_V_6.3VM_R18

1 AO4712_SO8 AO4712_SO8

GND
1

EN0

VIN
2

2
+ +
PC52

PC53

PC126
4 4
1

PR86 TPS51125RGER_QFN24_4X4

13

14

15

16

17

18
1

1
680P_0603_50V8J

680P_0603_50V8J
499K_0402_1%

1
2 2
PC54

PC55
@ 1 2
B+
2

1
2
3

3
2
1

2
1
100K_0402_5%
@

PR87
1 2 VL

PC56
4.7U_0805_10V6K
PR88

2
B @ 0_0402_5% B

2
ENTRIP1 22,38 ENTRIP2 22,38
B++

0.1U_0603_25V7K
2
PC57
1

D D
2VREF_51125
PQ26 2 2 PQ27
SSM3K7002FU_SC70-3 G G SSM3K7002FU_SC70-3
S S
3

VL 2 1

PR89
100K_0402_1%
1

VS 1 2 2 PQ28
G SSM3K7002FU_SC70-3
49.9K_0402_1%

@ 0.01U_0402_16V7K

PR90 S
3
1

100K_0402_1%
1
PR91

PC58

A A
2
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 41 of 48
5 4 3 2 1
 A B C D

PL21
HCB4532KF-800T90_1812

1.05V_B+ 2 1 B+

2200P_0402_50V7K

4.7U_1206_25V6K
0.1U_0402_25V6

4.7U_1206_25V6K
2

1
PC141

PC145

PC59

PC60
5
6
7
8

2
1 1

PQ29 @
AO4466_SO8

PR92
255K_0402_1% 4
1 2
PR93 PR94
0_0402_5% 2.2_0603_1%
1 2 BST_1.05V1 2
17,26,30,33,36,39 SUSP#

3
2
1
1
PL6

15

14
PC62

1
PC61 PU7 1.8UH_SIL104R-1R8PF_9.5A_30%
@.1U_0402_16V7K BST_1.05V-1 1 2 1 2

EN_PSV

TP

VBST
+1.05VSP

4.7_1206_5%
2 13 DH_1.05V 0.1U_0603_25V7K
TON DRVH

PR95
PR96 3 12 LX_1.05V
VOUT LL

5
6
7
8

220U_6.3VM_R15

.1U_0402_16V7K
422_0603_1% 1
1 2 4 11 1 2 +5VALW

D
D
D
D
+5VALW V5FILT TRIP

2
PC63

PC128
PR97 +

2
5 10 14.7K_0402_1% PQ30
VFB V5DRV FDS6670AS_NL_SO8

1
1

1
2

680P_0603_50V8J
6 9 DL_1.05V 4 G
PGOOD DRVL

PGND

PC65
PC64

GND
1U_0603_10V6K PC66 @

2
1

S
S
S
@ 47P_0402_50V8J
1 2 TPS51117RGYR_QFN14_3.5x3.5 PC67

3
2
1
4.7U_0805_10V6K

2
2
PR98 2

8.25K_0402_1%
1 2

PR99
20.5K_0402_1%
2

PL22
HCB4532KF-800T90_1812

1.5V_B+ 2 1 B+

2200P_0402_50V7K

4.7U_1206_25V6K

4.7U_1206_25V6K
0.1U_0402_25V6
2

1
PC142

PC146

PC68

PC69
5
6
7
8

2
PQ31 @
AO4466_SO8
255K_0402_1%
PR100 4
1 2
PR101 PR102
0_0402_5% 2.2_0603_1%
1 2 BST_1.5V 1 2
17,26,30,33,36,39 SUSP#

3
2
1
3 3
1

PL7
15

14

PC71
1

PC70 PU8 1.8UH_SIL104R-1R8PF_9.5A_30%

@.1U_0402_16V7K BST_1.5V-1 1 2 1 2
EN_PSV

TP

VBST

+1.5VSP
2

4.7_1206_5%
2 13 DH_1.5V 0.1U_0603_25V7K
TON DRVH

PR103

220U_6.3VM_R15

.1U_0402_16V7K
PR104 3 12 LX_1.5V 1
VOUT LL

5
6
7
8
422_0603_1%

2
PC72

PC127
1 2 4 11 1 2 +5VALW PQ32 +
+5VALW V5FILT TRIP PR105 AO4712_SO8

2
5 10 13.7K_0402_1%

1
VFB V5DRV 2
1

680P_0603_50V8J
6 9 DL_1.5V 4
PGOOD DRVL
PGND

PC74
PC73 @
GND

1U_0603_10V6K PC75
2

2
1
@ 47P_0402_50V8J
1 2 TPS51117RGYR_QFN14_3.5x3.5 PC76
7

3
2
1
4.7U_0805_10V6K
2

PR106
20.5K_0402_1%
1 2
1

PR107
20.5K_0402_1%
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 42 of 48
A B C D
 5 4 3 2 1

PL23
HCB4532KF-800T90_1812

51117_B+ 2 1 B+
D D

330P_0402_25V8K~D

4.7U_1206_25V6K

4.7U_1206_25V6K
680P_0402_50V7K

1000P_0402_50V7K
2

1
PC143

PC147

PC77

PC78

PC149
5
6
7
8
PQ33

2
AO4466_SO8

PR108
255K_0402_1% 4
1 2
PR109 PR110
0_0402_5% 2.2_0603_1%
1 2 BST_1.8V 1 2
26,33 SYSON

3
2
1
1
PL8

15

14
PC80

1
PC79 PU9 1.8UH_SIL104R-1R8PF_9.5A_30%
@.1U_0402_16V7K BST_1.8V-1 1 2 1 2

EN_PSV

TP

VBST
+1.8VP

2
2 13 DH_1.8V 0.1U_0603_25V7K
TON DRVH

4.7_1206_5%
PR111 3 12 LX_1.8V
VOUT LL

5
6
7
8

PR113

220U_6.3VM_R15

.1U_0402_16V7K
422_0603_1% 1
+5VALW 1 2 4 11 1 2 +5VALW PQ34
V5FILT TRIP

2
PC81

PC129
PR112 AO4712_SO8 +

2
5 10 18K_0402_1%
VFB V5DRV

1
1

1
DL_1.8V 2
6 PGOOD DRVL 9 4

PGND

PC83
680P_0603_50V8J
PC82

GND
C 1U_0603_10V6K PC84 @ C
2

2
1
@ 47P_0402_50V8J
1 2 TPS51117RGYR_QFN14_3.5x3.5 PC85

3
2
1
4.7U_0805_10V6K

2
PR114
28.7K_0402_1%
1 2
1

PR115
20.5K_0402_1%
2

+1.8V

1
1 PJ17
@ JUMP_43X79
B B
2

PU10
2

1 VIN VCNTL 6 +3VALW

2 GND NC 5
1

1U_0603_6.3V6M
PC86 1

PC87
4.7U_0805_6.3V6K 3 7
PR116 VREF NC
2

2
1K_0402_1% 4 8
VOUT NC
9
2

TP
APL5331KAC-TRL_SO8
1

PR117 +0.9VSP
1

0_0402_5% D PR118

10U_0805_6.3V6M
1 2 2 1K_0402_1% PC88
36 SUSP 1
G .1U_0402_16V7K
2
1

PC90
S PQ35
3

PC89 SSM3K7002FU_SC70-3
2

@ .1U_0402_16V7K
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 43 of 48
5 4 3 2 1
 5 4 3 2 1

+5VS

2
6

6
CPU_VID6

CPU_VID5
CPU_VID4

CPU_VID3

CPU_VID2

CPU_VID1

CPU_VID0
PR119
+CPU_B+ PL9

33
VR_ON
1_0603_5%
FBMA-L11-453215-121LMA90T_2
1 2 B+

680P_0402_50V7K
10U_1206_25V6M

10U_1206_25V6M

330P_0402_25V8K~D
0.1U_0402_25V6
D 1 1 D

3300P_0402_50V7K
220U_25V_M

220U_25V_M
1000P_0402_25V8J

680P_0603_50V8J
2

1
PC131

PC93

PC94

PC134

PC133

PC132

PC98

PC99
+ +

0.022U_0402_16V7K
PR120 0_0402_5%

1
PC92

@ PC95

PC96
2.2U_0603_6.3V6K
8,23 PM_DPRSLPVR 1 2 PC97

PC91
0.01U_0402_25V7K

2
PR121 0_0402_5% 2 2
@

2
PR129

PR123

PR124

PR125

PR126

PR130

PR131
PR128
5,8,22 H_DPRSTP# 1 2

5
PR122 0_0402_5%
CLK_ENABLE# 1 2

1
1

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%
0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%
PQ36
PR127 0_0402_5% TPCA8023-H_SO8
+3VS 1 2 4
+3VS

1U_0603_6.3V6M
PL10

2
2
1.91K_0402_1%
2.2_0603_1% 0.22U_0603_10V7K 0.36UH_PCMC104T-R36MN1R17_30A_20%

1
PC100
PR140 PC101

3
2
1
1 BOOT_CPU1 1 2 1 2 1 4 +CPU_CORE
2

PR132

TPCA8028-H_SOP-ADVANCE8-5

TPCA8028-H_SOP-ADVANCE8-5
2

1
PR133 2 3

1
499_0402_1% PR134

49

48

47

46

45

44

43

42

41

40

39

38

37

10K_0402_1%
3.65K_0805_1%
4.7_1206_5% PR141
2

PR135

PR136
1_0402_5%

3V3

CLK_EN#

DPRSTP#

VID6

VID5

VID4

VID3

VID2

VID1

VID0
GND

DPRSLPVR

VR_ON
1

PQ37

PQ42

1 2
1 36 4 4

2
8,23,33 VGATE PGOOD BOOT1 PC102 PR137 0_0603_5%

2
5 H_PSI# 2 35 UGATE_CPU1 @ 680P_0603_50V8J 1 2
PR138 4.99K_0402_1% PSI# UGATE1

2
PMON 1 2 3 34 PHASE_CPU1 VSUM 1 2

3
2
1

3
2
1
0.1U_0603_25V7K PC130 PMON PHASE1
VCC_PRM
2 1 1 2 4 33 ISEN1 PC103
PR139 147K_0402_1% RBIAS PGND1 0.22U_0603_10V7K
C VR_TT# LGATE_CPU1 C
5 VR_TT# LGATE1 32 +CPU_B+

10U_1206_25V6M

10U_1206_25V6M
@PR142
@ PR142 4.22K_0402_1% PH3

1
1 2 1 2 6 NTC PVCC 31

1
PC104

PC106
@ 100K_0603_1%_TH11-4H104FT 7 30 LGATE_CPU2 PQ38

2
SOFT LGATE2 TPCA8023-H_SO8
1 2

2
@ 0.015U_0402_16V7K PC105 8 29
0.022U_0603_25V7K PC107 OCSET ISL6266AHRZ-T_QFN48_7X7 PGND2
4
1 2 9 28 PHASE_CPU2
VW PHASE2 PL11
PR143 13K_0402_1% 10 27 UGATE_CPU2 0.36UH_PCMC104T-R36MN1R17_30A_20%
COMP UGATE2
1 2

3
2
1
11 26 BOOT_CPU2
1 2 1 2 1 4
FB BOOT2 PR144
1 2

1
1000P_0402_50V7K PC109 2.2_0603_1% PC108
DROOP

12 FB2 NC 25 2 3

5
VDIFF

ISEN2

ISEN1
VSUM
VSEN

PR145 8.25K_0402_1% 0.22U_0603_10V7K PR146

GND

VDD
RTN

DFB

VIN

4.7_1206_5%

TPCA8028-H_SOP-ADVANCE8-5

TPCA8028-H_SOP-ADVANCE8-5
VO

1 2

3.65K_0805_1%
1 2 PU11
13

14

15

16

17

18

19

20

21

22

23

24

1 2

1
PQ39

PQ41

10K_0402_1%
PR147

1
PR148
PC110 1000P_0402_50V7K 4 4
ISEN1 PC111 PR149
ISEN2 @ 680P_0603_50V8J 1_0402_5%

2
PR152 97.6K_0402_1% PC112 270P_0402_50V7K 1 2 +5VS

2
1

1 2 2 1

3
2
1

3
2
1

2
1

PR151 1_0603_5% PR154 0_0603_5%

PR153 PC113 VSUM 1 2
1 2 1U_0402_6.3V6K
2

1K_0402_5% <BOM Structure>

2

PC114 100P_0402_50V8J 1 2
PR156
B 100_0402_1% PC116 2200P_0402_50V7K 10_0603_5% PC115 B
1 2 1 2 1 2 +CPU_B+ 0.22U_0603_10V7K
VCC_PRM
1

PR155 1 2 PC117 ISEN2

0.1U_0603_25V7K
PR157 1K_0402_1%
2

PC118 330P_0603_50V8
6 VCCSENSE 1 2 1 2
VSUM
1

PR158 0_0402_5%
1

2.61K_0402_1%

PC119 PC120
PR160

+CPU_CORE 1 2 330P_0603_50V8 0.01U_0603_50V7K

2

PR159 20_0402_5% 1 2
6 VSSSENSE PR161 0_0402_5%
2
1

11K_0402_1%

PC121 180P_0402_50V8J
PR163

PR162 1 2
2

20_0402_5% 1 2 1 2 PH4
10KB_0603_5%_ERTJ1VR103J
2

PR164 1K_0402_1% PR165 3.9K_0402_1%

PC122 .1U_0402_16V7K
1

VCC_PRM 1 2

PC124 0.22U_0402_6.3V6K
PC123 2 1 2 1
0.22U_0603_10V7K

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 44 of 48
5 4 3 2 1
 5 4 3 2 1

NO DATE PAGE MODIFICATION LIST PURPOSE

-------------------------------------------------------------------------------------------------------------
EVT DCIN/DECTOR Change location PU3A to PU1B Circuit modify
Change ENTRIP1 to EN0 ,ENTRIP2 to ACON
VL to RTCVREF in PR23 Pin6
Change PR23 to10k ohm, PR25 to unpop
D
Delete PD13 D
EVT BATTERY CONN/OTP Change location PU4A to PU3A Circuit modify
EVT +CPU_CORE Add PR137 0ohm_0402,PR154 0ohm_0402 Circuit modify
EVT 3VALWP/5VALWP Change PR82 and PR83 to 2.2ohm EMI request
Add PC136 1000P_0402,PC137 330P_0402,
PC138 680P_0402
EVT 1.8VP/0.9VSP Change PR110 to 2.2ohm EMI request
EVT +CPU_CORE Change PR140 and PR144 to 2.2ohm, EMI request
PL9 to FBMA-L11-453215-121LMA90T_2
Add PC131 0.1U_00402,PC132 680P_0402,
PC133 330P_0402, PC134 1000P_0402
PC102 680P_0603,PC111_680P_0603
PR134 4.7ohm _0402,PR146 4.7ohm_0402

EVT CHARGER Change PR70 to 24k ohm Circuit modify for 75W
C C
EVT CHARGER Change PL3 to 10UH_4.5A_20%,PR71 to 120Kohm Circuit modify
DVT 1.8VP/0.9VSP Add PC143 330P_0402,PC147 680P_0402 EMI request
PC149 680P_0402
DVT CHARGER Add PC139 0.1U_0402, PC144 2200P_0402, SED request
PC140 680P_0603,PR166 4.7ohm_0603
Change PR69 to 2.2 ohm

DVT 3VALWP/5VALWP Add PC148 0.1U_0402,PC54 680P_0603, SED request

PC55 680P_0603,PR84 4.7ohm_1206,
PR85 4.7ohm_1206
DVT 1.05V/1.5V Add PC141 0.1U_0402, PC142 0.1U_0402,
PC145 2200P_0402,PC146 2200P_0402, SED request
PC65 680P_0603,PC74 680P_0603,
PR95 4.7 ohm_0402,PR103 4.7 ohm_0402
B
Change PR94 and PR102 to2.2 ohm B

Add PC143 0.1U_0402,PC147 2200P_0402, SED request

DVT 1.8VP/0.9VSP PC83 680P_0603,PR113 4.7 ohm_0402

DVT CHARGER Change PR71 to 120k ohm Circuit modify

DVT CHARGER Change PR70 to 75k ohm Circuit modify for 65W
DVT +CPU_CORE Change PR145 to 11.3k ohm Circuit modify
PVT DCIN/DECTOR Change PU1 Pin8 from VS to N1 Circuit modify
PVT-3 DCIN/DECTOR Change PC135 from 0.1U_0402_16V Circuit modify
to 0.1U_0402_25V
PVT-3 CHARGER Change PR74 to 15.4k ohm Circuit modify
Change PJ12 to PL19,add PR167 10K ohm

PVT-3 3VALWP/5VALWP Change PJ13 to PL20

Circuit modify
A PVT-3 1.05V/1.5V Change PJ14 to PL21,Change PJ15 to PL22 A
Circuit modify
PVT-3 1.8VP/0.9VSP Change PJ16 to PL23
Circuit modify
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 45 of 48
5 4 3 2 1
 5 4 3 2 1

PIR (Product Improve Record)

KSKAA LA-4991P SCHEMATIC CHANGE LIST
REVISION CHANGE: ISPD
Revision Change: 0.1 to 0.2
U3 ZZZ
NO DATE PAGE MODIFICATION LIST PURPOSE
------------------------------------------------------------------------------------------------------ NB_PM_R3 PCB
D
1 12/12 4 Add R14 Spec requestion D

2 12/12 8 Add U3.N28->DP_CLK and U3.M28->DP_DATA support dongle CANTIGA PM PCB ZKU LA-4991P REV0
PMR3@
3 12/12 10 Add R97,Q27,U13,U14 support dongle
U3 PJP1
4 12/12 12 Add C225 For EMI reserv
5 12/12 23 Add J3 For cost down NB_PM_R1 DC-IN
6 12/12 19 Add Q160A/B,Q158A/B, Q159A/B,RV42,RV38,Rv45,CV59 Support dongle
CANTIGA PM PJP1
7 12/12 19 Add RV107 PMR1@ 45@

8 12/12 23 Change HDMI_HPD_R to VGA_HDMI_R from U9C.C21 to D58.2 power connect error U3 UL3

9 12/12 32 QC1 Stuff For card reader LED display Trans

NB_G5_R3
10 12/12 33 Change R758 and R759 from 2.2K to 4.7K Display
For portrequest
customr detect reference voltage former
11 12/12 34 Change Gsenser LDO solution==>UG1,DG1,CG11,CG12,CG13 For cost down CANTIGA GM45 10/100M transformer
G5R3@ 8103EL@
12 12/12 35 Change JPOWER from 4pin to 6pin Add light sensor circuit for test
U3 UL1
13 12/12 35 Change L2,L3 use FBMA-121-100505-301T_0402 Caps sensoe EMI reserve
14 12/12 35 Add R401,R402,C226,C227 Caps sensoe EMI reserve NB_GL_R1 LAN
15 12/12 36 Change C835 from 0.1uf to 0.22uf For power sequence
CANTIGA GL40 8103EL
GMLR1@ 8103EL@

U3 U9
C Revision Change: 0.2 to 0.3 C

SB_GL_R1
NO DATE PAGE MODIFICATION LIST PURPOSE NB_GL_R3
------------------------------------------------------------------------------------------------------ CANTIGA GL40 ICH9-M ES
1 12/24 16 Change R107,R108 use (FBMH1608HM601)BEAD For SED team request GMLR3@ ICH9R1@

2 12/24 16 Change C212,C219 from 0.1uf to 47pf For SED team request U5

3 12/24 16 Add C228,C229,C230 For SED team request

4 12/24 19 Add Q52 For UMA display port use
NB_GM7_R1
5 12/24 20 Add Q13,Q39,R290,R262,R204,R220,R958,C65 For CEC function CANTIGA GM47
GMLR1@
6 12/24 27 Delete Q26 and change R432 from 1M to 100K, R441 from Correct BT schematic
U6
100K to 1K
7 12/24 29 Change CM1,CM4,CM17,CM20 from 0.01uf to 47P For SED team request NB_GM_R3
8 12/24 33 Change HDPPD netname to HDPLOCK and HDPACT to HDPINT For customer request
CANTIGA GM47
9 12/24 34 Add RG2,RG10 and change 2ND source For customer request @

10 12/24 34 Change UG1.6 pull down and UG3.3 from GND to +5VS For customer request U10

NB_GM9_R1
B Revision Change: 0.3 to 0.4 CANTIGA GM49 B
GMLR1@

U11
NO DATE PAGE MODIFICATION LIST PURPOSE
------------------------------------------------------------------------------------------------------
1 02/02 35 Change Q29.3,Q42.3 from +5VALW to +3VALW For suspend LED breathing concern
NB_GM9_R3
2 02/02 17 connect JMXMB.158 via a bead(SM010032020) to U49.45 For VGA SPDIF request CANTIGA GM49
@
3 02/02 17 Reserve JMXMB.134 for HDA_RST For VGA SPDIF request
4 02/02 34 UG2 from R5F211B4D23SP to R5F211B4D31SP(SA000037Y60) For cost down request
5 02/02 20 U8 from R5F211A4C32SP to R5F211B4D33SP(SA000037Z70) For cost down request
6 02/02 33 Change U43.79,U43.80 pull high from +3VS_HDP change to +3Vs For G-Sensor issue
7 02/02 27 ADD R293 R294 for Camera output to LVDS For Camera issue
8 02/02 20 Change Q39 , Q13 footprint Due to footprint error
9 02/02 17 DELETE R185,R217,R218,R227,R275,R105,R187,R188,R790,R791 For Display port issue
17 ADD CV62,CV63,CV64,CV65,CV66,CV67,CV68,CV69
19 ADD RV89
10 02/02 34 ADD D16,R794 For ESATA surpport charge on S4/S5
A
11 02/02 31 CA35 Move to RA24 right side For MIC issue A

12 02/02 27 JFM1 change to JFM For common design request

13 02/02 28 JUWB change to JNAND For common design request
14 02/04 19 DELETE D20 ,ADD Q162 For Display port change design
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 46 of 48
5 4 3 2 1
 5 4 3 2 1

PIR (Product Improve Record)

KSKAA LA-4991P SCHEMATIC CHANGE LIST
REVISION CHANGE:

Revision Change: 0.3 to 0.4

Revision Change: 0.5 to 0.6
NO DATE PAGE MODIFICATION LIST PURPOSE
NO DATE PAGE MODIFICATION LIST PURPOSE
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
D
15 02/04 18 ADD C267 For LVDS change PMOS Design 01 04/01 32 Replace JMB380 to JMB385 Layout placement high limit D

16 02/04 26 ADD C486 For B-CAS change PMOS Design 02 04/01 32 Remove RC11, add RC2,XC1,RC6,CC11,CC13 Replacement JMB380
17 02/04 20 DELETE D8,D53 ,ADD Q161,R130,C876 Change HDMI design 03 04/01 32 Remove J1394,RC20,RC21,RC22,RC23,CC16,RC19,CC20 Remove 1394 , request from customer
18 02/04 27 ADD C232,C233 For Blue tooth and Felica change PMOS 04
Design
04/01 19 Remove Q162, Add D23 Customer request
19 02/04 34 unmount RG2 ; mount CG12,DG1,UG3,CG14,CG13 For G-Sensor Design change 05 04/01 29 Change CL43 connect to JLAN pin12 For common design with KSKAE
20 02/04 36 ADD C837 For +3VALW -> +3V_LAN Change PMOS Design
06 04/01 29 Change CL44 connect to JLAN pin10 For common design with KSKAE
21 02/04 26 unmount RN4,RN5,CN7,UN2,Q21 ; mount RN6 For cost down 07 04/01 18 Change R673 from 0 to 10K For common design with KSKAE
22 02/04 30 DELETE UA1,CA11 For cost down 08 04/01 27 Change R722 from 0 to 100K For common design with KSKAE
23 02/04 19 DELETE R134,R135,L6 For EMI Request 09 04/02 20 Remove Q161,Q26,R220,R558,C861, Add D53 For common design with KSKAE
24 02/04 30 DELETE R204,R220 For HDMI issue 10 04/02 28 Add R825 ES Status review
25 02/04 19 Modify JBLG footprint to ACES_85201-0405N_4P For KB Bcaklight 11 04/02 32 Remove CC11, CC13, XC1, RC2, RC6, RC9 For common design with KSKAE
26 02/05 33 exchange U43.25 , U43.26 For Backlight KB issue 12 04/03 30 Add CA56, CA57, CA58 FOR EMC status update
27 02/05 26 JEXP USB20_N8,USB20_P8 Change to USB20_N4,USB20_P4 For design change 13 04/03 32 Add RC2, RC6, RC9, RC11 FOR JMB380 W/O 1394
28 02/05 27 JFP USB20_N4,USB20_P4 Change to USB20_N8,USB20_P8 For design change 14 04/06 20 Change U7 from STHDLS101TQT to CH7318C-BF FOR HDMI fuction measure
29 02/05 35 D20,D22 For EMI request 15 04/06 20 Change L9,L10,L11,L12 from WCM-2012-900T to WCM-2012-121T FOR EMI request
30 02/05 27 D21 For EMI request 16 04/06 27 Change R722 from 10K ohm to 0ohm Need meet Blue tooth spec
C
31 02/05 31 C860 For EMI request C

32 02/05 25 Change D15 PN to SC300000P00 For EMI request

33 02/05 31 Change DA4,DA5,DA6,DA7 PN to SCA00000G00 For EMI request
34 02/05 30 Change CA36 to 10p ,RA33 to 10 ohm For EMI request
35 02/05 30 C694 For EMI request
36 02/05 20 HDMI CEC schematic modify Cut-in New Design
37 02/06 10 ADD C644,C649,R204,R217,R218,R188,R135 For Display port issue
38 02/05 30 Modify J3 Footprint to JUMP_43X39 For Design request
39 02/05 28 Modify J3GSIM footprint to MOLEX_47273-0001_6P-S For ME request
40 02/07 19 Remove RV45 ,RV81 Change to 1Mohm For Display port issue
41 02/07 10 U13.2 Change DP_AUX_NB to DP_AUX For Display port issue
U13.5 Change DP_AUX#_NB to DP_AUX#
42 02/07 10 U14.2 Change DP_AUX_NB to DP_AUX
U14.5 Change DP_AUX#_NB to DP_AUX# For Display port issue

43 02/07 10 R797.2 Change DP_HPD_NB to DP_HPD For Display port issue

For B-CAS issue
44 02/10 26 change JBCAS1 connect method
B
45 02/10 33 ADD D4 leakage electircity issue B

46 02/10 28 Change JWLAN +3VS->+3V_LAN For Design change

47 02/10 28 ADD PJ18,PJ19 For Design change
48 02/10 19 Remove RV37,RV79 For Display port issue
49 02/10 10 ADD R135 For Display port issue
50 02/10 8 ADD RA35,CA43 For HDMI noise issue
51 02/10 20 ADD R220,Q26,R558,C861 Cut-in New design
52 02/11 20 Change R156 to 4.12kohm For HDMI issue
53 02/11 20 UV12.1,UV12.5 don't connect For design issue
54 02/11 28 RM6.2 change to +3VS For design issue
55 02/11 20 C861 footprint change to 0603 For design issue
56 02/11 29 UL3 PN -> SP050005L00 For EMI request
57 02/11 34 UG1 PN -> SA000039900 For customer request
58 02/11 32 Remove 1394 function For customer request

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 47 of 48
5 4 3 2 1
 5 4 3 2 1

PIR (Product Improve Record)

KSKAA LA-4991P SCHEMATIC CHANGE LIST
REVISION CHANGE:

Revision Change: 0.4 to 0.5

NO DATE PAGE MODIFICATION LIST PURPOSE
------------------------------------------------------------------------------------------------------
01 03/14 18 Change R103 from 100K to 10K with BKOFF# To solve some panel still have white screen when insert and un-insert AC adapter
D D
02 03/14 18 Mount R431 and un-mount R429 For LVDS connector with camera power to +5VS For design change
03 03/14 20 Change U8 net for HDMI_SCLK/SDATA to HDMI CLK/DATA to CEC For wrong connect impact leakage current
04 03/14 20 Change R570 from 100K to 10K To avoid low voltage when insert HDMI device
05 03/14 20 Change C861 floorprint from 0603 to 0402 For common design with KSWAA
06 03/14 21 Change R794 connect to D16 pin1 For wrong pull-up rail of USB_OC#2
07 03/14 21 Exchange U9 USB port4 and port8 For customer request
08 03/14 23 Add U47,R227,C234 and remove D4 For CMOS discharge fail
09 03/14 25 Mount C350 and unmount C353 For USB power function
10 03/14 26 Change RN1 and RN2 pull high from +3VALW to +3V_SB For common design with KSWAA
11 03/14 27 Add R428 with 0ohm for reserve +5VALW For use module on camera connector & LVDS connector
12 03/14 27 JFM inverse connection For pin no match with MB and cable
13 03/14 28 Connect to JGPS.49 and JGPS.51 reserve To avoid some issue happen
14 03/14 28 Unmount RM3 For common design with KSKAE
15 03/14 28 un-mount RL3 with +3V_LAN for LAN_WAKE# For common design with KSKAA
16 03/14 30 Add CA43,CA44,CA45,CA46,CA52,CA53 on codec input/power pins For common design with KSKAE
17 03/14 31 Add R790,R791,R792,R798 with 100ohm For speaker ouput voltage to high
C C
18 03/14 31 Change Q38 from SI2301BDS to AO3413 and change R587 from For use module on camera connector & LVDS connector
100K to 10K
19 03/14 32 Add RC9 with 10K For common design with KSKAE
20 03/14 32 Change schematic design from JMB380 to JMB385 For customer change spec
21 03/14 33 R751 pull-up to +3VL of CEC_INT# For common design with KSKAE
22 03/14 33 Change R755 and R756 from 4.7K to 2.2K and pull up +3VL For common design with KSKAE
23 03/14 33 Exchange HDPINT and HDPACT For G-sensor function work normal
24 03/14 33 un-mount R788 for +5VS power switch For reduce inrush current
25 03/14 33 Add R761,R762,R763,R764 To prevent voltage leakage in S5
26 03/14 34 Change UG3 from APL5151 to G9191 and unmount CG13 For common design with KSKAE
27 03/14 35 Connect JLIGHT pin5,6 to GND For common design with KSKAE
28 03/14 36 un-mount R594 for +5V_SB power switch Let the power switch can get more Vgs voltage when battery low voltage state
29 03/14 36 change R789 from 330K to 820K and R786 from 100K to 220K For +1.8VS power sequence For power question request
30 03/15 36 Remove R790,R791,R792,R798 with 100ohm For speaker out voltage is normal
31 03/15 36 Add RA12 with 0ohm For common desin with KSKAE

B Revision Change: 0.6 to 1.0 B

NO DATE PAGE MODIFICATION LIST PURPOSE

------------------------------------------------------------------------------------------------------
01 04/10 23 Add R811 and connect to U9C.AF18 For single and dual panel select
02 04/10 20 Change R156 from 4.12K to 976 ohm For change level shifter IC of HDMI function
03 04/10 31 Add RA36, RA37, RA38, RA39 with 0ohm For Int. MIC noise
04 04/10 35 Change Q42 power from +3VALW to +5VALW For Power LED too dark issue
05 04/10 20 Add R220 with 0ohm For use ASM1442T reserve.
06 04/20 20 Change U7 to ASM1442T For HDMI signal quality bad issue
07 04/20 20 Delete R149,R159,R160,R161,R162,C251,C252,C253,C254 For HDMI signal quality bad issue
08 04/20 20 Change R151,R152,R153,R154,R689 to 2.2K and R156 to 3.3K For HDMI signal quality bad issue
09 05/05 20 For HDMI signal quality bad issue

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A4991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401662
Date: Thursday, May 21, 2009 Sheet 48 of 48
5 4 3 2 1
www.s-manuals.com