VHDL code for Halfadder

library ieee;

use ieee.std_logic_1164.all;;

entity halfadder is

port (a, b : in std_logic;

sum, carry : out std_logic);

end halfadder;

architecture structural of halfadder is

component logic_xor is

port ( a, b : in std_logic ; z : out std_logic);

end component;

component logic_and is

port ( a, b : in std_logic ; z : out std_logic);

end component;

begin

g1:logic_xor port map (a, b, sum);

g2:logic_and port map (a, b, carry);

end structural;

--logic_xor

library ieee;

use ieee.std_logic_1164.all;

entity logic_xor is

port ( a, b : in std_logic ; z : out std_logic);

end logic_xor;
architecture behavioral of logic_xor is

begin

z <= a xor b;

end behavioral;

--logic_and

library ieee;

use ieee.std_logic_1164.all;

entity logic_and is

port ( a , b : in std_logic ; z : out std_logic);

end logic_and;

architecture behavioral of logic_and is

begin

z <= a and b;

end behavioral;
 VHDL code for Fulladder

library ieee;

use ieee.std_logic_1164.all ;

entity fulladder is

port (a, b, c : in std_logic;

sum, carry : out std_logic);

end fulladder;

architecture structural of fulladder is

component logic_xor is

port ( a, b : in std_logic ; z : out std_logic);

end component;

component logic_and is

port ( a, b : in std_logic ; z : out std_logic);

end component;

component logic_or is

port ( a, b, c : In std_logic ; z : out std_logic);

end component;

signal s0, s1, s2, s3 : std_logic;

begin

g1:logic_xor port map (a, b, s0);

g2: logic_xor port map (s0, c, sum);

g3: logic_and port map (a, b, s1);

g4: logic_and port map ( b, c, s2);

g5:logic_and port map (a, c, s3);

end structural;

--logic_xor

library ieee;

use ieee.std_logic_1164.all;

entity logic_xor is

port ( a, b : in std_logic ; z : out std_logic);

end logic_xor;

architecture behavioural of logic_xor is

begin

z <= a xor b;

end behavioral;

--logic_and

library ieee;

use ieee.std_logic_1164.all;

entity logic_and is

port ( a , b : in std_logic ; z : out std_logic);

end logic_and;

architecture behavioral of logic_and is

begin

z <= a and b;

end behavioral;
 --logic_or

library ieee;

use ieee.std_logic_1164.all;

entity logic_or is

port ( a , b , c: in std_logic ; z : out std_logic);

end logic_or;

architecture behavioral of logic_or is

begin

z <= a or b or c ;

end behavioral;
 VHDL code for Half-subtractor
entity halfsub is

port (a, b : in std_logic ; difference, borrow : out std_logic);

end halfsub;

architecture structural of halfsub is

component logic_xor is

port (a, b : in std_logic ; z : out std_logic);

end component;

component logic_not is

port ( a : in std_logic ; z : out std_logic);

end component;

component logic_and is

port (a, b : in std_logic ; z : out std_logic);

end component;

signal s0 : std_logic;

begin

g1: logic_xor port map (a, b, difference);

g2: logic_not port map (a, s0);

g3 : logic_and port map( b, s0, borrow);

end structural;

--logic_not

library ieee;

use ieee.std_logic_1164.all;

entity logic_not is

port ( a : in std_logic ; z : out std_logic);

architecture behavioral of logic_not is

begin

z <= not a;

end behavioral;

--logic_xor

library ieee;

use ieee.std_logic_1164.all;

entity logic_xor is

port ( a, b : in std_logic ; z : out std_logic);

end logic_xor;

architecture behavioural of logic_xor is

begin

z <= a xor b;

end behavioral;

--logic_and

library ieee;

use ieee.std_logic_1164.all;

entity logic_and is

port ( a , b : in std_logic ; z : out std_logic);

end logic_and;

architecture behavioral of logic_and is

begin

z <= a and b;

end behavioral;
 VHDL code for Full-subtractor
entity fullsub is

port (a, b, c : in std_logic ; difference, borrow : out std_logic);

end fullsub;

architecture structural of fullsub is

component logic_xor is

port (a, b : in std_logic ; z : out std_logic);

end component;

component logic_not is

port ( a : in std_logic ; z : out std_logic);

end component;

component logic_and is

port (a, b : in std_logic ; z : out std_logic);

end component;

component logic_or is

port (a, b, c : in std_logic ; z : out std_logic);

end component;

signal s0, s1, s2, s3, s4 : std_logic;

begin

g1: logic_xor port map ( a, b, s0) ;

g2: logic_xor port map ( s0, c, difference) ;

g3: logic_not port map ( a, s1) ;

g4: logic_and port map ( s1, b, s2) ;

g5: logic_and port map ( s1, c, s3) ;

g6: logic_and port map ( b, c, s4) ;

end structural ;

--logic_not

library ieee;

use ieee.std_logic_1164.all;

entity logic_not is

port ( a : in std_logic ; z : out std_logic);

end logic_not;

architecture behavioral of logic_not is

begin

z <= not a;

end behavioral;

--logic_xor

library ieee;

use ieee.std_logic_1164.all;

entity logic_xor is

port ( a, b : in std_logic ; z : out std_logic);

end logic_xor;

architecture behavioural of logic_xor is

begin

z <= a xor b;

end behavioral;
 --logic_and

library ieee;

use ieee.std_logic_1164.all;

entity logic_and is

port ( a , b : in std_logic ; z : out std_logic);

end logic_and;

architecture behavioral of logic_and is

begin

z <= a and b;

end behavioral;

--logic_or

library ieee;

use ieee.std_logic_1164.all;

entity logic_or is

port ( a , b , c: in std_logic ; z : out std_logic);

end logic_or;

architecture behavioral of logic_or is

begin

z <= a or b or c ;

end behavioral;
 VHDL code for 4-bit Adder/Subtractor
library ieee ;

use ieee.std_logic_1164.all ;

entity addsub is

port (a , b : in std_logic_vector (3 downto 0) ;

s : out std_logic_vector (3 downto 0) ;

m : in std_logic ;

cout : out std_logic) ;

end addsub ;

architecture structural of addsub is

component logic_xor is

port (a, b : in std_logic ; z : out std_logic) ;

end component ;

component fulladder is

port (a ,b, c : in std_logic ; sum, carry : out std_logic) ;

end component ;

signal d0, d1, d2, d3, c0, c1, c2 : std_logic ;

begin

g0 : logic_xor port map (m, b (0), d0) ;

g1 : logic_xor port map (m, b (1), d1) ;

g2 : logic_xor port map (m, b (2), d2) ;

g3 : logic_xor port map (m, b (3), d3) ;

fa0: fulladder port map (a (0), d0, m, s (0), c0) ;

fa1: fulladder port map (a (1), d1, c0, s (1), c1) ;

fa2: fulladder port map (a (2), d2, c1, s (2), c2) ;

end structural ;

--Logic_xor

library ieee ;

use ieee.std_logic_1164.all ;

entity logic_xor is

port (a, b : in std_logic ; z : out std_logic) ;

end logic_xor ;

architecture behavioral of logic_xor is

begin

z <= a xor b ;

end behavioral ;

-- fulladder

library ieee ;

use ieee.std_logic_1164.all ;

entity fulladder is

port (a, b, c : in std_logic ; sum, carry : out std_logic) ;

end fulladder ;

architecture behavioral of fulladder is

begin

sum <= a xor b xor c ;

carry <= (a and b) or (b and c) or (c and a) ;

end behavioral ;
 VHDL Code for 4-bit BCD Adder
library ieee ;

use ieee.std_logic_1164.all ;
entity bcdadder is
Port ( a, b : in std_logic_vector (3 downto 0) ;

cin : in std_logic ;

z : out std_logic_vector (3 downto 0) ;

cout: out std_logic) ;

end bcdadder ;
architecture structural of bcdadder is
component fulladder is

port (a, b, c : in std_logic ; sum, carry : out std_logic) ;

end component ;

component logic_and is

port (a, b : in std_logic ; z : out std_logic) ;

end component ;

component logic_or is

port (a, b, c : in std_logic ; z : out std_logic) ;

end component ;

signal s0, s1, s2, s3, s4, s5, s6, s7, c0, c1, c2, c3, c4, c5, c6 : std_logic ;

begin

fa0 : fulladder port map (a (0), b (0), cin, s0, c0) ;

fa1 : fulladder port map (a (1), b (1), c0, s1, c1) ;

fa2 : fulladder port map (a (2), b (2), c1, s2, c2) ;

fa3 : fulladder port map (a (3), b (3), c2, s3, s4) ;

fa5 : fulladder port map (s1, s7, c3, z (1), c4) ;

fa6 : fulladder port map (s2, s7, c4, z (2), c5) ;

fa7:fulladder port map (s3,'0',c5,z(3),c6) ;

g0 : logic_and port map (s3, s2, s5) ;

g1 : logic_and port map (s3, s1, s6) ;

g2 : logic_or port map (s4, s5, s6, s7) ;

cout <= s7 ;

end structural ;

--full adder

library ieee ;

use ieee.std_logic_1164.all ;

entity fulladder is

port (a, b, c : in std_logic ; sum, carry : out std_logic) ;

end fulladder ;

architecture behavioral of fulladder is

begin

sum <= a xor b xor c ;

carry <= (a and b) or (b and c) or (c and a) ;

end behavioral ;
 --logic_and

library ieee ;
use ieee.std_logic_1164.all ;
entity logic_and is
port(a, b: in std_logic ; z : out std_logic) ;
end logic_and ;
architecture behavioral of logic_and is
begin
z <= a and b ;
end behavioral ;
--logic_or

library ieee ;
use ieee.std_logic_1164.all ;
entity logic_or is
port(a, b, c : in std_logic ; z : out std_logic) ;
end logic_or ;
architecture behavioral of logic_or is
begin
z <= a or b or c ;
end behavioral ;
 VHDL code for 4 to 1 Multiplexer

library ieee ;

use ieee.std_logic_1164.all ;
entity multiplexer is
port(i0, i1, i2, i3, s0, s1, enable : in std_logic ;

y : out std_logic) ;

end multiplexer ;
architecture structural of multiplexer is
component logic_not is

port (a: in std_logic ; z : out std_logic) ;

end component ;

component logic_and is

port(a, b, c, d : in std_logic ; z : out std_logic) ;

end component ;

component logic_or is

port (a, b, c, d : in std_logic; z : out std_logic) ;

end component ;

signal w0, w1, w2, w3, w4, w5, w6 : std_logic ;

begin

g0: logic_not port map (s0, w0) ;

g1: logic_not port map (s1, w1) ;

g2:logic_and port map (i0, w1,w0, enable, w2) ;

g3: logic_and port map (i1, w1, s0, enable, w3) ;

g4: logic_and port map (i2, s1, w0, enable, w4) ;

g6: logic_or port map (w2,w3,w4,w5, y) ;

end structural ;

--logic_not

library ieee ;

use ieee.std_logic_1164.all ;

entity logic_not is

port(a : in std_logic ;

z: out std_logic) ;

end logic_not ;

architecture behavioral of logic_not is

begin

z <= not a ;

end behavioral ;

--logic_and

library ieee ;

use ieee.std_logic_1164.all ;

entity logic_and is

port (a, b, c, d : in std_logic ;

z: out std_logic) ;

end logic_and ;

architecture behavioral of logic_and is

begin

z <= a and b and c and d ;

end behavioral ;
 --logic_or

library ieee ;

use ieee.std_logic_1164.all ;

entity logic_or is

port (a, b , c, d : in std_logic ;

z: out std_logic) ;

end logic_or ;

architecture behavioral of logic_or is

begin

z <= a or b or c or d ;

end behavioral ;
 VHDL code for 1 to 4 De-multiplexer

library ieee ;

use ieee.std_logic_1164.all ;
entity demultiplexer is
port(i, s0, s1, enable : in std_logic ;

y0,y1,y2,y3 : out std_logic) ;

end demultiplexer ;
architecture structural of demultiplexer is
component logic_not is

port (a: in std_logic ; z : out std_logic) ;

end component ;

component logic_and is

port(a, b, c, d : in std_logic ; z : out std_logic) ;

end component ;

signal w0, w1 : std_logic ;

begin

g0: logic_not port map (s0, w0) ;

g1: logic_not port map (s1, w1) ;

g2:logic_and port map (i, w1,w0, enable, y0);

g3: logic_and port map (i, w1, s0, enable, y1) ;

g4: logic_and port map (i, s1, w0, enable, y2) ;

g5:logic_and port map (i, s1, s0, enable, y3) ;

end structural ;
 --logic_not

library ieee ;

use ieee.std_logic_1164.all ;

entity logic_not is

port(a : in std_logic ;

z: out std_logic) ;

end logic_not ;

architecture behavioral of logic_not is

begin

z <= not a ;

end behavioral ;

--logic_and

library ieee ;

use ieee.std_logic_1164.all ;

entity logic_and is

port (a, b , c, d : in std_logic ;

z: out std_logic) ;

end logic_and ;

architecture behavioral of logic_and is

begin

z <= a and b and c and d ;

end behavioral ;
 VHDL code for D-Flipflop

library ieee ;
use ieee.std_logic_1164.all ;
entity dflipflop is
port (d, clock, reset : in std_logic ; q, qbar : out std_logic) ;
end dflipflop ;
architecture behavioral of dflipflop is
signal qs: std_logic;
begin
process (clock, reset)
begin
if reset='1' then
qs <= '0' ;
elsif clock'event and clock = '1' then
qs <= d ;
end if ;
end process ;
q <= qs;
qbar <= not qs ;
end behavioral ;
 VHDL code for T-Flipflop

library ieee ;
use ieee.std_logic_1164.all ;
entity tflipflop is
port (t, clock, reset : in std_logic ; q, qbar : out std_logic) ;
end tflipflop ;
architecture behavioral of tflipflop is
signal qs : std_logic;
begin
process (clock, reset)
begin
if reset='1' then
qs <= '0' ;
elsif clock'event and clock = '1' then
case t is
when ‘0’ => qs <= qs ;
when ‘1’ => qs <= not qs ;
when others => qs <= ‘-’ ;
end case ;
end if ;
end process ;
q <= qs;
qbar <= not qs ;
end behavioral ;
 VHDL code for SR-Flipflop

library ieee ;
use ieee.std_logic_1164.all ;
entity SRflipflop is
port (s, r, clock, reset : in std_logic ; q, qbar : out std_logic) ;
end SRflipflop ;
architecture behavioral of SRflipflop is
signal qs : std_logic;
begin
process (clock, reset)
variable sr : std_logic_vector (1 downto 0) ;
begin
if reset='1' then
qs <= '0' ;
elsif clock'event and clock = '1' then
sr := (s & r ) ;
case sr is
when “00” => qs <= qs ;
when “01” => qs <= ‘0’ ;
when “10” => qs <= ‘1’ ;
when “11” => qs <= ‘-’ ;
when others => qs <= ‘-’ ;
end case ;
end if ;
end process ;
q <= qs;
qbar <= not qs ;
end behavioral ;
 VHDL code for JK-Flipflop

library ieee ;
use ieee.std_logic_1164.all ;
entity JKflipflop is
port (j, k, clock, reset : in std_logic ; q, qbar : out std_logic) ;
end JKflipflop ;
architecture behavioral of JKflipflop is
signal qs : std_logic;
begin
process (clock, reset)
variable jk : std_logic_vector (1 downto 0) ;
begin
if reset='1' then
qs <= '0' ;
elsif clock'event and clock = '1' then
jk := (j & k ) ;
case jk is
when “00” => qs <= qs ;
when “01” => qs <= ‘0’ ;
when “10” => qs <= ‘1’ ;
when “11” => qs <= not qs ;
when others => qs <= ‘-’ ;
end case ;
end if ;
end process ;
q <= qs;
qbar <= not qs;
end behavioral ;
 VHDL code for 3-bit Synchronous Up-Counter
library ieee ;
use ieee.std_logic_1164.all ;
entity upcounter is
port (reset, clock : in std_logic ; q : out std_logic_vector (2 downto 0)) ;
end upcounter ;
architecture structural of upcounter is
component tflipflop is
port (t, clock, reset : in std_logic ; q, qbar : out std_logic) ;
end component ;
component logic_and is
port (a, b : in std_logic ; z : out std_logic) ;
end component ;
signal s0, s1, s2, s3, s4, s5, s6 : std_logic ;
begin
C : tflipflop port map ('1', clock, reset, s0, s1) ;
B : tflipflop port map (s0, clock, reset, s2, s3) ;
A : tflipflop port map (s6, clock, reset, s4, s5) ;
g: logic_and port map(s0, s2, s6) ;
q(0) <= s0 ;
q(1) <= s2 ;
q(2) <= s4 ;
end structural ;
 --tflipflop

library ieee ;
use ieee.std_logic_1164.all ;
entity tflipflop is
port (t, clock, reset : in std_logic ; q, qbar : out std_logic) ;
end tflipflop ;
architecture behavioral of tflipflop is
signal qs : std_logic;
begin
process (clock, reset)
begin
if reset='1' then
qs <= '0' ;
elsif clock'event and clock = '1' then
case t is
when ‘0’ => qs <= qs ;
when ‘1’ => qs <= not qs ;
when others => qs <= ‘-’ ;
end case ;
end if ;
end process ;
q <= qs;
qbar <= not qs ;
end behavioral ;
 --logic_and

library ieee ;
use ieee.std_logic_1164.all ;
entity logic_and is
port(a, b: in std_logic ; z : out std_logic) ;
end logic_and ;
architecture behavioral of logic_and is
begin
z <= a and b ;
end behavioral ;
 VHDL code for 3-bit Synchronous Down-Counter
library ieee ;
use ieee.std_logic_1164.all ;
entity downcounter is
port (reset, clock : in std_logic ; q : out std_logic_vector (2 downto 0)) ;
end downcounter ;
architecture structural of downcounter is
component tflipflop is
port (t, clock, reset : in std_logic ; q, qbar : out std_logic) ;
end component ;
component logic_and is
port (a, b : in std_logic ; z : out std_logic) ;
end component ;
signal s0, s1, s2, s3, s4, s5, s6 : std_logic ;
begin
C : tflipflop port map ('1', clock, reset, s0, s1) ;
B : tflipflop port map (s1, clock, reset, s2, s3) ;
A : tflipflop port map (s6, clock, reset, s4, s5) ;
g: logic_and port map(s1, s3, s6) ;
q(0) <= s0 ;
q(1) <= s2 ;
q(2) <= s4 ;
end structural ;
 --tflipflop

library ieee ;
use ieee.std_logic_1164.all ;
entity tflipflop is
port (t, clock, reset : in std_logic ; q, qbar : out std_logic) ;
end tflipflop ;
architecture behavioral of tflipflop is
signal qs : std_logic;
begin
process (clock, reset)
begin
if reset='1' then
qs <= '0' ;
elsif clock'event and clock = '1' then
case t is
when ‘0’ => qs <= qs ;
when ‘1’ => qs <= not qs ;
when others => qs <= ‘-’ ;
end case ;
end if ;
end process ;
q <= qs;
qbar <= not qs ;
end behavioral ;
 --logic_and

library ieee ;
use ieee.std_logic_1164.all ;
entity logic_and is
port(a, b: in std_logic ; z : out std_logic) ;
end logic_and ;
architecture behavioral of logic_and is
begin
z <= a and b ;
end behavioral ;