Mapping Function

Because there are fewer cache lines than main memory blocks, an algorithm
is needed for mapping main memory blocks into cache lines
Three techniques can be used:

Direct Associative Set Associative

The simplest technique Permits each main memory A compromise that exhibits
Maps each block of main block to be loaded into any the strengths of both the
memory into only one line of the cache direct and associative
possible cache line approaches while reducing
The cache control logic their disadvantages
interprets a memory
address simply as a Tag and
a Word field
To determine whether a
block is in the cache, the
cache control logic must
simultaneously examine
 Desktop, Drawer, and File Cabinet Analogy

the drawer, very few trips to

the file cabinet are needed.
Access cabinet
Access drawer
in 30 s
in 5 s

Register Access
file desktop in 2 s Cache
memory

Main
memory

Fig. Items on a desktop (register) or in a drawer (cache) are more

readily accessible than those in a file cabinet (main memory).
 Direct Mapping

32 17 3 1

TAG Block offset

One of the 214 Byte offset to

blocks select the bytes
 Direct-Mapped Cache
2-bit word offset in line 0-3 Main
3-bit line index in cache 4-7
8-11 mem ory
Word locations
Tag address
32-35
36-39
40-43

64-67
68-71
72-75

Tags Read tag and

Valid bits specified word 96-99
100-103
104-107
Data out

1,Tag Com- 1 if equal Cache miss

pare

Fig. Direct-mapped cache holding 32 words within eight 4-word lines. Each
line is associated with a tag and a valid bit.
Disadvantages of Direct mapping

Disadv: Empty blocks-increase miss rate

 Fullly Associative mapping

TAG DATA

TAG bits are searched in the entire main memory TAG and then the
data is located.
In this case, no part of cache will be empty/we wont be using empty
portions of cache (improved cache hit rate)
Any part of MM can be loaded anywhere in cache
 +

Cache Main Memory

Memory Address Tag Data W0
Tag W1
W2
B0
L0
W3

L
s
W4
W(4 +1)
Compare w B
W(4 +2)
W(4 +3)
(hit in cache)
1 if match
0 if no match
L

0 if match
1 if no match
(miss in cache)

Figure 4.11 Fully Associative Cache Organization

 Disadvantages
Hardware circuit is complex
 Set Associative Mapping
Advantages of Direct mapping + Advantages of Associative mapping

TAG SET DATA

SET 0

SET 1

SET 2

SET 3
 Set associative
MM-64B
CS-32B
Block size-4B
Set size = 2 Blocks (2 way set associative)
No of line=cache size/block size=32/4=8
No of sets=no of lines/set size= 8/2=4
 Set-Associative Cache
2-bit word offset in line 0-3 Main
2-bit set index in cache memory
Word 16-19 locations
Tag
address
32-35
Option 0 Option 1
48-51

64-67
Read tag and specified
Tags word from each option
Valid bits 80-83
0
Data
out 96-99
1
1,Tag Com-
pare Cache 112-115
1 if equal miss
Com-
pare

Fig. 18.6 Two-way set-associative cache holding 32 words of

data within 4-word lines and 2-line sets.
 Direct Mapping

Block Placement Set Associative

Fully Associative

Tag

Block Identification Index

Offset
Cache Memory Management
Techniques
FCFS

Block Replacement LRU

Random

Write Through

Write back
Update Policies
Write around

Write allocate13
 CPU,Cache,DRAM
Write thru cache CPU
Copy back on swap out
Dirty bit
Cache

Miss penalty

DRAM
 Write thru cache
When CPU writes into cache,
CPU
It also writes into DRAM

Content of cache and DRAM are

same. Cache

Speed associated with writing

Into cache and DRAM are different
DRAM
 Copy back on swap out
When Cache contents are modified/
Swap out the data will be copied to
DRAM CPU

Suppose there is I/O signal, and

specific block is transferred from
cache to CPU (active) and I/O signal
Will focus on content of DRAM
Cache
In the above system, cache will be
having updated data and DRAM will
be having out-dated data

Dirty bit (like valid bit) which indicates

cache contents are changed (dirty or not) DRAM
All 4 words needs to be updated
 Miss penalty
Miss penalty should be as low as
possible CPU

Memory access time

1 clock to send address
10 clocks to access the data
Cache
1 clock (1MHz= 1µsec) to send
the word from DRAM to cache C

Cache width-C
DRAM width-D
Cache and DRAM have different organization. DRAM
This is assuming bus width constant D
 Miss penalty
Memory access time
1 clock to send address
10 clocks to access the data
1 clock (1MHz= 1µsec) to send
the word from DRAM to cache

C D Clock time Total time

4 words 1 word 1+ (4*10)+ 45
(4*1)
4 words 4 words 1+ 12
(1*10)+(1*1)
4 2 1+(2*10)+(2* 23
1)

4 4(Each 1 1+(1*10)+(1* 15
word) 4)
Different organization

Cache
C

DRA DRA DRA DRA

M M M M
D D D D
4 memory banks
Interleaved memory

Parallel process
Optimal block size of cache:64 KB (based on studies)
Bandwidth= Bytes transferred/clock
Interleaved Memory
Composed of a collection of
DRAM chips

Grouped together to form a

memory bank

Each bank is independently able

to service a memory read or
write request

K banks can service K requests

simultaneously, increasing
memory read or write rates by a
factor of K
If consecutive words of memory
are stored in different banks, the
transfer of a block of memory is
speeded up
Thank you for your listening