K. J.
Somaiya College of Engineering, Mumbai-77
Batch: B2 Roll No.: 1813086
Experiment / assignment / tutorial No.___9___
Grade: AA / AB / BB / BC / CC / CD /DD
Signature of the Staff In-charge with date
Title: To design and simulate R-2R Ladder Network Digital to Analog Converter (DAC)
Objective:
1. To design and implement 4-bit R-2R ladder DAC with Vref = 5V.
2. To modify the circuit such that full scale output voltage of -15 V is obtained.
3. To modify the circuit to 6-bit R-2R ladder DAC and find output voltage for 101100, if Rf =
2K, R = 1K. Assume Vref = 5V.
OUTCOME: Student will to understand the techniques of Digital to Analog Conversion.
Theory (Derive the output voltage expression for 4-bit R-2R ladder network):
Department of Electronics and Telecommunication Engineering
DICL/SEM-V/AUG-DEC_2020/Pg. No.___
K. J. Somaiya College of Engineering, Mumbai-77
Department of Electronics and Telecommunication Engineering
DICL/SEM-V/AUG-DEC_2020/Pg. No.___
K. J. Somaiya College of Engineering, Mumbai-77
Department of Electronics and Telecommunication Engineering
DICL/SEM-V/AUG-DEC_2020/Pg. No.___
K. J. Somaiya College of Engineering, Mumbai-77
Department of Electronics and Telecommunication Engineering
DICL/SEM-V/AUG-DEC_2020/Pg. No.___
K. J. Somaiya College of Engineering, Mumbai-77
Procedure
Design the 4-bit R-2R ladder DAC network.
Take R = 10K, 2R = 20K and Vref = 5V.
Implement the circuit using simulator
Verify the theoretical and practical output voltage values for all combinations of
binary input 0000 to 1111 and fill the observation table.
Modify the circuit to get full scale voltage of -15 V and verify the output voltage
practically.
Modify the circuit to 6-bit R-2R ladder DAC network. Calculate the output voltage
for binary input 101100, if Rf = 2K, R = 1K and Vref = 5V.
Write effective discussion/conclusion
Circuit Diagram
Simulated Circuit Diagram
Department of Electronics and Telecommunication Engineering
DICL/SEM-V/AUG-DEC_2020/Pg. No.___
K. J. Somaiya College of Engineering, Mumbai-77
Output:
Observation Table
Department of Electronics and Telecommunication Engineering
DICL/SEM-V/AUG-DEC_2020/Pg. No.___
K. J. Somaiya College of Engineering, Mumbai-77
Decimal Digital Inputs
Theoretical Practical
Equivalent
D0 Output Output
of Binary D3(MSB) D2 D1
(LSB) Voltage Voltage
Inputs Vref/2 Vref/4 Vref/8
Vref/16
0 0 0 0 0 0 0.00503713
1 0 0 0 1 -0.625 -0.619953
2 0 0 1 0 -1.25 -1.24494
3 0 0 1 1 -1.875 -1.86993
4 0 1 0 0 -2.5 -2.49492
5 0 1 0 1 -3.125 -3.11991
6 0 1 1 0 -3.75 -3.7449
7 0 1 1 1 -4.375 -4.36989
8 1 0 0 0 -5 -4.99489
9 1 0 0 1 -5.625 -5.61988
10 1 0 1 0 -6.25 -6.24487
11 1 0 1 1 -6.875 -6.86986
12 1 1 0 0 -7.5 -7.49485
13 1 1 0 1 -8.125 -7.49485
14 1 1 1 0 -8.75 -8.74483
15 1 1 1 1 -9.375 -9.36982
Modified circuit diagram for full scale output voltage of -15 V and relevant
calculations
Department of Electronics and Telecommunication Engineering
DICL/SEM-V/AUG-DEC_2020/Pg. No.___
K. J. Somaiya College of Engineering, Mumbai-77
Output:
Department of Electronics and Telecommunication Engineering
DICL/SEM-V/AUG-DEC_2020/Pg. No.___
K. J. Somaiya College of Engineering, Mumbai-77
Department of Electronics and Telecommunication Engineering
DICL/SEM-V/AUG-DEC_2020/Pg. No.___
K. J. Somaiya College of Engineering, Mumbai-77
Modified circuit diagram 6-bit R-2R ladder DAC and calculations for output voltage
if binary input is 101100
Output:
Department of Electronics and Telecommunication Engineering
DICL/SEM-V/AUG-DEC_2020/Pg. No.___
K. J. Somaiya College of Engineering, Mumbai-77
Conclusion/Discussion:
Three R-2R ladder DAC were designed using op amp IC 741. Simulation was donefor two 4
bit R2R and one 6 bit R2R. The simulation was done on LT Spice for all 4bit binary
combination input and with refrence voltages 5V and 15 V to chek effect of saturation voltage
and how to overcome it, and a 6 bit 5V R2R ladder.
Signature of Faculty
Department of Electronics and Telecommunication Engineering
DICL/SEM-V/AUG-DEC_2020/Pg. No.___
