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FPGA-realization of a speed control IC for induction motor drive

Article  in  Engineering Computations · August 2016

DOI: 10.1108/EC-08-2015-0260

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FPGA-realization of a Speed control

IC for IM drive
speed control IC for induction
motor drive
Ying-Shieh Kung, Seng-Chi Chen, Jin-Mu Lin and 1835
Tsung-Chun Tseng Received 31 August 2015
Department of Electrical Engineering, Revised 21 January 2016
Accepted 20 February 2016
Southern Taiwan University of Science and Technology, Tainan, Taiwan

Abstract
Purpose – The purpose of this paper is to integrate the function of a speed controller for induction
motor (IM) drive, such as the speed PI controller, the current vector controller, the slip speed estimator,
the space vector pulse width modulation scheme, the quadrature encoder pulse, and analog to digital
converter interface circuit, etc. into one field programmable gate array (FPGA).
Design/methodology/approach – First, the mathematical modeling of an IM drive, the field-
oriented control algorithm, and PI controller are derived. Second, the very high speed IC hardware
description language (VHDL) is adopted to describe the behavior of the algorithms above. Third, based
on electronic design automation simulator link, a co-simulation work constructed by ModelSim and
Simulink is applied to verify the proposed VHDL code for the speed controller intellectual properties
(IP). Finally, the developed VHDL code will be downloaded to the FPGA for further control the
IM drive.
Findings – In realization aspect, it only needs 5,590 LEs, 196,608 RAM bits, and 14 embedded 9-bit
multipliers in FPGA to build up a speed control IP. In computational power aspect, the operation time
to complete the computation of the PI controller, the slip speed estimator, the current vector controller
are only 0.28 μs, 0.72 μs, and 0.96 μs, respectively.
Practical implications – Fast computation in FPGA can speed up the speed response of IM drive
system to increase the running performance.
Originality/value – This is the first time to realize all the function of a speed controller for IM drive
within one FPGA.
Keywords Field programmable gate array, Induction motor drive, Modelsim/Simulink co-simulation,
Speed control IC
Paper type Research paper

1. Introduction
An induction motor (IM) is an asynchronous alternating current motor. The IM has many
advantages like simplicity, reliability, low cost, and virtually maintenance free. Also, due
to good dynamic performance, such as wide speed range, easy to implement, good
decouple control, IM becomes a research work in literature (Finch and Giaouris, 2008;
Holmes et al., 2012; Novotny and Lipo, 1997; Rodríguez et al., 2014). These applications of
IM include electric vehicles, fans, air conditioners, pumps, and some home appliances, etc.
Currently, indirect field-oriented control (FOC) technique is one of the choice controllers
for high-performance IM drives. The technique known as vector control has resulted in a
large change in the field of electrical drives. This is because the IM can be controlled with
high performance and provides the same performance as achieved from a separately Engineering Computations:
International Journal for Computer-
excited DC motor. Aided Engineering and Software
Vol. 33 No. 6, 2016
pp. 1835-1852
This work was supported by the Ministry of Science and Technology in ROC under Grant © Emerald Group Publishing Limited
0264-4401
No. MOST 104-2221-E-218-012. DOI 10.1108/EC-08-2015-0260
EC In the realization of the digital controller of IM drives, the PC based, digital signal
33,6 processor (DSP) based and field programmable gate array (FPGA) based provide a
possible system solution in this issue (Curkovic et al., 2013; Sutikno et al., 2013; Soufien
et al., 2015; Song et al., 2010). Comparing with FPGA, although the control technique
using DSP provides a flexible skill, it suffers from a long period of development and
exhausts many resources of the CPU. The advantages of the FPGA includes their
1836 programmable hard-wired feature, fast time-to-market, shorter design cycle,
embedding processor, hardware software co-design, low power consumption, and
higher density; therefore, it has been widely used in the implementation of the digital
system and motor drive system (Kung et al., 2009; Monmasson et al., 2011).
Recently, a co-simulation work by electronic design automation (EDA) simulator
link has been gradually applied to verify the effectiveness of the Verilog and VHDL
code in the motor drive system (Kung et al., 2015; Li et al., 2010). The EDA simulator
link (MathWorks, 2016) provides a co-simulation interface between MATLAB or
Simulink and HDL simulators-ModelSim (Modeltech, 2012). Using it you can verify a
VHDL, Verilog, or mixed-language implementation against your Simulink model or
MATLAB algorithm. Therefore, EDA simulator link lets you use MATLAB code and
Simulink models as a test bench that generates stimulus for an HDL simulation and
analyzes the simulation’s response.
In this paper, a co-simulation by EDA simulator link is applied to speed control for
IM drive. The IM, inverter and speed command are performed in Simulink and the slip
speed estimator and integrator, current vector controller, space vector pulse width
modulation (SVPWM) generation, and PI speed controller described by VHDL code are
executed in ModelSim. After successful verification in simulation, an FPGA-based
experimental system is established for testing the developed VHDL code of speed
control intellectual properties (IP) again, and experiment results will validate the
effectiveness of the speed control system of IM drive.

2. FOC of IM
The mathematical model of a typical IM is described, in two-axis d-q rotating reference
frame, as follows (Novotny and Lipo, 1997):
2 Rs Rr ð1sÞ Por Lm 32
2 3 sLs  sLr oe Lm Rr
2
3 2 3
ids sL 2sLs Lr
7 ids
L vds
6 s r

6 7 6 Rs Rr ð1sÞ Por Lm 7 6 7

o  76 qs 7 1 6 vqs 7
6
Lm R r
d66
i qs 7 6
7¼6
e sLs sLr 2sLs Lr 2
sLs Lr 76
i
7 7
6 7
dt 4 ldr 5 66 76 ldr 7 þ sLs 6
4 0
7
5
Lm R r
0  Lr
Rr
o e  2 o r 74
P 5
4 Lr
  5
lqr lqr 0
0 Lm R r
Lr  oe P2 or RLrr

(1)
and the electromagnetic torque can be expressed regarding stator current and rotor
flux linkage:
3P Lm  
Te ¼ iqs ldr ids lqr (2)
4 Lr
with:

s ¼ 1L2m =ðLs Lr Þ (3)

where P is number of poles; ωr, ωe, ωsl are rotor angular speed, electrical angular speed, Speed control
and slip angular speed, respectively; vds, vqs are d-axis and q-axis stator voltage; ids, iqs IC for IM drive
are d-axis and q-axis stator current; λdr, λqr are d-axis and q-axis rotor flux linkage; Rr is
rotor resistance; Lr, Ls, Lm are rotor inductance, stator inductance, and magnetizing
inductance, respectively.
From the third and fourth row in (1), the rotor flux equation can be re-arranged in
the form of: 1837
" # 2 Rr 3" # " #
d ldr Lr osl ldr Lm Rr ids
¼ 4 5 þ (4)
dt lqr osl RLr r
lqr Lr iqs
 
where ωsl is the speed slip defined by oe  P=2 or .
In the ideally de-coupled IM using FOC, the rotor flux linkage is forced to align with
the d-axis, and it follows that:
d
lqr ¼ 0 and lqr ¼ 0 (5)
dt
Therefore, from the first row in (4), the desired rotor flux linkage can be in term of ids as:
Lm ids
ldr ¼ (6)
1 þ Lr s=Rr
Comparing with the mechanical system, the dynamic term in (6) can be neglected, and
the equation can be represented by:
lndr ¼ Lm ids (7)
Therefore, substituting the (5) and (7) into (2), the generated torque becomes:
T e ¼ K t inqs (8)

with:

3P L2m n
Kt ¼ i (9)
4 Lr ds
In (8), it shows that the electromagnetic torque is proportional with the current of inqs .
Further, substituting (5) into the second row of (4), the estimated slip speed can be given
as follows:
Rr inqs
^ sl ¼
o (10)
Lr inds
Finally, the IM dynamic equation with mechanical load is given by:
d
Jm or þ Bm or ¼ T e T L (11)
dt
where Te is the motor torque, Kt is force constant; Jm is the total inertial value; Bm is
total damping ratio; TL is the external torque.
EC According to the FOC approach for IM, the architecture of an FPGA-realization
33,6 speed control system for IM drive is shown in Figure 1. Inside the FPGA, it shows a
Nios II processor for speed command generation, others it displays the configuration
of a speed loop PI controller and a current control loop using FOC. In the current
control circuit, it includes two PI controllers, one coordinate transformations of
Clark, modified inverse Clark, Park, inverse Park as well as a SVPWM, a slip
1838 speed estimation and integrator, a quadrature encoder pulse (QEP) interface circuit
and other element. Except FPGA, the system in Figure 1 also has an inverter, a
rectifier, two analog-to-digital converters (ADCs) and one IM, etc. The formulations
about the transformations among the stationary a-b-c frame, the stationary α-β frame
and the synchronously rotating d-q frame in Figure 1. Finally, the difference form of
a digital PI controller in the speed loop and the current loop can be expressed
as follows:

up ðnÞ ¼ K p eðnÞ (12)

ui ðnÞ ¼ ui ðn1Þ þ K i eðn1Þ (13)

uðnÞ ¼ up ðnÞþ ui ðnÞ ¼ ui ðn1Þþ K p eðnÞþ K i eðn1Þ (14)

where the up, ui, u are the output of P controller, I controller and PI controller,
respectively, as well as the Kp, Ki are the gain of the P controller and I controller,
respectively.

3. The design of the FPGA-based speed control IC for IM drive

Figure 2 illustrates the internal architecture of the proposed FPGA implementation of
a speed control IC for IM drive system. The FPGA herein uses Cyclone IV-EP4CE115,
which is the product of Altera cooperation. There are 114,480 logic elements (LEs),
3,981,312 RAM bits, 532 embedded 9-bit multipliers and maximum 529 available I/O
pins in the Cyclone IV. The internal circuit comprises a Nios II embedded processor IP
and a speed control IP. The Nios II processor is depicted to generate the speed
command and collect the response data. All programs in Nios II processor are coded
in the C language. The speed control IP includes mainly a circuit of an a speed PI
controller, a slip speed estimator and an integrator, a circuit for current controllers
and coordinate transformation (CCCT), an SVPWM circuit, a QEP interface circuit
and an ADC interface circuit. The sampling frequency of the speed control loop and
current control loop are designed with 2 and 16 kHz, respectively. The frequency
divider generates 50 MHz (Clk) and 12.5 MHz (Clk-step) clock to supply all circuits
in Figure 2.
Herein, only the digital hardware circuit design of the CCCT, the slip speed
estimator and integrator, and the PI controller are described and shown in Figures 3-5.
To reduce the FPGA resource usage, a finite state machine (FSM) is employed to
model the algorithm as mentioned earlier. The design circuits in Figures 3-5 that uses
one adder, one multiplier, one divider, some look-up tables, comparators, shifters,
registers, etc. to carry out the overall computation. The multiplier, adder, and divider
apply Altera library parameterized modules (LPM) standard. The internal circuit of
CCCT performs the function of two PI controllers, table look-up for sin/cos function
 ac source

Rectifier
Nios II Processor FPGA C L
Speed Current
CPU
UART controller controller Modify
r* *
iqs vqs Park–1 Clark–1 PWM 1
PIO vα vra
PI PI PWM 2
On-Chip
ROM Timer + + d,q α,β vrb PWM 3
–
– SVPWM PWM 4 Inverter

AvalonTM Bus
SPI
On-Chip
*
ids vβ
Weak flux vds α,β vrc PWM 5
RAM SDRAM a,b,c
Controller control PI PWM 6
+
r –
Speed command
ia iu
generation iqs iα
A/D LPF
d,q α,β
ib A/D
ids iβ Interface iw
α,β a,b,c ic LPF
A/D
Park Clark
ˆ e ˆ e ˆ slip Rr iqs
T(1 + z–1) ids
A
–1 + iqs
2(1 – z ) + Lr ids
QEP B QEP Induction
Interface Z Circuit Motor
Integrator Slip speed
and
estimator r encoder
Transformation

Load
Speed control

IM drive
1839

FPGA-realization of
Figure 1.

control system for

a FOC-based speed
IC for IM drive
EC FPGA-based Speed Control IC
33,6 A[22]
Nios II Embedded Processor IP

A[0] CPU UART

D[31]
ωr [15..0]

Avalon Bus

Avalon Bus
On-chip PIO
D[0] ROM
sram_be[3] r* [15..0] Speed Control IP
Timer
1840 sram_be[2]
sram_be[1]
sram_be[0]
On-chip
RAM Clk
sram_oe SPI
sram_we Clk-step Frequency
sram_cs CK
divider

Clk Clk ADIN[11]

Clk-step
Speed Clk-step Clk

r* [15..0] controller iq* [11..0] ADIN[0]

ia [11..0] ADC Interface
ωr [15..0] (PI controller) BDIN[11]
Circuit
ib [11..0]
ˆe [11..0] Current controllers
ωr [15..0] ic [11..0] BDIN[0]
Slip speed ids [11..0] and coordinate R/C-A
R/C-B
Clk estimator and transformation
integrator iqs [11..0] Clk
Figure 2. Clk-step (CCCT)
Clk-step PWM 1
Internal architecture vra [11..0] SVPWM
PWM 2
PWM 3
of an FPGA-based clk
vrb [11..0] generation
PWM 4
PWM 5
PWM 6
speed control IC for A-pulse
B-pulse
QEP Interface
vrc [11..0]
Circuit
IM drive Z-pulse ωr [15..0]

and the coordinate transformation for Clark, Park, inverse Park, modified inverse
Clarke. The CCCT circuit designed using by FSM is shown in Figure 3 and it
manipulates 24 steps machine to carry out the overall computation. The data type is
12-bit length with a Q11 format and 2’s complement operation. In Figure 3, steps s0~s1
is for the look-up sin/cos table; steps s2~s5 and s5~s8 are for the transformation of
Clarke and Park, respectively; steps s9~s14 is for the computation of d-axis and q-axis
PI controller; and steps s15~s19 and s20~s23 represent the transformation of the inverse
Park and the modified inverse Clarke, respectively. The operation of each step in
FPGA completes within 40 ns (25 MHz clock); therefore whole 24 steps need 0.96 μs
operation time. Although the FSM method requires more operation time than the
parallel processing method in executing CCCT circuit, it does not lose any control
performance in the overall system because the 0.96 μs operation time is much less than
the designed sampling interval, 62.5 μs (16 kHz) of the current control loop in Figure 1.
Further, the slip speed estimator and integrator developed using by FSM are shown in
Figure 4, and it manipulates 18 steps machine to carry out the overall computation. In
Figure 4, steps s0~s8 performs the function of the slip speed estimation; steps s9~s10 is
the summation of slip speed and rotor speed; steps s11~s13 executes the integration
and s14~s17 generates the LUT address for rotor position, respectively. In the division
operation in Figure 4, the dividend, divisor, and quotient are 32-bit Q0, 16-bit Q0, and
16-bit Q8 format, respectively. The divider is a component in the LPM provided by
Altera cooperation. Also, the transfer function for the trapezoid rule integration in
Figure 1 is shown as:
 
Y z1 T samp 1 þ z1
¼ (15)
U ðz1 Þ 2 1z1
 e _adadr sine
LUT
cose

x iq*
– + e_q
+
ia i x
1 –
3 i iq
x + vq
ib x kp_q x + x
–1
3 ki_q x
id
ic x + x + e_q
i_q +
i_q vrx
– e_d v
+ v 2 vrz
–
+ x + LS,1 +
id*=0 3
vd 2 –
kp_d x + – vry
vd +
x + x +
ki_d x
e_d –
v
i_d + vq x
i_d

s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 s18 s19 s20 s21 s22 s23

Look up d-axis PI q-axis PI Modified

Clark Park Park–1
Sin/Cos controller controller Clark–1
Table
Speed control

1841

Figure 3.
IC for IM drive

circuit using FSM

Designed CCCT
EC tsamp

33,6 No
iqs Rr /Lr r u(n–1) 2 y(n–1)
ids < X “01”
ids iqs /ids u(n) y(n)
sl
÷ x RS,1 + + x +
Yes

idsX “010”
1842
s0 s1 s8 s9 s10 s11 s12 s13

Slip speed estimation Speed summation Integrator

 625
– 2
Yes y y1
y + e – addr
y1 LS,1 x


No Yes
y– y y1
+

y1y
Figure 4.
Designed slip speed
estimator and s14 s15 s16 s17
integrator using
FSM
Rotor flux position generation

Kp
r* e Yes
+ e500 e1 = 500 *
iqs
Ki
– e1 x +
r
e(n –1) u(n) No Yes
x + e–500 e1 = –500
u(n –1)
Figure 5.
u(n –1) e1 = e
Designed PI
controller using FSM
s0 s1 s2 s3 s4 s5 s6

and it will be converted to the difference equation for realization. It is presented

as follows:
T samp
yðnÞ ¼ yðn1Þþ ðuðnÞuðn1ÞÞ (16)
2
where Tsamp is the sampling time. Further, the data type in the slip speed estimator and
integrator uses 16bit Q6 format and 32bit Q22 format, respectively. The ratio of Rr/Lr
will be calculated off-line and taken as a constant input value. In Figure 4, total 18 steps
need 0.72 μs operation time. Finally, the PI controller designed using by FSM is shown
in Figure 5 and it manipulates seven steps machine to carry out the overall
computation. In the PI controller design, the speed error adopts the 16bit Q0 format.
The value will multiply a gain with 64; then be converted to a 16bit Q15 format for
further executing the calculation of the PI controller. The range of a singed 16bit Q0 Speed control
number is within ±32,768, so after it divides by 64, the speed error is limited within IC for IM drive
±500 rpm. In Figure 5, whole seven steps need 0.28 μs operation time.
Finally, the FPGA utility of the speed control IC for IM drive in Figure 2 is evaluated
and the result is listed in Table I. The resource usage of the controller architecture shows
that the overall circuits of the proposed speed control IC. It includes a Nios II embedded
processor IP (8,701 LEs, 28,842 RAM bits and 12 embedded 9-bit multipliers) and a speed 1843
control IP (5,590 LEs, 196,608 RAM bits and 14 embedded 9-bit multipliers), which uses
12.48 per cent of the LEs resources, 5.66 per cent of the RAM resources and 2.63 per cent
of the embedded 9-bit multipliers resources of a Cyclone IV-EP4CE115.

4. ModelSim/Simulink co-simulation of speed control IC for IM

The Simulink/Modelsim co-simulation architecture for speed control system for IM
drive is shown in Figure 6. The SimPowerSystem blockset in the Simulink executes the
IM and the IGBT-based inverter. The EDA simulator link for ModelSim performs
the co-simulation using VHDL code running in ModelSim program. It implements the
function of the speed controller by three works. The work-1 to work-3 of ModelSim in
Figure 6 performs the function of speed loop PI controller, the function of CCCT and
SVPWM, and the function of slip speed estimator and integrator, respectively.
The sampling frequency in work-2 and work-3 is designed with 16 kHz but in work-1 is
1 kHz. The clocks of 50 and 12.5 MHz will supply all works of ModelSim. The PI
parameters in work-1 and work-2 can be set in the Simulink. In the simulation
environment in Figure 6, the speed command is generated by the “speed cmd” block.
Further, the speed command and the rotor speed feedback from the “Induction Motor”
block will be sent into work-1 to perform the calculation of the speed loop PI controller
and generate an output of the q-axis current command to work-2. Except iq-axis current
command, the three-phase current detected from the “Induction Motor” block and the
rotor position (or electrical θ) estimated from the work-3 will be sent into the work-2 to
execute the function of CCCT and SVPWM; then generate the six-channel PWM
outputs to drive the IGBT-based inverter working and the IM running. Also, the work-3
will receive the iq current and id current from the work-2 and the rotor speed feedback
from the “Induction Motor” block to perform the estimation of the slip speed and the
rotor position (or electrical θ). Several scopes in Figure 6, such as named with “rotor
speed,” “speed slip,” “address,” “iq-iq*,” “id-id*,” etc. will, respectively display their
simulation results throughout the overall simulation time.

Logic elements Memory Embedded

IP Module circuit (LEs) (bits) 9-bit multiplier

Nios II embedded processor IP 8,701 28,824 12

Speed PI controller 588 0 2
control IP Slip speed estimator and integrator 2,575 0 10
Current controllers and coordination Table I.
transformation (CCCT) 772 196,608 2 The FPGA utility
SVPWM generation 1,324 0 0 evaluation of the
ADC interface circuit 180 0 0 proposed speed
QEP interface circuit 151 0 0 control IC in
Total 14,291 225,432 26 Figure 2
 EC
33,6

1844

ModelSim
Figure 6.

of IM drive
co-simulation

speed control
The Simulink/

architecture for
Slip speed estimator and integrator

SLIP
ModelSim.
PI controller speed Convert 1
Gain1 Rotor Speed
address
Data Type Conversion3 Gain18
9.549 ModelSim. (work-3)
rotor_speed ID
speed slip
(work-1)
Convert slip
cmd
SPEED CMD address IQ
speed_out

24,000 Convert kp
Continuous
kp
Convert ki ModelSim. iq-iq* powergui
60 1 Rotor
address iq_out torque1
SPEED PI
ki
CONTROLLER Gain9
(work-2)
Convert cmd_iq
id_out
id-id* <Rotor speed (wm)>
600 Convert
cmd_id
<Electromagnetic torque Te (N m)>
cmd_id
300 PWM1 In1 Conn1 0.001 Tm
Convert Ki_d <Rotor angle thetam (rad)>
ki_d rad
Constant
A
<Stator current is_d (A)>
1,500 PWM2 In2 Conn2 m
Convert Kp_d
kp_d B <Stator current is_q (A)>
+ Stator current dq
DC Voltage
300 Source1 C <Stator current is_a (A)>
Convert Ki_q
PWM3 In3 Conn3
ki_q Asynchronous Machine <Stator current is_b (A)>
SI Units
2,000 Convert Kp_q <Stator current is_c (A)>
PWM4 In4 Conn4
kp_q
Gain6 Saturation Data Type Conversion10
Induction Motor
info_a
Three phase current (stator)
100 Convert Conn5
PWM5 In5
info_b
Gain7 Saturation1 Data Type Conversion11

100 Convert PWM6 In6 Conn6

info_c
Gain8 Saturation2 Data Type Conversion12
(6) IGBT
100 Convert CCCT
IGBT-based Inverter
FOC & SVPWM
In the simulation, the designed PMSM parameters used in Figure 6 are that pole pairs is 2, Speed control
stator resistance Rs is 1.115 Ω; stator inductance Ls is 5.974 mH; rotor resistance Rr is 1.083 IC for IM drive
Ω; rotor inductance Lr is 5.974 mH; mutual inductance Lm is 203.7 mH; inertia is J ¼ 0.02
kg m2; friction factor is F ¼ 0.005752 N m s; base voltage is 460 V (rms); base frequency is
60 Hz; rated power is 3.730 kW (5HP). In current loop, the PI gains in d-axis and q-axis are
chosen by Kp ¼ 1,500 (12bit Q11), Ki ¼ 300 (12bit Q11) and Kp ¼ 2,000 (12bit Q11), Ki ¼ 300
(12bit Q11). In speed loop, the PI gains are set by Kp ¼ 24,000 (16bit Q15) and Ki ¼ 60 (16bit 1845
Q15). In the proposed system, the maximum current is limited by 20 A and the current for
20.4 A is equivalent with 2,047 by 12bit Q11 format. The external load is 0.001 N m.
To evaluate the proposed controller performance, IM running command at low
speed (300 rpm) and inverse speed (from 300 to −300 rpm or vice versa) condition is
first considered. Also, its simulation results regarding as the speed step response, the
d-axis and q-axis current response, the slip speed estimation and the electrical angle are
shown in Figure 7. It shows that the rotor speed in Figure 7(a) presents a dynamic

(a)
300 Rotor
Speed
(rpm)

0 Speed
Speed
–300 Command

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

time (s)

(b)
20
10 *
iqs
Current
(A)

0
–10 iqs
–20
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
time (s)

(c)
10
*
ids
Current
(A)

5
ids
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
time (s)

(d)
Slip speed

30
(rad/s)

–50
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
time (s)

(e)
360
(degree)
Elec. θ

180
Figure 7.
0 Simulated results for
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
time (s)
IM running at +300
rpm to −300 rpm
Notes: (a) Speed step response; (b) q-axis current response; (c) d-axis current condition
response; (d) slip speed estimation; (e) electrical θ response
EC response performance with a 90 ms rising time, 25 per cent overshoot and near 0 steady-
33,6 state error. It also demonstrates a successful FOC in Figure 7(b) and (c) that the actual
current can track the current command very well both in d-axis and q-axis direction.
Figure 7(d) and (e) also show the results of the slip speed estimation and electrical angle
response. The maximum/minimum slip speed in transient condition is about 32 rad/s
(305 rpm) and −50 rad/s (about −477 rpm), but the slip speed value is near 0 value in the
1846 steady-state condition. Further, another simulation case while the IM runs at high speed
(from 0 → 300 → 600 → 900 rpm) is tested, and its simulation results are shown in
Figure 8. The rotor speed response shown in Figure 8(a) reveals a dynamic response
performance with a 90 ms rising time in the initial step speed command from 0 to 300
rpm, but only 40 ms rising time in the following step speed command from 300 to 600
rpm and from 600 to 900 rpm. It also shows that the overshoot is about 25 per cent, and
the steady-state error is near 0. The current responses in Figure 8(b) and (c) are similar

(a)
900
Speed
Speed
(rpm)

600 Command
300 Rotor
Speed
0
0 0.2 0.4 0.6 0.8 1.0 1.2
time (s)

(b)
10 iqs
Current

*
iqs
(A)

5
0
–5
0 0.2 0.4 0.6 0.8 1.0 1.2
time (s)

(c)
10
Current
(A)

5
*
ids ids
0
0 0.2 0.4 0.6 0.8 1.0 1.2
time (s)

(d)
Slip speed

30
(rad/s)

15
0

0 0.2 0.4 0.6 0.8 1.0 1.2

time (s)

(e)
360
(degree)
Elec. θ

180

0
Figure 8. 0 0.2 0.4 0.6 0.8 1.0 1.2
Simulated results for time (s)
IM running at 300 to Notes: (a) Speed step response; (b) q-axis current response; (c) d-axis current
900 rpm condition response; (d) slip speed estimation; (e) electrical θ response
with those in Figure 7(b) and (c). The slip speed response curve in Figure 8(d) is Speed control
proportional to the q-axis current response that exhibit that a successful FOC is IC for IM drive
achieved in the current loop system. However, the maximum slip speed in the transient
condition is about 35 rad/s (333 rpm), but in the steady-state condition is near 0.
The simulated results displayed in Figures 7 and 8 demonstrate the correctness and
effectiveness of the proposed speed control IP for IM drive.
1847
5. The experimental system and results of the FPGA-based speed control
IC for IM
After confirming the effectiveness of the proposed speed control IP by ModelSim/
Simulink co-simulation, the VHDL codes for speed control IP are directly applied to
the experimental FPGA-based IM drive system. The experimental system is
presented in Figure 9. The main devices are an IM, a DE2-115 board with Altera
Cyclone IV-EP4CE115 FPGA, a voltage source intelligent power modules-based (IPM)
inverter and a rectifier. The input voltage, continuous current, rating torque, rating
speed, continuous power, and pole pairs of the IM are 220 V, 5.6 A, 6.4 N m, 1,800 rpm,
1,500 W, 2, respectively. An encoder with 1,024 pulses/rotate is attached at the IM.
Inside IPM, it has six sets of IGBT type power transistors with emitter of the rated
voltage of 600 V, collector DC rating of 20 A, and a short time (1 ms) rated current of
40 A. Photo coupler IC adopts TLP250, which output has push-pull amplifier
functions. Input signals of the inverter are PWM signals from the FPGA device.
The Altera Cyclone IV-EP4CE115 chip adopted in the design possesses 114,480 LEs,
maximum 529 available I/O pins, 3,981,312 RAM, and 532 embedded 9-bit multipliers.
The chip can embeds with a Nios II processor that is equipped with several 32-bit
CPU, a flexibility of core size, 1-16 Mbytes of flash memory in the available memory
chip, 1 Mbyte SRAM, 16 Mbyte SDRAM, and 4 Gbytes memory outside of the chip.

Inverter

Rectifier

FPGA
Board

External
Load IM

Figure 9.
Experimental system
EC In the implementation, the VHDL codes of speed control IP which includes CCCT,
33,6 PI controller, slip speed estimator and integrator, ADC and QEP interface circuits,
will integrate with Nios II embedded processor IP, to downloaded into FPGA. In the
controller design, the PI gains in d-axis and q-axis are chosen by Kp ¼ 800 (12bit Q11),
Ki ¼ 10 (12bit Q11) in the current loop. In the speed loop, the PI gains are set by
Kp ¼ 24,000 (16bit Q15) and Ki ¼ 60 (16bit Q15). In the flux control, the d-axis current
1848 command is set at 1.5 A. In the realization, two control approaches are adopted to IM
drive. One is the scalar control which typically applies in the industry; the other is the
FOC. The former approach is based on the voltage-frequency (V/f) control method
and shown in Figure 10, and the latter approach is presented in Figure 1. The scalar
controller shown in Figure 10 is an open-loop control structure with no current
feedback but closed-loop control architecture in the speed loop system. The V/f curve
in Figure 10 is 220/60 V/Hz.
In the experiment, the control performance of the scalar control approach is first
evaluated. When the speed command of the IM drive is a square wave with a 3.3 s
period, and with two different magnitude ranges from 900-1,200 rpm and 600-900 rpm,
the speed step responses are reveals in Figure 11(a) and (b), respectively. However, the
transient conditions present very fast response, but the steady-state conditions appear
severe oscillation. Second, the FOC approach applied to IM drive in Figure 1 is
evaluated. When the speed command runs at the condition that the speed command is a
square wave with magnitude ±300 rpm and period 2 s is considered. The experiment
results regarding as the speed step response, the d-axis and q-axis current response
and slip speed estimation are shown in Figure 12. In Figure 12(a), it shows that the
motor speed gives a good dynamic response performance with a little overshoot and
near 0 steady-state error. It has 20 ms rising time. Figure 12(b) shows the actual d-axis
current can track to the d-axis current command at 1.5 A and the actual q-axis current
can follow to the q-axis current command very well. It reveals that the de-coupled effect
is a success after the FOC is adopted. Figure 12(c) shows the slip speed response and its
maximum/minimum slip speed within ± 330 rpm. Further, the IM running at a wide-
range speed from 300 → 600→ 900→ 1,200→ 1,500 rpm is tested, and the experiment
results regarding as the speed step response, the d-axis and q-axis current response
and slip speed estimation are shown in Figure 13. In Figure 13(a), the rotor speed can
track the speed command well with 0 error in the steady-state condition as well as 5~10
per cent overshoot and about 20 ms rising time in the transient condition. In Figure 13
(b), the FOC also present the success due to the actual d-axis and q-axis current that can
track the current command very well. In Figure 13(c), it shows the slip speed estimation
with maximum 460 rpm. The result is reasonable because the slip speed response is
similar to the response in q-axis current. However, comparing with the results of
Figures 11-13, the speed control performance of IM drive using the FOC approach is
more smooth and accurate than the scalar control approach. Finally, the power
consumption is also evaluated. When the voltage of the DC bus provides a 220 V, the
current and power use in different operating speed (300-1,800 rpm) of IM drive using
two different control approaches is listed in Table II. It presents that the current value
measured in DC bus are between 0.25 and 0.46 A if the scalar control approach is
applied, but between 0.06 and 0.16 A if the FOC approach is used. Besides, the saving
power rate is about 65-75 per cent when the FOC approach is adopted.
Therefore, from the simulation results in Figures 7-8 and the experimental results in
Figures 11-13, it demonstrates that the proposed FPGA-based speed control IC used in
IM drive is effectiveness and correctness.
 ac source

Rectifier

Nios II Processor V/f FPGA C L

Speed controller
UART controller Modify
CPU
r* slip Park–1 Clark–1 PWM 1
vqs vra
PIO e* vα
PWM 2
On-Chip PI d,q α,β
ROM Timer + + vrb PWM 3
– + SVPWM PWM 4 Inverter

AvalonTM Bus
SPI vβ
On-Chip
vds α,β vrc PWM 5
RAM
a,b,c
SDRAM PWM 6
Controller r r

Speed command
generation ∫ sin/cos

Integrator A
r QEP
B QEP Induction
Interface
Circuit Motor
and Z
Transformation encoder

Load
Speed control

scalar control
The speed control
1849

approach
drive based on the
system for an IM
IC for IM drive

Figure 10.
EC (a)
33,6 1,200 Speed

Speed (rpm)
command
1,100
Rotor
1,000 speed

900

1850 800
0 2 4 6 8 10
time (s)
Figure 11.
Speed step response
(b)
1,000
of IM running at (a)
900 Speed
Speed (rpm)

900-1,200 rpm and command

(b) 600-900 rpm 800
Rotor
condition when the 700 speed
controller adopts
scalar control 600
approach 0 2 4 6 8 10
time (s)

(a)
400
Speed (rpm)

200 Rotor
Speed speed
0 command

–200
–400
0 1 2 3 4 5
time (s)

(b)
2
Current (A)

1.5
1 id id* iq
iq*
0.5
0
Figure 12.
IM running at ±300 0 1 2 3 4 5
rpm condition and time (s)
its (a) speed step (c)
response (b) current 468
Slip Speed

response (c) slip

(rpm)

speed estimation 0
when the controller
adopts FOC –468
approach 0 1 2 3 4 5
time (s)

6. Conclusion
In this paper, an FPGA-based speed control IC for IM drive has been successfully
demonstrated its performance through co-simulation by using Simulink/ModelSim and
implementation by using FPGA. In realization aspect, the VHDL is used to describe the
behavior of the PI controller, the slip speed estimator, the CCCT, the SVPWM generation,
the QEP, and ADC interface circuit. The FSM is adopted for reducing the FPGA resource
usage; therefore, it only needs 5,590 LEs, 196,608 RAM bits and 14 embedded 9-bit
multipliers to build up the speed control IP. In computational power aspect, the operation
 (a)
1,600
Speed control
1,400
Rotor
1,500 IC for IM drive
Speed
Speed (rpm)

1,200
command speed 1,200
1,000
800 900
600
400 600
200
0
300 1851
0 1 2 3 4
time (s)

(b)
2.5
Current (A)

1.25
id* id iq* Figure 13.
0 IM running at the
iq condition from 300
–1.25 rpm to 1,500 rpm
0 1 2 3 4
time (s) and its (a) speed step
response (b) current
(c) response (c) slip
Slip Speed

468
speed estimation
(rpm)

0 when the controller

–468 adopts FOC
0 1 2 3 4 approach
time (s)

Current/power consumption
Operating speed of IM Scalar approach FOC approach Saving power rate (%)

300 rpm 0.25 A/55.0 W 0.06 A/13.2 W 76.0

600 rpm 0.27 A/59.4 W 0.08 A/17.6 W 70.3
900 rpm 0.32 A/70.4 W 0.10 A/22.0 W 68.7 Table II.
1,200 rpm 0.36 A/79.2 W 0.12 A/26.4 W 66.6 Power consumption
1,500 rpm 0.40 A/88.0 W 0.14 A/30.8 W 65.0 evaluation under two
1,800 rpm 0.46 A/101.2 W 0.16 A/35.2 W 65.2 different control
Note: DC bus voltage: 220 V approaches

time to complete the computation of the PI controller, the slip speed estimator, the CCCT
are, respectively only 0.28, 0.72, and 0.96 μs, which are less than the 62.5 μs (16 KHz)
sampling time in the current control loop. In the experimental results, it shows that the FOC
approach reveals a better control performance and saving power than the scalar control
approach. However, it also demonstrates that the proposed FPGA-based speed control IC is
effectiveness and correctness both from the simulated and experimental results.

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Corresponding author
Ying-Shieh Kung can be contacted at: [email protected]

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