Elinon, Leonel S. A. Engr. Ranil M.

Montaril, MSECE
BSCS 3 – 4 Assignment #1
Simple-As-Possible (SAP-1) Architecture
The Simple-As-Possible computer, is a basic model of computer that primarily focuses
in introducing every crucial and functional idea, as well as advanced concepts, behind the computer
operations with a microprocessor in a very simple yet detailed design without unnecessary information
and SAP-1 leads as the first stage of the evolution towards modern computers and getting you ready for
the 8080 and 8085, two widely used microprocessors.
SAP-1 is mainly comprised of these components or features: a control unit that consists of
program counter, the instruction register, and the controller-sequencer that produces the control
word, the clear signals, and the clock signals; an ALU consists of an accumulator (A), an adder-
subtracter, and a B register; Memory Address Register (MAR) and 16 x 8 RAM (16 memory location
with 8 bits in each location); and I/O unit includes the input programming switches, the output port or
output register, and the binary display. These components are bus-organized where all registers and
units are connected to the W Bus, and all register outputs to the W bus are three-state; this allows orderly
transfer of data and addresses. All other register outputs are two-state; these outputs continuously drive
the boxed they are connected to.
As it is a basic model of computer, SAP cannot perform logical operation but only addition and
subtraction by using an adder/subtractor unit. There is one general purpose register (B register) used to
hold one operand of the arithmetic operation while another is kept by the accumulator register (A) of the
SAP-1. In addition, there are 8 LEDs which work as output unit and connected with the 8-bit output
register. All timely moment of data or activities are performed by the controller/sequencer part of the
SAP-1.
The SAP-1 architecture is 8 bits and comprises of 16x8 RAM, hence, requires 4-bit address
which either comes from the PC during computer run phase or may come from the 4-bit address switches
during the Program Phase. The instruction set get stored in the RAM, therefore it cannot store program
having more than 16 instructions. SAP-1 can only perform five abbreviated (called Mnemonics) basic
operations from its instruction set, which are: Memory-reference instructions--LDA, ADD, and
SUB--because they used data stored in memory and NOT memory reference instructions--OUT and
HLT--because they do not involve the data stored in the memory. Explaining every operation of the
instruction set of SAP-1; LDA (Load the Accumulator) instruction loads RAM data into accumulator;
ADD adds RAM data to accumulator; SUB subtracts RAM data to accumulator; OUT loads accumulator
data into output register; and HLT (Halt) stops the processing. SAP-1 has six T-states to fetch and
execute each instruction called a machine cycle which consists of 3 fetch—T 1, T2, T3—and 3 execute—T4,
T5, T6.
Assembly language involves mnemonics when writing a program, and this program is called a
source program. Machine language works with strings of 0s and 1s, and that program written is called
object program. In SAP-1, the operator translates the source program into an object program when
programming the address and data switches. In machine language instruction, the 4 Most Significant Bits
(MSBs) specify the operation to perform and the 4 Least Significant Bits (LSBs) determine the Address
or Data.

Simple-As-Possible 1 (SAP-1) Architecture: A Block Diagram

W Bus
8
Program Accumulator
Counter 4 A
 8
Input &
MAR
Adder/
4 8 Subtractor

8
4 4

16x8 8
RAM 8
B Register

8
Output
Instruction 8 Register
Register
4

4 8

Binary
Controller-
sequencer
Display

12
 SAP-1 Components
Program Counter
Implemented in "pc.v" file. The program is stored at the beginning of the memory with the first
instruction at binary address 0000, the second instruction at address 0001, the third at address 0010, and
so on. This part of control unit counts from 0000 to 1111 and it signals the memory address of next
instruction to be fetched and executed. It does this as follows.
The program counter is reset to 0000 before each computer run. When the computer run begins,
the program counter sends address 0000 to the memory. The program counter is then incremented to get
0001. After the first instruction is fetched and executed, the program counter sends address 0001 to the
memory. Again, the program counter is incremented. After the second instruction is fetched and executed,
the program counter sends address 0010 to the memory. In this way, the program counter is keeping track
of the next instruction to be fetched and executed.
The program counter is like someone pointing a finger at a list of instructions, saying do this first,
do this second, do this third, etc. This is why the program counter is sometimes called a pointer; it points
to an address in memory where something important is being stored.

Input and MAR (Memory Address Register)

Implemented in "inputMAR.v" file. It includes the address and data switch registers. These
switch registers, which are part of the input unit allow you to send 4 address bits and 8 data bits to the
RAM. Instruction and data words are written into the RAM before a computer run.

The memory address register (MAR) is part of the SAP-1 memory. During a computer run, the
address in the program counter is latched into the MAR. A bit later, the MAR applies this 4-bit address to
the RAM, where a read operation is performed. When SAP1 is in Running Mode, the (4-bit) address is
generated by the Program Counter which is then stored into the MAR through W bus. A bit later, the
MAR Applies this 4-bit address to the RAM, where Data or instruction is read from RAM. i.e., the 0000
from PC goes to MAR through W-Bus, it will be copied to RAM, then RAM will read this address and
fetch the data from RAM, ex. 0000 1011 which 1011 is the data and 0000 is the address.

The RAM
Implemented in "mem16k.v' file. The RAM is a 16 x 8 static TTL RAM. You can program the
RAM by means of the address and data switch registers. This allows you to store a program and data in
the memory before the execution or computer run. During a computer run, the RAM receives 4-bit
addresses from the MAR and a read operation is performed. In this way, the instruction or data word
stored in the RAM is placed on the W bus for use in some other part of the computer. It is asynchronous
RAM, which means that the output data is available as soon as valid address and control signal are
applied.

Instruction Register (IR)

 Implemented in "ir.v" file. The instruction register is part of the control unit. IR contains the
instruction (composed of OPCODE + ADDRESS) to be executed by SAP-1 computer. To fetch an
instruction from the memory, the computer does a memory read operation. This is placing the contents of
the addressed memory location on the W bus. At the same time, the instruction register is set up for
loading on the next positive clock edge.
The contents of the instruction register are split into two nibbles. The upper nibble is a two-state
output that goes directly to the block labeled “Controller-sequencer.” The lower nibble is a three-state
output that is read onto the W bus when needed. Ex. 0000 1011, 0000, which is the upper nibble, goes to
Controller-Sequencer, while the 1011, the lower nibble, goes to W-Bus and goes to MAR.

Controller-Sequencer
Implemented in "cu.v" file. • It generates the control signals for each block so that actions
occur in desired sequence. CLK signal is used to synchronize the overall operation of the SAP1
computer. Before each computer run, a signal is sent to the program counter and a CLR signal to the
instruction register. This resets the program counter to 0000 and wipes out the last instruction in the
instruction register.
A clock signal CLK is sent to all buffer registers; this synchronizes the operation of the computer,
ensuring that things happen when they are supposed to happen. In other words, all register transfers occur
on the positive edge of a common CLK signal. Notice that a signal also goes to the program counter.
The 12 bits that come out of the controller-sequencer form a word controlling the rest of the
computer (like a supervisor telling others what to do.) The 12 wires carrying the control word are called
the control bus. The control word has the format of:
´ ∙ ĹI ∙ ÉI ∙ ĹA ∙ E A ∙ SU ∙ EU ∙ ĹB ∙ ĹO
CON =C P ∙ E P ∙ Ĺ M ∙ CE
This word determines how the registers will react to the next positive CLK edge. For instance, a
high EP and a low LM mean that the contents of the program counter are latched into the MAR on the next
positive clock edge. As another example, a low and a low mean that the addressed RAM word will be
transferred to the accumulator on the next positive clock edge.

Accumulator
Implemented in "accumulator.v" file. The accumulator (A) is an 8-bit buffer register that stores
intermediate answers during a computer run. It is always one of the operands of ADD, SUB, and OUT
instructions. The accumulator has two outputs. The two-state output goes directly to the adder-
subtracter. The three-state output goes to the W bus. Therefore, the 8-bit accumulator word
continuously drives the adder-subtracter; the same word appears on the W bus when E A is high.

The Adder-Subtracter
SAP-1 uses a 2's-complement adder-subtracter. When S U is low, the sum out of the adder-
subtracter is S = A+ B, and when SU is high, the difference appears: A = A+ B'
 The adder-subtracter is asynchronous (unclocked); this means that its contents can change as soon
as the input words change. When EU is high, these contents appear on the W bus.

B Register
Implemented in "register.v" file. The B register is another 8-bit buffer register primarily used to
hold the other operand (one operand is always accumulator) of mathematical operations. It is used in
arithmetic operations. A low and positive clock edge load the word on the W bus into the B register. The
two-state output of the B register drives the adder-subtracter, supplying the number to be added or
subtracted from the contents of the accumulator. To add/sub two 8-bit numbers A and B, the B register
stored the number B.

Output Register
At the end of an arithmetic operation or computer run, this is where the output register is used,
this register holds the output of OUT instruction the accumulator contains the answer to the problem
being solved. Then the answer stored in the accumulator register is then loaded into the output register
through W bus. When EA is high and is low, the next positive clock edge loads the accumulator word into
the output register.
The output register is often called an output port because processed data can leave the computer
through this register. In microcomputers, the output ports are connected to interface circuits that drive
peripheral devices like printers, cathode-ray tubes, teletypewriters, and so forth. (An interface circuit
prepares the data to drive each device.)

Binary Display
The binary display is a row of eight light-emitting diodes (LEDs). Because each LED connects to
one flip-flop of the output port, the binary display shows us the contents of the output port. Therefore,
after we've transferred an answer from the accumulator to the output port, we can see the answer in binary
form.

Instruction Sets

1. LDA Instruction

LDA stands for "load the accumulator." A complete LDA instruction includes the
hexadecimal address of the data to be loaded. LDA 8H means "load the accumulator with the contents
of memory location 8H."

2. ADD Instruction

ADD is another SAP-I instruction. A complete ADD instruction includes the address of the
word to be added. ADD 9H means "add the data of memory location 9H with data of accumulator and
save the result in accumulator.
3. SUB Instruction
SUB is another SAP-I instruction. A complete SUB instruction includes the address of the word
to be subtracted. SUB 9H means "subtract the data of memory location 9H from data of accumulator
and save the result in accumulator.
4. OUT Instruction

It tells the SAP1 computer to transfer the accumulator contents to the output port. After OUT
has been executed, you can see the answer to the problem being solved on LEDs display. OUT is
complete by itself; that is, you do not have to include an address when using OUT because instruction
does not involve data in the memory.

5. HLT Instruction

HLT stands for halt. This instruction tells the computer to stop processing data so it stops the
clock. HLT marks the end of a program, similar to the way a period marks the end of a sentence. You
must use a HLT instruction at the end of every SAP1 program; otherwise, you get computer trash
(meaningless answers caused by runaway processing). HL T is complete by itself; you do not have to
include a RAM word when using HL T because this instruction does not involve the memory.

Operation Code (OP code) for SAP-1 instruction set

Mnemonic OP Code
LDA 0000
ADD 0001
SUB 0010
OUT 1110
HLT 1111
 What is the Machine Code of the following arithmetic operations?
2+20-6+4-23 = -3
02H + 14H – 06H + 04H – 17H = FDH (2’s complement)
Solution:
First, let the operation code (OP code) of the instruction set be

Mnemonic OP Code
LDA 0000
ADD 0001
SUB 0010
OUT 1110
HLT 1111

In order to determine the Machine Code for the arithmetic operations in a 16x8 RAM, specifying
the Assembly Language must be performed first, then convert those instructions into Machine Language
or 0s & 1s (Binary) in order for the computer or machine to understand them.

Address Assembly Language Machine Language

Instruction (Source Instruction (Object
Program) Program)
0H LDA 9H 0000 1001
1H ADD AH 0001 1010
2H SUB BH 0010 1011
3H ADD CH 0001 1100
4H SUB DH 0010 1101
5H OUT 1110 XXXX
6H HLT 1111 XXXX
7H XX XXXX XXXX
8H XX XXXX XXXX
9H 02H 0000 0010
AH 14H 0001 0100
SBH 06H 0000 0110
CH 04H 0000 0100
DH 17H 0001 0111
EH XX XXXX XXXX
FH XX XXXX XXXX
Reference
Malvino, A. P. (1977). PART 2: SAP (SIMPLE-AS-POSSIBLE) COMPUTERS. Digital
Comupter Electronics. Gregg Division, McGraw-Hill. ISBN-10: 0070398615. ISBN-13: 978-
0070398610. Retrieved from https://www.rt-
rk.uns.ac.rs/sites/default/files/materijali/predavanja/SAP_Malvino_Description_Digital_Computer_Electr
onics_Malvino_0.pdf