Case 1: -

Problem Definition: - Design has S1 violations. Fix using command.

Inputs: -

• Synthesis Netlist
• Library Model
• Dofile commands
Outputs: -

• Scan inserted Netlist

• ATPG Dofile
• ATPG Testproc
• Scan Def
What is issue?
Design has four S1 violations.
How resolved?
Set test logic –set on –reset on –clock on => This command adds required mux and inverter gates
to clear DRC violations.
Observations: -

1) Write block diagram with all DFT inputs?

2) How many clock domains? One Fastclk 3)

How many resets?
One Reset
4) Number of scan chains?
4
5) Clock mixing or not clock mixing?

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 Not clock mixing.
6) How many Lockup-latches are added during scan
insertion? Zero
7) Is it top-down or bottom up approach?
Top – down approach.
8) How many terminal lockup latches are added?
Zero
9) Number of scan flops and non-scan flops in the design?
36 scannable and 4 non-scan elements.
10) Chain length?
Given as 10 in dofile (40 elements. So 4 chains with 10 flops each)
11) Number of DRC violations? 4 S1 / D5 violations.
12) Write diagram with issues?

S1 VIOLATIONS

a) clock is connected to the previous output of the flipflop. so clock is not

controllable.

b) reset is connected to the previous output of th flipflop.so reset is not

controllable.

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c) reset is connected to the previous output of th flipflop.so reset is not
controllable.

d) Both clock and reset are connected to the previous outputs. So, both clock
and reset are not controllable.

D5 VIOLATIONS
a) Non scan memory element converted to TIE-X

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b) Non scan memory element converted to INIT-X

c) Non scan memory converted to INIT-X

d) Non scan memory converted to TIE-X

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 13) Write diagram with solution?

a) we are going to adding a MUX logic with the test mode pin to the functional
clock.

14) Log file: - please note your observations from the log file

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 ➢ Top module is DmaWr
➢ Number of shift registers =2
➢ Number of INV inserted =2
➢ Number of MUX inserted =3
➢ Number of new Pins inserted= 12 (4 scan inputs, 4 scan outputs, scan_en,
scan_set, scan_reset, test_en)

Test Case 2: -

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Problem Definition: - Design has S2 violations. Fix using command or manual edit in netlist.
Inputs: -

• Synthesis Netlist
• Library Model
• Dofile commands
Outputs: -

• Scan inserted Netlist

• ATPG Dofile
• ATPG Testproc
• Scan Def What is issue?
Design has S2 violations.
How resolved?
It was corrected by manually editing the netlist. In 3 places the clock was grounded. In
netlist 1’b0 was manually changed to the top level clock.
Observations: -

1) Write block diagram with all DFT inputs?

2) How many clock domains?

One. Fastclk
3) How many resets?
One. Reset
4) Number of scan chains?
4 Scan chains. Total number of flops was 40 and max chain length was given as 10.
5) Clock mixing or not clock mixing?
Not clock mixing.
6) How many Lockup-latches are added during scan insertion?
Zero
7) Is it top-down or bottom up approach?
Top-down approach
8) How many terminal lockup latches are added?
Zero
9) Number of scan flops and non-scan flops in the design?

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 37 scannable and 3 non-scan elements.
10) Chain length?
10
11) Number of DRC violations? Three S2 violations.
12) Write diagram with issues?

13) Write diagram with solution?

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 14) Log file: - please note your observations

➢ Top module is DmaWr

➢ Number of shift registers = 0
➢ Number of INV inserted = 0
➢ Number of MUX inserted = 0
➢ Number of new Pins inserted= 9 (4 scan inputs, 4 scan outputs, scan_en)

Test Case 4: - Problem Definition: - Design has bus contention. Fix the violation by command
or manual edit to netlist Inputs: -

• Synthesis Netlist

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 • Library Model
• Dofile commands
Outputs: -

• Scan inserted Netlist

• ATPG Dofile
• ATPG Testproc
• Scan Def
What is issue?
Design has bus contention.
How resolved?
Set test logic –tristate on => This command adds required and gates or gates and inverter gates
to clear the bus contention violations.
Observations: -

1) Write block diagram with all DFT inputs?

2) How many clock domains?

One. Clk
3) How many resets? One. Reset_
4) Number of scan chains
Total 18 flops. Max chain length was given as 10. So 2 chains having 9 flops each. 5)
Clock mixing or not clock mixing?
Clock non mixing.
6) How many Lockup-latches are added during scan insertion? Zero
7) Is it top-down or bottom up approach?
Top Down

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8) How many terminal lockup latches are added? Zero
9) Number of scan flops and non-scan flops in the design?
18 scan flops. 0 non scan flops.
10) Chain length?
10
11) Number of DRC violations?
Four E4 and one E10 warnings. 12)
Write diagram with issues?

13) Write diagram with solution?

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 14) Log file: - please note your observations from the log file
➢ Top module is RegEnBusWidth
➢ Number of shift registers = 0
➢ Number of INV inserted = 1
➢ Number of OR gate inserted = 1
➢ Number of AND gate inserted = 2
➢ Number of new Pins inserted= 5 (2scan inputs, 2 scan outputs, scan_en)

Test Case 5: -

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Scenario: - Design has 1 clock domain with DFFs and latches. Insert 2 scan chains.
Inputs: -

• Synthesis Netlist
• Library Model
• Dofile commands
Outputs: -

• Scan inserted Netlist

• ATPG Dofile
• ATPG Testproc
• Scan Def
What is the scenario?
Design has flip-flops and latches. We have to insert 2 scan chains.
How it is done?
Insert_test_logic –number 2 => This command will insert 2 scan chains.

Observations: -

1) Write block diagram with all DFT inputs?

2) How many clock domains?

One domain with 2 clocks FastClk and ProcClk.

3) How many resets?

One. Reset

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 4) Number of scan chains?
2 scan chains inserted
5) Clock mixing or not clock mixing?
Not clock mixing
6) How many Lockup-latches are added during scan insertion? Zero
7) Is it top-down or bottom up approach?
Top Down
8) How many terminal lockup latches are added? Zero
9) Number of scan flops and non-scan flops in the design?
54 scannable flops and 2 latches 10)
Chain length?
Chain 1 length is 26 and chain 2 length is 28
11) Number of DRC violations?
D5 warnings for 2 latches as they are non-scan elements. 12)
Write diagram of scan chain inserted?

13) Log file: - please note your observations from the log file
➢ Top module is IdmaRd
➢ Number of shift register flops = 0
➢ Number of latches = 2
➢ Number of flops = 54
➢ Number of new Pins inserted= 5 (2scan inputs, 2 scan outputs, scan_en)

Test Case 6: -

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Scenario: - Design has one clock domain with only scan FFs. Insert 3 scan chains.
Inputs: -

• Synthesis Netlist
• Library Model
• Dofile commands
Outputs: -

• Scan inserted Netlist

• ATPG Dofile
• ATPG Testproc
• Scan Def
What is scenario?
Design has all scannable flops. We have to insert 3 scan chains.
How it is done?
Insert_test_logic –number 3 =>do file command will insert 3 scan chains.
Observations: -

1) Write block diagram with all DFT inputs?

2) How many clock domains?

One. BIST_CLK 3)
How many resets?
One MBIST_RST_L 4)
Number of scan chains?
3 scan chains inserted.
5) Clock mixing or not clock mixing?
Not clock mixing

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6) How many Lockup-latches are added during scan insertion?
Zero
7) Is it top-down or bottom up approach?
Top down.
8) How many terminal lockup latches are added? Zero
9) Number of scan flops and non-scan flops in the design?
Total 102 elements. All scannable.
10) Chain length?
3 scan chains each with 34 flops.
11) Number of DRC violations?
Zero
12) Write diagram of scan chain inserted?

13) Log file: - please note your observations from the log file
➢ Top module name: cntl2
➢ Number of shift register flops: 59
➢ Number of shift register scan inserted: 25
➢ Total number of flops: 102
➢ Number of new pins inserted: 7(3scan inputs, 3 scan outputs, scan_en)

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Test Case 7: -
scenario: - Design has no ATPG model for a flip-flop used in the netlist. Create the model and
insert 2 scan chains.
Inputs: -

• Synthesis Netlist
• Library Model
• Dofile commands
Outputs: -

• Scan inserted Netlist

• ATPG Dofile
• ATPG Testproc
• Scan Def
What is scenario?
Missing of ATPG library for a flip-flop in the design. Correct it and insert 2 scan chains

How it is done?
Check for which module the library is missing and go to ATPG library and add it or
uncomment the lines if commented. Inserting 2 scan chains is done by the command in dofile
insert_test_logic –number 2.
Observations: -

1) Write block diagram with all DFT inputs?

2) How many clock domains?

One. Clk

3) How many resets? One. Reset

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4) Number of scan chains?
2 scan chains inserted
5) Clock mixing or not clock mixing?
Not clock mixing
6) How many Lockup-latches are added during scan insertion? Zero
7) Is it top-down or bottom up approach?
Top down
8) How many terminal lockup latches are added? Zero
9) Number of scan flops and non-scan flops in the design?
14. All scannable 10)
Chain length?
2 chains each with 7 flops 11) Number of DRC
violations?
Nil
12) Write diagram of scan chain?

13) Log file: - please note your observations from the log file
➢ Top module name: EnReg_BusWidth14_15
➢ Number of shift register flops: 0
➢ Total number of flops: 14
➢ Number of new pins inserted: 5(2scan inputs, 2scan outputs, scan_en)

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Test Case 8: -
Scenario: - Design has 1 clock domain and 10-bit shift register. Insert scan for the design and
make the 10-bit shift register as part of scan chain without converting it to scan FFs. Use 2 scan
chains with 2 ports scan-in and scan-out.
Inputs: -

• Synthesis Netlist
• Library Model
• Dofile commands
Outputs: -

• Scan inserted Netlist

• ATPG Dofile
• ATPG Testproc
• Scan Def
What is the scenario?
The design has shift registers. We have to scan stitch the shift registers.
How it is done?
Insert_test_logic –number 2 =>do file command will insert 2 scan chains.
Observations: -

1) Write block diagram with all DFT inputs?

2) How many clock domains?

One. sysclk
3) How many resets?

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 One. Reset
4) Number of scan chains?
2 scan chains are inserted.
5) Clock mixing or not clock mixing?
Not clock mixing
6) How many Lockup-latches are added during scan insertion? Zero
7) Is it top-down or bottom up approach?
Top down
8) How many terminal lockup latches are added? Zero
9) Number of scan flops and non-scan flops in the design?
82 scannable flops and no non scannable flops.
10) Chain length?
41 flops in each chain 11)
Number of DRC violations?
Zero
12) Write diagram of scan chain?

13) Log file: - please note your observations from the log file
➢ Top module name: loop_stack
➢ Number of shift register flops: 10
➢ Number of shift register scan inserted: 1
➢ Total number of flops: 82
➢ Number of new pins inserted: 5(2scan inputs, 2 scan outputs, scan_en)

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Test Case 9: -
Scenario: - Design has 1 clock domain. Insert 2 scan chains for the design containing 2
memories but no memory BIST or collar around the memory.
Inputs: -

• Synthesis Netlist
• Library Model
• Dofile commands
Outputs: -

• Scan inserted Netlist

• ATPG Dofile
• ATPG Testproc • Scan Def
What is the scenario?
The design has one clock domain and memories but no memory bist or collar. We have
to insert 2 scan chains.
How it is done?
The 2 memory modules which are not having bist or collar is declared as a black
box using the command in dofile as add_black_boxes –modules {\name of module1 \
name of module2 \}
2 scan chains are inserted by the command in dofile as insert_test_logic –number 2
Observations: -

1) Write block diagram with all DFT inputs?

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2) How many clock domains?
One. clk
3) How many resets?
One. Reset1
4) Number of scan chains?
2 scan chains are inserted
5) Clock mixing or not clock mixing?
Not clock mixing
6) How many Lockup-latches are added during scan insertion?
Zero
7) Is it top-down or bottom up approach?
Top down
8) How many terminal lockup latches are added? Zero
9) Number of scan flops and non-scan flops in the design?
77. All scannable 10)
Chain length?
Chain1 consist of 39 flops and chain2 of 38 flops.
11) Number of DRC violations?
S7 warnings.
12) Write diagram of scan chain?

13) Log file: - please note your observations from the log file
➢ Top module name: icache
➢ Number of shift register flops: 0
➢ Total number of memory elements: 77
➢ Number of new pins inserted: 5(2scan inputs, 2 scan outputs, scan_en)

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Test Case 10: -
Scenario: - Design has modules where block 1 is already scan inserted with 4 scan chains.
Insert scan for other blocks with 4 scan chains. Balance the scan chain for the entire design
from the top module using 4 scan chains.
Inputs: -

• Synthesis Netlist
• Library Model
• Dofile commands
Outputs: -

• Scan inserted Netlist

• ATPG Dofile
• ATPG Testproc
• Scan Def
What is scenario?
Block 1 is already scan inserted with 4 scan chains. We have to insert scan chains for
other blocks and balance the scan chain so that from top level the number of scan chain should
remain 4.
How resolved? add_sub_chains object_name subchain_name scan_input_pin
scan_output_pin length
scan_type.
This command in dofile specifies a pre-existing scan chain (subchain) within a module, library
model, instance, blackbox, or empty module in a hierarchical design to be stitched into the
toplevel scan chain during the stitching process.
add_black_boxes –modules {\name of module1 \} command is added as the design contains a
memory element which is not scannable.
The command insert_test_logic –number 4 –clock merge is used to insert 4 scan chains and has
more than one clock domain.

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Observations: -

1) Write block diagram with all DFT inputs?

2) How many clock domains?

3 clock domains.
➢ rx_clk ➢ tx_clk ➢
clk_sys 3) How many
resets?
One. rx_rst
4) Number of scan chains?
4 scan chains are inserted.
5) Clock mixing or not clock mixing?
Clock mixing
6) How many Lockup-latches are added during scan insertion? 2
lockup latches.
7) Is it top-down or bottom up approach?
Bottom up
8) How many terminal lockup latches are added? Zero
9) Number of scan flops and non-scan flops in the design?
Out of 212 elements 195 scannable memory elements and 17 non scan memory
elements ignored as black box declared.
10) Chain length?
4 chains each with 53 flops.
11) Number of DRC violations? nill
12) Write diagram of scan chain?

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13) Log file: - please note your observations from the log file
➢ Top module name: rmon
➢ Number of shift register flops: 15
➢ Number of shift register flops scan inserted: 6
➢ Number of lockup latches added: 2
➢ Number of inverter added: 2
➢ Number of new pins inserted: 9 (4scan inputs, 4 scan outputs, scan_en)

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Test Case 11: -
Scenario: - Design has 2 modules block 1 and block 2. Insert 4 scan chains to the design by
ignoring block 2 and insert lockup latch at the end of chains.
Inputs: -

• Synthesis Netlist
• Library Model
• Dofile commands
Outputs: -

• Scan inserted Netlist

• ATPG Dofile
• ATPG Testproc • Scan Def
What is the scenario?
Design has 2 modules block 1 and block 2. Insert 4 scan chains to the design by ignoring
block 2 and insert lockup latch at the end of chains.

How it is done?
The command in dofile add_nonscan_instances –module block2 will not touch block2
for scan insertion as it is already scan inserted. So we insert scan for block1 alone. Addition of
terminal lockup latches is done by the command set_lockup_latch_on –last.
Observations: -

1) Write block diagram with all DFT inputs?

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2) How many clock domains?
One. tx_clk

3) How many resets?

One. reset_tx
4) Number of scan chains?
4 scan chains are inserted 5)
Clock mixing or not clock mixing?
Not clock mixing
6) How many Lockup-latches are added during scan insertion? Zero
7) Is it top-down or bottom up approach?
Bottom up
8) How many terminal lockup latches are added?
4 terminal lockup latches.
9) Number of scan flops and non-scan flops in the design?
183 memory elements. All scannable.
10) Chain length?
First 3 chains consist of 38 flops and 4th chain consist of 39 flops.
11) Number of DRC violations? nill
12) Write diagram of scan chain?

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 13) Log file: - please note your observations from the log file
➢ Top module name: txer
➢ Number of shift register flops: 6
➢ Number of shift register flops scan inserted: 2
➢ Number of terminal lockup latches added: 4
➢ Number of inverter added: 4
➢ Number of new pins inserted: 9 (4scan inputs, 4 scan outputs, scan_en)

Test Case 12: -

Scenario: - Design has 3 clocks (one +ve one –ve and one using both edges). a) Use default scan
insertion b) Mix clock domains and insert scan c) Mix edges and clock domains and insert scan
d) Use a single test clock and insert 4 scan chains.
Inputs: -

• Synthesis Netlist
• Library Model
• Dofile commands
Outputs: -

• Scan inserted Netlist

• ATPG Dofile
• ATPG Testproc
• Scan Def
What is scenario?
The design has 3 clocks. We have to insert scan with and without clock mixing and edge
mixing and use a separate clock for scan insertion called test clock.

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How it is done?
The command in dofile insert_test_logic –number 4 –clock merge –edge merge will give
us the answer for part a b and c. Clock mixing and edge mixing is done. To use a separate clock
as test clock we use the command in dofile as set_scan_signals –TClk testclk.
So a new clock ‘testclk’ will only be used as test clock.
Observations: -

1) Write block diagram with all DFT inputs?

2) How many clock domains?

3 clock domains. Fastclk, ProcClk and St81.
3) How many resets?
One. Reset
4) Number of scan chains?
3 scan chains inserted
5) Clock mixing or not clock mixing?
Clock mixing
6) How many Lockup-latches are added during scan insertion? 2
7) Is it top-down or bottom up approach?
Top down
8) How many terminal lockup latches are added? Zero
9) Number of scan flops and non-scan flops in the design?
Total 130 memory elements out of which 4 are latches. So 128 scannable and 4 non
scannable elements 10) Chain length?
32 flops in each scan chain when clock and edge are mixed. (c) 11)
Number of DRC violations?
Warnings for latches
12) Write diagram of scan chain?

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 The below diagram shows the d part of the question when testclk is inserted. All scan
chains are scanned using a new testclk and 4 scan chains are inserted.

13) Log file: - please note your observations from the log file for (c) part
➢ Top module name: Idma
➢ Number of shift register flops: 2
➢ Number of shift register flops scan inserted: 1
➢ Number of lockup latches added: 2
➢ Number of inverter added: 2
➢ Number of new pins inserted: 9 (4scan inputs, 4 scan outputs, scan_en)

Observations for (d) part:

➢ Top module name: Idma

➢ Number of shift register flops: 2
➢ Number of shift register flops scan inserted: 1
➢ Number of MUX inserted: 3
➢ Number of new pins inserted: 11 (4scan inputs, 4 scan outputs, scan_en, testclk,
test_en)

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