5 .

1 SEQUENTIAL CIRCUITS
Jean-Pierre Deschamps
University Rovira i Virgili, Tarragona, Spain
 5 .1
Motivation
Most digital system specifications cannot be implemented by combinational circuits because
the value of an output signal could be a function of
 (not only) the value of the input signals at the same time,
 (but also) the value of the input signals at preceding times.

Example: vehicle access control system.

Input signals:
 entrance request,
 gate lower and upper positions,
 vehicle present within the gate area,
Output signals:
 motor control (on/off, up/down). 2
 5 .1
Motivation

The values of the signals that control the motor depend on

the sequence of events:
 entrance request,
 open the gate,
 wait for upper gate position,
 wait for clear gate area,
 wait for lower gate position.

A new entrance request is not attended until this

sequence of events is completed.

Conclusion: Some type of memory is necessary.

3
 5 .1
1. Sequential systems
Digital circuits with memory:
 Output values at time t depend on input values at times t, t-1, t-2, etc.
 Able to generate sequences.
 Able to detect sequences.

Example of sequence detection: implement a circuit that detects the

following sequence: 1557.
if x(t-3) = 1 and x(t-2) = 5 and x(t-1) = 5 and x = 7 then y <= detected;
else y <= not_detected; end if;

Example of sequence generation: Implement a circuit that continuously

generates 011011011011··· .
if y(t-2) = 1 and y(t-1) = 1 then y <= 0;
else y <= 1; end if;
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 5 .1
1. Sequential systems
Digital circuits with memory: HOW?

5
 5 .1
1. Sequential systems
Digital circuits with memory: HOW?

6
 5 .1
1. Sequential systems: Concept of STATE

CURRENT
STATE NEXT
STATE

7
 5 .1
1. Sequential systems

SEQUENTIAL CIRCUIT
EXTERNAL EXTERNAL
INPUTS OUTPUTS

CURRENT
STATE NEXT
STATE

8
 5 .1
2. Synchronization: Synchronous sequential circuits
What does mean t, t-1, t-2,… etc.? If t is the current time, does t-1 mean t minus 1 second, t
minus 1 minute, ··· ?

Clock
1
0
time

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 5 .1
2. Synchronization: Synchronous sequential circuits
What does mean t, t-1, t-2,… etc.? If t is the current time, does t-1 mean t minus 1 second, t
minus 1 minute, ··· ?

Clock
1
0
time

10
 5 .1
2. Synchronization: Synchronous sequential circuits
What does mean t, t-1, t-2,… etc.? If t is the current time, does t-1 mean t minus 1 second, t
minus 1 minute, ··· ?

Clock
1
0
time

Positive edge
cycle Positive pulse

Period=T Negative pulse

Frequency=1/T

11
 5 .1
2. Synchronization: Synchronous sequential circuits
Period Frequency
1 msec (milisecond) = 10-3 sec. 1Hz = 1 cycle/sec
1 mseg (microsecond) = 10-6 sec. 1 KHz (kiloHertz) = 103 Hz.
1 nsec (nanosecond) = 10-9 sec. 1 MHz (megaHertz) = 106 Hz.
1 psec (picosecond) = 10-12 sec. 1 GHz (gigaHertz) = 109 Hz.
… 1 THz (teraHertz) = 1012 Hz.
…

Positive edge
cycle Positive pulse

Period=T Negative pulse

Frequency=1/T

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Quiz
What is the period of a clock signal of 20 GHz?

1. 20 msec
2. 50 msec
3. 20 microsec
4. 50 microsec
5. 20 psec
6. 50 psec

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 5 .1
3. Sequential circuit

SEQUENTIAL CIRCUIT
EXTERNAL EXTERNAL
INPUTS OUTPUTS

CURRENT
STATE NEXT
STATE

CK

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 5 .1
SUMMARY
1. Need of other types of circuits (apart from the combinational circuits)
2. Sequential circuits.
3. Concept of circuit internal state (memory).
4. Concept of synchronization. Clock signal CK.

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5 .1

16
5 .2 EXPLICIT FUNCTIONAL DESCRIPTION OF
SEQUENTIAL CIRCUITS

Jean-Pierre Deschamps
University Rovira i Virgili, Tarragona, Spain
 5 .2
1. State transition graph
Set of vertices and directed edges.
Vertices: correspond to the states.
Edges: state transitions .

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 5 .2
1. State transition graph
Set of vertices and directed edges.
Vertices: correspond to the states.
Edges: state transitions.
X=1

Q0
X=1, X=2 o X=3
X=3
X=2
Q1

Q2 X=1 o X=2

X=0

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 5 .2
2. Moore and Mealy machines
What about the circuit outputs?: Two possibilities…

X=1

Q0
Y=1
X=1, X=2 o X=3
X=3
X=2 Q1
Y=0
Q2
Y=1 X=1 o X=2

X=0

MOORE MACHINE MEALY MACHINE

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 5 .2
Example
OBJECTIVE: define a circuit that controls a robot vacuum cleaner.

 Obstacle detection sensor: OB input signal.

 Movements: forward, 90º to the right, 90º to the left .
Specification. In case of obstacle detection:
 turn to the right until there is no more obstacle ,
 then move forward.
Next time an obstacle is detected:
 turn to the left until there is no more obstacle ,
 then move forward.
And so on.
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 5 .2
Example

OB=1 : obstacle detection

RR : Rotate Right
RL : Rotate Left

4 states: SAL (forward, last left), SAR (forward, last right),

SRR (rotate right), SRL(rotate left)

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 5 .2
Example

OB=1 : obstacle detection

RR : Rotate Right
RL : Rotate Left

4 states: SAL (forward, last left), SAR (forward, last right),

SRR (rotate right), SRL(rotate left)

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 5 .2
Example

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 5 .2
Example

OB=0

SAR
RR=RL=00
OB=1 OB=1 OB=0 OB=1

SRL SRR
RR,RL=01 RR,RL=10
OB=0
OB=1
SAL
OB=0 RR=RL=00

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 5 .2
(EXERCISE)
ODD PARITY DETECTION:
Define the state transition graph of a sequential circuit with one binary input X and one
binary output Y. It generates Y = 1 if the input sequence received up to the current time
includes an odd number of 1’s.

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 5 .2
(SOLUTION)
ODD PARITY DETECTION:
Define the state transition graph of a sequential circuit with one binary input X and one
binary output Y. It generates Y = 1 if the input sequence received up to the current time
includes an odd number of 1’s.

How many states?

S0: an even number of 1’s has been inputted,
S1: an odd number of 1’s has been inputted.

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 5 .2
3. Next state table and output table

Any state transition graph can be represented by two tables:

 Next state table: next state in functions of the current
state and of the input values.
 Output table:
 MOORE: output values in function of the current state.
 MEALY: output values in function of the current state
and of the input values.

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 5 .2
3. Next state table and output table

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 5 .2
3. Next state table and output table
NEXT STATE TABLE

OUTPUT TABLE

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 5 .2
Question

Which assertions are true?

1. The state transition graph defines a circuit with 3 states, 1 input and 1 output
2. The state transition graph defines a circuit with 3 states, 2 inputs and 2 outputs
3. The state transition graph defines a Moore machine
4. The state transition graph defines a Mealy machine

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 5 .2
(EXERCISE)
Define the next state table and the output table, and check the correct assertions:

1. The next state table has 3 rows and 3 columns

2. The next state table has 6 rows and 3 columns
3. The output table has 3 rows and 2 columns
4. The output table has 3 rows and 3 columns
5. The output table has 6 rows and 3 columns

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 5 .2
(SOLUTION)
Define the next state table and the output table, and check the correct assertions:

1. The next state table has 3 rows and 3 columns

2. The next state table has 6 rows and 3 columns
3. The output table has 3 rows and 2 columns
4. The output table has 3 rows and 3 columns
5. The output table has 6 rows and 3 columns

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 5 .2
SUMMARY
1. Exhaustive functional definition of sequential machines.
2. State transition graph.
3. Moore and Mealy machines.
4. Next state table and output table.

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5 .2

35
5 .3 COMPONENTS : BISTABLES
Jean-Pierre Deschamps
University Rovira i Virgili, Tarragona, Spain
 5 .3
1. Library components
 Components that store 1 bit
 Generic names : Bistable, Memory element

37
 5 .3
1. Library components
 Components that store 1 bit
 Generic names : Bistable, Memory element

 Basic memory cell

0 1
1

1 0
2

STATE_0 STATE_1

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 5 .3
1. Library components
0 1
1

1 0
2

STATE_0 STATE_1

D b1 1 Q

b2 2

Load Q

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 5 .3
1.a Type D bistable

D b1 1 Q D Q

b2 2
Load Q
Load Q
LATCH D

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 5 .3
1.a Type D bistable

D b1 1 Q D Q

b2 2
Load Q
Load Q
LATCH D

Load D Q Q Equation:
Next state when Load=1
0 x x Q
1 0 x 0 Q   f (Q, D )  D
1 1 x 1

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 5 .3
1.b Other bistables

Bistable Equation

S=R=1 not allowed

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 5 .3
2. Latches and flip-flops
 Type D bistables: LATCHES and FLIP-FLOPS.
 Latch: the state can change at any time when the synchronization input signal
Load = 1.
 Flip-flop: the state can only change on a positive edge (0 to 1 transition) of the
synchronization signal.
LATCH

D Q D Q

FF
Load Load
Q Q

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 5 .3
2. Latches and flip-flops

LATCH
D Q D Q

FF
Load Load
Q Q

Load

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 5 .3
2. Latches and flip-flops

LATCH
D Q D Q

FF
Load Load
Q Q

Load

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 5 .3
2. Latches and flip-flops

LATCH
D Q D Q

FF
Load Load
Q Q

Load Load

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 5 .3
2. Latches and flip-flops

LATCH
D Q D Q

FF
Load Load
Q Q

Load Load

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 5 .3
2. Latches and flip-flops

LATCH
D Q D Q

FF
Load Load
Q Q

Load Load

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 5 .3
Question

The state of the latch do not change if:

1. Q = 0
2. ENABLE = 0 D D Q

ENABLE
3. D = 0 Q

4. In all preceding cases.

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 5 .3
3. Asynchronous Set and Reset inputs
 Inputs that can modify the bistable state, independently of the synchronization input :
 Reset : makes state = 0
 Set : makes state = 1

Set Set Reset Set

Set
D Q T Q J Q
K
CK CK
CK CK
Q Q Q

D
Reset Reset Reset

Q
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 5 .3
3. Asynchronous Set and Reset inputs
 Inputs that can modify the bistable state, independently of the synchronization input :
 Reset : makes state = 0
 Set : makes state = 1

Set Set Reset Set

Set
D Q T Q J Q
K
CK CK
CK CK
Q Q Q

D
Reset Reset Reset

Q
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 5 .3
4. Time diagram
 Describes the circuit behavior in function of the time.

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 5 .3
(Exercise)
Complete the following time diagram:

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 5 .3
(Exercise: solution)
Complete the following time diagram:

x = 1: Q0 = Not(Q0);
x = 0: Q0 = 1;
Q0 = 0: Q1 = Not(Q1);
Q0 = 1: Q1 = 1;

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 5 .3
SUMMARY
1. Bistables. Type D bistables.
2. Latches and flip-flops: behavior of latches and flip-flops.
3. Time diagrams.

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5 .4 SYNTHESIS FROM TABLES
Jean-Pierre Deschamps
University Rovira i Virgili, Tarragona, Spain
 5 .4
Summing up …

57
 5 .4
1. Flip-flops or latches?
 Latches: smaller circuits (rougly: half the number of transistors of a flip-flop)
 Flip-flops: more reliable circuits (flip-flops: inputs are sampled on an edge of CK; latches:
transparent while CK=1)

D FLIP-FLOPS WILL BE USED

Set Set Set

Equation:
D Q T Q
Next state when JKCK= Q
CK CK CK
Q Q
Q   f (Q, D )  DQ
Reset Reset Reset

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 5 .4
2. Problem statement

1) How many flip-flops?

2) Definition of functions Di and outi?

𝐷𝑖 = 𝑓(𝑖𝑛0 ,…, 𝑖𝑛𝑛−1 , 𝑞0 , …, 𝑞𝑚−1 )

𝑜𝑢𝑡𝑖 = 𝑓(𝑖𝑛0 ,.., 𝑖𝑛𝑛−1 , 𝑞0 , . . , 𝑞𝑚−1 ) : Mealy
𝑜𝑢𝑡𝑖 = 𝑓(𝑞0 , …, 𝑞𝑚−1 ) : Moore

The problem amounts to the synthesis of a combinational circuit

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 5 .4
3. Synthesis

1) How many flip-flops?

4 states  we need 2 flip-flops to
encode 4 internal states (q1, q0)

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 5 .4
3.1 Synthesis: STATE ASSIGNMENT

Encode the internal states with 0s and 1s:

state q1 q0
SAR 0 0
SRR 0 1
SAL 1 0
SRL 1 1

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 5 .4
3.2 Synthesis: tables with encoded internal states

STATE TABLE OUTPUT TABLE

q1 q0 OB q1 q0 q1 q0 RR RL
SAR 0 0 0 SAR 0 0
SAR 0 0 1 SRR 0 1
SRR 0 1 0 SAL 1 0
SRR 0 1 1 SRL 1 1
SAL 1 0 0
SAL 1 0 1
state q1 q0 SRL 1 1 0
SAR 0 0 SRL 1 1 1
SRR 0 1
SAL 1 0
SRL 1 1
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 5 .4
3.3 Synthesis: circuit design
TABLA DE ESTADOS
q1 q0 OB q1 q0
SAR 0 0 0 0 0
SAR 0 0 1 1 1
SRR 0 1 0 0 0 𝐷1 = 𝑞1 Δ = 𝑞1 . 𝑞0 . 𝑂𝐵 + 𝑞1 . 𝑂𝐵 + 𝑞1 . 𝑞0
SRR 0 1 1 0 1
SAL 1 0 0 1 0 𝐷0 = 𝑞0 Δ = 𝑂𝐵
SAL 1 0 1 0 1
SRL 1 1 0 1 0
SRL 1 1 1 1 1

TABLA DE SALIDAS
q1 q0 RR RL
SAR 0 0 0 0 𝑅𝑅 = 𝑞1 . 𝑞0
SRR 0 1 1 0
SAL 1 0 0 0 𝑅𝐿 = 𝑞1 . 𝑞0
SRL 1 1 0 1

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 5 .4
3.3 Synthesis: circuit design

𝐷1 = 𝑞1 . 𝑞0 . 𝑂𝐵 + 𝑞1 . 𝑂𝐵 + 𝑞1 . 𝑞0
𝐷0 = 𝑂𝐵

𝑅𝑅 = 𝑞1 . 𝑞0
𝑅𝐿 = 𝑞1 . 𝑞0

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 5 .4
4. Mealy
 Next state table and output table can be merged. Example:

a=0 / z=0
S0 Estado
State a State 
Estado z
S0 0 S0 0
a=1 / z=0
S0 1 S1 0
a=1 / z=1
S1 S1 0 S2 1
S1 1 S2 1
a=x / z=1
S2 0 S2 0
S2 S2 1 S0 1

a=0 / z=0 𝑧 = 𝑓 𝑎, 𝑠𝑡𝑎𝑡𝑒𝑠

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 5 .4
5. Comment
 In most cases a reset signal is necessary to put the circuit in a known initial state.

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 5 .4
Question 1

How many states does have this circuit?

1. 1
2. 2
3. 4
4. It depends on the values of A and B

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 5 .4
Question 2

What table describes the behavior of the circuit?

1. 1
2. 2
3. Both
4. None

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 5 .4
SUMMARY
Steps that must be followed to synthesize a sequential circuit from its next state table and
its output table:
a) Compute the number of flip-flops.
b) Encode the states with 0’s and 1’s.
c) Compute 𝑞𝑖 Δ = 𝑓 𝑖𝑛𝑝𝑢𝑡𝑠, 𝑠𝑡𝑎𝑡𝑒𝑠 from the next state tables.
d) Compute 𝐷𝑖 in function of 𝑞𝑖 Δ (in the case of type D flip-flops: 𝐷𝑖 = 𝑞𝑖 Δ).
e) Compute 𝑜𝑢𝑡𝑖 = 𝑓 𝑖𝑛𝑝𝑢𝑡𝑠, 𝑠𝑡𝑎𝑡𝑒𝑠 (Mealy), or 𝑜𝑢𝑡𝑖 = 𝑓 𝑠𝑡𝑎𝑡𝑒𝑠 (Moore).
f) Design the circuit (don’t forget CK and Reset).

69
5 .5 AN EXAMPLE OF SYNTHESIS
Jean-Pierre Deschamps
University Rovira i Virgili, Tarragona, Spain
 5 .5
Specification

Design a Serial Adder: it adds two n-bit numbers A and B that are serially inputted (inputs
inA and inB, one bit per clock cycle):

∀𝑛
0, an-1, an-2, …, a1, a0 inA
0, bn-1, bn-2, …, b1, b0 inB
Serial Adder S sn, sn-1, …, s1, s0
CK >

(initial most significant bits 0's are added to A and B as the sum of two
n-bit numbers is an (n+1)-bit number)

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 5 .5
Question 1

What information should be internally stored within the circuit in order to perform the
desired operation?

o The value of n.
o The latest computed 1-bit sum
ai+bi .
o The carry generated by the latest
computed 1-bit sum ai+bi .
o None; the serial adder can be
implemented by a combinational
circuit.
an-1, an-2, …, a1, a0 inA
bn-1, bn-2, …, b1, b0 inB
Serial Adder S sn, sn-1, …, s1, s0
CK >

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 5 .5
Question 2

The correct answer is “The carry generated by the latest computed 1-bit sum ai+bi .”
So, which are the minimum number of internal states and the minimum number of flip-
flops necessary to implement the circuit?:

an-1, an-2, …, a1, a0

o 1 state, 1 flip-flop bn-1, bn-2, …, b1, b0
inA
inB sn, sn-1, …, s1, s0
Serial Adder
o 2 states, 1 flip-flop S
CK >
o 2 states, 2 flip-flops
o 4 states, 2 flip flops
o 4 states, 4 flip flops

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 5 .5
Question 3

The correct answer is “2 states, 1 flip flop “. Assume that state C0 corresponds to a latest
generated carry = 0, and C1 to a latest generated carry = 1. What state transition graph(s)
describe(s) the circuit?

1. 2. 3.
(inA,inB)=00, S=0 (inA,inB)=00, S=1 (inA,inB)=11, S=0
(inA,inB)=01 or 10, S=1 (inA,inB)=01 or 10, S=0 (inA,inB)=01 or 10, S=1
C0 C0 C0

(inA,inB)=00, S=1 (inA,inB)=11, S=0 (inA,inB)=00, S=0 (inA,inB)=11, S=1 (inA,inB)=00, S=1 (inA,inB)=11, S=0

C1 C1 C1

(inA,inB)=11, S=0 (inA,inB)=11, S=1 (inA,inB)=00, S=0

(inA,inB)=01 or 10, S=0 (inA,inB)=01 or 10, S=1 (inA,inB)=01 or 10, S=0

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 5 .5
Question 4

Is the state transition graph a Moore model or a Mealy model?

o Moore
o Mealy

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 5 .5
Question 5

Consider the following graph and assign 0 to state C0 and 1 to state C1. Which of the
following tables correspond to the graph? (q is the flip-flop state)

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 5 .5
Question 6
Synthesize the Boolean functions D (next state) and S (output) that correspond to the
preceding tables. Check which of them is correct:

𝐷 = 𝑖𝑛𝐴 .𝑖𝑛𝐵 + 𝑞.𝑖𝑛𝐵 + 𝑞. 𝑖𝑛𝐴

o
𝑆 = 𝑞.𝑖𝑛𝐵 + 𝑞. 𝑖𝑛𝐵 + 𝑞. 𝑖𝑛𝐴

𝐷 = 𝑖𝑛𝐴 .𝑖𝑛𝐵 + 𝑞.𝑖𝑛𝐵 + 𝑞. 𝑖𝑛𝐴

o
𝑆 = 𝑞⨁𝑖𝑛𝐴 ⨁𝑖𝑛𝐵

o 𝐷 = 𝑖𝑛𝐴 .𝑖𝑛𝐵 + 𝑞.𝑖𝑛𝐵 + 𝑞. 𝑖𝑛𝐴

𝑆 = 𝑞⨁𝑖𝑛𝐵

o 𝐷 = 𝑖𝑛𝐴 .𝑖𝑛𝐵 + 𝑞.𝑖𝑛𝐵 + 𝑞. 𝑖𝑛𝐴

𝑆 = 𝑞⨁𝑖𝑛𝐴

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 5 .5
Question 7

Design the circuit and check the correct one:

1. 3.

2.

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 5 .5
SUMMARY
A Serial Adder has been implemented.

79