8-by-8 Bit Multiply Accumulator

Jean Jewry Ramos

8-by-8 Bit Multiplier Accumulator

Jean Jewry Ramos

ID : 5037220

Digital Design and Synthesis

COEN 6501
Department of
Electrical and Computer Engineering
Concordia University
April 2004

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Table of Contents

1 INTRODUCTION………………………………………………………………………4

2 GENERAL REQUIREMENTS……………………………………………………….. 5

3 DESIGN SPECIFICATIONS…………………………………………………………. 6
3.1 CONTROLLER DESIGN…………………………………………………………………………………... 6
3.1.1 Design……………………….……………………………………………………………..………...7
3.1.2 Simulation and Timing…….……………………………………………………………………….8
3.2 MULTIPLIER BLOCK DESIGN.…….…………….………………………………………………………..8
3.2.1 Design………………………………………………………………………………………………...8
3.2.2 Simulation and Timing……………………….…………………………………………………….9
3.3 INPUT REGISTER BLOCK DESIGN.……………………………………….……………………………...10
3.4 ADD ACCUMULATOR BLOCK DESIGN………………..…………………...……………………………10
3.4.1 Design………………………………………………………………………………………………..10
3.4.2 Simulation and Timing…………………………………………………………………….………11
3.5 ADDER DESIGN.…………………………………………………………………….…………………….12
3.5.1 Design…………………………………………………………………………………….………….12
3.5.2 Simulation and Timing……………………………………………………………………..……...13
3.6 MULTIPLIER ACCUMULATOR DESIGN.………….…. …………………………………………………13
3.6.1 Design…………………………………………………………………………………….………….13
3.6.2 Test Bench…………………………………………………………………………………………..13
3.6.3 Simulation and Timing……………………………………………………………………………..14

4 CONCLUSION…………………………………………………………………………15

APPENDIX A: VHDL SOURCE CODE………………………………………………………16

APPENDIX B: SIMULATION RESULT FILES……………………………………………..45

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List of Figures

FIGURE 2-1: MAC BLOCK DIAGRAM……………………………………………………………….5

FIGURE 3-1: MAC DESIGN BLOCK DIAGRAM…………………………………………………….6
FIGURE 3-2: CONTROLLER FSM DIAGRAM……………………………………………………….7
FIGURE 3-3: MAC CONTROLLER SIMULATION TIMING DIAGRAM…………………………...8
FIGURE 3-4: MULTIPLIER DESIGN BLOCK DIAGRAM…………………………………………...9
FIGURE 3-5: MULTIPLIER SIMULATION TIMING DIAGRAM……………………………………9
FIGURE 3-6: INPUT REGISTER BLOCK DIAGRAM………………………………………………10
FIGURE 3-7: ADD ACCUMULATOR BLOCK DIAGRAM…………………………………………11
FIGURE 3-8: ADD_ACCUMULATOR SIMULATION TIMING DIAGRAM………………………11
FIGURE 3-9: 4-BIT RIPPLE CARRY ADDER……………………………………………………….12
FIGURE 3-10: 20-BIT CARRY SELECT ADDER BLOCK DIAGRAM……………………………..12
FIGURE 3-11: 20-BIT CARRY SELECT ADDER SIMULATION TIMING DIAGRAM……………13
FIGURE 3-12: TESTBENCH SIMULATION BLOCK DIAGRAM…………………………………...13
FIGURE 3-13: MAC SIMULATION TIMING DIAGRAM……………………………………………14
FIGURE 3-14: MAC SIMULATION TIMING DIAGRAM (MAX. ACCUMULATED VALUE)……14

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Abstract--- A general design methodology of a multiply accumulator (MAC) is described. A multiply

accumulator (MAC) performs complex multiply operations for modern special-purpose processors. It
has various applications in DSP areas such as, digital filters, image and graphical applications. High
speed, lower power consumption and regularity of layout are the design constraints faced by design
engineer.

1 INTRODUCTION
This project describes a design methodology of an 8-by-8 unsigned multiplier accumulator. At the highest
abstraction level, the project starts with the conception of functional blocks to accommodate multiplication,
addition and accumulation of data as a general requirement. Based upon design specifications, a detailed
Design Block Diagram is constructed; at this level, the block diagram contains major blocks, connections
between blocks and signal flow direction.

Principles of design strategies such as hierarchy, regularity, modularity and locality coupled with
constraints of area, speed and power dissipation are considered. These considerations further determine
detail implementations of each functional block. Each functional block would be designed, tested and
simulated.

The design would be modeled and coded in VHDL and simulated for proper functionality and timing. The
simulation results, design diagrams and VHDL codes would be included.

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2 GENERAL REQUIREMENTS
The requirement is to design a Multiplier-Accumulator circuit. 10 pairs of operands have to be multiplied
and added.

The MAC receives operands Ai and Bi, each an 8 bit unsigned binary number. The output results C, is the
summation of these results. Each pair of operand A & B are loaded in parallel in the RA & RB registers
the beginning of each multiplication cycle. Each multiplication cycle starts with a BEGIN signal and ends
with an END signal. The result of each multiplication is added to the previously accumulated data in the
RC register. The start of each multiply-accumulate cycle is indicated with a START signal.

The overall architecture is shown in Figure 2-1.

Figure 2-1: MAC Block Diagram

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3 DESIGN SPECIFICATIONS
The MAC would be designed for high speed and good regularity. To improve speed operation with good
regularity, a Carry Select Adder would be used in all addition processes. An 8-by-8-bit Shift/Add
multiplier designed by Giovanni D’Aliesio would be used with a slight modification of addition operation
to improve speed. The process of addition and accumulation are integrated into an add-accumulate unit.
A detailed block diagram is shown in Figure 3-1.

Figure 3-1: MAC Design Block Diagram

3.1 Controller Design

The MAC controller has four inputs and five outputs. The RESET input signal is an asynchronous master
reset; it resets all registers, multiplier unit and add-accumulator unit. The START input signal starts
multiply-accumulate cycle. The END_MULT input signal indicates an end of each multiplication cycle.

The LOAD_cmd output signal commands Register A and Register B to load operands. The begin output
signal commands the multiplier to begin multiplication operation. The ADD_cmd output signal commands
the add-accumulator unit to add and accumulate result of multiplication. The FINISH_cmd output signal is
used for a test purpose only telling stimuli of testbench to send a next pair of operands. It also indicates that
each multiply-accumulate cycle is done.

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3.1.1 Design

A finite state machine (FSM) of the controller is shown in Figure 3-2. An active START signal transitions
the state from IDLE state to INITIALIZATION state; at initialization state, a RESET command is generated
to reset all the functional units and the registers. After one clock cycle, the FSM goes to LOAD state
whereby it commands the input registers to load a pair of operands. Then the FSM goes to RUN state to
start multiplication process. After one clock cycle, the FSM goes to TEST state, and it waits for the
multiplier unit to complete its multiplication process.

Once complete, the FSM receives an active END_MULT signal from the multiplier unit, and it transitions
to ADD state. At the ADD state, the controller commands the add-accumulator unit to add and accumulate
result of multiplication. It also decrements an counter which keeps track the number of pair of operands
being cycled; there are 10 pair of operands to be cycled. If the number of pair of operands is not equal to
10, then the FSM goes to LOAD state to load the next pair of operands, else it goes to IDLE state waiting
for the next 10 pairs of operands.

Figure 3-2: Controller FSM Diagram

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3.1.2 Simulation and Timing

Figure 3-3 shows the simulation and timing result of the MAC controller. The active RESET signal puts
the controller in IDLE state and temporary counter (TEMP_COUNT) at 1001. Temporary counter keeps
track the number of operand pairs loaded into MAC. The simulation shows that the state changes from
IDLE to INIT state at 50 ns after a START signal goes high/active; the transition happens on the rising clock
edge. During LOAD state, the controller activates a LOAD_MULT_cmd signal to the input registers
(register A and register B) to accept a pair of operands.

Once the operands loaded into the multiplier, the controller commands the multiplier to begin
multiplication process by activating BEGIN_MULT_cmd signal. When the multiplier unit completes its
tasks, it generates a multiplication complete (END_MULT) signal to the controller. The simulation
indicates that when the controller receives the END_MULT signal, the controller commands the add-
accumulator unit to add and accumulate the multiplication result. The simulation also shows that the state
changes back to IDLE state when a reset signal is applied to the controller.

Figure 3-3: MAC Controller Simulation Timing Diagram

3.2 Multiplier Block Design

The Multiplier block is an 8-by-8-bit Shift/Add multiplier designed by Giovanni D’Aliesio with a
modification in the addition unit to improve speed. It is composed of a controller, a multiplicand unit, an
adder unit and a multiplier_result unit. The multiplier starts multiplication process when a START signal is
received. It generates a STOP signal when the multiplication process completes and data is ready at output
register (RC).

3.2.1 Design
The Shift/Add multiplier performs multiplication process using shift and add methods. A value of the
multiplicand is added and accumulated based upon the value of multiplier LSB bit. Multiplier is shifted
one bit to the right at each clock cycle, and its LSB value is tested. If the LSB value is 0, then it performs a
shift operation. If the LSB value is 0, then multiplicand is added to the accumulator and is shifted by one
bit to the right.
The multiplicand block is composed of 8 D flip-flop blocks, and it is loaded when the LOAD_cmd signal is
received from the controller. The multiplier/result block stores the accumulated output of the adder and the

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multiplier. It consists of a 17-bit shift register and a multiplexer to perform shift-right operation. The
addition section is replaced with an 8-bit Carry Select Adder to improve speed. The previous adder was a
Carry Propagate Adder. The 8-bit CPA has 8-delay unit of full-adder (FA), but the 8-bit CSA has only 5-
delay unit of full adder (FA). That is an improvement of 37.5% in speed.

Figure 3-4: Multiplier Design Block Diagram

3.2.2 Timing and Simulation

Figure 3-5 shows that each multiplication process starts with a START signal (start_tb). After a series of
adding and shifting operations, the correct result becomes available when the stop_tb signal goes high.

Figure 3-5: Multiplier Simulation Timing Diagram

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3.3 INPUT REGISTER BLOCK DESIGN

The input registers (register A and register B) are composed of 8 D flip-flop blocks. They load a pair of
operands into the input of multiplier when a LOAD_cmd signal is received from the controller. Figure 3-6
shows the design block diagram of one of the register.

Figure 3-6: Input Register Block Diagram

3.4 ADD ACCUMULATOR BLOCK DESIGN

The add-accumulate block performs additions and accumulations processes. It accepts multiplication result
from the multiplier adds the result and accumulates them. It consists of an inverter, two 20-bit registers,
and a 20-bit Carry Select Adder.

3.4.1 Design
The important aspect of the add-accumulate block is its ability to hold the accumulated value. Figure 3-7
shows that the operand fed to the input of the add-accumulator is a 16-bit value, and the output of the add-
accumulate is a 20-bit value.

The storing register is 20 bits wide to hold the maximum accumulated value. The maximum accumulated
value is determined by the number of pair of the operands and the width of the operands. On this project,
the add-accumulator receives 10 pairs of operands and (after multiplication process) each of them generates
a 16-bit wide value. The binary representation of 10 is 1010, so it is a 4-bit value. Since we are adding the
operand ten times, it means that we are basically multiplying the operand by ten. So we are multiplying a
16-bit value and a 4-bit value; the result would be 16+4 = 20 bits of storing register.

To accept a 16-bit value and convert it into a 20-bit value, the inputs of the upper 4 bits of the register are
connected to zeros.

To avoid a race problem between addition and accumulation processes, the two registers are triggered at
different clock edge. This ensures the addition process is completed before the result is being transferred to
the accumulation unit and fed back to input of the adder. An inverter is used for this technique.

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Figure 3-7: Add Accumulator Block Diagram

3.4.2 Timing and Simulation

The timing diagram for the Add_Accumulator simulation is shown in Figure 3-8. For this simulation, the
input operand (operand_in) is fed with a value of 2 when it receives a command to add (add_cmd). The
simulation shows that the add_accumulator accepts the value, adds it with previous value and store the new
value at RC. The accumulator (RC) gets the new value on the negative edge of the clock because on the
rising edge of the clock, the addition process takes place.

Figure 3-8: Add_Accumulator Simulation Timing Diagram

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3.5 Adder Design

Addition is one of the important designs on this project. To achieve a high-speed addition with good
regularity, a carry-select adder is selected for addition process in multiplier block and add-accumulator
block. A 20-bit carry-select adder would be discussed here.

3.5.1 Design
A carry-select adder has some 4-bit Ripple Carry Adders (Figure 3-9) and some multiplexers. A carry-
select adder can be divided into section of 4 bits (linear expansion), or it can be apportioned non-linearly to
maximize speed. For this project, a linear expansion carry-select adder is selected for better regularity.
Figure 3-10 displays the block diagram of a 20-Bit Carry-Select adder implemented for this project.

A regular 20-bit Carry Ripple Adder would have a delay of 20 ϑFull-Adder, a 20-bit carry-select adder
would require only 6ϑ Full-Adder. That is an improvement of 70% in speed with a penalty in the size of
area.

Figure 3-9: 4-Bit Ripple Carry Adder

Figure 3-10: 20-Bit Carry Select Adder Block Diagram

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3.5.2 Timing and Simulation

Addition of 20 bits operands is shown in Figure 3-11.

Figure 3-11: 20-Bit Carry Select Adder Simulation Timing Diagram

3.6 Multiplier Accumulator Design

3.6.1 Design
A complete Multiplier Accumulator consists of components described in the previous sections.
The associated VHDL source code is included in Appendix A: VHDL Source Code.

3.6.2 Testbench
Testbench provides inputs to the design unit and monitors any outputs. Figure 3-12 shows a structure of a
testbench and its design under test (D.U.T). All Testbench source code is included in Appendix B.

Figure 3-12: Testbench Simulation Block Diagram

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3.6.3 Timing and Simulation

To verify functionality of the design of the MAC, two test benches were written. One is to verify that the
MAC is multiplying and accumulating, and the other one is to verify the add-accumulator holds the
maximum possible accumulated value. Figure 3-13 shows the first testbench feeds the MAC with two
ascending-descending operands; one operand ascends from 0 to 9, and the other operand descends from
255 to 247. Figure 3-14 shows the second testbench feeds the MAC with two operands with the same value
ten times; each has a maximum value of FF16.

Figure 3-13: MAC Simulation Timing Diagram

Figure 3-14: MAC Simulation Timing Diagram (Maximum Accumulated Value)

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4 CONCLUSION

A complete design of an 8-by-8 unsigned Multiplier Accumulator was presented. The project aimed to
design a high speed MAC with good regularity; this was achieved by using Carry Select Adders on all
addition process. An Add/Shift Multiplier is selected because it generates a signal when it completes its
multiplication process; this feature is one of the design requirements. A complete design analysis of the
add/shift multiplier can be found on a paper written by Giovanni D’Aliesio. A 20-Bit Add Accumulator
was selected to handle maximum accumulated value for ten pairs of 8-bit operands.

All components were modeled with VHDL at structural level and RTL level. The VHDL source codes
were written and simulated on various UNIX-based and windows-based CAD tools such as ModelSim EE
5.4d and Synopsys VHDL System Simulator. More projects could be done to explore and extend the
power of MAC by accepting floating-point numbers, optimizing the control unit and increasing speed by
using Booth-Wallace Tree multiplier.

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APPENDIX A: VHDL CODES

CONTROLLER BLOCK
-----------------------------------------------------------------------
-- --------------
-- Purpose : CONTROLLER MAC
-- --------------
-- This file describes a VHDL behavioral model of a controller mac.
-- Controller_mac is a finite state machine that has the following
-- states:
-- IDLE > samples the START signal
-- INIT > commands all registers to be reset
-- LOAD > commands input registers to load operands
-- RUN > executes multiplication operation
-- TEST > checks for end of multiplication process
-- ADD > executes addition accumulation operation
--
-----------------------------------------------------------------------

-- Author : Jean Jewry Ramos

-- Date : March 2004
-- File Name: controller_mac.vhd

-----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity CONTROLLER_MAC is
port( reset : in std_logic;
clk : in std_logic;
START : in std_logic;
END_MULT : in std_logic;
FINISH_cmd : out std_logic;
RESET_cmd : out std_logic;
LOAD_MULT_cmd : out std_logic;
BEGIN_MULT_cmd: out std_logic;
ADD_cmd : out std_logic
);
end;

architecture RTL of CONTROLLER_MAC is

signal temp_count : std_logic_vector(3 downto 0);

type state_type is (IDLE, INIT, LOAD, RUN, TEST, ADD);

signal state : state_type;

begin

-----------------------------------------------------------------------
-- On the following process, when the reset signal activated, the
-- FSM goes to IDLE state and operand pair counter is set to 9. On
-- each leading edge clock transition, state's status is

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-- investigated.

-- When the state is in IDLE and START signal is activated, it goes

-- to INIT (initialization) state. It would stay in IDLE state if
-- START signal is not activated.

-- When state is in INIT state, an active RESET_cmd signal is

-- generated to reset all registers, and after one clock cycle, it
-- goes to LOAD state.

-- At the LOAD state, an active LOAD_MULT_cmd signal is generated

-- to load operands from input registers to multipliers. After one
-- clock cycle, it goes to RUN state.

-- At RUN state, BEGIN_MULT_cmd signal is activated to begin the

-- multiplying process. It goes to TEST state after one clock
-- cycle.

-- TEST state samples the END_MULT signal generated by multiplier.

-- When multipler finishes its multiplication process, END_MULT
-- signal goes high, and state machine moves to ADD state after one
-- clock cycle.

-- During ADD cycle, if operand pair counter is 0 then it goes to

-- IDLE state. Else, the counter is decremented by 1 and new pair
-- of operands is loaded to the multiplier by activating ADD_cmd.

-----------------------------------------------------------------------

process(clk,reset)
begin
if reset = '0' then
state <= IDLE;
temp_count <= "1001";

elsif (clk'event and clk='1') then

case state is
when IDLE =>
if START = '1' then
state <= INIT;
else
state <= IDLE;
end if;

when INIT =>

state <= LOAD;

when LOAD =>

state <= RUN;

when RUN =>

state <= TEST;

when TEST =>

if END_MULT = '0' then
state <= TEST;

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else
state <= ADD;
end if;

when ADD =>

if temp_count = "0000" then
temp_count <= "1001";
state <= IDLE;
else
temp_count <= temp_count - 1;
state <= LOAD;
end if;

end case;

end if;

end process;

FINISH_cmd <= '1' when state = IDLE else '0';

LOAD_MULT_cmd <= '1' when state = LOAD else '0';
BEGIN_MULT_cmd <= '1' when state = RUN else '0';
ADD_cmd <= '1' when state = ADD else '0';
RESET_cmd <= '0' when state = INIT or reset = '0' else '1';

end RTL;

configuration CFG_CONTROLLER_MAC of CONTROLLER_MAC is

for RTL
end for;
end CFG_CONTROLLER_MAC;

MULTIPLIER BLOCK
-----------------------------------------------------------------------

-- -------------------------
-- Purpose : EDGE TRIGGER D FLIP-FLOP
-- -------------------------
-- This file describes a VHDL structural model of a D Flip-Flop.
-- This component is part of an 8-bit register.

-----------------------------------------------------------------------

-- Author : Jean Jewry Ramos

-- Date : March 2004
-- File Name: DFF.vhd

-----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is

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port (
reset : in std_logic;
clk : in std_logic;
D : in std_logic;
Q : out std_logic

);
end DFF;

architecture BEHAV of DFF is

begin

process (clk,reset)
begin
if reset = '0' then
Q <= '0'; -- clear register
elsif (clk'event and clk='1') then
Q <= D; -- load Register
end if;
end process;

end BEHAV;

configuration CFG_DFF of DFF is

for BEHAV
end for;
end CFG_DFF;

-----------------------------------------------------------------------

-- --------------
-- Purpose : 8-BIT REGISTER
-- --------------
-- This file describes a VHDL structural model of an 8-bit register
-- This component is part of multiplier block.

-----------------------------------------------------------------------

-- Author : Jean Jewry Ramos

-- Date : March 2004
-- File Name: register8.vhd

-----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity REGISTER8 is
port (
reset : in std_logic;
A_in_reg : in std_logic_vector (7 downto 0);
LOAD_cmd : in std_logic;
RA : out std_logic_vector (7 downto 0)

);
end REGISTER8;

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architecture STRUCT of REGISTER8 is

component DFF
port (
reset : in std_logic;
clk : in std_logic;
D : in std_logic;
Q : out std_logic

);
end component;

begin

DFFS: for i in 7 downto 0 generate

DFFReg: DFF port map (reset, LOAD_cmd, A_in_reg(i), RA(i));
end generate;

end STRUCT;

configuration CFG_REGISTER8 of REGISTER8 is

for STRUCT
end for;
end CFG_REGISTER8;

-----------------------------------------------------------------------

-- -------------------------
-- Purpose : 4-BIT RIPPLE CARRY ADDER
-- -------------------------
-- This file describes a VHDL structural model of a 4-bit Ripple
-- Carry Adder. This component is part of 4-bit Carry Select Adder.

-----------------------------------------------------------------------

-- Author : Jean Jewry Ramos

-- Date : March 2004
-- File Name: ripple_carry4.vhd

-----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity ripple_carry4 is
port (
e, f : in std_logic_vector(3 downto 0);
carry_in : in std_logic;
S : out std_logic_vector(3 downto 0);
carry_out: out std_logic

);
end ripple_carry4;

architecture ARC_ripple_carry4 of ripple_carry4 is

begin

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process (e, f, carry_in)

variable tempC : std_logic_vector(4 downto 0);
variable P : std_logic_vector(3 downto 0);
variable G : std_logic_vector(3 downto 0);
begin
tempC(0) := carry_in;
for i in 0 to 3 loop
P(i) := e(i) xor f(i);
G(i) := e(i) and f(i);

S(i) <= P(i) xor tempC(i);

tempC(i+1) := G(i) or (tempC(i) and P(i));
end loop;
carry_out <= tempC(4);
end process;

end ARC_ripple_carry4;

configuration CFG_ripple_carry4 of ripple_carry4 is

for ARC_ripple_carry4
end for;
end CFG_ripple_carry4;

-----------------------------------------------------------------------

-- -------------------------
-- Purpose : 4-BIT CARRY SELECT ADDER
-- -------------------------
-- This file describes a VHDL structural model of the 4-bit Carry
-- Select Adder. This component is part of 8-bit Carry Select Adder
-- and 20-bit Carry Select Adder.

-----------------------------------------------------------------------

-- Author : Jean Jewry Ramos

-- Date : March 2004
-- File Name: carry_select4.vhd

-----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity carry_select4 is
port (
c, d : in std_logic_vector(3 downto 0);
C_input : in std_logic;
Result : out std_logic_vector(3 downto 0);
C_output : out std_logic
);
end carry_select4;

architecture ARC_carry_select4 of carry_select4 is

component ripple_carry4
port (
e, f : in std_logic_vector(3 downto 0);

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carry_in : in std_logic;
S : out std_logic_vector(3 downto 0);
carry_out: out std_logic
);
end component;

For S0: ripple_carry4 Use entity work.ripple_carry4(ARC_ripple_carry4);

For S1: ripple_carry4 Use entity work.ripple_carry4(ARC_ripple_carry4);

signal SUM0, SUM1 : std_logic_vector(3 downto 0);

signal carry0, carry1 : std_logic;
signal zero, one : std_logic;

begin
zero<='0';
one<= '1';

S0: ripple_carry4 port map(e=>c, f=>d, carry_in=>zero, S=>SUM0,

carry_out=>carry0);
S1: ripple_carry4 port map(e=>c, f=>d, carry_in=>one, S=>SUM1,
carry_out=>carry1);

Result<=SUM0 when C_input='0' else

SUM1 when C_input='1' else
"ZZZZ";
C_output<= (C_input and carry1) or carry0;

end ARC_carry_select4;

configuration CFG_carry_select4 of carry_select4 is

for ARC_carry_select4
end for;
end CFG_carry_select4;

-----------------------------------------------------------------------

-- -------------------------
-- Purpose : 8-BIT CARRY SELECT ADDER
-- -------------------------
-- This file describes a VHDL structural model of the 8-bit Carry
-- Select Adder. This component is part of the multiplier block.

-----------------------------------------------------------------------

-- Author : Jean Jewry Ramos

-- Date : March 2004
-- File Name: carry_select8.vhd

-----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity carry_select8 is
port (
A, B : in std_logic_vector(7 downto 0);
C_in : in std_logic;

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SUM : out std_logic_vector(7 downto 0);

C_out : out std_logic
);
end carry_select8;

architecture ARC_carry_select8 of carry_select8 is

component carry_select4
port (
c, d : in std_logic_vector(3 downto 0);
C_input : in std_logic;
Result : out std_logic_vector(3 downto 0);
C_output : out std_logic
);
end component;

For S0: carry_select4 Use entity work.carry_select4(ARC_carry_select4);

For S1: carry_select4 Use entity work.carry_select4(ARC_carry_select4);

signal tempc1 : std_logic;

begin

S0: carry_select4 port map(c=>A(3 downto 0), d=>B(3 downto 0),

C_input=>C_in, Result=>SUM(3 downto 0), C_output=> tempc1);
S1: carry_select4 port map(c=>A(7 downto 4), d=>B(7 downto 4),
C_input=>tempc1, Result=>SUM(7 downto 4), C_output=> C_out);

end ARC_carry_select8;

configuration CFG_carry_select8 of carry_select8 is

for ARC_carry_select8
end for;
end CFG_carry_select8;

-----------------------------------------------------------------------

-- ----------
-- Purpose : CONTROLLER
-- ----------
-- This file describes a VHDL structural model of a controller.
-- This component is part of the 8-by-8-multiplier block.

-----------------------------------------------------------------------

-- Author : Jean Jewry Ramos

-- Date : March 2004
-- File Name: controller.vhd

-----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

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use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity CONTROLLER is
port (
reset : in std_logic;
clk : in std_logic;
START : in std_logic;
LSB : in std_logic;
ADD_cmd : out std_logic;
SHIFT_cmd : out std_logic;
LOAD_cmd : out std_logic;
STOP : out std_logic
);
end CONTROLLER;

architecture RTL of CONTROLLER is

signal temp_count : std_logic_vector(2 downto 0);

type state_type is (IDLE, INIT, TEST, ADD, SHIFT);

signal state : state_type;

begin

process(clk, reset)
begin
if reset='0' then
state <= IDLE;
temp_count <= "000";

elsif (clk'event and clk='1') then

case state is
when IDLE =>
if START = '1' then
state<=INIT;
else
state<=IDLE;
end if;
when INIT =>
state <= TEST;

when TEST =>

if LSB ='0' then
state <= SHIFT;
else
state <= ADD;
end if;

when ADD =>

state<= SHIFT;

when SHIFT =>

if temp_count = "111" then
temp_count <= "000";
state <= IDLE;

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8-by-8 Bit Multiply Accumulator
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else
temp_count <= temp_count + 1;
state <= TEST;
end if;
end case;
end if;
end process;

STOP <= '1' when state = IDLE else '0';

ADD_cmd <= '1' when state = ADD else '0';
SHIFT_cmd <= '1' when state = SHIFT else '0';
LOAD_cmd <= '1' when state = INIT else '0';

end RTL;

configuration CFG_CONTROLLER of CONTROLLER is

for RTL
end for;
end CFG_CONTROLLER;

-----------------------------------------------------------------------

-- ------------
-- Purpose : MULTIPLICAND
-- ------------
-- This file describes a VHDL structural model of Multiplicand
-- Block.
-- This component is part of the 8-by-8-multiplier block.

-----------------------------------------------------------------------

-- Author : Jean Jewry Ramos

-- Date : March 2004
-- File Name: multiplicand.vhd

-----------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity MULTIPLICAND is
port (
reset : in std_logic;
A_in : in std_logic_vector (7 downto 0);
LOAD_cmd : in std_logic;
RA : out std_logic_vector (7 downto 0)

);
end MULTIPLICAND;

architecture STRUCT of MULTIPLICAND is

component DFF
port (
reset : in std_logic;
clk : in std_logic;
D : in std_logic;

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8-by-8 Bit Multiply Accumulator
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Q : out std_logic

);
end component;

begin

DFFS: for i in 7 downto 0 generate

DFFReg: DFF port map (reset, LOAD_cmd, A_in(i), RA(i));
end generate;

end STRUCT;

configuration CFG_MULTIPLICAND of MULTIPLICAND is

for STRUCT
end for;
end CFG_MULTIPLICAND;

-----------------------------------------------------------------------
-- -----------------
-- Purpose : MULTIPLIER_RESULT
-- -----------------
-- This file describes a VHDL structural model of the
-- Multiplier_Result block. This component is part of the 8-by-8-
-- multiplier block.
-- This block performs shifting operation of the multiplication
-- process.
-----------------------------------------------------------------------

-- Author : Jean Jewry Ramos

-- Date : March 2004
-- File Name: multiplier_result.vhd

-----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity MULTIPLIER_RESULT is
port (
reset : in std_logic;
clk : in std_logic;
B_in : in std_logic_vector (7 downto 0);
LOAD_cmd : in std_logic;
SHIFT_cmd : in std_logic;
ADD_cmd : in std_logic;
Add_out : in std_logic_vector (7 downto 0);
C_out : in std_logic;
RC_MULT : out std_logic_vector (15 downto 0);
LSB : out std_logic;
RB : out std_logic_vector (7 downto 0)

);
end MULTIPLIER_RESULT;

architecture RTL of MULTIPLIER_RESULT is

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signal temp_register : std_logic_vector (16 downto 0);

signal temp_Add : std_logic;

begin

process (clk, reset)

begin
if reset = '0' then
temp_register <= (others =>'0'); -- initialize temp
register
temp_Add <= '0';
elsif (clk'event and clk = '1') then
if LOAD_cmd = '1' then
temp_register (16 downto 8) <= (others => '0');
temp_register (7 downto 0) <= B_in; -- Load
B_in into register
end if;

if ADD_cmd = '1' then

temp_Add <= '1';
end if;

if SHIFT_cmd = '1' then

if temp_ADD = '1' then
-- Store adder output while shifting register
right 1 bit
temp_Add <= '0';
temp_register <= '0' & C_out & Add_out &
temp_register (7 downto 1);

else
-- No Add Simply shift 1 bit
temp_register <= '0' & temp_register (16 downto
1);

end if;
end if;
end if;
end process;
RB <= temp_register(15 downto 8);
LSB <= temp_register(0);
RC_MULT <= temp_register(15 downto 0);

end RTL;

configuration CFG_MULTIPLIER_RESULT of MULTIPLIER_RESULT is

for RTL
end for;
end CFG_MULTIPLIER_RESULT;

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INPUT REGISTER BLOCK

-----------------------------------------------------------------------
-- -----------------
-- Purpose : 8-BIT REGISTER
-- -----------------
-- This file describes a VHDL structural model of the input Register
-- A and Register B. These registers load a pair of operands into
-- the MAC. These components are part of the MAC.
-----------------------------------------------------------------------

-- Author : Jean Jewry Ramos

-- Date : March 2004
-- File Name: register8.vhd

-----------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity REGISTER8 is
port (
reset : in std_logic;
A_in_reg : in std_logic_vector (7 downto 0);
LOAD_cmd : in std_logic;
RA : out std_logic_vector (7 downto 0)

);
end REGISTER8;

architecture STRUCT of REGISTER8 is

component DFF
port (
reset : in std_logic;
clk : in std_logic;
D : in std_logic;
Q : out std_logic

);
end component;

begin

DFFS: for i in 7 downto 0 generate

DFFReg: DFF port map (reset, LOAD_cmd, A_in_reg(i), RA(i));
end generate;

end STRUCT;

configuration CFG_REGISTER8 of REGISTER8 is

for STRUCT
end for;
end CFG_REGISTER8;

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ADD-ACCUMULATE BLOCK
-----------------------------------------------------------------------

-- ---------------
-- Purpose : 20-BIT REGISTER
-- ---------------
-- This file describes a VHDL structural model of a 20-bit Register.
-- It has asynchronous reset input signal, and it loads data from
-- A_in to RA when a LOAD_cmd signal is triggered.

-----------------------------------------------------------------------

-- Author : Jean Jewry Ramos

-- Date : March 2004
-- File Name: register20.vhd

-----------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity REGISTER20 is
port (
reset : in std_logic;
A_in : in std_logic_vector (19 downto 0);
LOAD_cmd : in std_logic;
RA : out std_logic_vector (19 downto 0)

);
end REGISTER20;

architecture STRUCT of REGISTER20 is

component DFF
port (
reset : in std_logic;
clk : in std_logic;
D : in std_logic;
Q : out std_logic

);
end component;

begin

DFFS: for i in 19 downto 0 generate

DFFReg: DFF port map (reset, LOAD_cmd, A_in(i), RA(i));
end generate;

end STRUCT;

configuration CFG_REGISTER20 of REGISTER20 is

for STRUCT
end for;

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8-by-8 Bit Multiply Accumulator
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end CFG_REGISTER20;

-----------------------------------------------------------------------

-- -------------------------
-- Purpose : 20-BIT CARRY SELECT ADDER
-- -------------------------
-- This file describes a VHDL structural model of a 20-bit Carry
-- Select Adder.

-----------------------------------------------------------------------

-- Author : Jean Jewry Ramos

-- Date : March 2004
-- File Name: carry_select20.vhd

-----------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity carry_select20 is
port (
A, B : in std_logic_vector(19 downto 0);
C_in : in std_logic;
SUM : out std_logic_vector(19 downto 0);
C_out : out std_logic
);
end carry_select20;

architecture ARC_carry_select20 of carry_select20 is

component carry_select4
port (
c, d : in std_logic_vector(3 downto 0);
C_input : in std_logic;
Result : out std_logic_vector(3 downto 0);
C_output : out std_logic
);
end component;

For S0: carry_select4 Use entity work.carry_select4(ARC_carry_select4);

For S1: carry_select4 Use entity work.carry_select4(ARC_carry_select4);
For S2: carry_select4 Use entity work.carry_select4(ARC_carry_select4);
For S3: carry_select4 Use entity work.carry_select4(ARC_carry_select4);
For S3: carry_select4 Use entity work.carry_select4(ARC_carry_select4);

signal tempc1, tempc2, tempc3, tempc4 : std_logic;

begin

S0: carry_select4 port map(c=>A(3 downto 0), d=>B(3 downto 0),

C_input=>C_in, Result=>SUM(3 downto 0), C_output=> tempc1);
S1: carry_select4 port map(c=>A(7 downto 4), d=>B(7 downto 4),
C_input=>tempc1, Result=>SUM(7 downto 4), C_output=> tempc2);

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Jean Jewry Ramos

S2: carry_select4 port map(c=>A(11 downto 8), d=>B(11 downto 8),

C_input=>tempc2, Result=>SUM(11 downto 8), C_output=> tempc3);
S3: carry_select4 port map(c=>A(15 downto 12), d=>B(15 downto 12),
C_input=>tempc3, Result=>SUM(15 downto 12), C_output=> tempc4);
S4: carry_select4 port map(c=>A(19 downto 16), d=>B(19 downto 16),
C_input=>tempc4, Result=>SUM(19 downto 16), C_output=> C_out);

end ARC_carry_select20;

configuration CFG_carry_select20 of carry_select20 is

for ARC_carry_select20
end for;
end CFG_carry_select20;

MULTIPLY ACCUMULATOR BLOCK

-----------------------------------------------------------------------
-- --------------------
-- Purpose : MULTIPLY ACCUMULATOR
-- --------------------
-- This file describes a VHDL structural model of a MAC.
-- This particular MAC consists of 2 8-Bit Input Registers, an 8-by-
-- 8 Add/Shift Multiplier, a MAC controller and a 20 Bit Add-
-- Accumulator.

-----------------------------------------------------------------------

-- Author : Jean Jewry Ramos

-- Date : March 2004
-- File Name: MAC.vhd

-----------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity MAC is
port (
OPA_in : in std_logic_vector (7 downto 0);
OPB_in : in std_logic_vector (7 downto 0);
clk : in std_logic;
reset : in std_logic;
START : in std_logic;
FINISH_cmd : out std_logic;
RC : out std_logic_vector(19 downto 0);
C_out : out std_logic;
STOP : out std_logic
);
end MAC;

use work.all;

architecture RTL of MAC is

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Jean Jewry Ramos

signal ROPA_in : std_logic_vector(7 downto 0);

signal ROPB_in : std_logic_vector(7 downto 0);
signal RA_in : std_logic_vector(7 downto 0);
signal RB_in : std_logic_vector(7 downto 0);
signal ROPERAND_in: std_logic_vector(15 downto 0);
signal RC_out : std_logic;
signal RLOAD_cmd : std_logic;
signal Rreset : std_logic; -- signal for internal reset
signal RSTART_BEG : std_logic;
signal RSTOP_END : std_logic;
signal RADD_cmd : std_logic;
signal RRC :std_logic_vector (19 downto 0);
-- signal RES : std_logic; -- signal for external reset

component REGISTER8
port (
reset : in std_logic;
A_in_reg : in std_logic_vector (7 downto 0);
LOAD_cmd : in std_logic;
RA : out std_logic_vector (7 downto 0)

);
end component;

component MULTIPLIER
port (
A_in : in std_logic_vector (7 downto 0);
B_in : in std_logic_vector (7 downto 0);
clk : in std_logic;
reset : in std_logic;
START : in std_logic;
RC_MULT : out std_logic_vector(15 downto 0);
STOP : out std_logic

);
end component;

component ADD_ACCUMULATOR
port (
OPERAND_in : in std_logic_vector (15 downto 0);
reset : in std_logic;
ADD_cmd: in std_logic;
C_out : out std_logic;
RC : out std_logic_vector (19 downto 0)

);
end component;

component CONTROLLER_MAC
port (
reset : in std_logic;
clk : in std_logic;
START : in std_logic;
END_MULT : in std_logic;

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Jean Jewry Ramos

FINISH_cmd : out std_logic;

RESET_cmd : out std_logic;
LOAD_MULT_cmd : out std_logic;
BEGIN_MULT_cmd: out std_logic;
ADD_cmd : out std_logic

);
end component;

begin

ROPA_in <= OPA_in;

ROPB_in <= OPB_in;
C_out <= RC_out;
RC <= RRC;
STOP <= RSTOP_END;

inst_register8_A: REGISTER8
port map (
reset => Rreset,
A_in_reg => ROPA_in,
LOAD_cmd => RLOAD_cmd,
RA => RA_in
);

inst_register8_B: REGISTER8
port map (
reset => Rreset,
A_in_reg => ROPB_in,
LOAD_cmd => RLOAD_cmd,
RA => RB_in

);
inst_MULTIPLIER: MULTIPLIER
port map (
A_in => RA_in,
B_in => RB_in,
clk => clk,
reset => Rreset,
START => RSTART_BEG,
RC_MULT => ROPERAND_in,
STOP => RSTOP_END
);

inst_ADD_ACCUMULATOR: ADD_ACCUMULATOR
port map (
OPERAND_in => ROPERAND_in,
reset => Rreset,
ADD_cmd => RADD_cmd,
C_out => RC_out,
RC => RRC
);

inst_CONTROLLER_MAC: CONTROLLER_MAC
port map (

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8-by-8 Bit Multiply Accumulator
Jean Jewry Ramos

reset => reset,

clk => clk,
START => START,
END_MULT => RSTOP_END,
FINISH_cmd => FINISH_cmd,
RESET_cmd => Rreset,
LOAD_MULT_cmd => RLOAD_cmd,
BEGIN_MULT_cmd => RSTART_BEG,
ADD_cmd => RADD_cmd

);

end RTL;

configuration CFG_MAC of MAC is

for RTL
end for;
end CFG_MAC;

TESTBENCH SOURCE FILES

-----------------------------------------------------------------------

-- ------------------------
-- Purpose : TESTBENCH CARRY_SELECT20
-- ------------------------
-- This file describes a VHDL model of a testbench for the 20-bit
-- carry select adder. A sample array is fed into DUT, and the
-- results of simulation would be compared with this sample array.
-- An error message would be generated if they do not match.

-----------------------------------------------------------------------

-- Author : Jean Jewry Ramos

-- Date : March 2004
-- File Name: testbench_carry_select20.vhd

-----------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity funct_test is
end funct_test;

architecture test_bench of funct_test is

type sample is record
A : std_logic_vector(19 downto 0);
B : std_logic_vector(19 downto 0);
C_in : std_logic;
SUM : std_logic_vector(19 downto 0);
C_out : std_logic;
end record;

type sample_array is array(natural range <>) of sample;

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constant test_data: sample_array :=

(
-- A B C_in SUM C_out
(x"00000", x"00000", '0' , x"00000", '0'),
(x"00001", x"00001", '0' , x"00002", '0'),
(x"00008", x"00002", '0' , x"0000A", '0'),
(x"FFFFE", x"00001", '0' , x"FFFFF", '0'),
(x"FFFFE", x"00002", '0' , x"00000", '1')

);

component carry_select20
port (
A, B : in std_logic_vector(19 downto 0);
C_in : in std_logic;
SUM : out std_logic_vector(19 downto 0);
C_out : out std_logic
);
end component;

signal A, B, SUM : std_logic_vector(19 downto 0);

signal C_in, C_out : std_logic;

begin
design: carry_select20 port map(A,B,C_in,SUM,C_out);
process
begin
for i in test_data'range loop
A <= test_data(i).A;
B <= test_data(i).B;
C_in <= test_data(i).C_in;
wait for 10 ns;
assert SUM = test_data(i).SUM
report "output SUM is wrong!"
severity error;
assert C_out = test_data(i).C_out
report "output C_out is wrong!"
severity error;
end loop;
wait;
end process;
end test_bench;

configuration CFG_funct_test_CS20 of funct_test is

for test_bench
end for;
end CFG_funct_test_CS20;

-----------------------------------------------------------------------

-- -------------------------
-- Purpose : TESTBENCH ADD_ACCUMULATOR
-- -------------------------
-- This file describes a VHDL model of a testbench for the add-

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8-by-8 Bit Multiply Accumulator
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-- accumulator unit. A sample array is fed into DUT, and the

-- results of simulation would be compared with this sample array.
-- An error message would be generated if they do not match.

-----------------------------------------------------------------------

-- Author : Jean Jewry Ramos

-- Date : March 2004
-- File Name: testbench_add_accumulator.vhd

-----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity FUNC_TEST_ADD_ACC is
end FUNC_TEST_ADD_ACC;

architecture test_bench of FUNC_TEST_ADD_ACC is

type sample is record
OPERAND_in : std_logic_vector (15 downto 0);
reset : std_logic;
ADD_cmd : std_logic;
C_out : std_logic;
RC : std_logic_vector (19 downto 0);

end record;

type sample_array is array(natural range <>) of sample;

constant test_data: sample_array :=

(
-- OPERAND_in reset ADD_cmd C_out RC
(x"0002",'0' , '0', '0', x"00000"),
(x"0002",'0' , '0', '0', x"00000"),
(x"0002",'1' , '1', '0', x"00000"),
(x"0002",'1' , '0', '0', x"00002"),
(x"0002",'1' , '1', '0',x"00002"),
(x"0002",'1' , '0', '0',x"00004"),
(x"0002",'1' , '1', '0',x"00004"),
(x"0002",'1' , '0', '0',x"00006"),
(x"0002",'1' , '1', '0',x"00006"),
(x"0002",'1' , '0', '0',x"00008"),
(x"0002",'1' , '1', '0',x"00008"),
(x"0002",'1' , '0', '0',x"0000A")

);

component ADD_ACCUMULATOR
port (
OPERAND_in : in std_logic_vector (15 downto 0);
reset : in std_logic;
ADD_cmd: in std_logic;
C_out : out std_logic;
RC : out std_logic_vector (19 downto 0)
);

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8-by-8 Bit Multiply Accumulator
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end component;

signal OPERAND_in : std_logic_vector (15 downto 0);

signal reset, ADD_cmd, C_out: std_logic;
signal RC : std_logic_vector(19 downto 0);

begin
design: ADD_ACCUMULATOR port map(OPERAND_in, reset, ADD_cmd,
C_out, RC);
process
begin
for i in test_data'range loop
OPERAND_in <= test_data(i).OPERAND_in;
reset <= test_data(i).reset;
ADD_cmd <= test_data(i).ADD_cmd;
wait for 10 ns;
assert C_out = test_data(i).C_out
report "output STOP is wrong!"
severity error;
assert RC = test_data(i).RC
report "output RC is wrong!"
severity error;

end loop;
wait;
end process;
end test_bench;

configuration CFG_FUNC_TEST_ADD_ACC of FUNC_TEST_ADD_ACC is

for test_bench
end for;
end CFG_FUNC_TEST_ADD_ACC;

-----------------------------------------------------------------------

-- --------------------
-- Purpose : TESTBENCH MULTIPLIER
-- --------------------
-- This file describes a VHDL model of a testbench for the
-- multiplier unit.

-----------------------------------------------------------------------

-- Author : Jean Jewry Ramos

-- Date : March 2004
-- File Name: TB_MULTIPLIER.vhd

-----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;

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8-by-8 Bit Multiply Accumulator
Jean Jewry Ramos

use std.textio.all;
use ieee.std_logic_textio.all;

entity TESTBENCH is
end TESTBENCH;

architecture BEHAVIORAL of TESTBENCH is

component MULTIPLIER
port (
A_in : in std_logic_vector (7 downto 0);
B_in : in std_logic_vector (7 downto 0);
clk : in std_logic;
reset : in std_logic;
START : in std_logic;
RC_MULT : out std_logic_vector(15 downto 0);
STOP : out std_logic
);
end component;

for inst_DUT: MULTIPLIER use entity work.MULTIPLIER(RTL);

signal A_in_TB, B_in_TB : std_logic_vector(7 downto 0);

signal clk_TB, reset_TB, START_TB: std_logic;
signal RC_TB : std_logic_vector(15 downto 0);
signal STOP_TB : std_logic;

begin

--instantiate the Device Under Test

inst_DUT : MULTIPLIER
port map (
A_in => A_in_TB,
B_in => B_in_TB,
clk => clk_TB,
reset => reset_TB,
RC_MULT => RC_TB,
START => START_TB,
STOP => STOP_TB);

-- generate clock stimulus

STIMULUS_CLK: process
variable j: integer;
begin
for i in 0 to 500 loop
clk_TB <= '0';
wait for 10 ns;
clk_TB <= '1';
wait for 10 ns;
end loop;
wait;
end process STIMULUS_CLK;

-- generate reset stimulus

STIMULUS_RST: process
begin
reset_TB <= '0';

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8-by-8 Bit Multiply Accumulator
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wait for 10 ns;

reset_TB <= '1';
wait;
end process STIMULUS_RST;

-- generate multiplication requests

STIMULUS_START: process

file logFile : text is out "bus_log.txt"; -- set output file name.

variable L : line;
variable A_temp, B_temp, i : integer;

begin

write(L, string'("A B Result")); --include heading

writeline(logFile,L);
A_temp := 0;
B_temp := 20;
i := 1;

for i in 1 to 20 loop

A_in_TB <= STD_LOGIC_VECTOR(to_unsigned(A_temp,8));

B_in_TB <= STD_LOGIC_VECTOR(to_unsigned(B_temp,8));

START_TB <= '0';

wait for 100 ns;
START_TB <= '1';
wait for 100 ns;
START_TB <= '0';
wait until STOP_TB = '1'; --wait for the xer to finish
hwrite(L, A_in_TB); -- insert hex value of A in
file
write(L, string'(" "));
hwrite(L, B_in_TB); -- insert hex value of B in
file
write(L, string'(" "));
hwrite(L, RC_TB); -- insert hex value of result
in file
writeline(logFile,L);
A_temp := A_temp + 1;
B_temp := B_temp - 1;

end loop;
wait;

end process STIMULUS_START;

end BEHAVIORAL;

configuration CFG_FUNC_TEST_TB of TESTBENCH is

for BEHAVIORAL
end for;
end CFG_FUNC_TEST_TB;

-----------------------------------------------------------------------

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8-by-8 Bit Multiply Accumulator
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-- --------------
-- Purpose : TESTBENCH MAC1
-- --------------
-- This file describes a VHDL model of a testbench for the
-- MAC unit. This testbench verifies that the MAC could handle
-- the maximum accumulated value; The maximum value is 255 x 255 x
-- 10 = 650250 or 9EC0A (HEX)

-- This testbench feeds the input registers with 10 pairs of maximum

-- input values that is FF. The results are stored in a text file
-- called "bus_log_maximum_accumulation.txt".

-----------------------------------------------------------------------

-- Author : Jean Jewry Ramos

-- Date : March 2004
-- File Name: testbench_MAC1.vhd

-----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;

entity FUNC_TEST_MAC1 is
end FUNC_TEST_MAC1;

architecture test_bench of FUNC_TEST_MAC1 is

component MAC
port (
OPA_in : in std_logic_vector (7 downto 0);
OPB_in : in std_logic_vector (7 downto 0);
clk : in std_logic;
reset : in std_logic;
START : in std_logic;
FINISH_cmd : out std_logic;
RC : out std_logic_vector(19 downto 0);
C_out : out std_logic;
STOP : out std_logic

);
end component;

signal OPA_in_TB, OPB_in_TB : std_logic_vector (7 downto 0);

signal clk_TB, reset_TB, START_TB, FINISH_cmd_TB: std_logic;
signal RC_TB : std_logic_vector(19 downto 0);
signal C_out_TB, STOP_TB : std_logic;

begin

--instantiate DUT
inst_DUT: MAC
port map(
OPA_in => OPA_in_TB,

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OPB_in => OPB_in_TB,

clk => clk_TB,
reset => reset_TB,
START => START_TB,
FINISH_cmd => FINISH_cmd_TB,
RC => RC_TB,
C_out => C_out_TB,
STOP => STOP_TB
);
-- Generating CLK STIMULUS
STIMULUS_CLK: process
variable j: integer;
begin
for i in 0 to 500 loop
clk_TB <= '0';
wait for 10 ns;
clk_TB <= '1';
wait for 10 ns;
end loop;
wait;
end process STIMULUS_CLK;

--Generating RESET STIMULUS

STIMULUS_RST: process
begin
reset_TB <= '0';
wait for 20 ns;
reset_TB <= '1';
wait;
end process STIMULUS_RST;

--Generate multiply accumulate requests

STIMULUS_START : process

file logFile: text is out "bus_log_maximum_accumulation.txt";

variable L: line;
variable A_temp, B_temp, i : integer;

begin
write(L, string'("A B RESULT")); -- include heading in
file
writeline(logFile,L);
A_temp := 255;
B_temp := 255;

for i in 1 to 10 loop
OPA_in_TB <= STD_LOGIC_VECTOR(to_unsigned(A_temp,8));
OPB_in_TB <= STD_LOGIC_VECTOR(to_unsigned(B_temp,8));

START_TB <= '0';

wait for 100 ns;
START_TB <= '1';
wait for 30 ns;
START_TB <= '0';
wait until STOP_TB = '1';
hwrite(L, OPA_in_TB);
write(L, string'(" "));

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hwrite(L, OPB_in_TB);
write(L, string'(" "));
hwrite(L, RC_TB);
writeline(logFile,L);

end loop;
wait;
end process STIMULUS_START;

end test_bench;

configuration CFG_FUNC_TEST_MAC1 of FUNC_TEST_MAC1 is

for test_bench
end for;
end CFG_FUNC_TEST_MAC1;

-----------------------------------------------------------------------

-- --------------
-- Purpose : TESTBENCH MAC2
-- --------------
-- This file describes a VHDL model of a testbench for the
-- MAC unit. This testbench feeds the input registers with a pair
-- of ascending-descending operands.
-- The results are stored in a text file called "bus_log_
-- ascending_descending.txt".

-----------------------------------------------------------------------

-- Author : Jean Jewry Ramos

-- Date : March 2004
-- File Name: testbench_MAC2.vhd

-----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;

entity FUNC_TEST_MAC2 is
end FUNC_TEST_MAC2;

architecture test_bench of FUNC_TEST_MAC2 is

component MAC
port (
OPA_in : in std_logic_vector (7 downto 0);
OPB_in : in std_logic_vector (7 downto 0);
clk : in std_logic;
reset : in std_logic;
START : in std_logic;
FINISH_cmd : out std_logic;
RC : out std_logic_vector(19 downto 0);
C_out : out std_logic;
STOP : out std_logic

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Jean Jewry Ramos

);
end component;

signal OPA_in_TB, OPB_in_TB : std_logic_vector (7 downto 0);

signal clk_TB, reset_TB, START_TB, FINISH_cmd_TB: std_logic;
signal RC_TB : std_logic_vector(19 downto 0);
signal C_out_TB, STOP_TB : std_logic;

begin

--instantiate DUT
inst_DUT: MAC
port map(
OPA_in => OPA_in_TB,
OPB_in => OPB_in_TB,
clk => clk_TB,
reset => reset_TB,
START => START_TB,
FINISH_cmd => FINISH_cmd_TB,
RC => RC_TB,
C_out => C_out_TB,
STOP => STOP_TB
);
-- Generating CLK STIMULUS
STIMULUS_CLK: process
variable j: integer;
begin
for i in 0 to 10000 loop
clk_TB <= '0';
wait for 10 ns;
clk_TB <= '1';
wait for 10 ns;
end loop;
wait;
end process STIMULUS_CLK;

--Generating RESET STIMULUS

STIMULUS_RST: process
begin
reset_TB <= '0';
wait for 20 ns;
reset_TB <= '1';
wait;
end process STIMULUS_RST;

--Generate multiply accumulate requests

STIMULUS_START : process

file logFile: text is out "bus_log_ascending_descending.txt";

variable L: line;
variable A_temp, B_temp, i : integer;

begin
write(L, string'("A B RESULT")); -- include heading in
file
writeline(logFile,L);
A_temp := 0;

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B_temp := 255;

for i in 1 to 255 loop

OPA_in_TB <= STD_LOGIC_VECTOR(to_unsigned(A_temp,8));
OPB_in_TB <= STD_LOGIC_VECTOR(to_unsigned(B_temp,8));

START_TB <= '0';

wait for 100 ns;
START_TB <= '1';
wait for 30 ns;
START_TB <= '0';
wait until STOP_TB = '1';
hwrite(L, OPA_in_TB);
write(L, string'(" "));
hwrite(L, OPB_in_TB);
write(L, string'(" "));
hwrite(L, RC_TB);
writeline(logFile,L);
A_temp := A_temp + 1;
B_temp := B_temp - 1;

end loop;
wait;
end process STIMULUS_START;

end test_bench;

configuration CFG_FUNC_TEST_MAC2 of FUNC_TEST_MAC2 is

for test_bench
end for;
end CFG_FUNC_TEST_MAC2;

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APPENDIX B: SIMULATION RESULT FILES

Simulation output for:
“bus_log_maximum_accumulation.txt”

A B RESULT A B RESULT A B RESULT

FF FF 00000 FF FF 00000 FF FF 00000
FF FF 0FE01 FF FF 0FE01 FF FF 0FE01
FF FF 1FC02 FF FF 1FC02 FF FF 1FC02
FF FF 2FA03 FF FF 2FA03 FF FF 2FA03
FF FF 3F804 FF FF 3F804 FF FF 3F804
FF FF 4F605 FF FF 4F605 FF FF 4F605
FF FF 5F406 FF FF 5F406 FF FF 5F406
FF FF 6F207 FF FF 6F207 FF FF 6F207
FF FF 7F008 FF FF 7F008 FF FF 7F008
FF FF 8EE09 FF FF 8EE09 FF FF 8EE09
FF FF 00000

Simulation output for:

“bus_log_ascending_descending.txt”

A B RESULT A B RESULT A B RESULT

00 FF 00000 21 DE 0515E 42 BD 119EA
01 FE 00000 22 DD 06DFC 43 BC 14AA4
02 FD 000FE 23 DC 08B56 44 BB 17BD8
03 FC 002F8 24 DB 0A96A 45 BA 1AD84
04 FB 005EC 25 DA 0C836 46 B9 00000
05 FA 009D8 26 D9 0E7B8 47 B8 03296
06 F9 00EBA 27 D8 107EE 48 B7 0659E
07 F8 01490 28 D7 00000 49 B6 09916
08 F7 01B58 29 D6 02198 4A B5 0CCFC
09 F6 02310 2A D5 043DE 4B B4 1014E
0A F5 00000 2B D4 066D0 4C B3 1360A
0B F4 00992 2C D3 08A6C 4D B2 16B2E
0C F3 0140E 2D D2 0AEB0 4E B1 1A0B8
0D F2 01F72 2E D1 0D39A 4F B0 1D6A6
0E F1 02BBC 2F D0 0F928 50 AF 00000
0F F0 038EA 30 CF 11F58 51 AE 036B0
10 EF 046FA 31 CE 14628 52 AD 06DBE
11 EE 055EA 32 CD 00000 53 AC 0A528
12 ED 065B8 33 CC 0280A 54 AB 0DCEC
13 EC 07662 34 CB 050AE 55 AA 11508
14 EB 00000 35 CA 079EA 56 A9 14D7A
15 EA 0125C 36 C9 0A3BC 57 A8 18640
16 E9 0258E 37 C8 0CE22 58 A7 1BF58
17 E8 03994 38 C7 0F91A 59 A6 1F8C0
18 E7 04E6C 39 C6 124A2 5A A5 00000
19 E6 06414 3A C5 150B8 5B A4 03A02
1A E5 07A8A 3B C4 17D5A 5C A3 0744E
1B E4 091CC 3C C3 00000 5D A2 0AEE2
1C E3 0A9D8 3D C2 02DB4 5E A1 0E9BC
1D E2 0C2AC 3E C1 05BEE 5F A0 124DA
1E E1 00000 3F C0 08AAC 60 9F 1603A
1F E0 01A5E 40 BF 0B9EC 61 9E 19BDA
20 DF 0357E 41 BE 0E9AC 62 9D 1D7B8

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63 9C 213D2 9B 64 131BE D3 2C 024EA

64 9B 00000 9C 63 16E4A D4 2B 0492E
65 9A 03C8C 9D 62 1AA9E D5 2A 06CCA
66 99 0794E 9E 61 1E6B8 D6 29 08FBC
67 98 0B644 9F 60 22296 D7 28 0B202
68 97 0F36C A0 5F 00000 D8 27 0D39A
69 96 130C4 A1 5E 03B60 D9 26 0F482
6A 95 16E4A A2 5D 0767E DA 25 114B8
6B 94 1ABFC A3 5C 0B158 DB 24 1343A
6C 93 1E9D8 A4 5B 0EBEC DC 23 00000
6D 92 227DC A5 5A 12638 DD 22 01E14
6E 91 00000 A6 59 1603A DE 21 03B6E
6F 90 03E4E A7 58 199F0 DF 20 0580C
70 8F 07CBE A8 57 1D358 E0 1F 073EC
71 8E 0BB4E A9 56 20C70 E1 1E 08F0C
72 8D 0F9FC AA 55 00000 E2 1D 0A96A
73 8C 138C6 AB 54 03872 E3 1C 0C304
74 8B 177AA AC 53 0708E E4 1B 0DBD8
75 8A 1B6A6 AD 52 0A852 E5 1A 0F3E4
76 89 1F5B8 AE 51 0DFBC E6 19 00000
77 88 234DE AF 50 116CA E7 18 01676
78 87 00000 B0 4F 14D7A E8 17 02C1E
79 86 03F48 B1 4E 183CA E9 16 040F6
7A 85 07E9E B2 4D 1B9B8 EA 15 054FC
7B 84 0BE00 B3 4C 1EF42 EB 14 0682E
7C 83 0FD6C B4 4B 00000 EC 13 07A8A
7D 82 13CE0 B5 4A 034BC ED 12 08C0E
7E 81 17C5A B6 49 0690E EE 11 09CB8
7F 80 1BBD8 B7 48 09CF4 EF 10 0AC86
80 7F 1FB58 B8 47 0D06C F0 0F 00000
81 7E 23AD8 B9 46 10374 F1 0E 00E10
82 7D 00000 BA 45 1360A F2 0D 01B3E
83 7C 03F7A BB 44 1682C F3 0C 02788
84 7B 07EEE BC 43 199D8 F4 0B 032EC
85 7A 0BE5A BD 42 1CB0C F5 0A 03D68
86 79 0FDBC BE 41 00000 F6 09 046FA
87 78 13D12 BF 40 0303E F7 08 04FA0
88 77 17C5A C0 3F 05FFE F8 07 05758
89 76 1BB92 C1 3E 08F3E F9 06 05E20
8A 75 1FAB8 C2 3D 0BDFC FA 05 00000
8B 74 239CA C3 3C 0EC36 FB 04 004E2
8C 73 00000 C4 3B 119EA FC 03 008CE
8D 72 03EE4 C5 3A 14716 FD 02 00BC2
8E 71 07DAE C6 39 173B8 FE 01 00DBC
8F 70 0BC5C C7 38 19FCE
90 6F 0FAEC C8 37 00000
91 6E 1395C C9 36 02AF8
92 6D 177AA CA 35 0555E
93 6C 1B5D4 CB 34 07F30
94 6B 1F3D8 CC 33 0A86C
95 6A 231B4 CD 32 0D110
96 69 00000 CE 31 0F91A
97 68 03D86 CF 30 12088
98 67 07ADE D0 2F 14758
99 66 0B806 D1 2E 16D88
9A 65 0F4FC D2 2D 00000

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8-by-8 Bit Multiply Accumulator
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