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RSLTE058 - Timing advance-NPKU 0065

This document contains data on the distribution of user equipment (UE) distances from base stations across different cell sizes ranging from 2.1km to 100km. It includes metrics such as the average UE distance, percentage of UEs within certain distance ranges from the base station, and the expected cell size. The data is aggregated over a period from December 16th to 19th, 2019.

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Mardianto Chandra

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0% found this document useful (0 votes)

100 views70 pages

RSLTE058 - Timing advance-NPKU 0065

Uploaded by

Mardianto Chandra

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as XLSX, PDF, TXT or read online on Scribd

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Data

Period start time MRBTS/SBTS name LNBTS type

16.12.2019 MRBTS-NPKU_0065#NYOA#0#202065-Hotel Resty_HS-1MacroBTS

16.12.2019 MRBTS-NPKU_0065#NYOA#0#202065-Hotel Resty_HS-1MacroBTS
16.12.2019 MRBTS-NPKU_0065#SS PKU 1#2#200065-Hotel Resty MacroBTS
16.12.2019 MRBTS-NPKU_0065#SS PKU 1#2#200065-Hotel Resty MacroBTS
16.12.2019 MRBTS-NPKU_0065#SS PKU 1#2#200065-Hotel Resty MacroBTS
16.12.2019 MRBTS-NPKU_0065#SS PKU 1#2#200065-Hotel Resty MacroBTS
16.12.2019 MRBTS-NPKU_0065#SS PKU 1#2#200065-Hotel Resty MacroBTS
16.12.2019 MRBTS-NPKU_0065#SS PKU 1#2#200065-Hotel Resty MacroBTS

Page 1
Data

UE distance to base station

LNBTS name LNCEL name Cell size Avg UE dist 0-78m
LTE_1340A LTE_1339A LTE_1341A
202065 15 2.100 0.742 0.47
202065 25 2.100 0.736 0.64
SS-NPKU_0065-200065-Hotel Resty NPKUTM0065-1 2.100 0.479 0.79
SS-NPKU_0065-200065-Hotel Resty NPKUTM0065-1 2.100 0.928 0.30
SS-NPKU_0065-200065-Hotel Resty NPKUTM0065-1 2.100 0.862 0.07
SS-NPKU_0065-200065-Hotel Resty NPKUTM0065-2 2.100 0.473 0.67
SS-NPKU_0065-200065-Hotel Resty NPKUTM0065-2 2.100 0.929 0.25
SS-NPKU_0065-200065-Hotel Resty NPKUTM0065-2 2.100 0.864 0.07

Page 2
Data

UE distance distribution in 2.1km cells

78-156m 156-312m 312-468m 468-624m 624-780m 780-1092m 1092-1404m
LTE_1342A LTE_1343A LTE_1344A LTE_1345A LTE_1346A LTE_1347A LTE_1349A
1.33 9.19 7.35 22.67 18.80 31.99 3.80
1.36 9.44 9.13 23.78 19.49 27.72 3.10
0.65 6.66 47.12 29.62 12.59 1.83 0.51
0.30 3.96 20.67 23.00 11.31 17.34 3.28
0.07 1.41 5.14 7.88 20.50 56.41 3.37
0.56 9.97 44.78 30.97 9.44 2.37 0.75
0.38 5.24 25.73 18.57 7.90 16.41 4.03
0.11 1.88 6.10 8.53 21.13 51.75 3.87

Page 3
Data

UE distance distribution in 5k
1404-1794m 1794-2262m +2262m 0-0.5km 0.5-1.0km 1.0-1.5km 1.5-2.0km
LTE_1350A LTE_1351A LTE_1352A LTE_1353A LTE_1354A LTE_1355A LTE_1357A
1.84 0.38 2.20
1.89 0.45 3.00
0.12 0.02 0.07
1.74 11.23 6.87
2.50 0.88 1.75
0.31 0.04 0.15
1.98 10.34 9.17
3.33 1.18 2.05

Page 4
Data

UE distance distribution in 5km cells

2.0-2.7km 2.7-3.4km 3.4-4.1km 4.1-4.8km 4.8-5.6km +5.6km 0-1.0km 1.0-2.0km
LTE_1359A LTE_1360A LTE_1361A LTE_1362A LTE_1363A LTE_1364A LTE_1365A LTE_1366A

Page 5
Data

UE distance distribution in 10km cells

2.0-3.0km 3.0-4.0km 4.0-5.3km 5.3-6.9km 6.9-8.6km 8.6-9.5km 9.5-11.1km +11.1km
LTE_1367A LTE_1368A LTE_1369A LTE_1370A LTE_1371A LTE_1372A LTE_1373A LTE_1374A

Page 6
Data

UE distance distribution in 15km cells

0-1.5km 1.5-3.0km 3.0-4.5km 4.5-6.0km 6.0-8.0km 8.0-10.4km 10.4-12.9km
LTE_1375A LTE_1376A LTE_1377A LTE_1378A LTE_1379A LTE_1380A LTE_1381A

Page 7
Data

m cells UE distance distribution in 30km cel

12.9-14.6km 14.6-16.6km +16.6km 0-3.0km 3.0-6.0km 6.0-9.0km 9.0-12km
LTE_1382B LTE_1383A LTE_1384A LTE_1385A LTE_1386A LTE_1387A LTE_1388A

Page 8
Data

UE distance distribution in 30km cells UE distan

12-16km 16-21km 21-26km 26-33km +33km 0-6.0km 6.0-12km 12-15km
LTE_1389A LTE_1390A LTE_1391A LTE_1392A LTE_1393A LTE_1394A LTE_1395A LTE_1396A

Page 9
Data

UE distance distribution in 60km cells

15-18km 18-24km 24-32km 32-41km 41-52km 52-63km +63km 0-10km
LTE_1397A LTE_1398A LTE_1399A LTE_1400A LTE_1401A LTE_1402A LTE_1403A LTE_1404A

Page 10
Data

UE distance distribution in 100km cells

10-20km 20-30km 30-40km 40-53km 53-69km 69-87km 87-105km +105km
LTE_1405A LTE_1406A LTE_1407A LTE_1408A LTE_1409A LTE_1410A LTE_1411A LTE_1412A

Page 11
Data

Page 12
Documentation

Report Title RSLTE058 - Timing advance

NOP Report Release Version rslte_LTE18SP
RS Report Release Version 18.4.3-16
Report ID rslte_LTE18SP/reports/RSLTE058.xml
Report Description Timing advance
Start Time 16.12.2019 00:00:00
End Time 19.12.2019 00:00:00
Objects Level: RSLTE-VLOFLNBTSPARENT; NPKU_0065#NYOA#0#202065-Hotel R
Object Aggregation Level PLMN/LNBTS_parent/LNBTS/LNCEL
Time Aggregation Level whole_period
Threshold none
Data Source pmrPool
Advanced Filter none

KPI ID KPI Alias KPI Title

LTE_1340a Cell size Expected ce
LTE_1339a Avg UE dist Average UE
LTE_1341a 0-78m % UEs with
LTE_1342a 78-156m % UEs with
LTE_1343a 156-312m % UEs with
LTE_1344a 312-468m % UEs with
LTE_1345a 468-624m % UEs with
LTE_1346a 624-780m % UEs with
LTE_1347a 780-1092m % UEs with
LTE_1349a 1092-1404m % UEs with
LTE_1350a 1404-1794m % UEs with
LTE_1351a 1794-2262m % UEs with
LTE_1352a +2262m % UEs with
LTE_1353a 0-0.5km % UEs with
LTE_1354a 0.5-1.0km % UEs with
LTE_1355a 1.0-1.5km % UEs with
LTE_1357a 1.5-2.0km % UEs with
LTE_1359a 2.0-2.7km % UEs with
LTE_1360a 2.7-3.4km % UEs with
LTE_1361a 3.4-4.1km % UEs with d
LTE_1362a 4.1-4.8km % UEs with d
LTE_1363a 4.8-5.6km % UEs with d
LTE_1364a +5.6km % UEs with
LTE_1365a 0-1.0km % UEs with
LTE_1366a 1.0-2.0km % UEs with
LTE_1367a 2.0-3.0km % UEs with
LTE_1368a 3.0-4.0km % UEs with
LTE_1369a 4.0-5.3km % UEs with
LTE_1370a 5.3-6.9km % UEs with
LTE_1371a 6.9-8.6km % UEs with
LTE_1372a 8.6-9.5km % UEs with
LTE_1373a 9.5-11.1km % UEs with
LTE_1374a +11.1km % UEs with

Page 13
Documentation

LTE_1375a 0-1.5km % UEs with

LTE_1376a 1.5-3.0km % UEs with
LTE_1377a 3.0-4.5km % UEs with
LTE_1378a 4.5-6.0km % UEs with
LTE_1379a 6.0-8.0km % UEs with
LTE_1380a 8.0-10.4km % UEs with
LTE_1381a 10.4-12.9km % UEs with
LTE_1382b 12.9-14.6km % UEs with
LTE_1383a 14.6-16.6km % UEs with
LTE_1384a +16.6km % UEs with
LTE_1385a 0-3.0km % UEs with
LTE_1386a 3.0-6.0km % UEs with
LTE_1387a 6.0-9.0km % UEs with
LTE_1388a 9.0-12km % UEs with
LTE_1389a 12-16km % UEs with
LTE_1390a 16-21km % UEs with
LTE_1391a 21-26km % UEs with
LTE_1392a 26-33km % UEs with
LTE_1393a +33km % UEs with
LTE_1394a 0-6.0km % UEs with
LTE_1395a 6.0-12km % UEs with
LTE_1396a 12-15km % UEs with
LTE_1397a 15-18km % UEs with
LTE_1398a 18-24km % UEs with
LTE_1399a 24-32km % UEs with
LTE_1400a 32-41km % UEs with
LTE_1401a 41-52km % UEs with
LTE_1402a 52-63km % UEs with
LTE_1403a +63km % UEs with
LTE_1404a 0-10km % UEs with
LTE_1405a 10-20km % UEs with
LTE_1406a 20-30km % UEs with
LTE_1407a 30-40km % UEs with
LTE_1408a 40-53km % UEs with
LTE_1409a 53-69km % UEs with
LTE_1410a 69-87km % UEs with
LTE_1411a 87-105km % UEs with
LTE_1412a +105km % UEs with

Page 14
Documentation

065#NYOA#0#202065-Hotel Resty_HS-1 ('209290774'), NPKU_0065#SS PKU 1#2#200065-Hotel Resty ('106583')

KPI FormulUnit
decode(lmac[km]
lmac_ext.ue[km]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]
100*decode([%]

Page 15
Documentation

100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]
100*decode(
[%]

Page 16
Documentation

y ('106583')

Page 17
Report Execution

Cache handler com.nokia.oss.qengine.support.CacheAwareEngine

Evaluation method tmp tables(1)
Init duration 0.14
Sql generation 0.064
Execution duration 12.388
Load from cache none
Create tmp Tables 11.534
Drop tmp Tables none
Load data db none
Load data and write to cache none

Start Time End Time

2019-12-19 11:32:34.692 2019-12-19 11:32:35.140

2019-12-19 11:32:35.140 2019-12-19 11:32:36.213

Page 18
Report Execution

2019-12-19 11:32:36.214 2019-12-19 11:32:46.195

Page 19
Report Execution

2019-12-19 11:32:46.196 2019-12-19 11:32:46.226

2019-12-19 11:32:46.226 2019-12-19 11:32:47.80

Page 20
Report Execution

Note Sql
executing sql extra step
create global temporary table jf_topo_vloflncel_1978718685 on commit preserve rows as
SELECT
"plmn".co_gid plmn_gid,
"vloflnbtsparent".co_gid vloflnbtsparent_gid,
"vloflnbtsparent".co_mr_gid vloflnbtsparent_mr_gid,
"lnbts".co_gid lnbts_gid,
"lnbts".co_mr_gid lnbts_mr_gid,
decode(substr(bts_type.co_sys_version,1,3),'FLF','FlexiZoneMicroBTS','TLF','FlexiZoneMicroBTS','FL
"lncel".co_gid lncel_gid,
"lncel".co_mr_gid lncel_mr_gid
FROM
utp_common_objects "plmn",
utp_common_objects "vloflnbtsparent",
utp_common_objects "lnbts",
ctp_common_objects bts_type,
utp_common_objects "lncel"
WHERE
"plmn".co_oc_id = 16
AND "vloflnbtsparent".co_parent_gid = "plmn".co_gid
AND ( "vloflnbtsparent".co_oc_id = 3128 or "vloflnbtsparent".co_oc_id = 739 )
AND "lnbts".co_parent_gid = "vloflnbtsparent".co_gid
AND "lnbts".co_oc_id = 3129
AND "lncel".co_parent_gid = "lnbts".co_gid
AND "lncel".co_oc_id = 3130
AND "lnbts".co_gid = bts_type.co_gid(+)
creating tmp table: jf_LMAC2_1990088628
create global temporary table jf_LMAC2_1990088628 on commit preserve rows as
select
a.period_start_time,
a.lncel_gid,
SUM(TIMING_ADV_BIN_1) TIMING_ADV_BIN_1,
SUM(TIMING_ADV_BIN_2) TIMING_ADV_BIN_2,
SUM(TIMING_ADV_BIN_3) TIMING_ADV_BIN_3,
SUM(TIMING_ADV_BIN_4) TIMING_ADV_BIN_4,
SUM(TIMING_ADV_BIN_5) TIMING_ADV_BIN_5,

Page 21
Report Execution

SUM(TIMING_ADV_BIN_6) TIMING_ADV_BIN_6,
SUM(TIMING_ADV_BIN_7) TIMING_ADV_BIN_7,
SUM(TIMING_ADV_BIN_8) TIMING_ADV_BIN_8,
SUM(TIMING_ADV_BIN_9) TIMING_ADV_BIN_9,
SUM(TIMING_ADV_BIN_10) TIMING_ADV_BIN_10,
SUM(TIMING_ADV_BIN_11) TIMING_ADV_BIN_11,
SUM(TIMING_ADV_BIN_12) TIMING_ADV_BIN_12,
SUM(TIMING_ADV_BIN_13) TIMING_ADV_BIN_13,
SUM(TIMING_ADV_BIN_14) TIMING_ADV_BIN_14,
SUM(TIMING_ADV_BIN_15) TIMING_ADV_BIN_15,
SUM(TIMING_ADV_BIN_16) TIMING_ADV_BIN_16,
SUM(TIMING_ADV_BIN_17) TIMING_ADV_BIN_17,
SUM(TIMING_ADV_BIN_18) TIMING_ADV_BIN_18,
SUM(TIMING_ADV_BIN_19) TIMING_ADV_BIN_19,
SUM(TIMING_ADV_BIN_20) TIMING_ADV_BIN_20,
SUM(TIMING_ADV_BIN_21) TIMING_ADV_BIN_21,
SUM(TIMING_ADV_BIN_22) TIMING_ADV_BIN_22,
SUM(TIMING_ADV_BIN_23) TIMING_ADV_BIN_23,
SUM(TIMING_ADV_BIN_24) TIMING_ADV_BIN_24,
SUM(TIMING_ADV_BIN_25) TIMING_ADV_BIN_25,
SUM(TIMING_ADV_BIN_26) TIMING_ADV_BIN_26,
SUM(TIMING_ADV_BIN_27) TIMING_ADV_BIN_27,
SUM(TIMING_ADV_BIN_28) TIMING_ADV_BIN_28,
SUM(TIMING_ADV_BIN_29) TIMING_ADV_BIN_29,
SUM(TIMING_ADV_BIN_30) TIMING_ADV_BIN_30
from
(
select
to_date('2019/12/16 00:00:00', 'yyyy/mm/dd hh24:mi:ss') period_start_time,
t.vloflnbtsparent_gid vloflnbtsparent_gid,
t.lnbts_type LNBTS_type,
t.lnbts_gid lnbts_gid,
t.lncel_gid lncel_gid,
SUM(TIMING_ADV_BIN_1) TIMING_ADV_BIN_1,
SUM(TIMING_ADV_BIN_2) TIMING_ADV_BIN_2,
SUM(TIMING_ADV_BIN_3) TIMING_ADV_BIN_3,
SUM(TIMING_ADV_BIN_4) TIMING_ADV_BIN_4,
SUM(TIMING_ADV_BIN_5) TIMING_ADV_BIN_5,
SUM(TIMING_ADV_BIN_6) TIMING_ADV_BIN_6,
SUM(TIMING_ADV_BIN_7) TIMING_ADV_BIN_7,
SUM(TIMING_ADV_BIN_8) TIMING_ADV_BIN_8,
SUM(TIMING_ADV_BIN_9) TIMING_ADV_BIN_9,
SUM(TIMING_ADV_BIN_10) TIMING_ADV_BIN_10,
SUM(TIMING_ADV_BIN_11) TIMING_ADV_BIN_11,
SUM(TIMING_ADV_BIN_12) TIMING_ADV_BIN_12,
SUM(TIMING_ADV_BIN_13) TIMING_ADV_BIN_13,
SUM(TIMING_ADV_BIN_14) TIMING_ADV_BIN_14,
SUM(TIMING_ADV_BIN_15) TIMING_ADV_BIN_15,
SUM(TIMING_ADV_BIN_16) TIMING_ADV_BIN_16,
SUM(TIMING_ADV_BIN_17) TIMING_ADV_BIN_17,

Page 22
Report Execution

SUM(TIMING_ADV_BIN_18) TIMING_ADV_BIN_18,
SUM(TIMING_ADV_BIN_19) TIMING_ADV_BIN_19,
SUM(TIMING_ADV_BIN_20) TIMING_ADV_BIN_20,
SUM(TIMING_ADV_BIN_21) TIMING_ADV_BIN_21,
SUM(TIMING_ADV_BIN_22) TIMING_ADV_BIN_22,
SUM(TIMING_ADV_BIN_23) TIMING_ADV_BIN_23,
SUM(TIMING_ADV_BIN_24) TIMING_ADV_BIN_24,
SUM(TIMING_ADV_BIN_25) TIMING_ADV_BIN_25,
SUM(TIMING_ADV_BIN_26) TIMING_ADV_BIN_26,
SUM(TIMING_ADV_BIN_27) TIMING_ADV_BIN_27,
SUM(TIMING_ADV_BIN_28) TIMING_ADV_BIN_28,
SUM(TIMING_ADV_BIN_29) TIMING_ADV_BIN_29,
SUM(TIMING_ADV_BIN_30) TIMING_ADV_BIN_30
from

jf_topo_vloflncel_1978718685 t,
noklte_ps_lmac_lncel_day p
where
t.vloflnbtsparent_gid in ( '209290774','106583' )
and period_start_time >= to_date('2019/12/16 00:00:00', 'yyyy/mm/dd hh24:mi:ss')
and period_start_time < to_date('2019/12/19 00:00:00', 'yyyy/mm/dd hh24:mi:ss')
and t.lncel_gid = p.lncel_id
group by
to_date('2019/12/16 00:00:00', 'yyyy/mm/dd hh24:mi:ss'),
t.vloflnbtsparent_gid,
t.lnbts_type,
t.lnbts_gid,
t.lncel_gid
)a
group by
a.period_start_time,
a.lncel_gid
creating tmp table: jf_LMAC_ext_1984644516
create global temporary table jf_LMAC_ext_1984644516 on commit preserve rows as
select
to_date('2019/12/16 00:00:00', 'yyyy/mm/dd hh24:mi:ss') period_start_time,
t.lncel_gid lncel_gid,
AVG(TIMING_ADV_SET_INDEX) TIMING_ADV_SET_INDEX,
AVG(decode(TIMING_ADV_SET_INDEX ,1,2.1 ,2,5 ,3,10 ,4,15 ,5,30 ,6,60 ,7,100 ,NULL)) AVG_T
AVG(DECODE((TIMING_ADV_BIN_1+TIMING_ADV_BIN_2+TIMING_ADV_BIN_3+TIMING_ADV
from

jf_topo_vloflncel_1978718685 t,
NOKLTE_PR_LMAC_MNC1_RAW p
where
t.vloflnbtsparent_gid in ( '209290774','106583' )
and period_start_time >= to_date('2019/12/16 00:00:00', 'yyyy/mm/dd hh24:mi:ss')
and period_start_time < to_date('2019/12/19 00:00:00', 'yyyy/mm/dd hh24:mi:ss')
and t.lncel_gid = p.lncel_id
group by

Page 23
Report Execution

to_date('2019/12/16 00:00:00', 'yyyy/mm/dd hh24:mi:ss'),

t.lncel_gid
creating tmp table: jf_ALLTABLES_1937533516
create global temporary table jf_ALLTABLES_1937533516 on commit preserve rows as
select
period_start_time,
lncel_gid
from
(
(
select
period_start_time, TO_CHAR(lncel_gid) lncel_gid
from
jf_LMAC2_1990088628
)
UNION
(
select
period_start_time, TO_CHAR(lncel_gid) lncel_gid
from
jf_LMAC_ext_1984644516
)
)p
report from tmp tables
select
ALLTABLES.period_start_time period_start_time,
case "vloflnbtsparent".co_oc_id when 3128 then 'MRBTS-' when 739 then 'SBTS-' end || nvl("vlofln
decode(substr(bts_type.co_sys_version,1,3),'FLF','FlexiZoneMicroBTS','TLF','FlexiZoneMicroBTS',
nvl("lnbts".co_name, nvl("lnbts".co_object_instance, 'NN('||"lnbts".co_gid||')')) "LNBTS name",
nvl("lncel".co_name, nvl("lncel".co_object_instance, 'NN('||"lncel".co_gid||')')) "LNCEL name",
ALLTABLES.lncel_gid, nvl("lncel".co_ext_dn, "lncel".co_dn) "DN",
to_number(decode(lmac_ext.avg_tim_adv_index,2.1,2.1,5,5,10,10,15,15,30,30,60,60,100,100,NU
to_number(lmac_ext.ue_dist_avg) LTE_1339a,
to_number(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,1,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,2,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,2,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,2,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,2,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,2,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,2,decode( (lmac2.timing_adv_bin_1 + lma

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Report Execution

to_number(100*decode(lmac_ext.timing_adv_set_index,2,decode( (lmac2.timing_adv_bin_1 + lma

to_number(100*decode(lmac_ext.timing_adv_set_index,2,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,2,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,2,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,3,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,3,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,3,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,3,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,3,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,3,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,3,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,3,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,3,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,3,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,4,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,4,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,4,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,4,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,4,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,4,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,4,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,4,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,4,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,4,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,5,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,5,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,5,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,5,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,5,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,5,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,5,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,5,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,5,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,6,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,6,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,6,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,6,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,6,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,6,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,6,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,6,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,6,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,6,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,7,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,7,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,7,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,7,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,7,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,7,decode( (lmac2.timing_adv_bin_1 + lma
to_number(100*decode(lmac_ext.timing_adv_set_index,7,decode( (lmac2.timing_adv_bin_1 + lma

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Report Execution

to_number(100*decode(lmac_ext.timing_adv_set_index,7,decode( (lmac2.timing_adv_bin_1 + lma

to_number(100*decode(lmac_ext.timing_adv_set_index,7,decode( (lmac2.timing_adv_bin_1 + lma
from
utp_common_objects "vloflnbtsparent",
utp_common_objects "lnbts",
utp_common_objects "lncel",
ctp_common_objects bts_type
,
jf_ALLTABLES_1937533516 ALLTABLES,
jf_LMAC2_1990088628 LMAC2,
jf_LMAC_ext_1984644516 LMAC_ext
where
"lnbts".co_parent_gid = "vloflnbtsparent".co_gid and
"lncel".co_parent_gid = "lnbts".co_gid and
ALLTABLES.lncel_gid = "lncel".co_gid
and "lnbts".co_gid = bts_type.co_gid
and ALLTABLES.period_start_time = LMAC2.period_start_time (+) and ALLTABLES.lncel_gid = LM
and ALLTABLES.period_start_time = LMAC_ext.period_start_time (+) and ALLTABLES.lncel_gid =

order by
2,1,3,4,5

Page 26
Report Execution

FlexiZoneMicroBTS','FLC','FlexiZoneControllerBTS','TLC','FlexiZoneControllerBTS','MacroBTS') lnbts_type,

Page 27
Report Execution

,7,100 ,NULL)) AVG_TIM_ADV_INDEX,

V_BIN_3+TIMING_ADV_BIN_4+TIMING_ADV_BIN_5+TIMING_ADV_BIN_6+TIMING_ADV_BIN_7+TIMING_ADV_BIN_8+TIM

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Report Execution

SBTS-' end || nvl("vloflnbtsparent".co_name, nvl("vloflnbtsparent".co_object_instance, 'NN('||"vloflnbtsparent".co_gid||')')) "MRB

F','FlexiZoneMicroBTS','FLC','FlexiZoneControllerBTS','TLC','FlexiZoneControllerBTS','MacroBTS') "LNBTS type",
)) "LNBTS name",
)) "LNCEL name",

0,30,60,60,100,100,NULL)) LTE_1340a,

iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +

Page 29
Report Execution

iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +

iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +
iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +

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Report Execution

iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +

LTABLES.lncel_gid = LMAC2.lncel_gid (+)

ALLTABLES.lncel_gid = LMAC_ext.lncel_gid (+)

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Report Execution

MING_ADV_BIN_8+TIMING_ADV_BIN_9+TIMING_ADV_BIN_10+ TIMING_ADV_BIN_11+TIMING_ADV_BIN_12+TIMING_AD

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Report Execution

arent".co_gid||')')) "MRBTS/SBTS name",

ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin

Page 33
Report Execution

ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin

ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin
ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin

Page 34
Report Execution

ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin

Page 35
Report Execution

V_BIN_12+TIMING_ADV_BIN_13+TIMING_ADV_BIN_14+TIMING_ADV_BIN_15+TIMING_ADV_BIN_16+TIMING_ADV_BIN_

Page 36
Report Execution

+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing

Page 37
Report Execution

+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing

+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing
+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing

Page 38
Report Execution

+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing

Page 39
Report Execution

_16+TIMING_ADV_BIN_17+TIMING_ADV_BIN_18+TIMING_ADV_BIN_19+TIMING_ADV_BIN_20+ TIMING_ADV_BIN_21+TI

Page 40
Report Execution

_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma

Page 41
Report Execution

_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma

_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma
_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma

Page 42
Report Execution

_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma

Page 43
Report Execution

MING_ADV_BIN_21+TIMING_ADV_BIN_22+TIMING_ADV_BIN_23+TIMING_ADV_BIN_24+TIMING_ADV_BIN_25+TIMING_A

Page 44
Report Execution

ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin

Page 45
Report Execution

ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin

ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin
ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin

Page 46
Report Execution

ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin

Page 47
Report Execution

ADV_BIN_25+TIMING_ADV_BIN_26+TIMING_ADV_BIN_27+TIMING_ADV_BIN_28+TIMING_ADV_BIN_29+TIMING_ADV_BI

Page 48
Report Execution

+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing

Page 49
Report Execution

+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing

+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing
+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing

Page 50
Report Execution

+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing

Page 51
Report Execution

N_29+TIMING_ADV_BIN_30),0,NULL, (DECODE(TIMING_ADV_SET_INDEX, 1,(39TIMING_ADV_BIN_1+117TIMING_ADV

Page 52
Report Execution

v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm

Page 53
Report Execution

v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm

v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm
v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm

Page 54
Report Execution

v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm

Page 55
Report Execution

N_1+117*TIMING_ADV_BIN_2+195*TIMING_ADV_BIN_3+273*TIMING_ADV_BIN_4+351*TIMING_ADV_BIN_5+429*TIMING

Page 56
Report Execution

iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a

Page 57
Report Execution

iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a

iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a
iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a

Page 58
Report Execution

iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a

Page 59
Report Execution

DV_BIN_5+429*TIMING_ADV_BIN_6+507*TIMING_ADV_BIN_7+585*TIMING_ADV_BIN_8+663*TIMING_ADV_BIN_9+741*TI

Page 60
Report Execution

),0,null, (lmac2.timing_adv_bin_1) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.tim

),0,null, (lmac2.timing_adv_bin_2) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14) / (lmac
),0,null, (lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18) / (lmac
),0,null, (lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2
),0,null, (lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2
),0,null, (lmac2.timing_adv_bin_30) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_1) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_2) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.tim

Page 61
Report Execution

),0,null, (lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2

),0,null, (lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2
),0,null, (lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2
),0,null, (lmac2.timing_adv_bin_30) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_1) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_2) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.t
),0,null, (lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lmac2
),0,null, (lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2
),0,null, (lmac2.timing_adv_bin_30) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_1) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_2) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_bin_13) / (lmac2.timing_adv_bin_1 + lmac2
),0,null, (lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2
),0,null, (lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2
),0,null, (lmac2.timing_adv_bin_30) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_1) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_2) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14) / (lmac
),0,null, (lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2
),0,null, (lmac2.timing_adv_bin_30) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_1) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_2) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_3) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_4) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14) / (lmac
),0,null, (lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2
),0,null, (lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.t
),0,null, (lmac2.timing_adv_bin_1) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_2) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.tim
),0,null, (lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14) / (lmac

Page 62
Report Execution

),0,null, (lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2

),0,null, (lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.t

Page 63
Report Execution

G_ADV_BIN_9+741*TIMING_ADV_BIN_10+819*TIMING_ADV_BIN_11+897*TIMING_ADV_BIN_12+975*TIMING_ADV_BIN_

Page 64
Report Execution

_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...

_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
g_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bi...
ng_adv_bin_14) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv...
ng_adv_bin_18) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv...
ng_adv_bin_22 + lmac2.timing_adv_bin_23) / (lmac2.timing_adv_bin_1 + lmac2.timing_ad...
ng_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29) / (lmac2.timing_a...
g_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bi...
_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
g_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bi...

Page 65
Report Execution

ng_adv_bin_14 + lmac2.timing_adv_bin_15) / (lmac2.timing_adv_bin_1 + lmac2.timing_ad...

ng_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv...
ng_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29) / (lmac2.timing_a...
g_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bi...
_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
g_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bi...
ng_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_b...
ng_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv...
ng_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lmac2.timing_adv...
g_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bi...
_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
g_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bi...
ming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_...
ng_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv...
ng_adv_bin_28 + lmac2.timing_adv_bin_29) / (lmac2.timing_adv_bin_1 + lmac2.timing_ad...
g_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bi...
_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
g_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bi...
ng_adv_bin_14) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv...
ng_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv...
g_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bi...
_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
g_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bi...
ng_adv_bin_14) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv...
ng_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv...
ng_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_b...
_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...
_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin...
g_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bi...
ng_adv_bin_14) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv...

Page 66
Report Execution

ng_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv...

ng_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_b...

Page 67
Report Execution

975*TIMING_ADV_BIN_13+1053*TIMING_ADV_BIN_14+1131*TIMING_ADV_BIN_15+1209*TIMING_ADV_BIN_16+1287*TIM

Page 68
Report Execution

ADV_BIN_16+1287*TIMING_ADV_BIN_17+1365*TIMING_ADV_BIN_18+1443*TIMING_ADV_BIN_19+1521*TIMING_...

Page 69
Report Execution

+1521*TIMING_...

Page 70

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RSLTE058 - Timing advance-NPKU 0065

Uploaded by

RSLTE058 - Timing advance-NPKU 0065

Uploaded by

Data

Period start time MRBTS/SBTS name LNBTS type

16.12.2019 MRBTS-NPKU_0065#NYOA#0#202065-Hotel Resty_HS-1MacroBTS

UE distance to base station

UE distance distribution in 2.1km cells

UE distance distribution in 5km cells

UE distance distribution in 10km cells

UE distance distribution in 15km cells

m cells UE distance distribution in 30km cel

UE distance distribution in 30km cells UE distan

UE distance distribution in 60km cells

UE distance distribution in 100km cells

Report Title RSLTE058 - Timing advance

KPI ID KPI Alias KPI Title

LTE_1375a 0-1.5km % UEs with

065#NYOA#0#202065-Hotel Resty_HS-1 ('209290774'), NPKU_0065#SS PKU 1#2#200065-Hotel Resty ('106583')

Cache handler com.nokia.oss.qengine.support.CacheAwareEngine

Start Time End Time

2019-12-19 11:32:35.140 2019-12-19 11:32:36.213

2019-12-19 11:32:36.214 2019-12-19 11:32:46.195

2019-12-19 11:32:46.196 2019-12-19 11:32:46.226

2019-12-19 11:32:46.226 2019-12-19 11:32:47.80

to_date('2019/12/16 00:00:00', 'yyyy/mm/dd hh24:mi:ss'),

to_number(100*decode(lmac_ext.timing_adv_set_index,2,decode( (lmac2.timing_adv_bin_1 + lma

to_number(100*decode(lmac_ext.timing_adv_set_index,7,decode( (lmac2.timing_adv_bin_1 + lma

,7,100 ,NULL)) AVG_TIM_ADV_INDEX,

SBTS-' end || nvl("vloflnbtsparent".co_name, nvl("vloflnbtsparent".co_object_instance, 'NN('||"vloflnbtsparent".co_gid||')')) "MRB

iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +

iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +

iming_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 +

LTABLES.lncel_gid = LMAC2.lncel_gid (+)

arent".co_gid||')')) "MRBTS/SBTS name",

ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin

ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin

ac2.timing_adv_bin_5 + lmac2.timing_adv_bin_6 + lmac2.timing_adv_bin_7 + lmac2.timing_adv_bin_8 + lmac2.timing_adv_bin

+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing

+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing

+ lmac2.timing_adv_bin_9 + lmac2.timing_adv_bin_10 + lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing

_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma

_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma

_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lma

ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin

ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin

ming_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin

+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing

+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing

+ lmac2.timing_adv_bin_20 + lmac2.timing_adv_bin_21 + lmac2.timing_adv_bin_22 + lmac2.timing_adv_bin_23 + lmac2.timing

N_29+TIMING_ADV_BIN_30),0,NULL, (DECODE(TIMING_ADV_SET_INDEX, 1,(39*TIMING_ADV_BIN_1+117*TIMING_ADV

v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm

v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm

v_bin_23 + lmac2.timing_adv_bin_24 + lmac2.timing_adv_bin_25 + lmac2.timing_adv_bin_26 + lmac2.timing_adv_bin_27 + lm

iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a

iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a

iming_adv_bin_27 + lmac2.timing_adv_bin_28 + lmac2.timing_adv_bin_29 + lmac2.timing_adv_bin_30),0,null, (lmac2.timing_a

),0,null, (lmac2.timing_adv_bin_1) / (lmac2.timing_adv_bin_1 + lmac2.timing_adv_bin_2 + lmac2.timing_adv_bin_3 + lmac2.tim

),0,null, (lmac2.timing_adv_bin_11 + lmac2.timing_adv_bin_12 + lmac2.timing_adv_bin_13 + lmac2.timing_adv_bin_14 + lmac2

),0,null, (lmac2.timing_adv_bin_15 + lmac2.timing_adv_bin_16 + lmac2.timing_adv_bin_17 + lmac2.timing_adv_bin_18 + lmac2

_adv_bin_3 + lmac2.timing_adv_bin_4 + lmac2.timing_adv_bin_5 + lmac2.timing_adv_bin...

ng_adv_bin_14 + lmac2.timing_adv_bin_15) / (lmac2.timing_adv_bin_1 + lmac2.timing_ad...

ng_adv_bin_18 + lmac2.timing_adv_bin_19 + lmac2.timing_adv_bin_20 + lmac2.timing_adv...

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N_29+TIMING_ADV_BIN_30),0,NULL, (DECODE(TIMING_ADV_SET_INDEX, 1,(39TIMING_ADV_BIN_1+117TIMING_ADV