8 7 6 5 4 3 2 1

CK ENG
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD APPD
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
SCHEM,CORNHOLIO,K19 REV

?
ZONE

?
ECN

?
DESCRIPTION OF CHANGE

?
DATE

?
DATE

D
a.k.a. K19i 4/24/2009 - PVT - D
(.csa) Date (.csa) Date

Page
TABLE_TABLEOFCONTENTS_HEAD
Contents Sync Page
TABLE_TABLEOFCONTENTS_HEAD
Contents Sync
1 N/A 52 12/12/2008

TABLE_TABLEOFCONTENTS_ITEM
1 Table of Contents N/A
TABLE_TABLEOFCONTENTS_ITEM
43 K19i SMBus Connections WFERRY_K19I
2 N/A 53 02/05/2009

TABLE_TABLEOFCONTENTS_ITEM
2 System Block Diagram N/A
TABLE_TABLEOFCONTENTS_ITEM
44 VOLTAGE SENSING K24_MLB
3 03/13/2008 54 12/16/2008

TABLE_TABLEOFCONTENTS_ITEM
3 Power Block Diagram DRAGON
TABLE_TABLEOFCONTENTS_ITEM
45 Current Sensing WFERRY_K19I
4 N/A 55 02/05/2009

TABLE_TABLEOFCONTENTS_ITEM
4 BOM Configuration N/A
TABLE_TABLEOFCONTENTS_ITEM
46 Thermal Sensors K24_MLB
5 N/A 56 02/05/2009

TABLE_TABLEOFCONTENTS_ITEM
5 Revision History N/A
TABLE_TABLEOFCONTENTS_ITEM
47 Fan K24_MLB
7 N/A 57 02/05/2009

TABLE_TABLEOFCONTENTS_ITEM
6 Functional / ICT Test N/A
TABLE_TABLEOFCONTENTS_ITEM
48 WELLSPRING 1 K24_MLB
8 N/A 58 02/25/2009

TABLE_TABLEOFCONTENTS_ITEM
7 Power Aliases N/A
TABLE_TABLEOFCONTENTS_ITEM
49 WELLSPRING 2 K24_MLB
9 01/13/2009 59 02/05/2009

TABLE_TABLEOFCONTENTS_ITEM
8 Signal Aliases WFERRY_K19I
TABLE_TABLEOFCONTENTS_ITEM
50 Sudden Motion Sensor (SMS) K19_MLB
10 02/05/2009 60 03/25/2009

TABLE_TABLEOFCONTENTS_ITEM
9 CPU FSB K24_MLB
TABLE_TABLEOFCONTENTS_ITEM
51 DEBUG SENSORS AND ADC K19_MLB
11 02/05/2009 61 02/05/2009

TABLE_TABLEOFCONTENTS_ITEM
10 CPU Power & Ground K24_MLB
TABLE_TABLEOFCONTENTS_ITEM
52 SPI ROM K19_MLB
12 02/05/2009 62 03/17/2009

TABLE_TABLEOFCONTENTS_ITEM
11 CPU Decoupling K24_MLB
TABLE_TABLEOFCONTENTS_ITEM
53 AUDIO: CODEC/REGULATOR K19_MLB
13 02/05/2009 63 03/02/2009

TABLE_TABLEOFCONTENTS_ITEM
12 eXtended Debug Port(MiniXDP) K19_MLB
TABLE_TABLEOFCONTENTS_ITEM
54 AUDIO: LINE INPUT FILTER K19_MLB
14 02/05/2009 65 02/05/2009

TABLE_TABLEOFCONTENTS_ITEM
13 MCP CPU Interface T18_MLB
TABLE_TABLEOFCONTENTS_ITEM
55 AUDIO: HEADPHONE FILTER K19_MLB
15 02/05/2009 66 02/05/2009

TABLE_TABLEOFCONTENTS_ITEM
14 MCP Memory Interface T18_MLB
TABLE_TABLEOFCONTENTS_ITEM
56 AUDIO:SPEAKER AMP K19_MLB
16 02/05/2009 67 03/20/2009
15 MCP Memory Misc 57 AUDIO: JACKS
C TABLE_TABLEOFCONTENTS_ITEM

16
17
MCP PCIe Interfaces
T18_MLB

T18_MLB
02/05/2009
TABLE_TABLEOFCONTENTS_ITEM

58
68
AUDIO: JACK TRANSLATORS
CASEYHARDY_K19

K19_MLB
03/17/2009 C
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

18 02/05/2009 69 03/18/2009

TABLE_TABLEOFCONTENTS_ITEM
17 MCP Ethernet & Graphics T18_MLB
TABLE_TABLEOFCONTENTS_ITEM
59 DC-In & Battery Connectors K19_MLB
19 02/05/2009 70 03/18/2009

TABLE_TABLEOFCONTENTS_ITEM
18 MCP PCI & LPC T18_MLB
TABLE_TABLEOFCONTENTS_ITEM
60 PBus Supply & Battery Charger K19_MLB
20 02/05/2009 71 02/05/2009

TABLE_TABLEOFCONTENTS_ITEM
19 MCP SATA & USB T18_MLB
TABLE_TABLEOFCONTENTS_ITEM
61 IMVP6 CPU VCore Regulator K19_MLB
21 02/05/2009 72 01/13/2009

TABLE_TABLEOFCONTENTS_ITEM
20 MCP HDA & MISC T18_MLB
TABLE_TABLEOFCONTENTS_ITEM
62 5V / 3.3V Power Supply WFERRY_K19I
22 02/05/2009 73 02/04/2009

TABLE_TABLEOFCONTENTS_ITEM
21 MCP Power & Ground T18_MLB
TABLE_TABLEOFCONTENTS_ITEM
63 1.5V DDR3 Supply K19_MLB
25 02/05/2009 75 02/03/2009

TABLE_TABLEOFCONTENTS_ITEM
22 MCP Standard Decoupling T18_MLB
TABLE_TABLEOFCONTENTS_ITEM
64 MCP CORE REGULATOR K19_MLB
26 02/05/2009 76 (12/05/2008)

TABLE_TABLEOFCONTENTS_ITEM
23 MCP Graphics Support K19_MLB
TABLE_TABLEOFCONTENTS_ITEM
65 CPU VTT Power Supply (K19_MLB)
28 01/06/2009 77 02/25/2009

TABLE_TABLEOFCONTENTS_ITEM
24 SB Misc WFERRY_K19I
TABLE_TABLEOFCONTENTS_ITEM
66 MISC POWER SUPPLIES K24_MLB
29 02/05/2009 78 02/05/2009

TABLE_TABLEOFCONTENTS_ITEM
25 FSB/DDR3 Vref Margining K24_MLB
TABLE_TABLEOFCONTENTS_ITEM
67 POWER SEQUENCING K24_MLB
31 02/05/2009 79 03/12/2009

TABLE_TABLEOFCONTENTS_ITEM
26 DDR3 SO-DIMM Connector A K19_MLB
TABLE_TABLEOFCONTENTS_ITEM
68 POWER FETS K24_MLB
32 02/05/2009 90 02/05/2009

TABLE_TABLEOFCONTENTS_ITEM
27 DDR3 SO-DIMM Connector B K19_MLB
TABLE_TABLEOFCONTENTS_ITEM
69 LVDS Display Connector K19_MLB
33 02/05/2009 93 12/19/2008

TABLE_TABLEOFCONTENTS_ITEM
28 DDR3 Support T18_MLB
TABLE_TABLEOFCONTENTS_ITEM
70 DISPLAYPORT SUPPORT K24_MLB
34 03/04/2009 94 02/05/2009

TABLE_TABLEOFCONTENTS_ITEM
29 Right Clutch Connector K19_MLB
TABLE_TABLEOFCONTENTS_ITEM
71 DisplayPort Connector K19_MLB
35 03/23/2009 97 02/10/2009

TABLE_TABLEOFCONTENTS_ITEM
30 SECUREDIGITAL CARD READER K19_MLB
TABLE_TABLEOFCONTENTS_ITEM
72 LCD BACKLIGHT DRIVER K19_MLB
37 02/05/2009 98 03/16/2009

TABLE_TABLEOFCONTENTS_ITEM
31 Ethernet PHY (RTL8211CL) (K19I_MLB)
TABLE_TABLEOFCONTENTS_ITEM
73 LCD Backlight Support K24_MLB
38 02/05/2009 99 02/09/2009

TABLE_TABLEOFCONTENTS_ITEM
32 Ethernet & AirPort Support K19_MLB
TABLE_TABLEOFCONTENTS_ITEM
74 LCD Backlight Driver (MC34845) VEMURI_K19I
39 03/13/2009 100 02/05/2009
B TABLE_TABLEOFCONTENTS_ITEM
33
41
Ethernet Connector K19_MLB
02/05/2009
TABLE_TABLEOFCONTENTS_ITEM
75
101
CPU/FSB Constraints T18_MLB
02/05/2009
B
TABLE_TABLEOFCONTENTS_ITEM
34 FireWire LLC/PHY (FW643E) T18_MLB
TABLE_TABLEOFCONTENTS_ITEM
76 Memory Constraints T18_MLB
42 03/18/2009 102 02/05/2009

TABLE_TABLEOFCONTENTS_ITEM
35 FireWire Port Power K19_MLB
TABLE_TABLEOFCONTENTS_ITEM
77 MCP Constraints 1 T18_MLB
43 02/05/2009 103 02/05/2009

TABLE_TABLEOFCONTENTS_ITEM
36 FireWire Ports K19_MLB
TABLE_TABLEOFCONTENTS_ITEM
78 MCP Constraints 2 T18_MLB
45 03/23/2009 104 02/05/2009

TABLE_TABLEOFCONTENTS_ITEM
37 SATA Connectors K19_MLB
TABLE_TABLEOFCONTENTS_ITEM
79 Ethernet Constraints T18_MLB
46 02/05/2009 105 02/05/2009

TABLE_TABLEOFCONTENTS_ITEM
38 External USB Connectors K19_MLB
TABLE_TABLEOFCONTENTS_ITEM
80 FireWire Constraints T18_MLB
48 02/05/2009 106 02/05/2009

TABLE_TABLEOFCONTENTS_ITEM
39 Front Flex Support K19_MLB
TABLE_TABLEOFCONTENTS_ITEM
81 SMC Constraints T18_MLB
49 02/05/2009 108 01/08/2009

TABLE_TABLEOFCONTENTS_ITEM
40 SMC T18_MLB
TABLE_TABLEOFCONTENTS_ITEM
82 K19i Specific Constraints WFERRY_K19I
50 (11/25/2008) 109 12/12/2008

TABLE_TABLEOFCONTENTS_ITEM
41 SMC Support (K19_MLB)
TABLE_TABLEOFCONTENTS_ITEM
83 K19i PCB Rule Definitions WFERRY_K19I
51 02/05/2009

TABLE_TABLEOFCONTENTS_ITEM
42 LPC+SPI Debug Connector K19_MLB

Integration Issues to be Resolved DIMENSIONS ARE IN MILLIMETERS

JTAG_MCP_TDO JTAG_MCP_TDO METRIC APPLE INC.

ALIASES RESOLVED
IN OUT
MAKE_BASE=TRUE XX
IN XDP_TDO XDP_TDO OUT
A MAKE_BASE=TRUE
(Should rename J1300 nets now that JTAG level-shifter is gone)
X.XX
DRAFTER DESIGN CK NOTICE OF PROPRIETARY PROPERTY A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
X.XXX PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
ENG APPD MFG APPD
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
ANGLES II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
QA APPD DESIGNER TITLE

Schematic / PCB #’s DO NOT SCALE DRAWING

PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION

RELEASE SCALE SCHEM,CORNHOLIO,K19
NONE
051-7903 1 SCHEM,CORNHOLIO,K19 SCH CRITICAL
SIZE DRAWING NUMBER REV.
MATERIAL/FINISH
820-2533 1 PCBF,MLB IG,K19 PCB CRITICAL NOTED AS D 051-7903 A
THIRD ANGLE PROJECTION APPLICABLE SHT 1 OF 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
U1000

U1300
INTEL CPU
2.X OR 3.X GHZ XDP CONN
PG 12

PENRYN
PG 9

FSB

D 64-Bit
J6950
D
800/1067/1333 MHz

PG 13
DC/BATT POWER SUPPLY
J2900 PG 60

2 UDIMMs
MAIN
GPIOs FSB INTERFACE DDR2-800MHZ
MEMORY DDR3-1067/1333MHZ
DIMM
PG 14 U4900
PG 25,26

TEMP SENSOR
PG 41
Misc
CLK
PG 24
U6100
SYNTH POWER PGSENSE
45
SPI
J4510 Boot ROM J5650,5600,5610,5611,5660,5720,5730,5750

SATA SPI FAN CONN AND CONTROL

PG 52 PG 48,49
Conn 1.05V/3GHZ. PG 20
PG 38
HD
J4520 NVIDIA J4900
SATA B,0 BSB ADC Fan Ser
J5100
Conn 1.05V/3GHZ. SATA MCP79 SMC Prt LPC Conn
PG 38 PG 19 LPC Port80,serial
C ODD
PG 18
PG 41
PG 43 C
U1400

J9000

LVDS PWR

CONN LVDS OUT CTRL

PG 71 RGB OUT
J4720 J4700 J4710 J4710 J3900,4635,4655

J9400
DP OUT
Bluetooth TRACKPAD/ IR CAMERA EXTERNAL
KEYBOARD USB
HDMI OUT Connectors
DISPLAY PORT PG 40 PG 40 PG 40 PG 40
PG 39

(UP TO 12 DEVICES)
CONN
DVI OUT

0 1 2 3 4 5 6 7 8 9
PG 71 TMDS OUT

USB
PG 19
PG 17
UP TO 20 LANES3
PCI-E
PG 16

B B
SMB
PG 20 SMB
CONN
RGMII PCI HDA DIMM’s
PG 44
(UP TO FOUR PORTS)
PG 17
PG 18 PG 20

U6200
Audio
Codec
PG 53

U3700
U6301 U6400 U6500 U6600,6605,6610,6620 System Block Diagram
SYNC_MASTER=N/A SYNC_DATE=N/A
A GB
E-NET
Line In HEADPHONE Line Out Speaker
NOTICE OF PROPRIETARY PROPERTY
A
Amp Amp Amp Amps
88E1116
PG 54 PG 55 PG 56 PG 57 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PG 31 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
J3400 U3900 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
Mini PCI-E J6800,6801,6802,6803
E-NET Audio
AirPort SIZE DRAWING NUMBER REV.
Conn
PG 28
PG 33
Conns D 051-7903 A
PG 59
APPLE INC. SCALE SHT OF
NONE 2 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

M97 POWER SYSTEM ARCHITECTURE

D6905
02
PPVIN_G3H_P3V42G3H ENABLE
3.425V G3HOT PP3V42_G3H_REG 03 SMC PWRGD 04
D6905 PBUS_VSENSE LT3470 RN5VD30A-F
VOUT
U6990 U5000
D PPVBAT_G3H_CHGR_REG
7A FUSE
PPBUS_G3H
V Q5315 D
02
01 23
VIN
PPCPUVTT_S0_REG_R R5492 PPCPUVTT_S0
CPUVTTS0_EN EN_PSV VOUT
CHGR_EN (S0) (8A MAX CURRENT)
(S5)
CPUVTT
U7970 (1.05V)
6A FUSE ENABLES
AC DCIN(16.5V) TPS51117 MCP79
ADAPTER
IN
A VIN
VOUT
U5403 U7600
PWRBTN*
06-1

SMC_BATT_ISENSE PGOOD
PBUS SUPPLY/ 31

SMC_DCIN_ISENSE
BATTERY CHARGER A CPUVTTS0_PGOOD PLTRST* LPC_RESET_L
RSMRST*
ISL6258A SMC_CPU_VSENSE
U7000 01
CPU VCORE
U5480 V MCP_PS_PWRGD PS_PWRGD
29 CPUPWRGD(GPIO49)
CPU_PWRGD

J6950
02
VIN
VOUT A SMC_CPU_ISENSE PPVCORE_CPU_S0_REG
(44A MAX CURRENT)
26
U2850 CPU_RESET#
30

FSB_CPURST_L
ISL9504B
U1400
IMVP_VR_ON VR_ON
3S2P Q7050 28
BATT_POS_F PPVBAT_G3H_CHGR_OUT 25 PGOOD VR_PWRGOOD_DELAY
(9 TO 12.6V)
C U7400 06 P1V05S0_EN 1.05V SO PP1V05_S0_FET CPU C
FETS 22
CHGR_BGATE PPBUS_G3H 4.6V AUDIO PWRGOOD
(Q7951 TO Q7953) MAX8902A
VIN PP4V6_AUDIO_ANALOG
1.05V (S5) U6201
EN VOUT RESET*

06 TPS62510
PP1V05_S5_REG U1000
32
MCP79 11 11-1
P3V3S3_EN P1V05_S5_EN U7750 VOUT
RC
PM_SLP_S4_L DELAY 08
SMC 02
P16
15 VIN
SLP_S3# 11-3
U4900 04 P5VRTS0_EN_L EN1 5V VOUT1
PP5VRT_S0_REG PP5VRT_S0 17
(RT) (4A MAX CURRENT)
U1400 RC DDRREG_EN P60
SMC_PM_G2_EN
DELAY (S5) Q7800 05 PP3V3_S5_REG PP3V3_S5
P3V3S5_EN_L
VOUT2
(4A MAX CURRENT) 07
EN2 3.3V
PCI_RESET0#
Q7910
TPS51125
02 PP3V3_S3_FET
15-1 11-2 SMC_PM_G2_EN U7200 13
RC P5VLTS3_EN PGOOD1,2 VREG3
DELAY VIN
P3V3S3_EN
GOSHAWK6P P5V3V3_PGOOD

BKLT_EN
U9701 PPVOUT_S0_LCDBKLT
ENA VOUT SMC 10
B 24
RSMRST_OUT(P15) PM_RSMRST_L B
Q7930 ALL_SYS_PWRGD PWRGD(P12) 99ms DLY
18 IMVP_VR_ON
15 PP3V3_S0_FET IMVP_VR_ON(P16) 25
1.2V YUKON 09 RSMRST_PWRGD RSMRST_IN(P13)
Q3801
PM_SLP_S3_L U3850 (1.9V) PLT_RST*
VIN PPVOUT_ENET_AVDD_REG SMC_ONOFF_L
PM_ENET_EN_L ENETADD_EN VOUT1 PWR_BUTTON(P90)
16 RUN1 (0.8A MAX CURRENT) P3V3S0_EN PM_PWRBTN_L
05 P17(BTN_OUT)
P1V2ENET_EN LTC34074 Q3810
RUN2 PP1V2_ENET_REG SMC_RESET_L
VOUT2 P3V3_ENET_FET RST*
(0.8A MAX CURRENT)
P5V3V3_PGOOD
SLP_S5_L
Q3802 P3V3ENET_EN_L SLP_S5_L(P95)
MCPCORESO_PGOOD SLP_S4_L
WOL_EN SLP_S4_L(P94)
CPUVTTS0_PGOOD SLP_S3_L
SMC_ADAPTER_EN 04-1 P5V_LT_S3_PGOOD
SLP_S3_L(P93)
S3 TO S0 R5491 U4900
PP1V5_S0_FET PP1V5_S0 21 S0PGOOD_PWROK
FETS
02 (Q7901 & Q7971) 1.8V LDO
VIN TPS79918DRV PP1V8_S0_REG
19-1
=DDRREG_EN 1.5V PP1V5_S3_REG U7760
S5 VOUT1
(12A MAX CURRENT) RST*
PM_SLP_S3_L =DDTVTT_EN 14
S3 0.75V PP3V3_S0 V1 Power Block Diagram
VOUT2 PP0V75_S0_REG
PP1V5_S0
(1A MAX CURRENT) V2 SYNC_MASTER=DRAGON SYNC_DATE=03/13/2008
A RC
DELAY
P1V8S0_EN 16-3
P1V05S0_EN
16-2 TPS51116
U7300
PP1V05_S0 V3 LTC2909 NOTICE OF PROPRIETARY PROPERTY
A
(S0) 20
R5490 U7870 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
MCPDDR_EN PPVCORE_S0_MCP_REG_R PPVCORE_S0_MCP PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
RC 16-2 MCP_CORE AGREES TO THE FOLLOWING
DELAY 16-2 P3V3S0_EN MCPCORES0_EN VOUT2
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
EN2 (25A MAX CURRENT)
(S0) II NOT TO REPRODUCE OR COPY IT

RC CPUVTTS0_EN 16-2 P5VLTS3_EN 5V (LT) PP5VLT_S3_REG 12 PP5VLT_S3 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DELAY
16-3 PBUSVSENS_EN 11-2 EN1
VOUT1
SIZE DRAWING NUMBER REV.
(S0) (7A MAX CURRENT)
16-1 VIN
D 051-7903 A
RC MCPCORES0_EN 16-4 P5VRTS0_EN_L ISL6236 APPLE INC. SCALE SHT OF
DELAY
(S0) 02 U7500 NONE 3 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
BOM Variant TABLE_BOMGROUP_HEAD
Bar Code Label / EEE #
BOM NUMBER BOM NAME BOM OPTIONS PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
TABLE_BOMGROUP_ITEM

630-9977 PCBA,CORNHOLIO,MLB,K19I K19_COMMON,CPU_2_53GHZ,EEE_6Z9 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEE:6Z9] CRITICAL EEE_6Z9

TABLE_BOMGROUP_ITEM

085-0737 K19I MLB DEVELOPMENT K19_DEVEL_PVT

BOM Groups TABLE_BOMGROUP_HEAD

BOM GROUP BOM OPTIONS

D K19_COMMON COMMON,ALTERNATE,K19_MCP,K19_MISC,K19_DEBUG_PVT,K19_PROGPARTS
TABLE_BOMGROUP_ITEM
D
TABLE_BOMGROUP_ITEM

K19_MCP MCP_B03,BOOT_MODE_USER
TABLE_BOMGROUP_ITEM

K19_MISC DP_ESD,EXTRACT_BUFF,ISL6258A,K19I,KB_BL,MIKEY,LDO_YES
TABLE_BOMGROUP_ITEM

K19_PROGPARTS BOOTROM_PROG,SMC_PROG,IR_PROG,WELLSPRING_PROG
TABLE_BOMGROUP_ITEM

K19_DEVEL_ENG BMON_ENG,DEBUG_ADC,XDP_CONN,LPCPLUS,VREFMRGN,BKLT_FS
TABLE_BOMGROUP_ITEM

K19_DEVEL_PVT LPCPLUS
TABLE_BOMGROUP_ITEM

K19_DEBUG_ENG DEVEL_BOM,SMC_DEBUG_YES,XDP
TABLE_BOMGROUP_ITEM

K19_DEBUG_PVT DEVEL_BOM,BMON_PROD,SMC_DEBUG_YES,XDP,NO_VREFMRGN
TABLE_BOMGROUP_ITEM

K19_DEBUG_PROD BMON_PROD,SMC_DEBUG_YES,XDP,LPCPLUS_NOT,NO_VREFMRGN

Module Parts
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
337S3693 1 PDC,SLGE3,PRQ,2.00,25W,1066,R0,3M,BGA U1000 CRITICAL CPU_2_0GHZ
337S3704 1 PDC,SLGE2,PRQ,2.26,25W,1066,R0,3M,BGA U1000 CRITICAL CPU_2_26GHZ
337S3680 1 PDC,LGDZ,PRQ,2.40,25W,1066,R0,3M,BGA U1000 CRITICAL CPU_2_4GHZ
337S3640 1 PDC,SL3BX,PRQ,2.5,35W,1066,C0,6M,BGA U1000 CRITICAL CPU_2_5GHZ
337S3756 1 PDC,SLCFG,PRQ,2.53,25W,1066,R0,3M,BGA U1000 CRITICAL CPU_2_53GHZ
337S3641 1 U1000 CRITICAL CPU_2_8GHZ
C 338S0710 1
PDC,SLB43,PRQ,2.8,35W,1066,C0,6M,BGA

IC,MCP79MXT-B3,35x35MM,BGA1437 U1400 CRITICAL MCP_B03

C
338S0694 1 IC,RTL8251CA-VB-GR,GIGE TRANSCEIVER,48P U3700 CRITICAL
338S0654 1 IC-FW643-E,1394B PHY/OHCI LINK/PCI-E,12 U4100 CRITICAL

Programmable Parts
338S0563 1 IC,SMC,HS8/2117,9X9MM,TLP,HF U4900 CRITICAL SMC_BLANK
341S2460 1 IC,PRGRM,SMC EXTERNAL,K19I U4900 CRITICAL SMC_PROG
335S0610 1 IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP U6100 CRITICAL BOOTROM_BLANK
341S2458 1 IC,PRGRM,UNLOCK,K19I U6100 CRITICAL BOOTROM_PROG
338S0633 1 IC,CYPRS,CY7C63803-LQXC,4X4MM,USB,24-QFN U4800 CRITICAL IR_BLANK
341S2384 1 IR,ENCORE II,CY7C63803-LQXC U4800 CRITICAL IR_PROG
337S2983 1 IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794 U5701 CRITICAL WELLSPRING_BLANK
341S2503 1 IC,TP PSOC,M97,M98 U5701 CRITICAL WELLSPRING_PROG

Development BOM
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
085-0737 1 K19I MLB DEVELOPMENT DEVEL CRITICAL DEVEL_BOM

B B
Alternate Parts TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

PART NUMBER
TABLE_ALT_ITEM

138S0603 138S0602 ALL Murata alt to Samsung

TABLE_ALT_ITEM

152S0968 152S0966 ALL Maglayer alt to Delta

TABLE_ALT_ITEM

128S0220 128S0262 ALL KEMET alt to SANYO

TABLE_ALT_ITEM

152S0778 152S0693 ALL CYNTEC AS ALTERNATE

TABLE_ALT_ITEM

152S0796 152S0685 ALL CYNTEC AS ALTERNATE

TABLE_ALT_ITEM

152S0694 152S0138 ALL MAGLAYERS AS ALTERNATE

TABLE_ALT_ITEM

157S0058 157S0055 ALL DELTA AS ALTERNATE

TABLE_ALT_ITEM

104S0018 104S0023 ALL DALE/VISHAY AS ALTERNATE

TABLE_ALT_ITEM

128S0093 128S0218 ALL KEMET AS ALTERNATE

TABLE_ALT_ITEM

152S0874 152S0516 ALL MAGLAYERS AS ALTERNATE

TABLE_ALT_ITEM

152S0847 152S0586 ALL MAGLAYERS AS ALTERNATE

BOM Configuration
SYNC_MASTER=N/A SYNC_DATE=N/A
A NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 4 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
Revision History

D D

C C

B B

Revision History
SYNC_MASTER=N/A SYNC_DATE=N/A
A NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
5 83
NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping. NONE

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
Fan Connectors Functional Test Points
FUNC_TEST
TRUE PP5V_S0
72
64 65 67
7 37 42
47 49 61
68 70
3 TPs
SATA ODD Connectors DC Power Connector ICT Test Points
TRUE FAN_RT_PWM 47

TRUE FAN_RT_TACH 47 FUNC_TEST FUNC_TEST NO_TEST

TRUE PP5V_SW_ODD 6 37 51 4 TPs TRUE PP18V5_DCIN_FUSE 59 3 TPs
TRUE GND 53 6 NC_AUD_LO1_N_L NC_AUD_LO1_N_L 6 53
5 TPs TRUE ADAPTER_SENSE 59 MAKE_BASE=TRUE TRUE
TRUE SMC_ODD_DETECT 37 40 53 6 NC_AUD_LO1_P_L NC_AUD_LO1_P_L 6 53
MAKE_BASE=TRUE TRUE
SATA_ODD_R2D_P GND NC_USB_10N NC_USB_10N
LVDS Connector TRUE 37 77 TRUE 3 TPs 19 6
MAKE_BASE=TRUE TRUE
6 19

D TRUE SATA_ODD_R2D_N
SATA_ODD_D2R_C_N
37 77 19 6 NC_USB_10P
NC_ENET_INTR_L
NC_USB_10P
NC_ENET_INTR_L MAKE_BASE=TRUE TRUE
6 19
D
FUNC_TEST
TRUE
TRUE SATA_ODD_D2R_C_P
37 77

37 77
Battery Connector 17 6

17 6 NC_ENET_PWRDWN_L NC_ENET_PWRDWN_L MAKE_BASE=TRUE TRUE

6 17

6 17
TRUE PP3V3_S0 58 61 66 67 68 69 71 72 82
6 7 12 17 18 20 21 22 23 26 27 MAKE_BASE=TRUE TRUE
PP3V3_SW_LCD
35 37 41 43 45 46 47 49 53 57
GND FUNC_TEST
TRUE 69 TRUE 3 TPs PPVBAT_G3H_CONN NC_ISSP_SCLK_P1_1 NC_ISSP_SCLK_P1_1
PPVOUT_S0_LCDBKLT TRUE 59 60 3 TPs 48 6 6 48
TRUE 6 51 69 72 74 MAKE_BASE=TRUE TRUE
TRUE SMBUS_SMC_BSA_SCL 6 40 43 59 60 81 48 6 NC_ISSP_SDATA_P1_0 NC_ISSP_SDATA_P1_0 6 48

TRUE LVDS_DDC_CLK 8 17 69
Keyboard Connector TRUE SMBUS_SMC_BSA_SDA 6 40 43 59 60 81 6 NC_LCDBKLT_FAIL NC_LCDBKLT_FAIL MAKE_BASE=TRUE
MAKE_BASE=TRUE
TRUE
TRUE
6

TRUE SYS_DETECT_L 59 18 6 NC_LPC_DRQ0_L NC_LPC_DRQ0_L 6 18

TRUE LVDS_DDC_DATA 8 17 69 MAKE_BASE=TRUE TRUE
FUNC_TEST TRUE GND_BATT_CHGND 8 59
TRUE LVDS_CONN_A_DATA_N<0> 8 69 6 TPs
TRUE PP3V3_S3 6 7 20 25 29 30 43 48 50 68 TP_MEM_A_CKE<3..2> NC_MEM_A_CKE<3..2> 15
TRUE LVDS_CONN_A_DATA_P<0> 8 69 MAKE_BASE=TRUE TRUE
TRUE PP3V42_G3H 6 7 20 21 24 38 40 41 42 43 45 14 6 NC_MEM_A_CLK2N NC_MEM_A_CLK2N 6 14
LVDS_CONN_A_DATA_N<1>
TRUE
TRUE LVDS_CONN_A_DATA_P<1>
8 69

8 69
TRUE WS_KBD1
48 59 60 67
48 BIL Connector 15 6 NC_MEM_A_CLK3N NC_MEM_A_CLK3N MAKE_BASE=TRUE
MAKE_BASE=TRUE
TRUE
TRUE
6 15

TRUE WS_KBD2 48 43 45 48 59 60 67 15 6 NC_MEM_A_CLK3P NC_MEM_A_CLK3P 6 15

TRUE LVDS_CONN_A_DATA_N<2> 8 69 FUNC_TEST 42 MAKE_BASE=TRUE TRUE
TRUE WS_KBD3 48
41
15 6 NC_MEM_A_CLK4P NC_MEM_A_CLK4P 6 15
TRUE LVDS_CONN_A_DATA_P<2> 8 69 TRUE PP3V42_G3H 38 40
6 7 20 3 TPs MAKE_BASE=TRUE TRUE
TRUE WS_KBD4 48 21 24 15 6 NC_MEM_A_CS_L<3> NC_MEM_A_CS_L<3> 6 15
TRUE LVDS_CONN_A_CLK_F_N 69 82 TRUE SMC_LID_R 59 MAKE_BASE=TRUE TRUE
TRUE WS_KBD5 48 TP_MEM_A_ODT<3..2> NC_MEM_A_ODT<3..2> 15
TRUE LVDS_CONN_A_CLK_F_P 69 82 TRUE SMBUS_SMC_BSA_SCL 6 40 43 59 60 81 MAKE_BASE=TRUE TRUE
TRUE WS_KBD6 48
TRUE LVDS_CONN_B_DATA_N<0> 8 69 TRUE SMBUS_SMC_BSA_SDA 6 40 43 59 60 81
TRUE WS_KBD7 48 15 6 NC_MEM_B_CKE<2> NC_MEM_B_CKE<2> 6 15
TRUE LVDS_CONN_B_DATA_P<0> 8 69 TRUE SMC_BIL_BUTTON_L 40 41 59 MAKE_BASE=TRUE TRUE
TRUE WS_KBD8 48 15 6 NC_MEM_B_CLK3P NC_MEM_B_CLK3P 6 15
TRUE LVDS_CONN_B_DATA_N<1> 8 69 MAKE_BASE=TRUE TRUE
TRUE WS_KBD9 48 15 6 NC_MEM_B_CLK4N NC_MEM_B_CLK4N 6 15
TRUE LVDS_CONN_B_DATA_P<1> 8 69 TRUE GND 3 TPs MAKE_BASE=TRUE TRUE
TRUE WS_KBD10 48 15 6 NC_MEM_B_CLK4P NC_MEM_B_CLK4P 6 15
TRUE LVDS_CONN_B_DATA_N<2> 8 69 MAKE_BASE=TRUE TRUE
WS_KBD11 NC_MEM_B_CLK5N NC_MEM_B_CLK5N
TRUE LVDS_CONN_B_DATA_P<2> 8 69
TRUE
TRUE WS_KBD12
48

48
Power Nets 15 6

15 6 NC_MEM_B_ODT<2> NC_MEM_B_ODT<2> MAKE_BASE=TRUE TRUE

6 15

6 15
TRUE LVDS_CONN_B_CLK_F_N 69 82 MAKE_BASE=TRUE TRUE
TRUE WS_KBD13 48 20 6 NC_MLB_RAM_SIZE NC_MLB_RAM_SIZE 6 20
TRUE LVDS_CONN_B_CLK_F_P 69 82 FUNC_TEST MAKE_BASE=TRUE TRUE
TRUE WS_KBD14 48 48 6 NC_P7_7 NC_P7_7 6 48
TRUE LED_RETURN_1 69 72 74 TRUE PPVCORE_S0_CPU 7 10 11 44 61 MAKE_BASE=TRUE TRUE
TRUE WS_KBD15_CAP 48 TP_PCI_AD<31..8> NC_PCI_AD<31..8> 18
TRUE LED_RETURN_2 69 72 74 TRUE PPVCORE_S0_MCP 7 21 22 44 64 MAKE_BASE=TRUE TRUE
TRUE WS_KBD16_NUM 48
LED_RETURN_3 PP0V75_S0_DDRVTT
C TRUE
TRUE LED_RETURN_4
69 72 74

69 72 74
TRUE
TRUE
WS_KBD17
WS_KBD18
48

48
TRUE
TRUE PP1V05_S0
7 26 27 63 68

7 9 10 11 12 13 16 17 19 21 22
23 35 61 65 66 67
TP_PCI_C_BE_L<3..0> NC_PCI_C_BE_L<3..0>
MAKE_BASE=TRUE TRUE
18
C
TRUE LED_RETURN_5 69 72 74 TRUE PP1V5_S0 7 10 11 15 22 37 66 67 68 82
TRUE WS_KBD19 48
TRUE LED_RETURN_6 69 72 74 TRUE PP1V8_S0 7 17 23 53 66 18 6 NC_PCI_CLK0 NC_PCI_CLK0 6 18
TRUE WS_KBD20 48 MAKE_BASE=TRUE TRUE
TRUE BKL_ISEN1 72 TRUE PP3V3_S0 58 61 66 67 68 69 71 72 82
6 7 12 17 18 20 21 22 23 26 27 18 6 NC_PCI_CLK1 NC_PCI_CLK1 6 18
TRUE WS_KBD21 48 35 37 41 43 45 46 47 49 53 57 MAKE_BASE=TRUE TRUE
TRUE BKL_ISEN2 72 TRUE PP1V5_S3 7 26 27 28 63 68 18 6 NC_PCI_DEVSEL_L NC_PCI_DEVSEL_L 6 18
TRUE WS_KBD22 48 MAKE_BASE=TRUE TRUE
TRUE BKL_ISEN3 72 TRUE PP3V3_S3 6 7 20 25 29 30 43 48 50 68 18 6 NC_PCI_FRAME_L NC_PCI_FRAME_L 6 18
TRUE WS_KBD23 48 MAKE_BASE=TRUE TRUE
TRUE BKL_ISEN4 72 TRUE PP1V05_S5 6 7 21 22 32 66 18 6 NC_PCI_GNT0_L NC_PCI_GNT0_L 6 18
TRUE WS_KBD_ONOFF_L 48 MAKE_BASE=TRUE TRUE
TRUE BKL_ISEN5 72 TRUE PP3V3_S5 7 17 19 21 22 24 28 32 35 36 42 18 6 NC_PCI_GNT1_L NC_PCI_GNT1_L 6 18
TRUE WS_LEFT_SHIFT_KBD 48 52 62 66 67 68 69 71 82 MAKE_BASE=TRUE TRUE
TRUE BKL_ISEN6 72 TRUE PP3V42_G3H 6 7 20 21 24 38 40 41 42 43 45 18 6 NC_PCI_INTW_L NC_PCI_INTW_L 6 18
TRUE WS_LEFT_OPTION_KBD 48 48 59 60 67 MAKE_BASE=TRUE TRUE
TRUE PPBUS_G3H 7 35 44 45 59 60 62 63 64 73 18 6 NC_PCI_INTX_L NC_PCI_INTX_L 6 18
TRUE WS_CONTROL_KBD 48 MAKE_BASE=TRUE TRUE
TRUE GND TRUE PP3V3_ENET 7 17 22 31 32 18 6 NC_PCI_INTZ_L NC_PCI_INTZ_L 6 18
5 TPs TRUE KBDLED_ANODE 6 49 MAKE_BASE=TRUE TRUE
TRUE PP1V05_ENET 7 17 22 31 32 18 6 NC_PCI_IRDY_L NC_PCI_IRDY_L 6 18
MAKE_BASE=TRUE TRUE
TRUE GND 2 TPs TRUE PP5V_S3 7 8 29 37 38 39 41 49 51 53 62 18 6 NC_PCI_PERR_L NC_PCI_PERR_L 6 18

IPD Flex Connector TRUE PP3V3_S5_AVREF_SMC

63 68
40 41 18 6 NC_PCI_RESET1_L NC_PCI_RESET1_L MAKE_BASE=TRUE
MAKE_BASE=TRUE
TRUE
TRUE
6 18

TRUE PP18V5_S3 6 49 18 6 NC_PCI_SERR_L NC_PCI_SERR_L 6 18

MAKE_BASE=TRUE TRUE
FUNC_TEST TRUE PP3V3_S3_LDO 6 49 18 6 NC_PCI_STOP_L NC_PCI_STOP_L 6 18

TRUE PP3V3_S3_LDO 6 49
Airport/BT/Camera Conn. TRUE PPVOUT_S0_LCDBKLT 6 51 69 72 74 18 6 NC_PCI_TRDY_L NC_PCI_TRDY_L MAKE_BASE=TRUE
MAKE_BASE=TRUE
TRUE
TRUE
6 18

TRUE PP4V5_AUDIO_ANALOG 53 16 6 NC_PCIE_CLK100M_PE4N NC_PCIE_CLK100M_PE4N 6 16

TRUE PP18V5_S3 6 49 FUNC_TEST MAKE_BASE=TRUE TRUE
TRUE SMC_PM_G2_EN 8 40 62 67 16 6 NC_PCIE_CLK100M_PE4P NC_PCIE_CLK100M_PE4P 6 16
TRUE Z2_CS_L 48 49 TRUE PCIE_MINI_D2R_P 16 29 77 MAKE_BASE=TRUE TRUE
TRUE PM_SLP_S4_L 20 38 40 41 67 16 6 NC_PCIE_CLK100M_PE5N NC_PCIE_CLK100M_PE5N 6 16
TRUE Z2_DEBUG3 48 49 TRUE PCIE_MINI_D2R_N 16 29 77 MAKE_BASE=TRUE TRUE
TRUE PM_SLP_S3_L 20 32 35 40 67 71 16 6 NC_PCIE_CLK100M_PE5P NC_PCIE_CLK100M_PE5P 6 16
TRUE Z2_MOSI 48 49 TRUE PCIE_MINI_R2D_P 29 77 82 MAKE_BASE=TRUE TRUE
TRUE PP1V05_S5 6 7 21 22 32 66 16 6 NC_PCIE_CLK100M_PE6P NC_PCIE_CLK100M_PE6P 6 16
TRUE Z2_MISO 48 49 TRUE PCIE_MINI_R2D_N 29 77 82 MAKE_BASE=TRUE TRUE
TRUE PP5V_SW_ODD 6 37 51 16 6 NC_PCIE_PE4_D2RN NC_PCIE_PE4_D2RN 6 16
TRUE Z2_SCLK 48 49 TRUE PCIE_CLK100M_MINI_CONN_P 29 82 MAKE_BASE=TRUE TRUE
TRUE PP5V_S0_HDD_FLT 6 37 16 6 NC_PCIE_PE4_R2D_CN NC_PCIE_PE4_R2D_CN 6 16
TRUE Z2_BOOST_EN 49 TRUE PCIE_CLK100M_MINI_CONN_N 29 82 MAKE_BASE=TRUE TRUE
TRUE BKL_VLDO 72 16 6 NC_PE4_PRSNT_L NC_PE4_PRSNT_L 6 16
TRUE Z2_HOST_INTN 48 49 TRUE MINI_CLKREQ_Q_L 29 MAKE_BASE=TRUE TRUE
48 6 NC_PSOC_P1_3 NC_PSOC_P1_3 6 48

B TRUE
TRUE
Z2_CLKIN
Z2_KEY_ACT_L
48 49

48 49
TRUE
TRUE
PCIE_WAKE_L
MINI_RESET_CONN_L
16 29

29
TRUE GND 6 TPs
48 6 NC_PSOC_SDA NC_PSOC_SDA MAKE_BASE=TRUE
MAKE_BASE=TRUE
TRUE
TRUE
6 48 B
19 6 NC_SATA_C_D2RP NC_SATA_C_D2RP 6 19
TRUE Z2_RESET 48 49 TRUE PP5V_WLAN 29 MAKE_BASE=TRUE TRUE
19 6 NC_SATA_C_R2D_CN NC_SATA_C_R2D_CN 6 19
TRUE PSOC_MISO 48 49 TRUE PP5V_S3_BTCAMERA_F 29 MAKE_BASE=TRUE TRUE
19 6 NC_SATA_C_R2D_CP NC_SATA_C_R2D_CP 6 19
TRUE PSOC_MOSI 48 49 TRUE SMBUS_SMC_A_S3_SDA 6 29 40 43 49 81 MAKE_BASE=TRUE TRUE
19 6 NC_SATA_D_D2RN NC_SATA_D_D2RN 6 19
TRUE PSOC_SCLK 48 49 TRUE SMBUS_SMC_A_S3_SCL 6 29 40 43 49 81 MAKE_BASE=TRUE TRUE
19 6 NC_SATA_D_D2RP NC_SATA_D_D2RP 6 19
TRUE SMBUS_SMC_A_S3_SDA 6 29 40 43 49 81 TRUE USB_CAMERA_CONN_P 29 82 MAKE_BASE=TRUE TRUE
20 6 NC_SB_A20GATE NC_SB_A20GATE 6 20
TRUE SMBUS_SMC_A_S3_SCL 6 29 40 43 49 81 TRUE USB_CAMERA_CONN_N 29 82 MAKE_BASE=TRUE TRUE
TRUE PSOC_F_CS_L 48 49 TRUE CONN_USB2_BT_P 29 82

TRUE PICKB_L 48 49 TRUE CONN_USB2_BT_N 29 82

GND GND NO_TEST

TRUE TRUE
2 TPs 10 TPs FSB_A_L<31..3>
TRUE 9 13 75 Note.
FSB_ADS_L
SD Card Connector SATA HDD Connector TRUE
TRUE FSB_ADSTB_L<1..0>
9 13 75

9 13 75
NO_TEST properties are also on page9,26,43,50

FUNC_TEST FUNC_TEST TRUE FSB_D_L<63..0> 9 13 75

TRUE PP5V_S0_HDD_FLT 6 37 4 TPs

TRUE SD_D<7..0> 30 82 TRUE FSB_DINV_L<3..0> 9 13 75
TRUE PP5V_S3_IR_R 37
TRUE SD_CMD 30 82
TRUE SATA_HDD_R2D_P 37 77 TRUE FSB_DSTB_L_N<3..0> 9 13 75
TRUE SD_CLK 30 82
TRUE SATA_HDD_R2D_N 37 77 TRUE FSB_DSTB_L_P<3..0> 9 13 75
TRUE SD_CD_L 30
TRUE SATA_HDD_D2R_C_P 37 77 TRUE FSB_HIT_L 9 13 75
TRUE SD_WP 30
TRUE SATA_HDD_D2R_C_N 37 77 TRUE FSB_HITM_L 9 13 75

TRUE GND TRUE IR_RX_OUT 37 39 TRUE FSB_LOCK_L 9 13 75

2 TPs SYS_LED_ANODE_R FSB_REQ_L<4..0> 13 75
TRUE 37 TRUE 9

Speaker Connectors TRUE GND 6 TPs

TRUE MCPCORES0_OCSET Functional / ICT Test
TRUE USB_BT_N 19 29 78
SYNC_MASTER=N/A SYNC_DATE=N/A
A FUNC_TEST
BI_MIC_LO
TRUE USB_BT_P
USB_CAMERA_N
19 29 78
A
TRUE
TRUE BI_MIC_SHIELD
57 58

57 58
KBD Backlight Conn. TRUE
TRUE USB_CAMERA_P
19 29 78

19 29 78
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
TRUE BI_MIC_HI 57 58 TRUE SATA_ODD_D2R_UF_N 37 82 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
SPKRCONN_L_OUT_P FUNC_TEST SATA_ODD_D2R_UF_P AGREES TO THE FOLLOWING
TRUE 56 57 82 TRUE 37 82
TRUE KBDLED_ANODE 6 49 2 TPs I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
TRUE SPKRCONN_L_OUT_N 56 57 82 TRUE DP_ML_C_P<3..0> 71 82
TRUE SMC_KDBLED_PRESENT_L 49 II NOT TO REPRODUCE OR COPY IT
TRUE SPKRCONN_R_OUT_P 56 57 82
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
TRUE SPKRCONN_R_OUT_N 56 57 82 TRUE GND
TRUE SPKRCONN_S_OUT_P 56 57 82 SIZE DRAWING NUMBER REV.
SPKRCONN_S_OUT_N
TRUE 56 57 82
D 051-7903 A
TRUE GND 6 TPs APPLE INC. SCALE SHT OF
NONE 6 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
"G3Hot" (Always-Present) Rails 3.3V Rails 1.5V S0 Rail
64 63 62 60 59 45 44 35 7 6 PPBUS_G3H PPBUS_G3H 6 7 35 44 45 59 60 62 63 64 73
82 71 69 68
22 21 19 17 7 6 PP3V3_S5 PP3V3_S5 68 69 71 82
6 7 17 19 21 22 68 67 66 37 22 15 11 10 7 6 PP1V5_S0 PP1V5_S0 6 7 10 11 15 22 37 66 67 68
73 MIN_LINE_WIDTH=0.4 mm 67 66 62 52 42 36 35 32 28 24 MIN_LINE_WIDTH=0.6 mm 24 28 32 35 36 42 52 62 66 67 82 MIN_LINE_WIDTH=0.6mm 82
MIN_NECK_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2mm
VOLTAGE=12.6V VOLTAGE=3.3V VOLTAGE=1.5V
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
PPBUS_G3H 6 7 35 44 45 59 60 62 63 64 73 PP3V3_S5 6 7 17 19 21 22 24 28 32 35 36 130 mA PP1V5_S0 6 7 10 11 15 22 37 66 67 68
42 52 62 66 67 68 69 71 82 82
PPBUS_G3H 6 7 35 44 45 59 60 62 63 64 73 PP3V3_S5 6 7 17 19 21 22 24 28 32 35 36 PP1V5_S0 6 7 10 11 15 22 37 66 67 68
42 52 62 66 67 68 69 71 82 82
PPBUS_G3H 6 7 35 44 45 59 60 62 63 64 73 PP3V3_S5 6 7 17 19 21 22 24 28 32 35 36 PP1V5_S0 6 7 10 11 15 22 37 66 67 68
42 52 62 66 67 68 69 71 82 82
PPBUS_G3H 6 7 35 44 45 59 60 62 63 64 73 PP3V3_S5 6 7 17 19 21 22 24 28 32 35 36
42 52 62 66 67 68 69 71 82
PPBUS_G3H 6 7 35 44 45 59 60 62 63 64 73 PP3V3_S5 6 7 17 19 21 22 24 28 32 35 36 4771 mA PP1V5_S0 6 7 10 11 15 22 37 66 67 68
42 52 62 66 67 68 69 71 82 82
PPBUS_G3H 6 7 35 44 45 59 60 62 63 64 73 PP3V3_S5 6 7 17 19 21 22 24 28 32 35 36
42 52 62 66 67 68 69 71 82
PP1V5_S0 6 7 10 11 15 22 37 66 67 68
82
PPBUS_G3H PP3V3_S5
6 7 35 44 45 59 60 62 63 64 73 6 7 17 19 21 22 24 28 32 35 36
42 52 62 66 67 68 69 71 82 DDR3 Reference Plane
D
PPBUS_G3H 6 7 35 44 45 59 60 62 63 64 73 PP3V3_S5
PP3V3_S5
6 7 17 19 21 22 24 28 32 35 36
42 52 62 66 67 68 69 71 82
6 7 17 19 21 22 24 28 32 35 36 GND
D
42 52 62 66 67 68 69 71 82
65 61 45 7 PPBUS_CPU_IMVP_ISNS PPBUS_CPU_IMVP_ISNS 7 45 61 65 PP3V3_S5 6 7 17 19 21 22 24 28 32 35 36 GND
MIN_LINE_WIDTH=0.6 mm 42 52 62 66 67 68 69 71 82
MIN_NECK_WIDTH=0.25 mm PP3V3_S5 6 7 17 19 21 22 24 28 32 35 36
VOLTAGE=12.6V
PP3V3_S5
42 52 62 66 67 68 69 71 82 K19i uses GND reference for ALL DDR3 signals.
MAKE_BASE=TRUE 6 7 17 19 21 22 24 28 32 35 36
42 52 62 66 67 68 69 71 82
PPBUS_CPU_IMVP_ISNS 7 45 61 65 PP3V3_S5 6 7 17 19 21 22 24 28 32 35 36
42 52 62 66 67 68 69 71 82
PPBUS_CPU_IMVP_ISNS 7 45 61 65 PP3V3_S5 6 7 17 19 21 22 24 28 32 35 36
42 52 62 66 67 68 69 71 82
1.05V Rails
PP3V3_S5 6 7 17 19 21 22 24 28 32 35 36
42 52 62 66 67 68 69 71 82 66 32 22 21 7 6 PP1V05_S5 PP1V05_S5 6 7 21 22 32 66
43 42 41 40 38 24 21 20 7 6 PP3V42_G3H PP3V42_G3H 6 7 20 21 24 38 40 41 42 43 45 PP3V3_S5 6 7 17 19 21 22 24 28 32 35 36 MIN_LINE_WIDTH=0.4 mm
67 60 59 48 45 MIN_LINE_WIDTH=0.3 mm 48 59 60 67 42 52 62 66 67 68 69 71 82 MIN_NECK_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm PP3V3_S5 6 7 17 19 21 22 24 28 32 35 36 VOLTAGE=1.05V
VOLTAGE=3.42V 42 52 62 66 67 68 69 71 82 MAKE_BASE=TRUE
MAKE_BASE=TRUE
105 mA/241 mA PP1V05_S5 6 7 21 22 32 66
68 50 48 43 30 29 25 20 7 6 PP3V3_S3 PP3V3_S3 6 7 20 25 29 30 43 48 50 68
PP3V42_G3H 6 7 20 21 24 38 40 41 42 43 45 MIN_LINE_WIDTH=0.40MM 139 mA/ 0 mA PP1V05_S5 6 7 21 22 32 66
48 59 60 67 MIN_NECK_WIDTH=0.20MM
PP3V42_G3H 6 7 20 21 24 38 40 41 42 43 45 VOLTAGE=3.3V
48 59 60 67 MAKE_BASE=TRUE
PP3V42_G3H 6 7 20 21 24 38 40 41 42 43 45 32 31 22 17 7 6 PP1V05_ENET PP1V05_ENET 6 7 17 22 31 32
48 59 60 67 PP3V3_S3 6 7 20 25 29 30 43 48 50 68 MIN_LINE_WIDTH=0.4 mm
PP3V42_G3H 6 7 20 21 24 38 40 41 42 43 45 MIN_NECK_WIDTH=0.2 mm
48 59 60 67 PP3V3_S3 6 7 20 25 29 30 43 48 50 68 VOLTAGE=1.05V
PP3V42_G3H 6 7 20 21 24 38 40 41 42 43 45 MAKE_BASE=TRUE
48 59 60 67 PP3V3_S3 6 7 20 25 29 30 43 48 50 68
PP3V42_G3H 6 7 20 21 24 38 40 41 42 43 45 PP1V05_ENET 6 7 17 22 31 32
48 59 60 67 PP3V3_S3 6 7 20 25 29 30 43 48 50 68
PP3V42_G3H 6 7 20 21 24 38 40 41 42 43 45 PP1V05_ENET 6 7 17 22 31 32
48 59 60 67 PP3V3_S3 6 7 20 25 29 30 43 48 50 68
PP3V42_G3H 6 7 20 21 24 38 40 41 42 43 45 PP1V05_ENET 6 7 17 22 31 32
48 59 60 67 PP3V3_S3 6 7 20 25 29 30 43 48 50 68
PP3V42_G3H 6 7 20 21 24 38 40 41 42 43 45
48 59 60 67 PP3V3_S3 6 7 20 25 29 30 43 48 50 68
PP3V42_G3H 6 7 20 21 24 38 40 41 42 43 45 21 19 17 16 13 12 11 10 9 7 6 PP1V05_S0 PP1V05_S0 6 7 9 10 11 12 13 16 17 19 21
48 59 60 67 PP3V3_S3 6 7 20 25 29 30 43 48 50 67 66 65 61 35 23 22 MIN_LINE_WIDTH=0.6 mm 22 23 35 61 65 66 67
PP3V42_G3H 6 7 20 21 24 38 40 41 42 43 45 68 MIN_NECK_WIDTH=0.2 mm
48 59 60 67 PP3V3_S3 6 7 20 25 29 30 43 48 50 68 VOLTAGE=1.05V
PP3V42_G3H 6 7 20 21 24 38 40 41 42 43 45
48 59 60 67
MAKE_BASE=TRUE
PP3V42_G3H 6 7 20 21 24 38 40 41 42 43 45 4500 mA PP1V05_S0 6 7 9 10 11 12 13 16 17 19 21
48 59 60 67 32 31 22 17 7 6 PP3V3_ENET PP3V3_ENET 6 7 17 22 31 32 22 23 35 61 65 66 67
MIN_LINE_WIDTH=0.6 mm PP1V05_S0 6 7 9 10 11 12 13 16 17 19 21
MIN_NECK_WIDTH=0.2 mm 22 23 35 61 65 66 67
VOLTAGE=3.3V 1182 mA PP1V05_S0 6 7 9 10 11 12 13 16 17 19 21
MAKE_BASE=TRUE 22 23 35 61 65 66 67
DCIN Rail PP1V05_S0
C
C 60 59 7 PPDCIN_S5 PPDCIN_S5 7 59 60
PP3V3_ENET
PP3V3_ENET
6 7 17 22 31 32

6 7 17 22 31 32
6600 MA
PP1V05_S0
6 7 9 10 11 12 13 16 17 19 21
22 23 35 61 65 66 67
6 7 9
22 23
10
35
11
61
12
65
13
66
16 17 19 21
67
MIN_LINE_WIDTH=0.6 mm 1034 mA PP1V05_S0 6 7 9 10 11 12 13 16 17 19 21
MIN_NECK_WIDTH=0.25 mm 22 23 35 61 65 66 67
VOLTAGE=18.5V 241 mA max load PP1V05_S0 6 7 9 10 11 12 13 16 17 19 21
MAKE_BASE=TRUE 82 72 71 69 68 67 66 61 58 57
26 23 22 21 20 18 17 12 7 6 PP3V3_S0 PP3V3_S0 58 61 66 67 68 69 71 72 82
6 7 12 17 18 20 21 22 23 26 27 22 23 35 61 65 66 67
53 49 47 46 45 43 41 37 35 27 MIN_LINE_WIDTH=0.6 mm 35 37 41 43 45 46 47 49 53 57 PP1V05_S0 6 7 9 10 11 12 13 16 17 19 21
PPDCIN_S5 7 59 60 MIN_NECK_WIDTH=0.2 mm 22 23 35 61 65 66 67
VOLTAGE=3.3V PP1V05_S0 6 7 9 10 11 12 13 16 17 19 21
MAKE_BASE=TRUE 22 23 35 61 65 66 67
PP1V05_S0
"FW" (FireWire) Rail PP3V3_S0 58 61 66 67 68 69 71 72 82
6 7 12 17 18 20 21 22 23 26 27
35 37 41 43 45 46 47 49 53 57
6 7 9 10 11 12 13 16 17 19 21
22 23 35 61 65 66 67

PP3V3_S0
36 35 7 PPVP_FW PPVP_FW 7 35 36
MIN_LINE_WIDTH=0.4 mm PP3V3_S0 58 61 66 67 68 69 71 72 82
6 7 12 17 18 20 21 22 23 26 27 66 22 7 PP1V05_S0_MCP_PLL_UF PP1V05_S0_MCP_PLL_UF 7 22 66
MIN_NECK_WIDTH=0.2 mm 35 37 41 43 45 46 47 49 53 57 MIN_LINE_WIDTH=0.4 mm
VOLTAGE=12.6V PP3V3_S0 6 7 12 17 18 20 21 22 23 26 27 MIN_NECK_WIDTH=0.2 mm
MAKE_BASE=TRUE 35 37 41 43 45 46 47 49 53 57 VOLTAGE=1.05V
PP3V3_S0 58 61 66 67 68 69 71 72 82
6 35 MAKE_BASE=TRUE
PPVP_FW 7 35 36 7 12 17 18 20 21 22 23 26 27
PP3V3_S0 37 41 43 45 46 47 49 53 57
58 61 66 67 68 69 71 72 82 PP1V05_S0_MCP_PLL_UF 7 22 66
PPVP_FW 7 35 36
PP3V3_S0
35 34 7 PP1V05_FW PP1V05_FW 7 34 35
PP3V3_S0 58 61 66 67 68 69 71 72 82
MIN_LINE_WIDTH=0.4 mm
5V Rails PP3V3_S0
6 7 12 17 18 20 21 22 23 26 27
35 37 41 43 45 46 47 49 53 57
6 7 12 17 18 20 21 22 23 26 27
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
35 37 41 43 45 46 47 49 53 57 MAKE_BASE=TRUE
53 51 49 41 39 38 37 29 8 7 6 PP5V_S3 PP5V_S3 6 7 8 29 37 38 39 41 49 51 53 PP3V3_S0 58 61 66 67 68 69 71 72 82
68 63 62 MIN_LINE_WIDTH=0.5MM 62 63 68 PP1V05_FW 7 34 35
MIN_NECK_WIDTH=0.2MM PP3V3_S0 58 61 66 67 68 69 71 72 82
6 7 12 17 18 20 21 22 23 26 27
VOLTAGE=5V 35 37 41 43 45 46 47 49 53 57 PP1V05_FW 7 34 35
MAKE_BASE=TRUE PP3V3_S0 6 7 12 17 18 20 21 22 23 26 27
35 37 41 43 45 46 47 49 53 57
PP5V_S3 PP3V3_S0 58 61 66 67 68 69 71 72 82

PP5V_S3
6 7 8 29 37 38 39 41 49 51 53
62 63 68
6 7 8 29 37 38 39 41 49 51 53 PP3V3_S0
6
12 37 41 43 45 46 47 49 53 57
6 58 61 66 67 68 69 71 72 82
35
41 7 12 17 18 20 21 22 23 26 27 Chipset "VCore" Rails
62 63 68 7
PP5V_S3 6 7 8 29 37 38 39 41 49 51 53 PP3V3_S0 17 18 20 21 22 23 26 27 35 37
43 45 46 47 49 53 57 58 61 61 44 11 10 7 6 PPVCORE_S0_CPU PPVCORE_S0_CPU 6 7 10 11 44 61
62 63 68 66 67 68 69 71 72 82 58 61 66 MIN_LINE_WIDTH=0.6 mm
PP5V_S3 6 7 8 29 37 38 39 41 49 51 53 PP3V3_S0 6 7 12 17 18 20 21 22 23 26 27 MIN_NECK_WIDTH=0.25 mm
62 63 68 35 37 41 43 45 46 47 49 53 57 VOLTAGE=1.25V
PP5V_S3 6 7 8 29 37 38 39 41 49 51 53 PP3V3_S0 67 68 69 71 72 82
6 35 37 41 43
41 7 12 17 18 20 21 22 23 26 27
MAKE_BASE=TRUE
62 63 68
PP5V_S3 6 7 8 29 37 38 39 41 49 51 53 PP3V3_S0 12 45 46 47 49 53 57 58 61 66
6 67 68 69 71 72 82 PPVCORE_S0_CPU 6 7 10 11 44 61
62 63 68 7 66 67 68
PP5V_S3 6 7 8 29 37 38 39 41 49 51 53
62 63 68
PP3V3_S0 17 18 20 21 22 23 26 27 35 37
43 45 46 47 49 53 57 58 61 PPVCORE_S0_CPU 6 7 10 11 44 61
69 71 72 82
PP5V_S3 6 7 8 29 37 38 39 41 49 51 53 PP3V3_S0
62 63 68

B PP5V_S3
PP5V_S3
6 7 8
62 63
29 37 38 39 41 49 51 53
68
6 7 8 29 37 38 39 41 49 51 53
PP3V3_S0
PP3V3_S0
58 61 66 67 68 69 71 72 82
6 7 12 17 18 20 21 22 23 26 27
35 37 41 43 45 46 47 49 53 57 64 44 22 21 7 6
6 7 12 17 18 20 21 22 23 26 27
PPVCORE_S0_MCP PPVCORE_S0_MCP
MIN_LINE_WIDTH=0.6 mm
6 7 21 22 44 64 B
62 63 68 35 37 41 43 45 46 47 49 53 57 MIN_NECK_WIDTH=0.2 mm
PP5V_S3 6 7 8 29 37 38 39 41 49 51 53 PP3V3_S0 58 61 66 67 68 69 71 72 82
6 35
41 7 12 17 18 20 21 22 23 26 27
VOLTAGE=1.05V
62 63 68 MAKE_BASE=TRUE
PP5V_S3 6 7 8 29 37 38 39 41 49 51 53 PP3V3_S0 12 37 41 43 45 46 47 49 53 57
6 58 61 66 67 68 69 71 72 82
62 63 68 7 PPVCORE_S0_MCP 6 7 21 22 44 64
PP5V_S3 6 7 8 29 37 38 39 41 49 51 53 PP3V3_S0 17 18 20 21 22 23 26 27 35 37
43 45 46 47 49 53 57 58 61
62 63 68 66 67 68 69 71 72 82 58 61 66 PPVCORE_S0_MCP 6 7 21 22 44 64
PP5V_S3 6 7 8 29 37 38 39 41 49 51 53 PP3V3_S0 6 7 12 17 18 20 21 22 23 26 27
62 63 68 35 37 41 43 45 46 47 49 53 57
PP5V_S3 PP3V3_S0 67 68 69 71 72 82

PP5V_S3
6 7 8
62 63
6 7 8
29 37 38 39 41 49 51 53
68
29 37 38 39 41 49 51 53 PP3V3_S0
6 35 37 41 43
41 7 12 17 18 20 21 22 23 26 27
12 45 46 47 49 53 57 58 61 66
6 67 68 69 71 72 82
0.75V Rails
62 63 68 7 66 67 68
PP5V_S3 6 7 8 29 37 38 39 41 49 51 53 PP3V3_S0 17 18 20 21 22 23 26 27 35 37
43 45 46 47 49 53 57 58 61 63 25 7 PPVTTDDR_S3 PPVTTDDR_S3 7 25 63
62 63 68 69 71 72 82 58 61 66 67 68 69 MIN_LINE_WIDTH=0.3 mm
PP3V3_S0 6 7 12 17 18 20 21 22 23 26 27 MIN_NECK_WIDTH=0.2 mm
35 37 41 43 45 46 47 49 53 57 VOLTAGE=0.75V
67 65 64 61 49 47 42 37 7 6 PP5V_S0 PP5V_S0 6 7 37 42 47 49 61 64 65 67 68 PP3V3_S0 71 72 82
6 35 37 41 43 45 46 47
41 7 12 17 18 20 21 22 23 26 27
MAKE_BASE=TRUE
72 70 68 MIN_LINE_WIDTH=0.4 MM 70 72
MIN_NECK_WIDTH=0.2 MM PP3V3_S0 12 49 53 57 58 61 66 67 68 69
6 71 72 82
VOLTAGE=5V 7 66 67 68 69 71 72 68 63 27 26 7 6
17 18 20 21 22 23 26 27 35 37
PP0V75_S0_DDRVTT PP0V75_S0_DDRVTT 6 7 26 27 63 68
MAKE_BASE=TRUE 43 45 46 47 49 53 57 58 61 MIN_LINE_WIDTH=2 mm
82 MIN_NECK_WIDTH=0.17 mm
PP5V_S0 6 7 37 42 47 49 61 64 65 67 68 36 35 34 7 PP3V3_FW PP3V3_FW 7 34 35 36 VOLTAGE=0.75V
70 72 MIN_LINE_WIDTH=0.6 mm MAKE_BASE=TRUE
PP5V_S0 6 7 37 42 47 49 61 64 65 67 68 MIN_NECK_WIDTH=0.2 mm
70 72 VOLTAGE=3.3V PP0V75_S0_DDRVTT 6 7 26 27 63 68
PP5V_S0 6 7 37 42 47 49 61 64 65 67 68 MAKE_BASE=TRUE
70 72 PP0V75_S0_DDRVTT 6 7 26 27 63 68
PP5V_S0 6 7 37 42 47 49 61 64 65 67 68 PP3V3_FW 7 34 35 36
70 72 PP0V75_S0_DDRVTT 6 7 26 27 63 68
PP5V_S0 6 7 37 42 47 49 61 64 65 67 68 PP3V3_FW 7 34 35 36
70 72
PP5V_S0 6 7 37 42 47 49 61 64 65 67 68
70 72
PP5V_S0
PP5V_S0
6 7 37 42 47 49 61 64 65 67 68
70 72
6 7 37 42 47 49 61 64 65 67 68
1.8V Rail
70 72
PP5V_S0 6 7 37 42 47 49 61 64 65 67 68 66 53 23 17 7 6 PP1V8_S0 PP1V8_S0 6 7 17 23 53 66
70 72 MIN_LINE_WIDTH=0.4 mm
PP5V_S0 6 7 37 42 47 49 61 64 65 67 68 500 mA max supply MIN_NECK_WIDTH=0.2 mm
70 72 VOLTAGE=1.8V
MAKE_BASE=TRUE

MCP79 PCIe/SATA Rails 190 mA PP1V8_S0 6 7 17 23 53 66 Power Aliases

PP1V8_S0 6 7 17 23 53 66
SYNC_MASTER=N/A SYNC_DATE=N/A
A GND
1.5V S3 Rail NOTICE OF PROPRIETARY PROPERTY
A
21 19 17 16 13 12 11 10 9 7 6 PP1V05_S0 PP1V05_S0 6 7 9 10 11 12 13 16 17 19 21
67 66 65 61 35 23 22 22 23 35 61 65 66 67
68 63 28 27 26 7 6 PP1V5_S3 PP1V5_S3 6 7 26 27 28 63 68 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
MIN_LINE_WIDTH=0.6 mm PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
GND MIN_NECK_WIDTH=0.2 mm AGREES TO THE FOLLOWING
VOLTAGE=1.5V
22 16 7 PP1V05_S0_MCP_PEX_AVDD PP1V05_S0_MCP_PEX_AVDD 7 16 22 MAKE_BASE=TRUE I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
MAKE_BASE=TRUE
PP1V5_S3 6 7 26 27 28 63 68 II NOT TO REPRODUCE OR COPY IT
21 19 17 16 13 12 11 10 9 7 6 PP1V05_S0 PP1V05_S0 6 7 9 10 11 12 13 16 17 19 21 PP1V5_S3 6 7 26 27 28 63 68 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
67 66 65 61 35 23 22 22 23 35 61 65 66 67
GND PP1V5_S3 6 7 26 27 28 63 68
SIZE DRAWING NUMBER REV.
PP1V5_S3 6 7 26 27 28 63 68

22 19 7 PP1V05_S0_MCP_SATA_AVDD
MAKE_BASE=TRUE
PP1V05_S0_MCP_SATA_AVDD 7 19 22 PP1V5_S3 6 7 26 27 28 63 68 D 051-7903 A
GND APPLE INC. SCALE SHT OF
NONE 7 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
Board Mounting Holes CPU Thermal Module Holes CPU Signals USB Signals
(Not to scale) ZT0985
61 8 IN TP_IMVP6_CLKEN_L TP_IMVP6_CLKEN_L 8 61 78 19 8 BI NC_USB_EXTCP NC_USB_EXTCP 8 19 78
STDOFF-4.5OD.98H-1.1-3.48-TH MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
ZT0965 ZT0960 75 10 IN CPU_VID<0..6> IMVP6_VID<0..6> OUT 61 75 78 19 8 BI NC_USB_EXTCN NC_USB_EXTCN 8 19 78
HOLE-VIA-P5RP25 3R2P5 MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
1 1 75 9 IN CPU_BSEL<0..2> =MCP_BSEL<0..2> OUT 13
MAKE_BASE=TRUE 78 19 8 BI NC_USB_EXTDP NC_USB_EXTDP 8 19 78
MAKE_BASE=TRUE NO_TEST=TRUE

1
ZT0986 ZT0981 13 8 BI TP_CPU_PECI_MCP TP_CPU_PECI_MCP
MAKE_BASE=TRUE
8 13
NC_USB_EXTDN NC_USB_EXTDN
STDOFF-4.5OD.98H-1.1-3.48-TH STDOFF-4.5OD.98H-1.1-3.48-TH 78 19 8 BI
MAKE_BASE=TRUE NO_TEST=TRUE
8 19 78

1 1
NC_USB_MINIP NC_USB_MINIP
PEG Signals 78 19 8 BI
MAKE_BASE=TRUE NO_TEST=TRUE
8 19 78

ZT0950 NC_USB_MININ NC_USB_MININ

ZT0942 ZT0940 NC_PEG_CLK100MP NC_PEG_CLK100MP 78 19 8 BI
MAKE_BASE=TRUE NO_TEST=TRUE
8 19 78

D
D TH
1 3R2P5 3R2P5
77 16 8 IN

NC_PEG_CLK100MN
MAKE_BASE=TRUE
NC_PEG_CLK100MN
NO_TEST=TRUE
8 16 77

NC_USB_EXCARDP NC_USB_EXCARDP
SL-3.1X2.7-6CIR-NSP
1 1
MCP Thermal Module Holes 77 16 8 IN
MAKE_BASE=TRUE NO_TEST=TRUE
8 16 77 78 19 8 BI
MAKE_BASE=TRUE NO_TEST=TRUE
8 19 78

78 19 8 NC_USB_EXCARDN NC_USB_EXCARDN 8 19 78
ZT0930 ZT0982 IN =PEG_R2D_C_P<0..15> NC_PEG_R2DCP<0..15>
MAKE_BASE=TRUE NO_TEST=TRUE
16
BI
MAKE_BASE=TRUE NO_TEST=TRUE
STDOFF-4.5OD.98H-1.1-3.48-TH STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0915 =PEG_R2D_C_N<0..15> NC_PEG_R2DCN<0..15> 16
ZT0990 3R2P5 ZT0945 1 1 IN
MAKE_BASE=TRUE NO_TEST=TRUE
Audio Signals
3R2P5 1 HOLE-VIA-P5RP25
1 16 NC_PEG_D2RP<0..15> =PEG_D2R_P<0..15> OUT
1 MAKE_BASE=TRUE NO_TEST=TRUE AUD_IPHS_SWITCH_EN

1
58 18 IN
16 NC_PEG_D2RN<0..15> =PEG_D2R_N<0..15> OUT
(ORIGIN) MAKE_BASE=TRUE NO_TEST=TRUE 1
R0902
16 8 TP_PEG_PRSNT_L TP_PEG_PRSNT_L OUT 8 16 10K
NOTE: VIAs represent non-plated holes with ground rings. ZT0984 MAKE_BASE=TRUE
(Internal pull-up)
5%
1/16W
Place VIAs in corresponding hole’s ground ring. STDOFF-4.5OD.98H-1.1-3.48-TH MF-LF
2 402
PCIe Signals
Left Speaker Standoffs 77 16 8 IN NC_PCIE_CLK100M_EXCARDP NC_PCIE_CLK100M_EXCARDP 8 16 77
MAKE_BASE=TRUE NO_TEST=TRUE
ZT0934 NC_PCIE_CLK100M_EXCARDN NC_PCIE_CLK100M_EXCARDN
STDOFF-4.0OD3.0H-TH Fan Screw Hole 77 16 8 IN
MAKE_BASE=TRUE NO_TEST=TRUE
8 16 77

(UPPER)
1
ZT0988 16 8 TP_EXCARD_CLKREQ_L TP_EXCARD_CLKREQ_L 8 16
XW0901
SM
OUT
STDOFF-4.5OD.98H-1.1-3.48-TH MAKE_BASE=TRUE
(Internal pull-up) 53 51 49 41 39 38 37 29 7 6 PP5V_S3 2 1 PP5V_S3_AUDIO_AMP 56
68 63 62 MIN_LINE_WIDTH=0.5 mm
ZT0935 1 77 16 8 IN NC_PCIE_EXCARD_R2DCP NC_PCIE_EXCARD_R2DCP
MAKE_BASE=TRUE NO_TEST=TRUE
8 16 77 MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V
STDOFF-4.0OD3.0H-TH
77 16 8 IN NC_PCIE_EXCARD_R2DCN NC_PCIE_EXCARD_R2DCN 8 16 77
1 MAKE_BASE=TRUE NO_TEST=TRUE
(LOWER)
NC_PCIE_EXCARD_D2RP NC_PCIE_EXCARD_D2RP
77 16 8
MAKE_BASE=TRUE NO_TEST=TRUE
OUT 8 16 77
Ethernet Signals
77 16 8 NC_PCIE_EXCARD_D2RN NC_PCIE_EXCARD_D2RN OUT 8 16 77
MAKE_BASE=TRUE NO_TEST=TRUE 32 20 8 IN PM_SLP_RMGT_L PM_SLP_RMGT_L OUT 8 20 32

C 16 8 TP_PCIE_EXCARD_PRSNT_L
MAKE_BASE=TRUE
TP_PCIE_EXCARD_PRSNT_L OUT 8 16
MAKE_BASE=TRUE
PM_SLP_RMGT_L OUT 8 20 32
C
(Internal pull-up)
31 8 IN NC_RTL8211_REGOUT NC_RTL8211_REGOUT 8 31
PCIE_FW_PRSNT_L OUT 16 35 MAKE_BASE=TRUE NO_TEST=TRUE
I/O Row Pogos 1NOSTUFF 31 8 RTL8211_VDDREG RTL8211_VDDREG 8 31
R0925 MAKE_BASE=TRUE
SH0914
1.4DIA-SHORT-EMI-MLB-M97-M98
CPU Pogo 0
5% IN GND
SM 1/16W
SH0903 MF-LF
2 402
1 2.0DIA-TALL-EMI-MLB-M97-M98
(Ethernet) SM
17 8 MCP_MII_PD MCP_MII_PD OUT 8 17
1 MAKE_BASE=TRUE
SH0913 MCP_MII_PD OUT 8 17
1 MCP_MII_PD
1.4DIA-SHORT-EMI-MLB-M97-M98 R0930 OUT 8 17
SM LVDS Signals 5%
47K
1 1/16W
(FW800) 77 69 17 8 IN LVDS_CONN_A_CLK_P LVDS_CONN_A_CLK_P OUT 8 17 69 77 MF-LF
MAKE_BASE=TRUE 2 402
77 69 17 8 IN LVDS_CONN_A_CLK_N LVDS_CONN_A_CLK_N OUT 8 17 69 77
SH0912
1.4DIA-SHORT-EMI-MLB-M97-M98
SO-DIMM Pogos MAKE_BASE=TRUE

SM 77 17 IN LVDS_IG_A_DATA_P<0..2> LVDS_CONN_A_DATA_P<0..2> OUT 6 69

SH0900 SH0902 MAKE_BASE=TRUE
1 2.0DIA-TALL-EMI-MLB-M97-M98 2.0DIA-TALL-EMI-MLB-M97-M98 77 17 IN LVDS_IG_A_DATA_N<0..2> LVDS_CONN_A_DATA_N<0..2> OUT 6 69 31 8 IN RTL8211_CLK125 RTL8211_CLK125
(Mini-DP) SM SM MAKE_BASE=TRUE MAKE_BASE=TRUE
1 1 77 17 8 IN NC_LVDS_IG_A_DATAP<3> NC_LVDS_IG_A_DATAP<3> 8 17 77
1
R0931
SH0911 MAKE_BASE=TRUE NO_TEST=TRUE
22
1.4DIA-SHORT-EMI-MLB-M97-M98 77 17 8 IN NC_LVDS_IG_A_DATAN<3> NC_LVDS_IG_A_DATAN<3> 8 17 77 5%
SM (LEFT) (RIGHT) MAKE_BASE=TRUE NO_TEST=TRUE 1/16W
MF-LF
1 2 402
(Upper USB) 77 69 17 8 LVDS_CONN_B_CLK_P LVDS_CONN_B_CLK_P 8 17 69 77

B Other Board Pogos 77 69 17 8

IN

IN LVDS_CONN_B_CLK_N
MAKE_BASE=TRUE
LVDS_CONN_B_CLK_N
OUT

OUT 8 17 69 77
B
SH0910 MAKE_BASE=TRUE
1.4DIA-SHORT-EMI-MLB-M97-M98 SH0905 SH0906 LVDS_IG_B_DATA_P<0..2> LVDS_CONN_B_DATA_P<0..2>
SM 2.0DIA-TALL-EMI-MLB-M97-M98 2.0DIA-TALL-EMI-MLB-M97-M98
77 17 IN
MAKE_BASE=TRUE OUT 6 69
Power Signals
1 SM SM 77 17 LVDS_IG_B_DATA_N<0..2> LVDS_CONN_B_DATA_N<0..2> 6 69
IN OUT SMC_PM_G2_EN SMC_PM_G2_EN
(Lower USB) 1 1
MAKE_BASE=TRUE 67 62 40 8 6 IN OUT 6 8 40 62 67
MAKE_BASE=TRUE
77 17 8 IN NC_LVDS_IG_B_DATAP<3> NC_LVDS_IG_B_DATAP<3> 8 17 77
SH0915 (Near BIL Connector) (Near IPD Connector)
MAKE_BASE=TRUE NO_TEST=TRUE
1.4DIA-SHORT-EMI-MLB-M97-M98 77 17 8 IN NC_LVDS_IG_B_DATAN<3> NC_LVDS_IG_B_DATAN<3>
MAKE_BASE=TRUE NO_TEST=TRUE
8 17 77 GMUX Signals
SM
16 8 IN TP_GMUX_JTAG_TCK_L TP_GMUX_JTAG_TCK_L 8 16
1 73 17 8 IN LVDS_BKL_ON LVDS_BKL_ON OUT 8 17 73 MAKE_BASE=TRUE
(SD Card) MAKE_BASE=TRUE
TP_GMUX_JTAG_TDI TP_GMUX_JTAG_TDI
18 8 IN 8 18
74 73 72 17 8 IN LCD_BKLT_PWM LCD_BKLT_PWM OUT 8 17 72 73 74 MAKE_BASE=TRUE
MAKE_BASE=TRUE
SH0916 18 8 IN TP_GMUX_JTAG_TMS TP_GMUX_JTAG_TMS 8 18
69 17 8 IN LCD_PWR_EN LCD_PWR_EN OUT 8 17 69 MAKE_BASE=TRUE
1.4DIA-SHORT-EMI-MLB-M97-M98 MAKE_BASE=TRUE
TP_GMUX_JTAG_TDO TP_GMUX_JTAG_TDO
16 8 OUT 8 16
SM MAKE_BASE=TRUE
69 17 8 6 IN LVDS_DDC_CLK LVDS_DDC_CLK OUT 6 8 17 69
1 GND_CHASSIS_AUDIO_JACK 57 MAKE_BASE=TRUE 17 8 MCP_HPLUG_DET2 MCP_HPLUG_DET2 OUT 8 17
(Audio) LVDS_DDC_DATA LVDS_DDC_DATA MAKE_BASE=TRUE
69 17 8 6 BI BI 6 8 17 69
MAKE_BASE=TRUE 1
R0920
20K
5%
DisplayPort Signals 1/16W
MF-LF
Bosses (Aliases on page70.csa) 2 402

Digital Ground ZT0951

4.0OD1.85H-M1.6X0.35
ZT0952
4.0OD1.85H-M1.6X0.35
FireWire Signals Signal Aliases
GND_BATT_CHGND 6 59 35 34 8 IN FW643_WAKE_L FW643_WAKE_L 8 34 35
1 1 SYNC_MASTER=WFERRY_K19I SYNC_DATE=01/13/2009
A GND
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
35 18 8 IN FW_PLUG_DET_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
FW_PLUG_DET_L OUT 8 18 35
NOTICE OF PROPRIETARY PROPERTY
A
VOLTAGE=0V (Keyboard Protector) (IPD Protector)
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
Memory Signals AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
68 63 24 8 IN MEM_VTT_EN MEM_VTT_EN OUT 8 24 63 68
MAKE_BASE=TRUE II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
26 8 NC_MEM_A_A<15> NC_MEM_A_A<15> OUT 8 26
MAKE_BASE=TRUE NO_TEST=TRUE
SIZE DRAWING NUMBER REV.
27 8 NC_MEM_B_A<15> NC_MEM_B_A<15> OUT 8 27
MAKE_BASE=TRUE NO_TEST=TRUE
D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 8 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
OMIT

75 13 6 BI FSB_A_L<3> J4 A3* U1000 ADS* H1 FSB_ADS_L BI 6 13 75

75 13 6 BI FSB_A_L<4> L5 A4* PENRYN BNR* E2 FSB_BNR_L BI 13 75

FSB_A_L<5> L4 FCBGA G5 FSB_BPRI_L

75 13 6 BI A5* BPRI* BI 13 75
1 OF 4 PP1V05_S0 6 7 10 11 12 13 16 17 19 21 22
75 13 6 BI FSB_A_L<6> K5 A6* 23 35 61 65 66 67

75 13 6 BI FSB_A_L<7> M3 A7* DEFER* H5 FSB_DEFER_L BI 13 75

75 13 6 BI FSB_A_L<8> N2 A8* DRDY* F21 FSB_DRDY_L BI 13 75

1
75 13 6 FSB_A_L<9> J1 A9* DBSY* E1 FSB_DBSY_L 13 75
R1000
BI BI
54.9
75 13 6 BI FSB_A_L<10> N3 A10* 1%

ADDR GROUP0
1/16W
75 13 6 BI FSB_A_L<11> P5 A11* BR0* F1 FSB_BREQ0_L BI 13 75 MF-LF
402

CONTROL
FSB_A_L<12> P2 A12* 2
75 13 6 BI

D 75 13 6

75 13 6
BI
BI
FSB_A_L<13>
FSB_A_L<14>
L2

P4
A13*
A14*
IERR*
INIT*
D20

B3
75 CPU_IERR_L
CPU_INIT_L IN 13 75
D
75 13 6 BI FSB_A_L<15> P1 A15*
75 13 6 BI FSB_A_L<16> R1 A16* LOCK* H4 FSB_LOCK_L BI 6 13 75

75 13 6 BI FSB_ADSTB_L<0> M1 ADSTB0*

RESET* C1 FSB_CPURST_L IN 12 13 75

75 13 6 BI FSB_REQ_L<0> K3 REQ0* RS0* F3 FSB_RS_L<0> IN 13 75

75 13 6 BI FSB_REQ_L<1> H2 REQ1* RS1* F4 FSB_RS_L<1> IN 13 75

75 13 6 BI FSB_REQ_L<2> K2 REQ2* RS2* G3 FSB_RS_L<2> IN 13 75

75 13 6 BI FSB_REQ_L<3> J3 REQ3* TRDY* G2 FSB_TRDY_L IN 13 75

75 13 6 BI FSB_REQ_L<4> L1 REQ4*

HIT* G6 FSB_HIT_L BI 6 13 75
OMIT
75 13 6 BI FSB_A_L<17> Y2 A17* HITM* E4 FSB_HITM_L BI 6 13 75

75 13 6 BI FSB_A_L<18> U5 A18* 75 13 6 BI FSB_D_L<0> E22 D0* U1000 D32* Y22 FSB_D_L<32> BI 6 13 75

75 13 6 BI FSB_A_L<19> R3 A19* BPM0* AD4 XDP_BPM_L<0> BI 12 75 75 13 6 BI FSB_D_L<1> F24 D1* PENRYN D33* AB24 FSB_D_L<33> BI 6 13 75

75 13 6 FSB_A_L<20> W6 A20* BPM1* AD3 XDP_BPM_L<1> 12 75

R1001 1 75 13 6 FSB_D_L<2> E26 D2* FCBGA D34* V24 FSB_D_L<34> 6 13 75
BI BI 54.9 BI BI

XDP/ITP SIGNALS
75 13 6 BI FSB_A_L<21> U4 A21* BPM2* AD1 XDP_BPM_L<2> BI 12 75 1% 75 13 6 BI FSB_D_L<3> G22 D3* 2 OF 4 D35* V26 FSB_D_L<35> BI 6 13 75

75 13 6 FSB_A_L<22> Y5 A22* ADDR GROUP1 BPM3* AC4 XDP_BPM_L<3> 12 75

1/16W
MF-LF 75 13 6 FSB_D_L<4> F23 D4* D36* V23 FSB_D_L<36> 6 13 75
BI BI BI BI
402
FSB_A_L<23> U1 A23* PRDY* AC2 XDP_BPM_L<4> 2 FSB_D_L<5> T22 FSB_D_L<37>
75 13 6 BI BI 12 75 75 13 6 BI G25 D5* D37* BI 6 13 75

75 13 6 BI FSB_A_L<24> R4 A24* PREQ* AC1 XDP_BPM_L<5> BI 12 75 75 13 6 BI FSB_D_L<6> E25 D6* D38* U25 FSB_D_L<38> BI 6 13 75

75 13 6 BI FSB_A_L<25> T5 A25* TCK AC5 XDP_TCK IN 9 12 75 75 13 6 BI FSB_D_L<7> E23 D7* D39* U23 FSB_D_L<39> BI 6 13 75

75 13 6 BI FSB_A_L<26> T3 A26* TDI AA6 XDP_TDI IN 9 12 75 75 13 6 BI FSB_D_L<8> K24 D8* D40* Y25 FSB_D_L<40> BI 6 13 75

75 13 6 BI FSB_A_L<27> W2 A27* TDO AB3 XDP_TDO OUT 1 9 12 75 75 13 6 BI FSB_D_L<9> G24 D9* D41* W22 FSB_D_L<41> BI 6 13 75

DATA GRP 0

DATA GRP 2
75 13 6 BI FSB_A_L<28> W5 A28* TMS AB5 XDP_TMS IN 9 12 75 75 13 6 BI FSB_D_L<10> J24 D10* D42* Y23 FSB_D_L<42> BI 6 13 75

75 13 6 BI FSB_A_L<29> Y4 A29* TRST* AB6 XDP_TRST_L IN 9 12 75 75 13 6 BI FSB_D_L<11> J23 D11* D43* W24 FSB_D_L<43> BI 6 13 75

75 13 6 BI FSB_A_L<30> U2 A30* DBR* C20 XDP_DBRESET_L OUT 12 24 75 13 6 BI FSB_D_L<12> H22 D12* D44* W25 FSB_D_L<44> BI 6 13 75

C 75 13 6

75 13
BI FSB_A_L<31>
FSB_A_L<32>
V4

W3
A31*
A32*
R1002 1
5%
68
75 13 6

75 13 6
BI FSB_D_L<13>
FSB_D_L<14>
F26
K22
D13*
D14*
D45*
D46*
AA23

AA24
FSB_D_L<45>
FSB_D_L<46>
BI 6 13 75

6 13 75
C
BI BI BI
1/16W
75 13 FSB_A_L<33> AA4 A33* THERMAL MF-LF 75 13 6 FSB_D_L<15> H23 D15* D47* AB25 FSB_D_L<47> 6 13 75
BI BI BI
402
FSB_A_L<34> AB2 2 FSB_DSTB_L_N<0> Y26 FSB_DSTB_L_N<2>
75 13 BI A34* 75 13 6 BI J26 DSTBN0* DSTBN2* BI 6 13 75

75 13 BI FSB_A_L<35> AA3 A35* PROCHOT* D21 CPU_PROCHOT_L OUT 13 41 61 75 75 13 6 BI FSB_DSTB_L_P<0> H26 DSTBP0* DSTBP2* AA26 FSB_DSTB_L_P<2> BI 6 13 75

75 13 6 BI FSB_ADSTB_L<1> V1 ADSTB1* THERMDA A24 CPU_THERMD_P OUT 46 82 75 13 6 BI FSB_DINV_L<0> H25 DINV0* DINV2* U22 FSB_DINV_L<2> BI 6 13 75

THERMDC B25 CPU_THERMD_N OUT 46 82

75 13 IN CPU_A20M_L A6 A20M*
OUT CPU_FERR_L PM_THRMTRIP_L FSB_D_L<16> FSB_D_L<48>
75 13 A5 FERR* THERMTRIP* C7 13 41 75 75 13 6 N22 D16* D48* AE24 6 13 75
OUT BI BI
IN CPU_IGNNE_L FSB_D_L<17> FSB_D_L<49>
75 13 C4 IGNNE* 75 13 6 K25 D17* D49* AD24 6 13 75
BI BI
ICH

75 13 6 BI FSB_D_L<18> P26 D18* D50* AA21 FSB_D_L<50> BI 6 13 75

H CLK
75 13 IN CPU_STPCLK_L D5 STPCLK* 75 13 6 BI FSB_D_L<19> R23 D19* D51* AB22 FSB_D_L<51> BI 6 13 75

75 13 IN CPU_INTR C6 LINT0 75 13 6 BI FSB_D_L<20> L23 D20* D52* AB21 FSB_D_L<52> BI 6 13 75

75 13 IN CPU_NMI B4 LINT1 BCLK0 A22 FSB_CLK_CPU_P IN 13 75 75 13 6 BI FSB_D_L<21> M24 D21* D53* AC26 FSB_D_L<53> BI 6 13 75

75 13 IN CPU_SMI_L A3 SMI* BCLK1 A21 FSB_CLK_CPU_N IN 13 75 75 13 6 BI FSB_D_L<22> L22 D22* D54* AD20 FSB_D_L<54> BI 6 13 75

75 13 6 BI FSB_D_L<23> M23 D23* D55* AE22 FSB_D_L<55> BI 6 13 75

DATA GRP 1

DATA GRP 3
TP_CPU_RSVD_M4 M4 RSVD0 75 13 6 BI FSB_D_L<24> P25 D24* D56* AF23 FSB_D_L<56> BI 6 13 75

TP_CPU_RSVD_N5 N5 RSVD1 75 13 6 BI FSB_D_L<25> P23 D25* D57* AC25 FSB_D_L<57> BI 6 13 75

TP_CPU_RSVD_T2 T2 RSVD2 75 13 6 BI FSB_D_L<26> P22 D26* D58* AE21 FSB_D_L<58> BI 6 13 75

TP_CPU_RSVD_V3 V3 RSVD3 75 13 6 BI FSB_D_L<27> T24 D27* D59* AD21 FSB_D_L<59> BI 6 13 75

RESERVED

TP_CPU_RSVD_B2 B2 RSVD4 75 13 6 BI FSB_D_L<28> R24 D28* D60* AC22 FSB_D_L<60> BI 6 13 75

TP_CPU_RSVD_F6 F6 RSVD5 75 13 6 BI FSB_D_L<29> L25 D29* D61* AD23 FSB_D_L<61> BI 6 13 75

TP_CPU_RSVD_D2 D2 RSVD6 75 13 6 BI FSB_D_L<30> T25 D30* D62* AF22 FSB_D_L<62> BI 6 13 75

TP_CPU_RSVD_D22 D22 RSVD7 1

75 13 6 BI FSB_D_L<31> N25 D31* D63* AC23 FSB_D_L<63> BI 6 13 75

TP_CPU_RSVD_D3 D3 RSVD8 R1005 75 13 6 BI FSB_DSTB_L_N<1> L26 DSTBN1* DSTBN3* AE25 FSB_DSTB_L_N<3> BI 6 13 75

1K
CPU JTAG Support 1%
1/16W
75 13 6 BI FSB_DSTB_L_P<1> M26 DSTBP1* DSTBP3* AF24 FSB_DSTB_L_P<3> BI 6 13 75

B R1090 2
MF-LF
402
75 13 6 BI FSB_DINV_L<1> N24 DINV1* DINV3* AC20 FSB_DINV_L<3> BI 6 13 75
B
54.9
75 12 9 XDP_TMS 1 2 CPU_GTLREF
75 25 AD26 GTLREF COMP0 R26 75 CPU_COMP<0>
MISC
1% CPU_TEST1 C23 TEST1 COMP1 U26 75 CPU_COMP<1>
1/16W
R1091 1 CPU_TEST2 D25 TEST2 COMP2 AA1 CPU_COMP<2>
54.9
MF-LF
402 R1006 75

75 12 9 XDP_TDI 1 2 2.0K TP_CPU_TEST3 C24 TEST3 COMP3 Y1 75 CPU_COMP<3>

1%
1% 1/16W CPU_TEST4 AF26 TEST4
1/16W
MF-LF R1092 MF-LF
NO STUFF TP_CPU_TEST5 AF1 TEST5 DPRSTP* E5 CPU_DPRSTP_L R1023 1 R1021 1
402 54.9 2 402 IN 13 61 75

75 12 9 1 XDP_TDO 1 2 C1014 1 TP_CPU_TEST6 A26 TEST6 DPSLP* B5 CPU_DPSLP_L IN 13 75 54.9 54.9

1% 1%
PLACEMENT_NOTE=Place R1092 near ITP connector (if present) 1% NO STUFF 0.1uF TP_CPU_TEST7 C3 TEST7 DPWR* D24 FSB_DPWR_L 13 75 1/16W 1/16W
1/16W 10% IN
16V MF-LF MF-LF
OUT CPU_BSEL<0> CPU_PWRGD
MF-LF B22 BSEL0 PWRGOOD D6
402 R1010 X5R
402
2 75 8 IN 12 13 75 402
2
402
2
OUT CPU_BSEL<1> FSB_CPUSLP_L
0 75 8 B23 BSEL1 SLP* D7 13 75
1 2 IN
OUT CPU_BSEL<2> CPU_PSI_L
75 8 C21 BSEL2 PSI* AE6 61
OUT 1 1
NO STUFF 5% NO STUFF R1022 R1020
1/16W
R1093 R1011 1 MF-LF
402
1
R1012 27.4
1%
27.4
1%
54.9 1K 1K PLACEMENT_NOTE=Place C1014 within 12.7mm of CPU. 1/16W 1/16W
75 12 9 XDP_TCK 1 2 5% 5% MF-LF MF-LF
1/16W 1/16W PLACEMENT_NOTE=Place R1005 within 12.7mm of CPU. 2
402
2
402
1% MF-LF MF-LF
R1094 1/16W 402 2 2 402 PLACEMENT_NOTE=Place R1006 within 12.7mm of CPU.
MF-LF
649 402
75 12 9 XDP_TRST_L 1 2 PLACEMENT_NOTE (all 4 resistors):
1%
1/16W Place within 12.7mm of CPU
MF-LF
402

CPU FSB
A SYNC_MASTER=K24_MLB

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=02/05/2009
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

SYNC FROM T18 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

CHANGE CPU FROM SOCKET TO BGA SYMBOL III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 9 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

A4 P6

(CPU CORE POWER) A8 P21

A11
OMIT
P24
PPVCORE_S0_CPU 6 7 10 11 44 61
A14
U1000 R2

44 A (SV Design Target) A16

PENRYN R5
FCBGA
41 A (SV HFM) A19 R22

D A7 AB20 30.4 A (SV LFM) A23

4 OF 4
R25 D
A9 OMIT AB7 23 A (LV Design Target) AF2 T1
A10 AC7 B6 T4
U1000
A12 AC9 B8 T23
PENRYN
A13 FCBGA AC12 B11 T26

A15 AC13 B13 U3

3 OF 4
A17 AC15 B16 U6

A18 AC17 B19 U21

A20 AC18 B21 U24

B7 AD7 B24 V2

B9 AD9 C5 V5
B10 AD10 C8 V22
B12 AD12 C11 V25

B14 AD14 C14 W1

B15 AD15 C16 W4
B17 AD17 C19 W23

B18 AD18 C2 W26

B20 AE9 C22 Y3
VCC
C9 AE10 C25 Y6
C10 AE12 D1 Y21

C12 AE13 D4 Y24

C13 AE15 D8 AA2

C15 AE17 D11 AA5

C17 AE18 D13 AA8

C18 AE20 D16 AA11

D9 AF9 D19 AA14

C D10

D12
AF10

AF12
D23

D26
AA16

AA19
C
D14 AF14 E3 AA22

D15 VCC AF15 E6 AA25

D17 AF17 E8 AB1

D18 AF18 E11 AB4

AF20
(CPU IO POWER 1.05V)
E7 E14 VSS VSS AB8
E9 PP1V05_S0 6 7 9 11 12 13 16 17 19 21 22 E16 AB11
23 35 61 65 66 67
E10 G21 E19 AB13

E12 V6
4500 mA (before VCC stable)
E21 AB16
E13 J6
2500 mA (after VCC stable)
E24 AB19

E15 K6 F5 AB23

E17 M6 F8 AB26
E18 J21 F11 AC3

E20 K21 F13 AC6

F7 M21 F16 AC8
VCCP
F9 N21 F19 AC11
F10 N6 F2 AC14
F12 R21 F22 AC16
F14 R6 F25 AC19

F15 T21 G4 AC21

F17 T6 G1 AC24
F18 V21 G23 AD2
(CPU INTERNAL PLL POWER 1.5V)
F20 W21 G26 AD5

AA7 (BR1#) PP1V5_S0 6 7 11 15 22 37 66 67 68 82 H3 AD8

AA9 B26 H6 AD11

AA10 VCCA C26
130 mA H21 AD13

B AA12 H24 AD16 B

AA13 VID0 AD6 CPU_VID<0> OUT 8 75 J2 AD19
AA15 VID1 AF5 CPU_VID<1> OUT 8 75 J5 AD22

AA17 VID2 AE5 CPU_VID<2> OUT 8 75 J22 AD25

PPVCORE_S0_CPU 6 7 10 11 44 61
AA18 VID3 AF4 CPU_VID<3> OUT 8 75 J25 AE1
AA20 VID4 AE3 CPU_VID<4> OUT 8 75 K1 AE4
1
AB9 VID5 AF3 CPU_VID<5> 8 75
R1100 K4 AE8
OUT 100
AC10 VID6 AE2 CPU_VID<6> OUT 8 75 1% K23 AE11
1/16W
AB10 MF-LF K26 AE14
402
AB12 2 L3 AE16
AB14 VCCSENSE AF7 CPU_VCCSENSE_P OUT 61 75 L6 AE19
AB15 L21 AE23
PLACEMENT_NOTE=Place R1100 within 25.4mm of CPU, no stubs.
AB17 PLACEMENT_NOTE=Place R1101 within 25.4mm of CPU, no stubs. L24 AE26
AB18 VSSSENSE AE7 CPU_VCCSENSE_N OUT 61 75 M2 A2
M5 AF6
1 M22 AF8
R1101
100 M25 AF11
1%
1/16W N1 AF13
MF-LF
402 N4 AF16
2
N23 AF19
N26 AF21
P3 A25
B1 (Socket-P KEY) AF25

CPU Power & Ground

A SYNC_MASTER=K24_MLB

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=02/05/2009
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
SYNC FROM T18 AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

CHANGE CPU FROM SOCKET TO BGA SYMBOL II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 10 83
Current numbers from Merom for Santa Rosa EMTS, doc #20905.

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

CPU VCore HF and Bulk Decoupling

4X 330UF. 20X 22UF 0805

PLACEMENT_NOTE (C1200-C1219):
61 44 10 7 6 PPVCORE_S0_CPU
Place inside socket cavity on secondary side.
D CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
D
1 1 1 1 1 1 1 1 1 1
C1200 C1201 C1202 C1203 C1204 C1205 C1206 C1207 C1208 C1209
22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R
805 805 805 805 805 805 805 805 805 805

CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1
C1210 1
C1211 1
C1212 1
C1213 1
C1214 1
C1215 1
C1216 1
C1217 1
C1218 1
C1219
22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R
805 805 805 805 805 805 805 805 805 805

C C
PLACEMENT_NOTE (C1240-C1243):

Place on secondary side. Place on secondary side.

CRITICAL CRITICAL CRITICAL CRITICAL

NOSTUFF 1 1 1 1
C1240 C1241 C1242 C1243
470UF-4MOHM 470UF-4MOHM 470UF-4MOHM 470UF-4MOHM
20% 20% 20% 20%
3 2 2.0V 3 2 2.0V 3 2 2.0V 3 2 2.0V
POLY-TANT POLY-TANT POLY-TANT POLY-TANT
D2T-SM D2T-SM D2T-SM D2T-SM

Place on secondary side. Place on secondary side.

VCCA (CPU AVdd) DECOUPLING

1x 10uF, 1x 0.01uF
82 68 67 66 37 22 15 10 7 6 PP1V5_S0
PLACEMENT_NOTE=Place C1281 near CPU pin B26.

C1250 1 1
C1251
10uF 0.01UF
20% 10%
6.3V 16V
X5R 2 2 CERM
603 402

B B
VCCP (CPU I/O) DECOUPLING
1x 330uF, 6x 0.1uF 0402
22 21 19 17 16 13 12 10 9 7 6 PP1V05_S0
67 66 65 61 35 23 PLACEMENT_NOTE=Place C1260 between CPU & NB.

CRITICAL
C1260 1 1 C1261 1 C1262 1 C1263 1 C1264 1 C1265 1 C1266
330UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20% 20% 20%
2.0V 10V 10V 10V 10V 10V 10V
2 3 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
POLY-TANT
D2T-SM2 402 402 402 402 402 402

CPU Decoupling
A SYNC_MASTER=K24_MLB

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=02/05/2009
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

SYNC FROM T18 II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
REMOVE NO STUFF CAPS C1220 TO C1231 SIZE DRAWING NUMBER REV.
REMOVE C1244 & C1245 D 051-7903 A
CHANGE C1240-C1243 AND C1260 FROM 128S0241(9 MILLI-OHM) TO 128S0231(6 MILLI-OHM) APPLE INC. SCALE SHT OF
NONE 11 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

Mini-XDP Connector
NOTE: This is not the standard XDP pinout.

D Use with 920-0620 adapter board to support CPU, MCP debugging.

D

MCP79-specific pinout
82 72 71 69 68 67 66 61 58
27 26 23 22 21 20 18 17 7 6
57 53 49 47 46 45 43 41 37 35
PP3V3_S0
22 21 19 17 16 13 11 10 9 7 6
67 66 65 61 35 23
PP1V05_S0

XDP
CRITICAL
R13151 XDP_CONN
54.9 J1300
1%
1/16W LTH-030-01-G-D-NOPEGS
MF-LF F-ST-SM
402 2
2 1
75 9 XDP_BPM_L<5> OBSFN_A0 4 3 OBSFN_C0 JTAG_MCP_TDO 1 20
BI IN
75 9 XDP_BPM_L<4> OBSFN_A1 6 5 OBSFN_C1 JTAG_MCP_TRST_L 20
BI OUT
8 7
75 9 XDP_BPM_L<3> OBSDATA_A0 10 9 OBSDATA_C0 MCP_DEBUG<0> 18 78
BI BI
75 9 XDP_BPM_L<2> OBSDATA_A1 12 11 OBSDATA_C1 MCP_DEBUG<1> 18 78
IN BI
14 13
75 9 XDP_BPM_L<1> OBSDATA_A2 16 15 OBSDATA_C2 MCP_DEBUG<2> 18 78
IN BI
75 9 XDP_BPM_L<0> OBSDATA_A3 18 17 OBSDATA_C3 MCP_DEBUG<3> 18 78
IN BI
20 19
C TP_XDP_OBSFN_B0 OBSFN_B0 22 21 OBSFN_D0 JTAG_MCP_TDI OUT 20
C
TP_XDP_OBSFN_B1 OBSFN_B1 24 23 OBSFN_D1 JTAG_MCP_TMS 20
OUT
26 25
TP_XDP_OBSDATA_B0 OBSDATA_B0 28 27 OBSDATA_D0 MCP_DEBUG<4> 18 78
BI
TP_XDP_OBSDATA_B1 OBSDATA_B1 30 29 OBSDATA_D1 MCP_DEBUG<5> 18 78
BI
32 31
TP_XDP_OBSDATA_B2 OBSDATA_B2 34 33 OBSDATA_D2 MCP_DEBUG<6> 18 78
BI
XDP TP_XDP_OBSDATA_B3 36 35 MCP_DEBUG<7>
OBSDATA_B3 OBSDATA_D3 BI 18 78
R1399 38 37
1K 40 39
75 13 9 IN CPU_PWRGD 1 2 XDP_PWRGD PWRGD/HOOK0 ITPCLK/HOOK4 FSB_CLK_ITP_P IN 13 75

5% XDP_OBS20 42 41 FSB_CLK_ITP_N XDP

HOOK1 ITPCLK#/HOOK5 IN 13 75
1/16W
MF-LF VCC_OBS_AB 44 43 VCC_OBS_CD R1303
402
46 45 1K
18 IN PM_LATRIGGER_L HOOK2 RESET#/HOOK6 75 XDP_CPURST_L 1 2 FSB_CPURST_L IN 9 13 75

20 JTAG_MCP_TCK HOOK3 48 47 DBR#/HOOK7 XDP_DBRESET_L 9 24 5% PLACEMENT_NOTE=Place close to CPU to minimize stub.

OUT OUT 1/16W
50 49 NOTE: XDP_DBRESET_L must be pulled-up to 3.3V. MF-LF
52 51 402
78 43 26 20 BI SMBUS_MCP_0_DATA SDA TDO XDP_TDO IN 1 9 75

78 43 27 26 20 SMBUS_MCP_0_CLK SCL 54 53 TRSTn XDP_TRST_L 9 75

BI OUT
TCK1 56 55 TDI XDP_TDI
NC OUT 9 75

75 9 XDP_TCK TCK0 58 57 TMS XDP_TMS 9 75

OUT OUT
60 59 XDP_PRESENT#
XDP XDP
C1300 1 1 C1301
0.1uF 0.1uF
10% 10%
16V 2 2 16V
X5R X5R
402 402

B 998-1571 B

Direction of XDP module

Please avoid any obstructions
on even-numbered side of J1300

eXtended Debug Port(MiniXDP)

A SYNC_MASTER=K19_MLB

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=02/05/2009
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 12 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
OMIT
U1400
MCP79-TOPO-B
BGA
(1 OF 11)
75 9 6 BI FSB_DSTB_L_P<0> T40 CPU_DSTBP0# CPU_D0# Y43 FSB_D_L<0> BI 6 9 75

75 9 6 BI FSB_DSTB_L_N<0> U40 CPU_DSTBN0# CPU_D1# W42 FSB_D_L<1> BI 6 9 75

75 9 6 BI FSB_DINV_L<0> V41 CPU_DBI0# CPU_D2# Y40 FSB_D_L<2> BI 6 9 75

CPU_D3# W41 FSB_D_L<3> BI 6 9 75

75 9 6 BI FSB_DSTB_L_P<1> W39 CPU_DSTBP1#
CPU_D4# Y39 FSB_D_L<4> BI 6 9 75
75 9 6 BI FSB_DSTB_L_N<1> W37 CPU_DSTBN1#
CPU_D5# V42 FSB_D_L<5> BI 6 9 75
75 9 6 BI FSB_DINV_L<1> V35 CPU_DBI1#
CPU_D6# Y41 FSB_D_L<6> BI 6 9 75

D 75 9 6

75 9 6
BI
BI
FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>
N37 CPU_DSTBP2#
L36 CPU_DSTBN2#
CPU_D7#
CPU_D8#
Y42
P42
FSB_D_L<7>
FSB_D_L<8>
BI
BI
6 9 75

6 9 75
D
75 9 6 BI FSB_DINV_L<2> N35 CPU_DBI2# CPU_D9# U41 FSB_D_L<9> BI 6 9 75

CPU_D10# R42 FSB_D_L<10> BI 6 9 75

75 9 6 BI FSB_DSTB_L_P<3> M39 CPU_DSTBP3#
CPU_D11# T39 FSB_D_L<11> BI 6 9 75
75 9 6 BI FSB_DSTB_L_N<3> M41 CPU_DSTBN3#
CPU_D12# T42 FSB_D_L<12> BI 6 9 75
75 9 6 BI FSB_DINV_L<3> J41 CPU_DBI3#
CPU_D13# T41 FSB_D_L<13> BI 6 9 75

CPU_D14# R41 FSB_D_L<14> BI 6 9 75

75 9 6 BI FSB_A_L<3> AC34 CPU_A3#
CPU_D15# T43 FSB_D_L<15> BI 6 9 75
75 9 6 BI FSB_A_L<4> AE38 CPU_A4#
CPU_D16# W35 FSB_D_L<16> BI 6 9 75
75 9 6 BI FSB_A_L<5> AE34 CPU_A5#
CPU_D17# AA37 FSB_D_L<17> BI 6 9 75
75 9 6 BI FSB_A_L<6> AC37 CPU_A6#
CPU_D18# W33 FSB_D_L<18> BI 6 9 75
75 9 6 BI FSB_A_L<7> AE37 CPU_A7#
CPU_D19# W34 FSB_D_L<19> BI 6 9 75
75 9 6 BI FSB_A_L<8> AE35 CPU_A8#
CPU_D20# AA36 FSB_D_L<20> BI 6 9 75
75 9 6 BI FSB_A_L<9> AB35 CPU_A9#
CPU_D21# AA34 FSB_D_L<21> BI 6 9 75
75 9 6 BI FSB_A_L<10> AF35 CPU_A10#
CPU_D22# AA38 FSB_D_L<22> BI 6 9 75
75 9 6 BI FSB_A_L<11> AG35 CPU_A11#
CPU_D23# AA35 FSB_D_L<23> BI 6 9 75
75 9 6 BI FSB_A_L<12> AG39 CPU_A12#
CPU_D24# U38 FSB_D_L<24> BI 6 9 75
75 9 6 BI FSB_A_L<13> AE33 CPU_A13#
CPU_D25# U36 FSB_D_L<25> BI 6 9 75
75 9 6 BI FSB_A_L<14> AG37 CPU_A14#
CPU_D26# U35 FSB_D_L<26> BI 6 9 75
75 9 6 BI FSB_A_L<15> AG38 CPU_A15#
CPU_D27# U33 FSB_D_L<27> BI 6 9 75
75 9 6 BI FSB_A_L<16> AG34 CPU_A16#
CPU_D28# U34 FSB_D_L<28> BI 6 9 75
75 9 6 BI FSB_A_L<17> AN38 CPU_A17#
CPU_D29# W38 FSB_D_L<29> BI 6 9 75
75 9 6 BI FSB_A_L<18> AL39 CPU_A18#
CPU_D30# R33 FSB_D_L<30> BI 6 9 75
75 9 6 BI FSB_A_L<19> AG33 CPU_A19#
CPU_D31# U37 FSB_D_L<31> BI 6 9 75
75 9 6 BI FSB_A_L<20> AL33 CPU_A20#
CPU_D32# N34 FSB_D_L<32> BI 6 9 75
75 9 6 BI FSB_A_L<21> AJ33 CPU_A21#
CPU_D33# N33 FSB_D_L<33> BI 6 9 75
FSB_A_L<22> AN36
C 75 9 6

75 9 6
BI
BI FSB_A_L<23> AJ35
CPU_A22#
CPU_A23#
CPU_D34#
CPU_D35#
R34
R35
FSB_D_L<34>
FSB_D_L<35>
BI 6 9 75 C

FSB
BI 6 9 75
75 9 6 BI FSB_A_L<24> AJ37 CPU_A24#
CPU_D36# P35 FSB_D_L<36> BI 6 9 75
75 9 6 BI FSB_A_L<25> AJ36 CPU_A25#
CPU_D37# R39 FSB_D_L<37> BI 6 9 75
75 9 6 BI FSB_A_L<26> AJ38 CPU_A26#
CPU_D38# R37 FSB_D_L<38> BI 6 9 75
75 9 6 BI FSB_A_L<27> AL37 CPU_A27#
CPU_D39# R38 FSB_D_L<39> BI 6 9 75
75 9 6 BI FSB_A_L<28> AL34 CPU_A28#
CPU_D40# L37 FSB_D_L<40> BI 6 9 75
75 9 6 BI FSB_A_L<29> AN37 CPU_A29#
CPU_D41# L39 FSB_D_L<41> BI 6 9 75
75 9 6 BI FSB_A_L<30> AJ34 CPU_A30#
CPU_D42# L38 FSB_D_L<42> BI 6 9 75
75 9 6 BI FSB_A_L<31> AL38 CPU_A31#
CPU_D43# N36 FSB_D_L<43> BI 6 9 75
75 9 BI FSB_A_L<32> AL35 CPU_A32#
CPU_D44# N38 FSB_D_L<44> BI 6 9 75
75 9 BI FSB_A_L<33> AN34 CPU_A33#
CPU_D45# J39 FSB_D_L<45> BI 6 9 75
75 9 BI FSB_A_L<34> AR39 CPU_A34#
CPU_D46# J38 FSB_D_L<46> BI 6 9 75
75 9 BI FSB_A_L<35> AN35 CPU_A35#
CPU_D47# J37 FSB_D_L<47> BI 6 9 75

75 9 6 BI FSB_ADSTB_L<0> AE36 CPU_ADSTB0# CPU_D48# L42 FSB_D_L<48> BI 6 9 75

75 9 6 BI FSB_ADSTB_L<1> AK35 CPU_ADSTB1# CPU_D49# M42 FSB_D_L<49> BI 6 9 75

CPU_D50# P41 FSB_D_L<50> BI 6 9 75

75 9 6 BI FSB_REQ_L<0> AC38 CPU_REQ0# CPU_D51# N41 FSB_D_L<51> BI 6 9 75

75 9 6 BI FSB_REQ_L<1> AA33 CPU_REQ1# CPU_D52# N40 FSB_D_L<52> BI 6 9 75

21 19 17 16 13 12 11 10 9 7 6 PP1V05_S0
67 66 65 61 35 23 22 75 9 6 BI FSB_REQ_L<2> AC39 CPU_REQ2# CPU_D53# M40 FSB_D_L<53> BI 6 9 75

75 9 6 BI FSB_REQ_L<3> AC33 CPU_REQ3# CPU_D54# H40 FSB_D_L<54> BI 6 9 75

75 9 6 BI FSB_REQ_L<4> AC35 CPU_REQ4# CPU_D55# K42 FSB_D_L<55> BI 6 9 75

R14101 R14151 1
R1416 CPU_D56# H41 FSB_D_L<56> BI 6 9 75
54.9 62 62
1% 5% 5% 75 9 6 BI FSB_ADS_L AD42 CPU_ADS# CPU_D57# L41 FSB_D_L<57> BI 6 9 75
1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF 75 9 BI FSB_BNR_L AD43 CPU_BNR# CPU_D58# H43 FSB_D_L<58> BI 6 9 75
402 2 402 2 2 402 75 9 BI FSB_BREQ0_L AE40 CPU_BR0# CPU_D59# H42 FSB_D_L<59> BI 6 9 75

B 75 41 9 IN PM_THRMTRIP_L 75 9 BI
75 FSB_BREQ1_L
FSB_DBSY_L
AL32
AD39
CPU_BR1#
CPU_DBSY#
CPU_D60#
CPU_D61#
K41
J40
FSB_D_L<60>
FSB_D_L<61>
BI
BI
6 9 75

6 9 75
B
75 9 IN CPU_FERR_L 75 9 BI FSB_DRDY_L AD41 CPU_DRDY# CPU_D62# H39 FSB_D_L<62> BI 6 9 75

75 9 6 BI FSB_HIT_L AB42 CPU_HIT# CPU_D63# M43 FSB_D_L<63> BI 6 9 75

75 9 6 BI FSB_HITM_L AD40 CPU_HITM#

75 9 6 IN FSB_LOCK_L AC43 CPU_LOCK# CPU_BPRI# AA41 FSB_BPRI_L OUT 9 75

75 9 OUT FSB_TRDY_L AE41 CPU_TRDY# CPU_DEFER# AA40 FSB_DEFER_L OUT 9 75

NO STUFF NO STUFF NO STUFF TP_CPU_PECI_MCP E41

8 OUT CPU_PECI
R1420 1
R1421 1 1
R1422 BCLK_OUT_CPU_P G42 FSB_CLK_CPU_P OUT 9 75
75 61 41 9 OUT CPU_PROCHOT_L AJ41 CPU_PROCHOT#
1K 1K 1K AG43
BCLK_OUT_CPU_N G41 FSB_CLK_CPU_N OUT 9 75
5% 5% 5% CPU_THERMTRIP#
1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF AH40 CPU_FERR# BCLK_OUT_ITP_P AL43 FSB_CLK_ITP_P OUT 12 75
402 2 402 2 2 402 BCLK_OUT_ITP_N AL42 FSB_CLK_ITP_N OUT 12 75

8 IN =MCP_BSEL<2> (MCP_BSEL<2>) F42 CPU_BSEL2

BCLK_OUT_NB_P AL41 75 FSB_CLK_MCP_P
8 IN =MCP_BSEL<1> (MCP_BSEL<1>) D42 CPU_BSEL1
BCLK_OUT_NB_N AK42 75 FSB_CLK_MCP_N
8 IN =MCP_BSEL<0> (MCP_BSEL<0>) F41 CPU_BSEL0
Loop-back clock for delay matching.
75 9 OUT FSB_RS_L<0> AC41 CPU_RS0# BCLK_IN_N AK41
75 9 OUT FSB_RS_L<1> AB41 CPU_RS1# BCLK_IN_P AJ40
75 9 OUT FSB_RS_L<2> AC42 CPU_RS2#

R14301 1
R1435 22 PP1V05_S0_MCP_PLL_FSB CPU_A20M# AF41 CPU_A20M_L OUT 9 75 PP1V05_S0 6 7 9 10 11 12 13 16 17 19 21
22 23 35 61 65 66 67
49.9 49.9 270 mA (A01) 206 mA AG27 +V_DLL_DLCELL_AVDD CPU_IGNNE# AH39 CPU_IGNNE_L OUT 9 75 NO STUFF
1% 1%
1/16W 1/16W 20 mA AH27 +V_PLL_MCLK CPU_INIT# AH42 CPU_INIT_L OUT 9 75
1
R1440
MF-LF MF-LF AF42 CPU_INTR 150
402 2 2 402 29 mA
15 mA
AG28
AH28
+V_PLL_FSB
+V_PLL_CPU
CPU_INTR
CPU_NMI AG41 CPU_NMI
OUT
OUT
9 75

9 75
5%
1/16W
MCP CPU Interface
MF-LF
CPU_SMI# AH41 CPU_SMI_L SYNC_MASTER=T18_MLB SYNC_DATE=02/05/2009
A 75 MCP_BCLK_VML_COMP_VDD AM39 BCLK_VML_COMP_VDD
CPU_PWRGD AH43 CPU_PWRGD
OUT 9 75
2 402

9 12 75 NOTICE OF PROPRIETARY PROPERTY

A
75 MCP_BCLK_VML_COMP_GND AM40 BCLK_VML_COMP_GND OUT
CPU_RESET# H38 FSB_CPURST_L OUT 9 12 75
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
75 MCP_CPU_COMP_VCC AM43 CPU_COMP_VCC CPU_SLP# AM33 FSB_CPUSLP_L OUT 9 75 AGREES TO THE FOLLOWING
75 MCP_CPU_COMP_GND AM42 CPU_COMP_GND CPU_DPSLP# AN33 CPU_DPSLP_L OUT 9 75 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
R14311 1
R1436 CPU_DPWR# AM32 FSB_DPWR_L OUT 9 75 II NOT TO REPRODUCE OR COPY IT
49.9 49.9
1% 1% CPU_STPCLK# AG42 CPU_STPCLK_L OUT 9 75 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1/16W 1/16W
MF-LF MF-LF CPU_DPRSTP# AN32 CPU_DPRSTP_L OUT 9 61 75
402 2 2 402 SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 13 83
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

OMIT OMIT
U1400 U1400
MCP79-TOPO-B MCP79-TOPO-B
BGA BGA
(2 OF 11) (3 OF 11)
76 26 BI MEM_A_DQ<63> AL8 MDQ0_63 MDQS0_7_P AL10 MEM_A_DQS_P<7> BI 26 76 76 27 BI MEM_B_DQ<63> AT4 MDQ1_63 MDQS1_7_P AT2 MEM_B_DQS_P<7> BI 27 76

76 26 BI MEM_A_DQ<62> AL9 MDQ0_62 MDQS0_7_N AL11 MEM_A_DQS_N<7> BI 26 76 76 27 BI MEM_B_DQ<62> AT3 MDQ1_62 MDQS1_7_N AT1 MEM_B_DQS_N<7> BI 27 76

76 26 BI MEM_A_DQ<61> AP9 MDQ0_61 MDQS0_6_P AR8 MEM_A_DQS_P<6> BI 26 76 76 27 BI MEM_B_DQ<61> AV2 MDQ1_61 MDQS1_6_P AY2 MEM_B_DQS_P<6> BI 27 76

76 26 BI MEM_A_DQ<60> AN9 MDQ0_60 MDQS0_6_N AR9 MEM_A_DQS_N<6> BI 26 76 76 27 BI MEM_B_DQ<60> AV3 MDQ1_60 MDQS1_6_N AY1 MEM_B_DQS_N<6> BI 27 76

D 76 26

76 26
BI
BI
MEM_A_DQ<59>
MEM_A_DQ<58>
AL6
AL7
MDQ0_59
MDQ0_58
MDQS0_5_P
MDQS0_5_N
AW7
AW8
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
BI
BI
26 76

26 76
76 27

76 27
BI
BI
MEM_B_DQ<59>
MEM_B_DQ<58>
AR4
AR3
MDQ1_59
MDQ1_58
MDQS1_5_P
MDQS1_5_N
BB6
BA6
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
BI
BI
27 76

27 76
D
76 26 BI MEM_A_DQ<57> AN6 MDQ0_57 MDQS0_4_P AP13 MEM_A_DQS_P<4> BI 26 76 76 27 BI MEM_B_DQ<57> AU2 MDQ1_57 MDQS1_4_P BA10 MEM_B_DQS_P<4> BI 27 76

76 26 BI MEM_A_DQ<56> AN7 MDQ0_56 MDQS0_4_N AR13 MEM_A_DQS_N<4> BI 26 76 76 27 BI MEM_B_DQ<56> AU3 MDQ1_56 MDQS1_4_N AY11 MEM_B_DQS_N<4> BI 27 76

76 26 BI MEM_A_DQ<55> AR6 MDQ0_55 MDQS0_3_P AV25 MEM_A_DQS_P<3> BI 26 76 76 27 BI MEM_B_DQ<55> AY4 MDQ1_55 MDQS1_3_P BB33 MEM_B_DQS_P<3> BI 27 76

76 26 BI MEM_A_DQ<54> AR7 MDQ0_54 MDQS0_3_N AW25 MEM_A_DQS_N<3> BI 26 76 76 27 BI MEM_B_DQ<54> AY3 MDQ1_54 MDQS1_3_N BA33 MEM_B_DQS_N<3> BI 27 76

76 26 BI MEM_A_DQ<53> AV6 MDQ0_53 MDQS0_2_P AU30 MEM_A_DQS_P<2> BI 26 76 76 27 BI MEM_B_DQ<53> BB3 MDQ1_53 MDQS1_2_P BB37 MEM_B_DQS_P<2> BI 27 76

76 26 BI MEM_A_DQ<52> AW5 MDQ0_52 MDQS0_2_N AU29 MEM_A_DQS_N<2> BI 26 76 76 27 BI MEM_B_DQ<52> BC3 MDQ1_52 MDQS1_2_N BA37 MEM_B_DQS_N<2> BI 27 76

76 26 BI MEM_A_DQ<51> AN10 MDQ0_51 MDQS0_1_P AT35 MEM_A_DQS_P<1> BI 26 76 76 27 BI MEM_B_DQ<51> AW4 MDQ1_51 MDQS1_1_P BA43 MEM_B_DQS_P<1> BI 27 76

76 26 BI MEM_A_DQ<50> AR5 MDQ0_50 MDQS0_1_N AU35 MEM_A_DQS_N<1> BI 26 76 76 27 BI MEM_B_DQ<50> AW3 MDQ1_50 MDQS1_1_N AY42 MEM_B_DQS_N<1> BI 27 76

76 26 BI MEM_A_DQ<49> AU6 MDQ0_49 MDQS0_0_P AU39 MEM_A_DQS_P<0> BI 26 76 76 27 BI MEM_B_DQ<49> BA3 MDQ1_49 MDQS1_0_P AT42 MEM_B_DQS_P<0> BI 27 76

76 26 BI MEM_A_DQ<48> AV5 MDQ0_48 MDQS0_0_N AT39 MEM_A_DQS_N<0> BI 26 76 76 27 BI MEM_B_DQ<48> BB2 MDQ1_48 MDQS1_0_N AT43 MEM_B_DQS_N<0> BI 27 76

76 26 BI MEM_A_DQ<47> AU7 MDQ0_47 76 27 BI MEM_B_DQ<47> BB5 MDQ1_47

76 26 BI MEM_A_DQ<46> AU8 MDQ0_46 76 27 BI MEM_B_DQ<46> BA5 MDQ1_46

MEMORY PARTITION 0

MEMORY PARTITION 1
76 26 BI MEM_A_DQ<45> AW9 MDQ0_45 76 27 BI MEM_B_DQ<45> BA8 MDQ1_45
76 26 BI MEM_A_DQ<44> AP11 MDQ0_44 76 27 BI MEM_B_DQ<44> BC8 MDQ1_44
76 26 BI MEM_A_DQ<43> AW6 MDQ0_43 76 27 BI MEM_B_DQ<43> BB4 MDQ1_43
76 26 BI MEM_A_DQ<42> AY5 MDQ0_42 MRAS0# AV17 MEM_A_RAS_L OUT 26 76 76 27 BI MEM_B_DQ<42> BC4 MDQ1_42 MRAS1# AW16 MEM_B_RAS_L OUT 27 76

76 26 BI MEM_A_DQ<41> AU9 MDQ0_41 MCAS0# AP17 MEM_A_CAS_L OUT 26 76 76 27 BI MEM_B_DQ<41> BA7 MDQ1_41 MCAS1# BA15 MEM_B_CAS_L OUT 27 76

76 26 BI MEM_A_DQ<40> AV9 MDQ0_40 MWE0# AR17 MEM_A_WE_L OUT 26 76 76 27 BI MEM_B_DQ<40> AY8 MDQ1_40 MWE1# BA16 MEM_B_WE_L OUT 27 76

76 26 BI MEM_A_DQ<39> AU11 MDQ0_39 76 27 BI MEM_B_DQ<39> BA9 MDQ1_39

76 26 BI MEM_A_DQ<38> AV11 MDQ0_38 76 27 BI MEM_B_DQ<38> BB10 MDQ1_38
76 26 BI MEM_A_DQ<37> AV13 MDQ0_37 76 27 BI MEM_B_DQ<37> BB12 MDQ1_37
76 26 BI MEM_A_DQ<36> AW13 MDQ0_36 76 27 BI MEM_B_DQ<36> AW12 MDQ1_36
76 26 BI MEM_A_DQ<35> AR11 MDQ0_35 76 27 BI MEM_B_DQ<35> BB8 MDQ1_35
76 26 BI MEM_A_DQ<34> AT11 MDQ0_34 MBA0_2 AP23 MEM_A_BA<2> OUT 26 76 76 27 BI MEM_B_DQ<34> BB9 MDQ1_34 MBA1_2 BB29 MEM_B_BA<2> OUT 27 76

76 26 BI MEM_A_DQ<33> AR14 MDQ0_33 MBA0_1 AP19 MEM_A_BA<1> OUT 26 76 76 27 BI MEM_B_DQ<33> AY12 MDQ1_33 MBA1_1 BB18 MEM_B_BA<1> OUT 27 76

C 76 26

76 26
BI MEM_A_DQ<32>
MEM_A_DQ<31>
AU13
AR26
MDQ0_32
MDQ0_31
MBA0_0 AW17 MEM_A_BA<0> OUT 26 76 76 27

76 27
BI MEM_B_DQ<32>
MEM_B_DQ<31>
BA12
BC32
MDQ1_32
MDQ1_31
MBA1_0 BB17 MEM_B_BA<0> OUT 27 76 C
BI BI
76 26 BI MEM_A_DQ<30> AU25 MDQ0_30 76 27 BI MEM_B_DQ<30> AW32 MDQ1_30
76 26 BI MEM_A_DQ<29> AT27 MDQ0_29 76 27 BI MEM_B_DQ<29> BA35 MDQ1_29
76 26 BI MEM_A_DQ<28> AU27 MDQ0_28 76 27 BI MEM_B_DQ<28> AY36 MDQ1_28
76 26 BI MEM_A_DQ<27> AP25 MDQ0_27 76 27 BI MEM_B_DQ<27> BA32 MDQ1_27
MA0_14 AR23 MEM_A_A<14> OUT 26 76 MA1_14 BA29 MEM_B_A<14> OUT 27 76
76 26 BI MEM_A_DQ<26> AR25 MDQ0_26 76 27 BI MEM_B_DQ<26> BB32 MDQ1_26
MA0_13 AU15 MEM_A_A<13> OUT 26 76 MA1_13 BA14 MEM_B_A<13> OUT 27 76
76 26 BI MEM_A_DQ<25> AP27 MDQ0_25 76 27 BI MEM_B_DQ<25> BA34 MDQ1_25
MA0_12 AN23 MEM_A_A<12> OUT 26 76 MA1_12 AW28 MEM_B_A<12> OUT 27 76
76 26 BI MEM_A_DQ<24> AR27 MDQ0_24 76 27 BI MEM_B_DQ<24> AY35 MDQ1_24
MA0_11 AW21 MEM_A_A<11> OUT 26 76 MA1_11 BC28 MEM_B_A<11> OUT 27 76
76 26 BI MEM_A_DQ<23> AP29 MDQ0_23 76 27 BI MEM_B_DQ<23> BC36 MDQ1_23
MA0_10 AN19 MEM_A_A<10> OUT 26 76 MA1_10 BA17 MEM_B_A<10> OUT 27 76
76 26 BI MEM_A_DQ<22> AR29 MDQ0_22 76 27 BI MEM_B_DQ<22> AW36 MDQ1_22
MA0_9 AV21 MEM_A_A<9> OUT 26 76 MA1_9 BB28 MEM_B_A<9> OUT 27 76
76 26 BI MEM_A_DQ<21> AP31 MDQ0_21 76 27 BI MEM_B_DQ<21> BA39 MDQ1_21
MA0_8 AR22 MEM_A_A<8> OUT 26 76 MA1_8 AY28 MEM_B_A<8> OUT 27 76
76 26 BI MEM_A_DQ<20> AR31 MDQ0_20 76 27 BI MEM_B_DQ<20> AY40 MDQ1_20
MA0_7 AU21 MEM_A_A<7> OUT 26 76 MA1_7 BA28 MEM_B_A<7> OUT 27 76
76 26 BI MEM_A_DQ<19> AV27 MDQ0_19 76 27 BI MEM_B_DQ<19> BA36 MDQ1_19
MA0_6 AP21 MEM_A_A<6> OUT 26 76 MA1_6 AY27 MEM_B_A<6> OUT 27 76
76 26 BI MEM_A_DQ<18> AN29 MDQ0_18 76 27 BI MEM_B_DQ<18> BB36 MDQ1_18
MA0_5 AR21 MEM_A_A<5> OUT 26 76 MA1_5 BA27 MEM_B_A<5> OUT 27 76
76 26 BI MEM_A_DQ<17> AV29 MDQ0_17 76 27 BI MEM_B_DQ<17> BA38 MDQ1_17
MA0_4 AN21 MEM_A_A<4> OUT 26 76 MA1_4 BA26 MEM_B_A<4> OUT 27 76
76 26 BI MEM_A_DQ<16> AN31 MDQ0_16 76 27 BI MEM_B_DQ<16> AY39 MDQ1_16
MA0_3 AV19 MEM_A_A<3> OUT 26 76 MA1_3 BB26 MEM_B_A<3> OUT 27 76
76 26 BI MEM_A_DQ<15> AU31 MDQ0_15 76 27 BI MEM_B_DQ<15> BB40 MDQ1_15
MA0_2 AU19 MEM_A_A<2> OUT 26 76 MA1_2 BA25 MEM_B_A<2> OUT 27 76
76 26 BI MEM_A_DQ<14> AR33 MDQ0_14 76 27 BI MEM_B_DQ<14> AW40 MDQ1_14
MA0_1 AT19 MEM_A_A<1> OUT 26 76 MA1_1 BB25 MEM_B_A<1> OUT 27 76
76 26 BI MEM_A_DQ<13> AV37 MDQ0_13 76 27 BI MEM_B_DQ<13> AV42 MDQ1_13
MA0_0 AR19 MEM_A_A<0> OUT 26 76 MA1_0 BA18 MEM_B_A<0> OUT 27 76
76 26 BI MEM_A_DQ<12> AW37 MDQ0_12 76 27 BI MEM_B_DQ<12> AV41 MDQ1_12
76 26 BI MEM_A_DQ<11> AT31 MDQ0_11 76 27 BI MEM_B_DQ<11> BA40 MDQ1_11
76 26 BI MEM_A_DQ<10> AV31 MDQ0_10 76 27 BI MEM_B_DQ<10> BC40 MDQ1_10
MEM_A_DQ<9> AT37 MEMORY MEM_B_DQ<9> AW42 MEMORY
76 26 BI MDQ0_9 76 27 BI MDQ1_9
MEM_A_DQ<8> AU37
CONTROL MEM_B_DQ<8> AW41
CONTROL
76 26 BI MDQ0_8 76 27 BI MDQ1_8
MEM_A_DQ<7> AW39 0A MEM_B_DQ<7> AT40 1A
76 26 BI MDQ0_7 76 27 BI MDQ1_7
MCLK0A_2_P AW33 TP_MEM_A_CLK2P MCLK1A_2_P BA42 TP_MEM_B_CLK2P
B 76 26

76 26
BI
BI
MEM_A_DQ<6>
MEM_A_DQ<5>
AV39
AR37
MDQ0_6
MDQ0_5
MCLK0A_2_N AV33 NC_MEM_A_CLK2N 6
76 27

76 27
BI
BI
MEM_B_DQ<6>
MEM_B_DQ<5>
AT41
AP41
MDQ1_6
MDQ1_5
MCLK1A_2_N BB42 TP_MEM_B_CLK2N B
76 26 BI MEM_A_DQ<4> AR38 MDQ0_4 MCLK0A_1_P BA24 MEM_A_CLK_P<1> OUT 26 76 76 27 BI MEM_B_DQ<4> AN40 MDQ1_4 MCLK1A_1_P BB22 MEM_B_CLK_P<1> OUT 27 76

76 26 BI MEM_A_DQ<3> AV38 MDQ0_3 MCLK0A_1_N AY24 MEM_A_CLK_N<1> OUT 26 76 76 27 BI MEM_B_DQ<3> AU40 MDQ1_3 MCLK1A_1_N BA22 MEM_B_CLK_N<1> OUT 27 76

76 26 BI MEM_A_DQ<2> AW38 MDQ0_2 76 27 BI MEM_B_DQ<2> AU41 MDQ1_2

MCLK0A_0_P BB20 MEM_A_CLK_P<0> OUT 26 76 MCLK1A_0_P BA19 MEM_B_CLK_P<0> OUT 27 76
76 26 BI MEM_A_DQ<1> AR35 MDQ0_1 76 27 BI MEM_B_DQ<1> AR41 MDQ1_1
MCLK0A_0_N BC20 MEM_A_CLK_N<0> OUT 26 76 MCLK1A_0_N AY19 MEM_B_CLK_N<0> OUT 27 76
76 26 BI MEM_A_DQ<0> AP35 MDQ0_0 76 27 BI MEM_B_DQ<0> AP42 MDQ1_0

76 26 OUT MEM_A_DM<7> AN5 MDQM0_7 MCS0A_1# AT15 MEM_A_CS_L<1> OUT 26 76 76 27 OUT MEM_B_DM<7> AT5 MDQM1_7 MCS1A_1# BB14 MEM_B_CS_L<1> OUT 27 76

76 26 OUT MEM_A_DM<6> AU5 MDQM0_6 MCS0A_0# AR18 MEM_A_CS_L<0> OUT 26 76 76 27 OUT MEM_B_DM<6> BA2 MDQM1_6 MCS1A_0# BB16 MEM_B_CS_L<0> OUT 27 76

76 26 OUT MEM_A_DM<5> AR10 MDQM0_5 76 27 OUT MEM_B_DM<5> AY7 MDQM1_5

76 26 OUT MEM_A_DM<4> AN13 MDQM0_4 MODT0A_1 AP15 MEM_A_ODT<1> OUT 26 76 76 27 OUT MEM_B_DM<4> BA11 MDQM1_4 MODT1A_1 BB13 MEM_B_ODT<1> OUT 27 76

76 26 OUT MEM_A_DM<3> AN27 MDQM0_3 MODT0A_0 AV15 MEM_A_ODT<0> OUT 26 76 76 27 OUT MEM_B_DM<3> BB34 MDQM1_3 MODT1A_0 AY15 MEM_B_ODT<0> OUT 27 76

76 26 OUT MEM_A_DM<2> AW29 MDQM0_2 76 27 OUT MEM_B_DM<2> BB38 MDQM1_2

76 26 OUT MEM_A_DM<1> AV35 MDQM0_1 MCKE0A_1 AU23 MEM_A_CKE<1> OUT 26 76 76 27 OUT MEM_B_DM<1> AY43 MDQM1_1 MCKE1A_1 AY31 MEM_B_CKE<1> OUT 27 76

76 26 OUT MEM_A_DM<0> AR34 MDQM0_0 MCKE0A_0 AT23 MEM_A_CKE<0> OUT 26 76 76 27 OUT MEM_B_DM<0> AR42 MDQM1_0 MCKE1A_0 BB30 MEM_B_CKE<0> OUT 27 76

MCP Memory Interface

SYNC_MASTER=T18_MLB SYNC_DATE=02/05/2009
A NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 14 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

OMIT
U1400
MCP79-TOPO-B
BGA
(4 OF 11)
TP_MEM_A_CLK5P AU33 MCLK0B_2_P MCLK1B_2_P BA41 TP_MEM_B_CLK5P
D

MEMORY CONTROL 0B
MEMORY CONTROL 1B
TP_MEM_A_CLK5N AU34 MCLK0B_2_N MCLK1B_2_N BB41 NC_MEM_B_CLK5N
D 6 NC_MEM_A_CLK4P BB24 MCLK0B_1_P MCLK1B_1_P AY23 NC_MEM_B_CLK4P
6

TP_MEM_A_CLK4N BC24 MCLK0B_1_N MCLK1B_1_N BA23 NC_MEM_B_CLK4N 6

6 NC_MEM_A_CLK3P BA21 MCLK0B_0_P MCLK1B_0_P BA20 NC_MEM_B_CLK3P 6

6 NC_MEM_A_CLK3N BB21 MCLK0B_0_N MCLK1B_0_N AY20 TP_MEM_B_CLK3N

TP_MEM_A_CS_L<2> AU17 MCS0B_0# MCS1B_0# BC16 TP_MEM_B_CS_L<2>

6 NC_MEM_A_CS_L<3> AR15 MCS0B_1# MCS1B_1# BA13 TP_MEM_B_CS_L<3>

6 NC_MEM_A_ODT<2> AN17 MODT0B_0 MODT1B_0 AY16 NC_MEM_B_ODT<2> 6

6 NC_MEM_A_ODT<3> AN15 MODT0B_1 MODT1B_1 BC13 TP_MEM_B_ODT<3>

6 NC_MEM_A_CKE<2> AV23 MCKE0B_0 MCKE1B_0 BA30 NC_MEM_B_CKE<2> 6

6 NC_MEM_A_CKE<3> AN25 MCKE0B_1 MCKE1B_1 BA31 TP_MEM_B_CKE<3>

22 PP1V05_S0_MCP_PLL_CORE
68 67 66 37 22 15 11 10 7 6 PP1V5_S0
82 87 mA (A01) 17 mA T27 +V_PLL_XREF_XS
12 mA U28 +V_PLL_DP
R16101 19 mA U27 +V_PLL_CORE
40.2 MRESET0# AY32 MCP_MEM_RESET_L OUT 28
1% 39 mA T28 +V_VPLL
1/16W TP or NC for DDR2.
MF-LF
402 2

76 MCP_MEM_COMP_VDD AN41 MEM_COMP_VDD

76 MCP_MEM_COMP_GND AM41 MEM_COMP_GND PP1V5_S0 6 7 10 11 15 22 37 66 67 68 82

+VDD_MEM1 AM17 4771 mA (A01, DDR3)

R16111 +VDD_MEM2 AM19
40.2
C 1%
1/16W
MF-LF
AA22
AP12
GND1
GND2
+VDD_MEM3
+VDD_MEM4
AM21
AM23
C
402 2
G30 GND3 +VDD_MEM5 AM25
P10 GND4 +VDD_MEM6 AM27
T10 GND5 +VDD_MEM7 AM29
T6 GND6 +VDD_MEM8 AN16
V10 GND7 +VDD_MEM9 BC29
V34 GND8 +VDD_MEM10 AN20
W5 GND9 +VDD_MEM11 AN24
AA39 GND10 +VDD_MEM12 AT17
AB22 GND11 +VDD_MEM13 AP16
AB7 GND12 +VDD_MEM14 AN22
AD22 GND13 +VDD_MEM15 AP20
AE20 GND14 +VDD_MEM16 AP24
AF24 GND15 +VDD_MEM17 AV16
AG24 GND16 +VDD_MEM18 AR16
AH35 GND17 +VDD_MEM19 AR20
AK7 GND18 +VDD_MEM20 AR24
AM28 GND19 +VDD_MEM21 AW15
AT25 GND20 +VDD_MEM22 AP22
AP30 GND21 +VDD_MEM23 AP18
AR36 GND22 +VDD_MEM24 AU16
AU10 GND23 +VDD_MEM25 AN18
F28 GND24 +VDD_MEM26 AU24
BC21 GND25 +VDD_MEM27 AT21
AY9 GND26 +VDD_MEM28 AY29

B BC9
D34
GND27
GND28
+VDD_MEM29
+VDD_MEM30
AV24
AU20
B
F24 GND29 +VDD_MEM31 AU22
G32 GND30 +VDD_MEM32 AW27
H31 GND31 +VDD_MEM33 BC17
K7 GND32 +VDD_MEM34 AV20
M38 GND33 +VDD_MEM35 AY17
M5 GND34 +VDD_MEM36 AY18
M6 GND35 +VDD_MEM37 AM15
M7 GND36 +VDD_MEM38 AU18
M9 GND37 +VDD_MEM39 AY25
N39 GND38 +VDD_MEM40 AY26
N8 GND39 +VDD_MEM41 AW19
P33 GND40 +VDD_MEM42 AW24
P34 GND41 +VDD_MEM43 BC25
P37 GND42 +VDD_MEM44 AL30
P4 GND43 +VDD_MEM45 AM31
P40 GND44
P7 GND45 GND55 T33
R36 GND46 GND56 T34
R40 GND47 GND57 T35
R43 GND48 GND58 T37
R5 GND49 GND59 T38
T18 GND50 GND60 T7
T20 GND51 GND61 T9 MCP Memory Misc
AK11 GND52 GND62 U18
SYNC_MASTER=T18_MLB SYNC_DATE=02/05/2009
A T24
T26
GND53
GND54
GND63
GND64
U20
U22 NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 15 83
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
OMIT
U1400
MCP79-TOPO-B
BGA
(5 OF 11)
8 IN NC_PEG_D2RP<0> F7 PE0_RX0_P PE0_TX0_P C5 NC_PEG_R2DCP<0> OUT 8

8 IN NC_PEG_D2RN<0> E7 PE0_RX0_N PE0_TX0_N D4 NC_PEG_R2DCN<0> OUT 8

8 IN NC_PEG_D2RP<1> D7 PE0_RX1_P PE0_TX1_P C4 NC_PEG_R2DCP<1> OUT 8

8 IN NC_PEG_D2RN<1> C7 PE0_RX1_N PE0_TX1_N B4 NC_PEG_R2DCN<1> OUT 8

8 IN NC_PEG_D2RP<2> E6 PE0_RX2_P PE0_TX2_P A4 NC_PEG_R2DCP<2> OUT 8

8 IN NC_PEG_D2RN<2> F6 PE0_RX2_N PE0_TX2_N A3 NC_PEG_R2DCN<2> OUT 8

8 NC_PEG_D2RP<3> E5 PE0_RX3_P PE0_TX3_P B3 NC_PEG_R2DCP<3> 8

D 8
IN
IN NC_PEG_D2RN<3> F5 PE0_RX3_N PE0_TX3_N B2 NC_PEG_R2DCN<3>
OUT
OUT 8 D
8 IN NC_PEG_D2RP<4> E4 PE0_RX4_P PE0_TX4_P C1 NC_PEG_R2DCP<4> OUT 8

8 IN NC_PEG_D2RN<4> E3 PE0_RX4_N PE0_TX4_N D1 NC_PEG_R2DCN<4> OUT 8

8 IN NC_PEG_D2RP<5> C3 PE0_RX5_P PE0_TX5_P D2 NC_PEG_R2DCP<5> OUT 8

8 IN NC_PEG_D2RN<5> D3 PE0_RX5_N PE0_TX5_N E1 NC_PEG_R2DCN<5> OUT 8

8 IN NC_PEG_D2RP<6> G5 PE0_RX6_P PE0_TX6_P E2 NC_PEG_R2DCP<6> OUT 8

8 IN NC_PEG_D2RN<6> H5 PE0_RX6_N PE0_TX6_N F2 NC_PEG_R2DCN<6> OUT 8

8 IN NC_PEG_D2RP<7> J7 PE0_RX7_P PE0_TX7_P F3 NC_PEG_R2DCP<7> OUT 8

PCI EXPRESS
8 IN NC_PEG_D2RN<7> J6 PE0_RX7_N PE0_TX7_N F4 NC_PEG_R2DCN<7> OUT 8

8 IN NC_PEG_D2RP<8> J5 PE0_RX8_P PE0_TX8_P G3 NC_PEG_R2DCP<8> OUT 8

8 IN NC_PEG_D2RN<8> J4 PE0_RX8_N PE0_TX8_N H4 NC_PEG_R2DCN<8> OUT 8

8 IN NC_PEG_D2RP<9> L11 PE0_RX9_P PE0_TX9_P H3 NC_PEG_R2DCP<9> OUT 8

8 IN NC_PEG_D2RN<9> L10 PE0_RX9_N PE0_TX9_N H2 NC_PEG_R2DCN<9> OUT 8

8 IN NC_PEG_D2RP<10> L9 PE0_RX10_P PE0_TX10_P H1 NC_PEG_R2DCP<10> OUT 8

8 IN NC_PEG_D2RN<10> L8 PE0_RX10_N PE0_TX10_N J1 NC_PEG_R2DCN<10> OUT 8

8 IN NC_PEG_D2RP<11> L7 PE0_RX11_P PE0_TX11_P J2 NC_PEG_R2DCP<11> OUT 8

8 IN NC_PEG_D2RN<11> L6 PE0_RX11_N PE0_TX11_N J3 NC_PEG_R2DCN<11> OUT 8

8 IN NC_PEG_D2RP<12> N11 PE0_RX12_P PE0_TX12_P K2 NC_PEG_R2DCP<12> OUT 8

8 IN NC_PEG_D2RN<12> N10 PE0_RX12_N PE0_TX12_N K3 NC_PEG_R2DCN<12> OUT 8

8 IN NC_PEG_D2RP<13> N9 PE0_RX13_P PE0_TX13_P L4 NC_PEG_R2DCP<13> OUT 8

8 IN NC_PEG_D2RN<13> P9 PE0_RX13_N PE0_TX13_N L3 NC_PEG_R2DCN<13> OUT 8

8 IN NC_PEG_D2RP<14> N7 PE0_RX14_P PE0_TX14_P M4 NC_PEG_R2DCP<14> OUT 8

8 IN NC_PEG_D2RN<14> N6 PE0_RX14_N PE0_TX14_N M3 NC_PEG_R2DCN<14> OUT 8

8 IN NC_PEG_D2RP<15> N5 PE0_RX15_P PE0_TX15_P M2 NC_PEG_R2DCP<15> OUT 8

8 IN NC_PEG_D2RN<15> N4 PE0_RX15_N PE0_TX15_N M1 NC_PEG_R2DCN<15> OUT 8

PE0_REFCLK_P E11 NC_PEG_CLK100MP

C 8 IN TP_PEG_PRSNT_L Int PU
C9 PE0_PRSNT_16# PE0_REFCLK_N D11 NC_PEG_CLK100MN
OUT
OUT
8 77

8 77
C
MINI_CLKREQ_L Int PU
D5 PEB_CLKREQ#/GPIO_49 PCIE_CLK100M_MINI_P
29 IN PE1_REFCLK_P G11 OUT 29 77

29 IN PCIE_MINI_PRSNT_L D9 PEB_PRSNT# Int PU PE1_REFCLK_N F11 PCIE_CLK100M_MINI_N OUT 29 77

FW_CLKREQ_L Int PU
E8 PEC_CLKREQ#/GPIO_50 PCIE_CLK100M_FW_P
35 IN PE2_REFCLK_P J11 OUT 34 77

35 8 IN PCIE_FW_PRSNT_L C10 PEC_PRSNT# Int PU PE2_REFCLK_N J10 PCIE_CLK100M_FW_N OUT 34 77

TP_EXCARD_CLKREQ_L Int PU
M15 PED_CLKREQ#/GPIO_51 NC_PCIE_CLK100M_EXCARDPOUT
8 IN PE3_REFCLK_P G13 8 77

8 IN TP_PCIE_EXCARD_PRSNT_L B10 PED_PRSNT# Int PU PE3_REFCLK_N F13 NC_PCIE_CLK100M_EXCARDNOUT 8 77

TP_PE4_CLKREQ_L Int PU NC_PCIE_CLK100M_PE4P

L16 PEE_CLKREQ#/GPIO_16 PE4_REFCLK_P J13 6

6 NC_PE4_PRSNT_L L18 PEE_PRSNT#/GPIO_46 PE4_REFCLK_N H13 NC_PCIE_CLK100M_PE4N 6

Int PU
AUD_IP_PERIPHERAL_DET Int PU
M16 PEF_CLKREQ#/GPIO_17 NC_PCIE_CLK100M_PE5P
58 IN PE5_REFCLK_P L14 6

8 OUT TP_GMUX_JTAG_TCK_L M18 PEF_PRSNT#/GPIO_47 PE5_REFCLK_N K14 NC_PCIE_CLK100M_PE5N 6

Int PU
CARDREADER_RESET Int PU NC_PCIE_CLK100M_PE6P
30 OUT
M17 PEG_CLKREQ#/GPIO_18 PE6_REFCLK_P N14 6

8 IN TP_GMUX_JTAG_TDO M19 PEG_PRSNT#/GPIO_48 PE6_REFCLK_N M14 TP_PCIE_CLK100M_PE6N

Int PU
29 6 IN PCIE_WAKE_L F17 PE_WAKE# Int PU (S5) PEX_RST0# K11 PCIE_RESET_L OUT 24 35

77 29 6 IN PCIE_MINI_D2R_P K9 PE1_RX0_P PE1_TX0_P D8 PCIE_MINI_R2D_C_P OUT 29 77

77 29 6 IN PCIE_MINI_D2R_N J9 PE1_RX0_N PE1_TX0_N C8 PCIE_MINI_R2D_C_N OUT 29 77

77 34 IN PCIE_FW_D2R_P H9 PE1_RX1_P PE1_TX1_P B8 PCIE_FW_R2D_C_P OUT 34 77

B 77 34 IN PCIE_FW_D2R_N G9 PE1_RX1_N PE1_TX1_N A8 PCIE_FW_R2D_C_N OUT 34 77

B
77 8 IN NC_PCIE_EXCARD_D2RP F9 PE1_RX2_P PE1_TX2_P A7 NC_PCIE_EXCARD_R2DCP OUT 8 77

77 8 IN NC_PCIE_EXCARD_D2RN E9 PE1_RX2_N PE1_TX2_N B7 NC_PCIE_EXCARD_R2DCN OUT 8 77

TP_PCIE_PE4_D2RP H7 PE1_RX3_P PE1_TX3_P B6 TP_PCIE_PE4_R2D_CP

6 NC_PCIE_PE4_D2RN G7 PE1_RX3_N PE1_TX3_N C6 NC_PCIE_PE4_R2D_CN 6

GND GND
57 mA (A01, DVDD0 & 1) T17 +DVDD0_PEX1 +AVDD0_PEX1 Y12 206 mA (A01, AVDD0 & 1)
W19 +DVDD0_PEX2 +AVDD0_PEX2 AA12
Minimum 1.025V for Gen2 support U17 AB12
Minimum 1.025V for Gen2 support
+DVDD0_PEX3 +AVDD0_PEX3
V19 +DVDD0_PEX4 +AVDD0_PEX4 M12
W16 +DVDD0_PEX5 +AVDD0_PEX5 P12
W17 +DVDD0_PEX6 +AVDD0_PEX6 R12
W18 +DVDD0_PEX7 +AVDD0_PEX7 N12
U16 +DVDD0_PEX8 +AVDD0_PEX8 T12
22 21 19 17 13 12 11 10 9 7 6 PP1V05_S0 +AVDD0_PEX9 U12
67 66 65 61 35 23
T19 +DVDD1_PEX1 +AVDD0_PEX10 AC12
U19 +DVDD1_PEX2 +AVDD0_PEX11 AD12
+AVDD0_PEX12 V12
+AVDD0_PEX13 W12
22 PP1V05_S0_MCP_PLL_PEX T16 +V_PLL_PEX PP1V05_S0_MCP_PEX_AVDD 7 22

84 mA (A01) +AVDD1_PEX1 M13

+AVDD1_PEX2 N13
77 MCP_PEX_CLK_COMP A11 PEX_CLK_COMP +AVDD1_PEX3 P13 MCP PCIe Interfaces
NO STUFF
SYNC_MASTER=T18_MLB SYNC_DATE=02/05/2009
A 1
R1710
2.37K
If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX.
NOTICE OF PROPRIETARY PROPERTY
A
1% If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.
1/16W
MF-LF THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
2 402 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
PLACEMENT_NOTE=Place within 12.7mm of U1400
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 16 83
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

OMIT
U1400
MCP79-TOPO-B
BGA
(6 OF 11) PP3V3_ENET 6 7 17 22 31 32

+3.3V_DUAL_RMGT1 J24 83 mA (A01)

+3.3V_DUAL_RMGT2 K24
D

LAN
D +V_DUAL_RMGT1 U23
PP1V05_ENET 6 7 22 31 32

131 mA (A01)
+V_DUAL_RMGT2 V23
79 31 IN ENET_RXD<0> C23 RGMII_RXD0 Network Interface Select
79 31 IN ENET_RXD<1> B23 RGMII_RXD1 MII_VREF E28 MCP_MII_VREF IN 22

79 31 IN ENET_RXD<2> E24 RGMII_RXD2

RGMII_TXD0 B24 ENET_TXD<0> OUT 31 79
Interface ENET_TXD<0>
79 31 IN ENET_RXD<3> A24 RGMII_RXD3
RGMII_TXD1 C24 ENET_TXD<1>
79 31 ENET_CLK125M_RXCLK A23 RGMII_RXC/MII_RXCLK RGMII_TXD2 C25 ENET_TXD<2>
OUT 31 79

31 79
RGMII 1
IN OUT
ENET_RX_CTRL C22 RGMII_RXCTL/MII_RXDV RGMII_TXD3 D25 ENET_TXD<3>
79 31 IN OUT 31 79
MII 0
17 8 IN MCP_MII_PD F23 MII_RXER/GPIO_36 RGMII_TXC/MII_TXCLK D24 ENET_CLK125M_TXCLK OUT 31 79

17 8 IN MCP_MII_PD B26 MII_COL/GPIO_20/MSMB_DATA RGMII_TXCTL/MII_TXEN C26 ENET_TX_CTRL OUT 31 79 NOTE: All Apple products set strap to
32 31 22 17 7 6 PP3V3_ENET
17 8 IN MCP_MII_PD B22 MII_CRS/GPIO_21/MSMB_CLK MII, RGMII products will enable
RGMII_MDC D21 ENET_MDC OUT 31 79

NC_ENET_INTR_L ENET_MDIO feature via software. This

R18101 6 J22 RGMII_INTR/GPIO_35 RGMII_MDIO C21 BI 31 79
avoids a leakage issue since
49.9
1% 22 PP1V05_ENET_MCP_PLL_MAC RGMII_PWRDWN/GPIO_37 G23 NC_ENET_PWRDWN_L 6 MCP79 requires a S5 pull-up.
1/16W
MF-LF 5 mA (A01) T23 +V_DUAL_MACPLL
402 2
BUF_25MHZ E23 MCP_CLK25M_BUF0_R OUT 32 79 PP3V3_S0 61 66 67 68 69 71 72 82
6 7 12 18 20 21 22 23 26 27 35
37 41 43 45 46 47 49 53 57 58
79 MCP_MII_COMP_VDD C27 MII_COMP_VDD
79 MCP_MII_COMP_GND B27 MII_COMP_GND MII_RESET# J23 ENET_RESET_L OUT 31 79

PP3V3_S0_MCP_DAC 23 R18601 1
R1861
R18111 +V_RGB_DAC J32 103 mA 206 mA (A01)
100K
5%
100K
5%
49.9 1/16W 1/16W
1% +V_TV_DAC K32 103 mA MF-LF MF-LF
1/16W 23 NC_MCP_RGB_DAC_RSET C39 RGB_DAC_RSET 402 2 2 402
MF-LF
402 2 23 NC_MCP_RGB_DAC_VREF B38 RGB_DAC_VREF
DDC_CLK0 B31 MCP_DDC_CLK0
DDC_DATA0 A31 MCP_DDC_DATA0

DACS
C RGB_DAC_RED B39 NC_MCP_RGB_RED RGB DAC Disable: C

RGB ONLY
23

RGB_DAC_GREEN A39 NC_MCP_RGB_GREEN 23 Okay to float all RGB_DAC signals.

77 23 OUT NC_MCP_TV_DAC_RSET E36 TV_DAC_RSET
RGB_DAC_BLUE B40 NC_MCP_RGB_BLUE 23 DDC_CLK0/DDC_DATA0 pull-ups still required.
77 23 OUT NC_MCP_TV_DAC_VREF A35 TV_DAC_VREF
RGB_DAC_HSYNC A40 NC_MCP_RGB_HSYNC 23

RGB_DAC_VSYNC A41 NC_MCP_RGB_VSYNC 23

TV / Component
PP3V3_S5 A36 NC_CRT_IG_R_C_PR TV DAC Disable:
36 35 32 28 24 22 21 19 7 6
82 71 69 68 67 66 62 52 42
C / Pr TV_DAC_RED OUT 23 77

Y / Y TV_DAC_GREEN B36 NC_CRT_IG_G_Y_Y OUT 23 77 Okay to float all TV_DAC signals.

23 IN NC_MCP_CLK27M_XTALIN C38 XTALIN_TV
R1820 1 Comp / Pb TV_DAC_BLUE C36 NC_CRT_IG_B_COMP_PB OUT 23 77 Okay to float XTALIN_TV and XTALOUT_TV.
23 OUT NC_MCP_CLK27M_XTALOUT D38 XTALOUT_TV
47K NC_CRT_IG_HSYNC DDC_CLK0/DDC_DATA0 pull-ups still required.
5% TV_DAC_HSYNC/GPIO_44 D36 OUT 23 77
1/16W
MF-LF TV_DAC_VSYNC/GPIO_45 C37 NC_CRT_IG_VSYNC OUT 23 77
402 2

42 BI LPCPLUS_GPIO E16 GPIO_6/FERR*/IGPU_GPIO_6 IFPA_TXC_P B35 LVDS_CONN_A_CLK_P OUT 8 69 77

70 IN DP_IG_CA_DET B15 GPIO_7/NFERR*/IGPU_GPIO_7 IFPA_TXC_N C35 LVDS_CONN_A_CLK_N OUT 8 69 77

(See below) IFPA_TXD0_P B32 LVDS_IG_A_DATA_P<0> OUT 8 77

74 73 72 8 OUT LCD_BKLT_PWM G39 LCD_BKL_CTL/GPIO_57
IFPA_TXD0_N A32 LVDS_IG_A_DATA_N<0> OUT 8 77
Interface Mode 73 8 OUT LVDS_BKL_ON E37 LCD_BKL_ON/GPIO_59
IFPA_TXD1_P D32 LVDS_IG_A_DATA_P<1> OUT 8 77
LCD_PWR_EN F40 LCD_PANEL_PWR/GPIO_58

FLAT PANEL
69 8 OUT
MCP Signal TMDS/HDMI DisplayPort IFPA_TXD1_N C32 LVDS_IG_A_DATA_N<1> OUT 8 77

IFPA_TXD2_P D33 LVDS_IG_A_DATA_P<2> OUT 8 77

=MCP_HDMI_TXC_P/N TMDS_IG_TXC_P/N DP_IG_ML_P/N<3> 70 OUT =MCP_HDMI_TXC_P D35 HDMI_TXC_P/ML0_LANE3_P
IFPA_TXD2_N C33 LVDS_IG_A_DATA_N<2> OUT 8 77
=MCP_HDMI_TXD_P/N<0> TMDS_IG_TXD_P/N<0> DP_IG_ML_P/N<2> 70 OUT =MCP_HDMI_TXC_N E35 HDMI_TXC_N/ML0_LANE3_N
IFPA_TXD3_P B34 NC_LVDS_IG_A_DATAP<3>OUT 8 77
=MCP_HDMI_TXD_P/N<1> TMDS_IG_TXD_P/N<1> DP_IG_ML_P/N<1> =MCP_HDMI_TXD_P<0> G35 C34 NC_LVDS_IG_A_DATAN<3>OUT
70 OUT HDMI_TXD0_P/ML0_LANE2_P IFPA_TXD3_N 8 77
=MCP_HDMI_TXD_P/N<2> TMDS_IG_TXD_P/N<2> DP_IG_ML_P/N<0> =MCP_HDMI_TXD_N<0> F35
70 OUT HDMI_TXD0_N/ML0_LANE2_N WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases
=MCP_HDMI_DDC_CLK TMDS_IG_DDC_CLK DP_IG_DDC_CLK =MCP_HDMI_TXD_P<1> F33
70 HDMI_TXD1_P/ML0_LANE1_P
B =MCP_HDMI_DDC_DATA
=MCP_HDMI_HPD
TMDS_IG_DDC_DATA
TMDS_IG_HPD
DP_IG_DDC_DATA
DP_IG_HPD
70
OUT
OUT =MCP_HDMI_TXD_N<1> G33 HDMI_TXD1_N/ML0_LANE1_N
IFPB_TXC_P L31
IFPB_TXC_N K31
LVDS_CONN_B_CLK_P
LVDS_CONN_B_CLK_N
OUT
OUT
8 69 77

8 69 77
B
82 71 70 OUT DP_ML_P<0> J33 HDMI_TXD2_P/ML0_LANE0_P
DP_IG_AUX_CH_P/N TP_DP_IG_AUX_CHP/N DP_IG_AUX_CH_P/N DP_ML_N<0> H33 J29 LVDS_IG_B_DATA_P<0> OUT
82 71 70 OUT HDMI_TXD2_N/ML0_LANE0_N IFPB_TXD4_P 8 77

NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used. IFPB_TXD4_N H29 LVDS_IG_B_DATA_N<0> OUT 8 77

NOTE: 20K pull-down required on DP_HPD_DET. 77 70 OUT DP_IG_AUX_CH_P D43 DP_AUX_CH0_P IFPB_TXD5_P L29 LVDS_IG_B_DATA_P<1> OUT 8 77

NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used. 77 70 OUT DP_IG_AUX_CH_N C43 DP_AUX_CH0_N IFPB_TXD5_N K29 LVDS_IG_B_DATA_N<1> OUT 8 77

IFPB_TXD6_P L30 LVDS_IG_B_DATA_P<2> OUT 8 77

NOTE: HDMI port requires level-shifting. IFP interface can MCP_HPLUG_DET2 (See below) C31 HPLUG_DET2/GPIO_22 K30 LVDS_IG_B_DATA_N<2> OUT
8 IN IFPB_TXD6_N 8 77
be used to provide HDMI or dual-channel TMDS without DP_HPD F31 HPLUG_DET3 N30 NC_LVDS_IG_B_DATAP<3>OUT
71 70 IN IFPB_TXD7_P 8 77
level-shifters. M30 NC_LVDS_IG_B_DATAN<3>OUT
IFPB_TXD7_N 8 77
LVDS: Power +VDD_IFPx at 1.8V 66 53 23 7 6 PP1V8_S0
Dual-channel TMDS: Power +VDD_IFPx at 3.3V 190 mA (A01, 1.8V) M27 +VDD_IFPA
M26 +VDD_IFPB DDC_CLK2/GPIO_23 C30 LVDS_DDC_CLK OUT 6 8 69
23 PP3V3_S0_MCP_VPLL
DDC_DATA2/GPIO_24 B30 LVDS_DDC_DATA BI 6 8 69
16 mA (A01) 8 mA M28 +V_PLL_IFPAB
8 mA M29 +V_PLL_HDMI
DDC_CLK3 D31 DP_IG_DDC_CLK OUT 70

22 21 19 16 13 12 11 10 9 7 6 PP1V05_S0 T25 +VDD_HDMI DDC_DATA3 E31 DP_IG_DDC_DATA BI 70

67 66 65 61 35 23
95 mA (A01)
77 23 OUT MCP_HDMI_RSET J31 HDMI_RSET IFPAB_RSET E32 MCP_IFPAB_RSET OUT 23 77

77 23 OUT MCP_HDMI_VPROBE J30 HDMI_VPROBE IFPAB_VPROBE G31 MCP_IFPAB_VPROBE OUT 23 77

1
R1850
10K
GPIOs 57-59 (if LCD panel is used): 5%
1/16W
In MCP79 these pins have undocumented internal
MF-LF
2 402 MCP Ethernet & Graphics
pull-ups (~10K to 3.3V S0). To ensure pins are low
SYNC_MASTER=T18_MLB SYNC_DATE=02/05/2009
A by default, pull-downs (1K or stronger) must be used.
NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
=DVI_HPD_GMUX_INT: PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
Alias to DVI_HPD for systems using IFP for DVI. I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
Alias to GMUX_INT for systems with GMUX. II NOT TO REPRODUCE OR COPY IT
Alias to HPLUG_DET2 for other systems. III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
Pull-down (20k) required in all cases.
SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 17 83
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
OMIT
U1400 82 72 71 69 68 67 66 61 58
27 26 23 22 21 20 17 12 7 6
57 53 49 47 46 45 43 41 37 35
PP3V3_S0
MCP79-TOPO-B
BGA R1989 8.2K
(7 OF 11) 18 MCP_RS232_SOUT_L 1 2
5% 1/16W MF-LF 402
PCI_REQ0_L T2 PCI_REQ0# PCI_GNT0# R3 NC_PCI_GNT0_L
78 18

PCI_REQ1_L V9 U10 NC_PCI_GNT1_L

6
78 18 PCI_REQ0_L R1990 8.2K 1 2
78 18 PCI_REQ1#/FANRPM2 PCI_GNT1#/FANCTL2 6
R1991 8.2K 5% 1/16W MF-LF 402
78 18 PCI_REQ1_L 1 2
35 18 OUT FW_PWR_EN T3 PCI_REQ2#/GPIO_40/RS232_DSR# PCI_GNT2#/GPIO_41/RS232_DTR# R4 TP_GMUX_JTAG_TMS OUT 8
R1992 8.2K 5% 1/16W MF-LF 402
35 18 FW_PWR_EN 1 2
58 8 OUT AUD_IPHS_SWITCH_EN U9 PCI_REQ3#/GPIO_38/RS232_CTS# PCI_GNT3#/GPIO_39/RS232_RTS# U11 TP_GMUX_JTAG_TDI OUT 8
R1994 8.2K 5% 1/16W MF-LF 402
18 MCP_RS232_SIN_L 1 2
18 IN MCP_RS232_SIN_L T4 PCI_REQ4#/GPIO_52/RS232_SIN# PCI_GNT4#/GPIO_53/RS232_SOUT# P3 MCP_RS232_SOUT_L OUT 18 5% 1/16W MF-LF 402

D 78 12 BI MCP_DEBUG<0> AC3 PCI_AD0 PCI_CBE0# AA3 NC_PCI_C_BE_L<0> 6

D
78 12 BI MCP_DEBUG<1> AE10 PCI_AD1 PCI_CBE1# AA6 NC_PCI_C_BE_L<1> 6

78 12 BI MCP_DEBUG<2> AC4 PCI_AD2 PCI_CBE2# AA11 NC_PCI_C_BE_L<2> 6

78 12 BI MCP_DEBUG<3> AE11 PCI_AD3 PCI_CBE3# W10 NC_PCI_C_BE_L<3> 6

78 12 BI MCP_DEBUG<4> AB3 PCI_AD4

78 12 BI MCP_DEBUG<5> AC6 PCI_AD5 PCI_DEVSEL# AA9 NC_PCI_DEVSEL_L 6

78 12 BI MCP_DEBUG<6> AB2 PCI_AD6 PCI_FRAME# Y4 NC_PCI_FRAME_L 6

78 12 BI MCP_DEBUG<7> AC7 PCI_AD7 PCI_IRDY# AA10 NC_PCI_IRDY_L 6

6 NC_PCI_AD<8> AC8 PCI_AD8 PCI_PAR Y1 TP_PCI_PAR

6 NC_PCI_AD<9> AA2 PCI_AD9 PCI_PERR#/GPIO_43/RS232_DCD# AB9 NC_PCI_PERR_L 6

6 NC_PCI_AD<10> AC9 PCI_AD10 PCI_SERR# AA7 NC_PCI_SERR_L 6

6 NC_PCI_AD<11> AC10 PCI_AD11 PCI_STOP# Y2 NC_PCI_STOP_L 6

NC_PCI_AD<12>

PCI
6 AC11 PCI_AD12
PCI_PME#/GPIO_30 T1 PM_LATRIGGER_L OUT 12
6 NC_PCI_AD<13> AA1 PCI_AD13
NC_PCI_AD<14> AA5 Int PU (S5)
6 PCI_AD14
6 NC_PCI_AD<15> Y5 PCI_AD15
6 NC_PCI_AD<16> W3 PCI_AD16 PCI_RESET0# R10 MEM_VTT_EN_R OUT 24

6 NC_PCI_AD<17> W6 PCI_AD17 PCI_RESET1# R11 NC_PCI_RESET1_L 6

6 NC_PCI_AD<18> W4 PCI_AD18
6 NC_PCI_AD<19> W7 PCI_AD19
6 NC_PCI_AD<20> V3 PCI_AD20
PCI_CLK0 R6 NC_PCI_CLK0 6
6 NC_PCI_AD<21> W8 PCI_AD21
PCI_CLK1 R7 NC_PCI_CLK1 6
6 NC_PCI_AD<22> V2 PCI_AD22
PCI_CLK2 R8 78 PCI_CLK33M_MCP_R
6 NC_PCI_AD<23> W9 PCI_AD23
6 NC_PCI_AD<24> U3 PCI_AD24 1
6 NC_PCI_AD<25> W11 PCI_AD25 R1910
22
C 6

6
NC_PCI_AD<26>
NC_PCI_AD<27>
U2
U5
PCI_AD26
PCI_AD27
5%
1/16W
MF-LF
C
6 NC_PCI_AD<28> U1 PCI_AD28 2 402
PLACEMENT_NOTE=Place close to pin R8
6 NC_PCI_AD<29> U6 PCI_AD29 PCI_CLKIN R9 78 PCI_CLK33M_MCP
6 NC_PCI_AD<30> T5 PCI_AD30
6 NC_PCI_AD<31> U7 PCI_AD31

6 NC_PCI_INTW_L P2 PCI_INTW#
NC_PCI_INTX_L N3 PCI_INTX#
6

TP_PCI_INTY_L N2
LPC_FRAME# AD4 LPC_FRAME_R_L R1960 22 1 2 LPC_FRAME_L OUT 40 42 78
PCI_INTY# 5% 1/16W MF-LF 402
LPC_PWRDWN#/GPIO_54/EXT_NMI# AE12 LPC_PWRDWN_L OUT 40 42
6 NC_PCI_INTZ_L N1 PCI_INTZ#
LPC_RESET0# AE5 LPC_RESET_L OUT 24 78

LPC
6 NC_PCI_TRDY_L Y3 PCI_TRDY#
LPC_AD0 AD3 LPC_AD_R<0> R1950 22 1 2 LPC_AD<0> BI 40 42 78
R1951 22 5% 1/16W MF-LF 402
42 40 IN PM_CLKRUN_L AD11 PCI_CLKRUN#/GPIO_42 LPC_AD1 AD2 LPC_AD_R<1> 1 2 LPC_AD<1> BI 40 42 78
5% 1/16W MF-LF 402
LPC_AD2 AD1 LPC_AD_R<2> R1952 22 1 2 LPC_AD<2> BI 40 42 78
5% 1/16W MF-LF 402
35 8 IN FW_PLUG_DET_L AE2 LPC_DRQ1#/GPIO_19 Int PU LPC_AD3 AD5 LPC_AD_R<3> R1953 22 1 2 LPC_AD<3> BI 40 42 78
5% 1/16W MF-LF 402
6 NC_LPC_DRQ0_L AE1 LPC_DRQ0# Int PU
42 40 BI LPC_SERIRQ AE6 LPC_SERIRQ Int PU LPC_CLK0 AE9 LPC_CLK33M_SMC_R OUT 24 78

1
U24 GND65 GND98 Y26 R1961
U26 Y27
10K
GND66 GND99 5%
1/16W
U39 GND67 GND100 AB18 MF-LF
U4 GND68 GND101 H34 2 402
U8 GND69 GND102 AB20 Strap for Boot ROM Selection (See HDA_SDOUT)
V16 GND70 GND103 AB21
B V17 GND71 GND104 AB23 B
V18 GND72 GND105 AB24
V20 GND73 GND106 AB25
V22 GND74 GND107 AB26
V24 GND75 GND108 AB27
V26 GND76 GND109 AB28
GND

V27 GND77 GND110 AB34

V28 GND78 GND111 AB37
V33 GND79 GND112 AB4
V37 GND80 GND113 AB40
V4 GND81 GND114 AC22
V40 GND82 GND115 AC36
V7 GND83 GND116 AC40
W20 GND84 GND117 AB33
W22 GND85 GND118 AC5
W24 GND86 GND119 AD16
W36 GND87 GND120 AD17
W40 GND88 GND121 AD18
W43 GND89 GND122 AD19
Y16 GND90 GND123 AD20
Y17 GND91 GND124 AD24
Y18 GND92 GND125 AD25
Y19 GND93 GND126 AD26
Y20
Y22
GND94
GND95
GND127
GND128
AD27
AD28
MCP PCI & LPC
Y24 AD33 SYNC_MASTER=T18_MLB SYNC_DATE=02/05/2009
A Y25
GND96
GND97
GND129
GND130 AD34
NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 18 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
OMIT
U1400
MCP79-TOPO-B
BGA
(8 OF 11) External A
77 37 OUT SATA_HDD_R2D_C_P AJ7 SATA_A0_TX_P USB0_P C29 USB_EXTA_P BI 38 78

77 37 OUT SATA_HDD_R2D_C_N AJ6 SATA_A0_TX_N USB0_N D29 USB_EXTA_N BI 38 78

AirPort (PCIe Mini-Card)

77 37 IN SATA_HDD_D2R_N AJ5 SATA_A0_RX_N USB1_P C28 NC_USB_MINIP BI 8 78

77 37 IN SATA_HDD_D2R_P AJ4 SATA_A0_RX_P USB1_N D28 NC_USB_MININ BI 8 78

External D
D USB2_P A28 NC_USB_EXTDP BI 8 78 D
USB2_N B28 NC_USB_EXTDN BI 8 78

77 37 OUT SATA_ODD_R2D_C_P AJ11 SATA_A1_TX_P Camera

77 37 OUT SATA_ODD_R2D_C_N AJ10 SATA_A1_TX_N USB3_P F29 USB_CAMERA_P BI 6 29 78

USB3_N G29 USB_CAMERA_N BI 6 29 78

77 37 IN SATA_ODD_D2R_N AJ9 SATA_A1_RX_N IR

77 37 IN SATA_ODD_D2R_P AK9 SATA_A1_RX_P USB4_P K27 USB_IR_P BI 39 78

USB4_N L27 USB_IR_N BI 39 78

Geyser Trackpad/Keyboard
USB5_P J26 USB_TPAD_P BI 48 78

6 NC_SATA_C_R2D_CP AK2 SATA_B0_TX_P USB5_N J27 USB_TPAD_N BI 48 78

6 NC_SATA_C_R2D_CN AJ3 SATA_B0_TX_N Bluetooth

USB6_P F27 USB_BT_P BI 6 29 78

TP_SATA_C_D2RN AJ2 SATA_B0_RX_N USB6_N G27 USB_BT_N BI 6 29 78

NC_SATA_C_D2RP AJ1 SATA_B0_RX_P External B

SATA
6

USB7_P D27 USB_EXTB_P

USB
BI 38 78

USB7_N E27 USB_EXTB_N BI 38 78

ExpressCard
TP_SATA_D_R2D_CP AM4 SATA_B1_TX_P USB8_P K25 NC_USB_EXCARDP BI 8 78 PP3V3_S5 6 7 17 21 22 24 28 32 35 36 42
52 62 66 67 68 69 71 82
TP_SATA_D_R2D_CN AL3 SATA_B1_TX_N USB8_N L25 NC_USB_EXCARDN BI 8 78

External C
6 NC_SATA_D_D2RN AL4 SATA_B1_RX_N USB9_P H25 NC_USB_EXTCP BI 8 78
1
R2051 1
R2053
6 NC_SATA_D_D2RP AK3 SATA_B1_RX_P USB9_N J25 NC_USB_EXTCN BI 8 78 8.2K 8.2K
5% 5%
1/16W 1/16W
MF-LF MF-LF
USB10_P F25 NC_USB_10P 6
2 402 2 402
USB10_N G25 NC_USB_10N 6

TP_SATA_E_R2D_CP AN1 SATA_C0_TX_P SD Card Reader

C TP_SATA_E_R2D_CN AM1 SATA_C0_TX_N USB11_P K23 USB_CARDREADER_P BI 30 78
R20501
8.2K
R20521
8.2K
C
USB11_N L23 USB_CARDREADER_N BI 30 78 5% 5%
1/16W 1/16W
TP_SATA_E_D2RN AM2 SATA_C0_RX_N MF-LF MF-LF
402 2 402 2
TP_SATA_E_D2RP AM3 SATA_C0_RX_P
USB_OC0#/GPIO_25 L21 USB_EXTA_OC_L 38

USB_OC1#/GPIO_26 K21 USB_EXTB_OC_L 38

USB_OC2#/GPIO_27/MGPIO J21 USB_EXTC_OC_L

TP_SATA_F_R2D_CP AP3 SATA_C1_TX_P USB_OC3#/GPIO_28/MGPIO H21 EXCARD_OC_L
TP_SATA_F_R2D_CN AP2 SATA_C1_TX_N

+V_PLL_USB L28 PP3V3_S0_MCP_PLL_USB 22

TP_SATA_F_D2RN AN3 SATA_C1_RX_N
TP_SATA_F_D2RP AN2 SATA_C1_RX_P
19 mA (A01)
USB_RBIAS_GND A27 78 MCP_USB_RBIAS_GND

R20601
TP_MCP_SATALED_L E12 SATA_LED# GND131 AD35 806
1%
GND132 AD37 1/16W
MF-LF
GND133 AD38 402 2
22 PP1V05_S0_MCP_PLL_SATA AE16 +V_PLL_SATA
GND134 AE22
84 mA (A01) AE24
GND135
22 21 17 16 13 12 11 10 9 7 6 PP1V05_S0
67 66 65 61 35 23 GND136 AE39
43 mA (A01, DVDD0 & 1) AF19 +DVDD0_SATA1
GND137 AE4
AG16 +DVDD0_SATA2
Minimum 1.025V for Gen2 support GND138 AD6
AG17 +DVDD0_SATA3
GND139 AF16
AG19 +DVDD0_SATA4
GND140 AF17
GND AF18
GND141
B AH17 +DVDD1_SATA1
AH19 +DVDD1_SATA2 GND142 AF20 B
GND143 AF22
22 7 PP1V05_S0_MCP_SATA_AVDD GND144 AF26
127 mA (A01, AVDD0 & 1) AJ12 +AVDD0_SATA1 GND145 AF27
AN11 +AVDD0_SATA2 GND146 AF28
Minimum 1.025V for Gen2 support AK12 AF33
+AVDD0_SATA3 GND147
AK13 +AVDD0_SATA4 GND148 AF34
AL12 +AVDD0_SATA5 GND149 AF37
AM11 +AVDD0_SATA6 GND150 AF40
AM12 +AVDD0_SATA7 GND151 AG18
AN12 +AVDD0_SATA8 GND152 AG20
AL13 +AVDD0_SATA9 GND153 AG22
GND GND154 AG26
AN14 +AVDD1_SATA1 GND155 AG36
AL14 +AVDD1_SATA2 GND156 AG40
AM13 +AVDD1_SATA3 GND157 AH18
AM14 +AVDD1_SATA4 GND158 AH20
GND159 AH22
77 MCP_SATA_TERMP AE3 SATA_TERMP GND160 AH24

1
R2010
2.49K
1% If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.
1/16W
MF-LF If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.
2 402 MCP SATA & USB
SYNC_MASTER=T18_MLB SYNC_DATE=02/05/2009
A NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 19 83
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

OMIT
U1400 PP3V3_S0
82
45 46 47 49 53 57 58 61 66 67
MCP79-TOPO-B 6 7 12 17 18 20 21 22 23 26 27
35 37 41 43
BGA 7 mA 68(A01)
69 71 72

(9 OF 11)
+V_DUAL_HDA1 J16 1
R2160
+V_DUAL_HDA2 K16 8.2K
5%
1/16W
D

HDA
MF-LF
D 2 402 R2170
22
78 53 IN HDA_SDIN0 G15 HDA_SDATA_IN0 HDA_SDATA_OUT F15 78 20 HDA_SDOUT_R 1 2 HDA_SDOUT OUT 53 78

Int PD 5%
1/16W BIOS Boot Select
R2171 MF-LF
402
22
6 NC_MLB_RAM_SIZE J14 HDA_SDATA_IN1_GPIO_2/PS2_KB_CLK HDA_BITCLK E15 78 20 HDA_BIT_CLK_R 1 2 HDA_BIT_CLK OUT 53 78 I/F HDA_SDOUT LPC_FRAME#
Int PD 5%
1/16W
MF-LF
402 R2172 LPC 0 0
TP_MLB_RAM_VENDOR J15 HDA_SDATA_IN2_GPIO_3/PS2_KB_DATA HDA_RST_R_L 22 HDA_RST_L
HDA_RESET* K15 78 20 1 2
71 69 68 67 66 61 58 57 53
26 23 22 21 20 18 17 12 7 6
49 47 46 45 43 41 37 35 27
PP3V3_S0
(MXM_OK for MXM systems) Int PD 5%
OUT 53 78
PCI 0 1
82 72 1/16W
1
R2110 R2173 MF-LF
402 SPI0 1 0
HDA_SYNC_R 22 HDA_SYNC
49.9 HDA_SYNC L15 78 20 1 2
OUT 53 78
1%
1/16W
MF-LF
5%
1/16W
SPI1 1 1
MF-LF
2 402 402
MCP_HDA_PULLDN_COMP A15 HDA_PULLDN_COMP MCP_GPIO_4 SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L
78 HDA_DOCK_EN*_GPIO_4/PS2_MS_CLK K17 20

HDA_DOCK_RST*_GPIO_5/PS2_MS_DATA L17 AUD_I2C_INT_L IN 20 58 R1961 and R2160 selects SPI0 ROM by

22 PP1V05_S0_MCP_PLL_NV default, LPC+ debug card pulls
37 mA (A01) 20 mA AE18 +V_PLL_NV_H SLP_S3* G17 PM_SLP_S3_L OUT 6 32 35 40 67 71 LPC_FRAME# high for SPI1 ROM override.
17 mA AE17 +V_PLL_SP_SPREF SLP_RMGT* J17 PM_SLP_RMGT_L OUT 8 32

PM_SLP_S4_L NOTE: MCP79 does not support FWH, only

SLP_S5* H17 OUT 6 38 40 41 67
LPC ROMs. So Apple designs will
45 43 42 41 40 38 24 21 7 6 PP3V42_G3H not use LPC for BootROM override.
67 60 59 48 42 OUT SPIROM_USE_MLB L24 GPIO_1/PWRDN_OK/SPI_CS1
THERM_DIODE_P B11 MCP_THMDIODE_P OUT 46 82
41 40 35 32 IN SMC_ADAPTER_EN L26 GPIO_12_SUS_STAT_ACCLMTR_EXT_TRIG_L NOTE: MCP79 rev A01 does not support
THERM_DIODE_N C11 MCP_THMDIODE_N OUT 46 82
PP3V3_S0 53 57 58 61 66 67 68 69 71
6 7 12 17 18 20 21 22 23 26 SPI1 option. Rev B01 will.
R21201 1
R2121 6 NC_SB_A20GATE K13 A20GATE Int PU BOOT_MODE_SAFE
27 35 37 41 43 45 46 47 49
72 82
49.9K 49.9K
C 1%
1/16W
MF-LF
1%
1/16W
MF-LF 40
TP_MCP_KBDRSTIN_L
SMC_WAKE_SCI_L
L13
C19
KBRDRSTIN* Int PU
SIO_PME* Int PU (S5)
MCP_VID0/GPIO_13 L20
MCP_VID1/GPIO_14 M20
MCP_VID<0>
MCP_VID<1>
OUT 20 64

20 64
1
R2180
10K BUF_SIO_CLK Frequency
C
IN OUT
402 2 2 402 5%
SMC_RUNTIME_SCI_L C18 EXT_SMI/GPIO_32* Int PU (S5) MCP_VID2/GPIO_15 M21 MCP_VID<2> 1/16W
40 IN OUT 20 64
MF-LF Frequency HDA_SYNC
2 402
SM_INTRUDER_L B20 INTRUDER*
SPKR C13 MCP_SPKR OUT 41

BOOT_MODE_USER
24 MHz 1
TP_MCP_LID_L M25 LID* Int PU (S5) 1
40 IN PM_BATLOW_L M24 LLB* Int PU (S5) SMB_CLK0 L19 SMBUS_MCP_0_CLK OUT 12 26 27 43 78
R2181 14.31818 MHz 0
10K
SMB_DATA0 K19 SMBUS_MCP_0_DATA BI 12 26 43 78 5% USER mode: Normal
1/16W

MISC
75 61 IN PM_DPRSLPVR M22 CPU_DPRSLPVR SMB_CLK1/MSMB_CLK G21 SMBUS_MCP_1_CLK OUT 43 58 72 78 MF-LF SAFE mode: For ROMSIP
SMB_DATA1/MSMB_DATA F21 SMBUS_MCP_1_DATA 43 58 72 78
2 402 recovery
BI
40 IN PM_PWRBTN_L C16 PWRBTN* Int PU (S5) SMB_ALERT*/GPIO_64 M23 AP_PWR_EN OUT 20 29 32
Connects to SMC for
SPI Frequency Select
24 IN PM_SYSRST_DEBOUNCE_L D16 RSTBTN* Int PU
automatic recovery.
(MGPIO2) FANRPM0/GPIO_60 B12 MEM_EVENT_L IN 20 26 27 40
Frequency SPI_DO SPI_CLK
RTC_RST_L C20 RTC_RST*
FANCTL0/GPIO_61 A12 ODD_PWR_EN_L
(MGPIO3) FANRPM1/GPIO_63 D12 SMC_IG_THROTTLE_L
OUT 37

20 40 41
31 MHz 0 0
PM_RSMRST_L D20 PWRGD_SB IN
40 IN
FANCTL1/GPIO_62 C12 ARB_DETECT
24 IN MCP_PS_PWRGD E20 PS_PWRGD 20
42 MHz 0 1
24 IN MCP_CPU_VLD C17 CPU_VLD CPUVDD_EN D17 MCP_CPUVDD_EN OUT 24 25 MHz 1 0
12 IN JTAG_MCP_TDI E19 JTAG_TDI Int PU
SPI_CS0/GPIO_10 C14 SPI_CS0_R_L 42 78
1 MHz 1 1
JTAG_MCP_TDO F19 OUT
12 1 OUT JTAG_TDO
SPI_CLK/GPIO_11 D13 SPI_CLK_R OUT 42 78
12 IN JTAG_MCP_TMS J19 JTAG_TMS Int PU NOTE: Straps not provided on this page.
SPI_DI/GPIO_8 C15 SPI_MISO IN 42 78
12 IN JTAG_MCP_TRST_L J18 JTAG_TRST*
SPI_DO/GPIO_9 B14 SPI_MOSI_R OUT 42 78
12 IN JTAG_MCP_TCK G19 JTAG_TCK

B 24 IN MCP_CLK25M_XTALIN A16 XTALIN SUS_CLK/GPIO_34 B18 PM_CLK32K_SUSCLK_R OUT 24 78

B
24 OUT MCP_CLK25M_XTALOUT B16 XTALOUT BUF_SIO_CLK AE7 TP_MCP_BUF_SIO_CLK

24 IN RTC_CLK32K_XTALIN A19 XTALIN_RTC TEST_MODE_EN K22 MCP_TEST_MODE_EN

24 OUT RTC_CLK32K_XTALOUT B19 XTALOUT_RTC PKG_TEST L22
1 1
R2163 R2190
R21501 1
R2151 5%
10K
1%
1K
10K 100K 1/16W 1/16W
5% 5% MF-LF MF-LF
1/16W 1/16W 2 402 2 402
MF-LF MF-LF
402 2 2 402

PP3V3_S0 58 61 66 67 68 69 71 72 82
6 7 12 17 18 20 21 22 23 26 27
35 37 41 43 45 46 47 49 53 57
PP3V3_S3
HDA Output Caps 1
R2140 1
R2141 1
R2142 1
R2143 2
R2154
6 7 25 29 30 43 48 50 68

For EMI Reduction on HDA interface 10K 10K 10K 10K 100K
5% 5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF MF-LF
HDA_SDOUT_R 20 78
2 402 2 402 2 402 2 402 1 402
HDA_BIT_CLK_R 20 78
MCP_GPIO_4 20 AP_PWR_EN 20 29 32

HDA_RST_R_L 20 78 AUD_I2C_INT_L 20 58

HDA_SYNC_R 20 78 MEM_EVENT_L 20 26 27 40 MCP HDA & MISC

SMC_IG_THROTTLE_L 20 40 41 MCP_VID<0> 20 64
SYNC_MASTER=T18_MLB SYNC_DATE=02/05/2009
A C2170
10PF
1 C2172
10PF
1
ARB_DETECT 20
MCP_VID<1>
MCP_VID<2>
20 64

20 64 NOTICE OF PROPRIETARY PROPERTY

A
5% 5%
50V 50V
CERM 2 CERM 2 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
402 402 1 1 1 1
R2147 R2155 R2156 R2157 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
100K 22K 22K 22K
5% 5% 5% 5% I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1 C2171 1 C2173 1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF II NOT TO REPRODUCE OR COPY IT
10PF 10PF
5% 5% 2 402 2 402 2 402 2 402 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
50V 50V
2 CERM 2 CERM
402 402
SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 20 83
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
OMIT OMIT
U1400 U1400
MCP79-TOPO-B MCP79-TOPO-B
BGA BGA
(11 OF 11) PPVCORE_S0_MCP
64 44 22 7 6
(10 OF 11) PP1V05_S0 66 67
6 7 9 10 11 12 13 16 17 19 22
23 35 61 65
AH26 GND161 GND253 AV40 23065 mA (A01, 1.2V) AA25 +VDD_CORE1 +VTT_CPU1 R32 1139 mA 1182 mA (A01)
AH33 GND162 GND254 BA1 16996 mA (A01, 1.0V) AC23 +VDD_CORE2 +VTT_CPU2 AC32
AH34 GND163 GND255 BA4 U25 +VDD_CORE3 +VTT_CPU3 E40
AH37 GND164 GND256 AW31 AH12 +VDD_CORE4 +VTT_CPU4 J36
AH38 GND165 GND257 AY6 AG10 +VDD_CORE5 +VTT_CPU5 N32
AJ39 GND166 GND258 L35 AG5 +VDD_CORE6 +VTT_CPU6 T32

D AJ8 GND167 GND259 BC33 Y21 +VDD_CORE7 +VTT_CPU7 U32 D

AK10 GND168 GND260 BC37 Y23 +VDD_CORE8 +VTT_CPU8 V32
AK33 GND169 GND261 BC41 AA16 +VDD_CORE9 +VTT_CPU9 W32
AK34 GND170 GND262 AY14 AA26 +VDD_CORE10 +VTT_CPU10 P31
AK37 GND171 GND263 BC5 AA27 +VDD_CORE11 +VTT_CPU11 AF32
AK4 GND172 GND264 C2 AA28 +VDD_CORE12 +VTT_CPU12 AE32
AK40 GND173 GND265 D10 AC16 +VDD_CORE13 +VTT_CPU13 AH32
AL36 GND174 GND266 D14 AC17 +VDD_CORE14 +VTT_CPU14 AJ32
AL40 GND175 GND267 D15 AC18 +VDD_CORE15 +VTT_CPU15 AK31
AL5 GND176 GND268 D18 AC19 +VDD_CORE16 +VTT_CPU16 AK32
AM10 GND177 GND269 D19 AC20 +VDD_CORE17 +VTT_CPU17 AD32
AM16 GND178 GND270 D22 AC21 +VDD_CORE18 +VTT_CPU18 AL31
AM18 GND179 GND271 D23 AA17 +VDD_CORE19 +VTT_CPU19 AB32
AM20 GND180 GND272 D26 AC24 +VDD_CORE20 +VTT_CPU20 B41
AM22 GND181 GND273 D30 AC25 +VDD_CORE21 +VTT_CPU21 B42
AM24 GND182 GND274 D37 AC26 +VDD_CORE22 +VTT_CPU22 C40
AM26 GND183 GND275 D6 AC27 +VDD_CORE23 +VTT_CPU23 C41
AM30 GND184 GND276 E13 AC28 +VDD_CORE24 +VTT_CPU24 C42
AM34 GND185 GND277 E17 AD21 +VDD_CORE25 +VTT_CPU25 D39
AM35 GND186 GND278 E21 AD23 +VDD_CORE26 +VTT_CPU26 D40
AM37 GND187 GND279 E25 W27 +VDD_CORE27 +VTT_CPU27 D41
AM38 GND188 GND280 E29 V25 +VDD_CORE28 +VTT_CPU28 E38
AM5 E33 AA18 E39

POWER
GND189 GND281 +VDD_CORE29 +VTT_CPU29
AM6 GND190 GND282 F12 AE19 +VDD_CORE30 +VTT_CPU30 F37
AM7 GND191 GND283 F16 AE21 +VDD_CORE31 +VTT_CPU31 F38
AM9 GND192 GND284 F32 AE23 +VDD_CORE32 +VTT_CPU32 F39
AP26 F8 AE25 G36
C AN28
GND193
GND194
GND285
GND286 G10 AE26
+VDD_CORE33
+VDD_CORE34
+VTT_CPU33
+VTT_CPU34 G37 C
AN30 GND195 GND287 G12 AE27 +VDD_CORE35 +VTT_CPU35 G38
AN39 GND196 GND288 G14 AE28 +VDD_CORE36 +VTT_CPU36 H35
AN4 GND197 GND289 G16 AF10 +VDD_CORE37 +VTT_CPU37 H37
Y7 GND198 GND290 BC12 AF11 +VDD_CORE38 +VTT_CPU38 J34
AP10 GND199 GND291 G22 AA19 +VDD_CORE39 +VTT_CPU39 J35
AU26 GND200 GND292 G24 AF2 +VDD_CORE40 +VTT_CPU40 K33
AP14 GND201 GND293 AW20 AF21 +VDD_CORE41 +VTT_CPU41 K34
AU14 GND202 GND294 G34 AF23 +VDD_CORE42 +VTT_CPU42 K35
AP28 GND203 GND295 G4 AF25 +VDD_CORE43 +VTT_CPU43 L32
AP32 GND204 GND296 G43 AF3 +VDD_CORE44 +VTT_CPU44 L33
GND

AP34 GND205 GND297 G6 AF4 +VDD_CORE45 +VTT_CPU45 L34

AP36 GND206 GND298 G8 AF7 +VDD_CORE46 +VTT_CPU46 M31
AP37 GND207 GND299 H11 AH23 +VDD_CORE47 +VTT_CPU47 M32
AP4 GND208 GND300 H15 AF9 +VDD_CORE48 +VTT_CPU48 M33
AP40 GND209 GND301 AW35 AA20 +VDD_CORE49 +VTT_CPU49 N31
AP7 GND210 GND302 H23 AG11 +VDD_CORE50 +VTT_CPU50 P32
AW23 GND211 GND303 AN8 AG12 +VDD_CORE51 +VTT_CPU51 Y32
AR28 GND212 GND304 G40 AG21 +VDD_CORE52 +VTT_CPU52 AA32
AR32 GND213 GND305 J12 AG23 +VDD_CORE53
AR40 GND214 GND306 J8 AG25 +VDD_CORE54 +VTT_CPUCLK AG32 43 mA
AT10 GND215 GND307 K10 AG3 +VDD_CORE55
AR12 GND216 GND308 K12 AG4 +VDD_CORE56
AT13 GND217 GND309 K18 AA21 +VDD_CORE57
AT29
PP3V3_S0 46 47 49 53 57 58 61 66 67 68
6 7 12 17 18 20 22 23 26 27 35
GND218 GND310 K26 AG6 +VDD_CORE58 37 41 43 45
+3.3V_1 AD10 450 mA 69(A01)
71 72 82
AT33 GND219 GND311 K37 AG7 +VDD_CORE59
B AT6 GND220 GND312 K4 AG8 +VDD_CORE60
+3.3V_2
+3.3V_3
AE8
AB10
B
AT7 GND221 GND313 K40 AG9 +VDD_CORE61
+3.3V_4 AD9
AT9 GND222 GND314 K8 AH1 +VDD_CORE62
+3.3V_5 Y10
AY21 GND223 GND315 AU1 AH10 +VDD_CORE63
+3.3V_6 AB11
AY22 GND224 GND316 L40 AH11 +VDD_CORE64
+3.3V_7 AA8
L12 GND225 GND317 L43 W26 +VDD_CORE65
+3.3V_8 Y9
AU12 GND226 GND318 L5 AH2 +VDD_CORE66
AU28 GND227 GND319 M10 AA23 +VDD_CORE67
AP33 GND228 GND320 M34 W28 +VDD_CORE68
AU32 GND229 GND321 M35 AH25 +VDD_CORE69 PP3V3_S5 68 69 71 82
6 7 17 19 22 24 28 32 35 36 42
52 62 66 67
AR30 GND230 GND322 M37 AH21 +VDD_CORE70 +3.3V_DUAL1 G18 16 mA 266 mA (A01)
AU36 GND231 GND323 Y28 AH3 +VDD_CORE71 +3.3V_DUAL2 H19
AU38 GND232 GND324 Y33 AH4 +VDD_CORE72 +3.3V_DUAL3 J20
AU4 GND233 GND325 Y34 AH5 +VDD_CORE73 +3.3V_DUAL4 K20
G28 GND234 GND326 Y35 AH6 +VDD_CORE74
F20 GND235 GND327 Y37 AH7 +VDD_CORE75 +3.3V_DUAL_USB1 G26 250 mA
AV28 GND236 GND328 Y38 AH9 +VDD_CORE76 +3.3V_DUAL_USB2 H27
AV32 GND237 GND329 AB17 AA24 +VDD_CORE77 +3.3V_DUAL_USB3 J28
AV36 GND238 GND330 AB16 W21 +VDD_CORE78 +3.3V_DUAL_USB4 K28
AV4 GND239 GND331 AN26 W23 +VDD_CORE79
AV7 GND240 GND332 AD7 W25 +VDD_CORE80
AW11 GND241 GND333 M11 AF12 +VDD_CORE81
PP1V05_S5 6 7 22 32 66
G20 GND242 GND334 AA4
+VDD_AUXC1 T21 105 mA (A01)
PP3V42_G3H
AR43
AW43
GND243
GND244
GND335
GND336
AB19
AY13
45 43 42 41 40 38 24 20 7 6
67 60 59 48
10 uA (G3)
+VDD_AUXC2 U21 MCP Power & Ground
A20 +VBAT +VDD_AUXC3 V21
AY10 P11 80 uA (S0) SYNC_MASTER=T18_MLB SYNC_DATE=02/05/2009
A AV12
GND245
GND246
GND337
GND338 Y6
NOTICE OF PROPRIETARY PROPERTY
A
AY30 GND247 GND339 T11
AY33 GND248 GND340 V11 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AY34 GND249 GND341 Y11 AGREES TO THE FOLLOWING
AY37 GND250 GND342 AH16 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
AY38 GND251 GND343 T22 II NOT TO REPRODUCE OR COPY IT
AY41 GND252 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 21 83
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
MCP Core Power NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)
PPVCORE_S0_MCP Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)
64 44 21 7 6

23065 mA (A01, 1.2V)

16996 mA (A01, 1.0V)
(No IG vs. EG data)
C2500 1 C2501 1 C2502 1 C2503 1 1 C2504 1 C2505 1 C2506 1 C2507 1 C2508 1 C2509 1 C2510 1 C2511 1 C2512 1 C2513
4.7UF 4.7UF 4.7UF 4.7UF 1UF 1UF 1UF 1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 10% 10% 10% 10% 20% 20% 20% 20% 20% 20%
4V 4V 4V 4V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V
X5R 2 X5R 2 X5R 2 X5R 2 X5R X5R X5R X5R CERM CERM CERM CERM CERM CERM
402 402 402 402 402-1 402-1 402-1 402-1 402 402 402 402 402 402

D MCP PCIE (DVDD) Power MCP SATA (DVDD) Power L2570 NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF) D
67 66 65 61 35
PP1V05_S0 PP1V05_S0 PP1V05_S0 30-OHM-5A Apple: 5x 2.2uF 0402 (11 uF) PP1V05_S0_MCP_PEX_AVDD 7 16
13 12 11 10 9 7 6 21 19 17 16 13 12 11 10 9 7 6 21 19 17 16 13 12 11 10 9 7 6
23 22 21 19 17 16 67 66 65 61 35 23 22 67 66 65 61 35 23 22
1 2 MIN_LINE_WIDTH=0.4 MM
57 mA (A01) 43 mA (A01) 333 mA (A01) MIN_NECK_WIDTH=0.2 MM 206 mA (A01)
0603 VOLTAGE=1.05V

C2515 1 1 C2516 1 C2517 1 C2518 1 C2519 C2520 1 1 C2521 1 C2570 1 C2571 1 C2572 1 C2573 1 C2574
4.7UF 1UF 1UF 0.1uF 0.1uF 4.7UF 0.1uF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 10% 10% 20% 20% 20% 20% 20% 20% 20% 20% 20%
4V 2 10V 2 10V 2 10V 2 10V 4V 2 10V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
X5R 2 X5R X5R CERM CERM X5R 2 CERM CERM CERM CERM CERM CERM
402 402-1 402-1 402 402 402 402 402-LF 402-LF 402-LF 402-LF 402-LF

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

MCP 1.05V AUX Power MCP 1.05V RMGT Power
L2575 Apple: 2x 2.2uF 0402 (4.4 uF)
66 32 21 7 6 PP1V05_S5 32 31 22 17 7 6 PP1V05_ENET 30-OHM-5A PP1V05_S0_MCP_SATA_AVDD 7 19
1 2 MIN_LINE_WIDTH=0.4 MM
105 mA (A01) 131 mA (A01) MIN_NECK_WIDTH=0.2 MM 127 mA (A01)
0603 VOLTAGE=1.05V
1 C2525 1 C2526 C2528 1 1 C2529 1 C2575 1 C2576
0.1uF 0.1uF 4.7uF 0.1uF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20%
10V
2 CERM 10V
2 CERM 4V 10V 6.3V 6.3V
X5R 2 2 CERM 2 CERM 2 CERM
402 402 402 402 402-LF 402-LF

MCP FSB (VTT) Power NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)
Apple: 7x 2.2uF 0402 (15.4 uF)
L2580
67 66 65 61 35
13 12 11 10 9 7 6 PP1V05_S0 66 7 PP1V05_S0_MCP_PLL_UF 30-OHM-1.7A PP1V05_S0_MCP_PLL_FSB 13
23 22 21 19 17 16
1 2 MIN_LINE_WIDTH=0.4 MM
1182 mA (A01) 562 mA (A01) MIN_NECK_WIDTH=0.2 MM270 mA (A01)
0402 VOLTAGE=1.05V

C 1 C2530
2.2UF
1 C2531
2.2UF
1 C2532
2.2UF
1 C2533
2.2UF
1 C2534
2.2UF
1 C2535
2.2UF
1 C2536
2.2UF
C2580 1
4.7UF
1 C2581
0.1UF
C
20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
4V
X5R 2 2 10V
CERM
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402 402

MCP Memory Power

L2582
66 37 15 11 10 7 6 PP1V5_S0 30-OHM-1.7A PP1V05_S0_MCP_PLL_PEX 16
82 68 67
1 2 MIN_LINE_WIDTH=0.4 MM
4771 mA (A01, DDR3) MIN_NECK_WIDTH=0.2 MM 84 mA (A01)
0402 VOLTAGE=1.05V

C2540 1 1 C2541 1 C2542 1 C2543 1 C2544 1 C2545 1 C2546 1 C2547 1 C2548 1 C2549 C2582 1 1 C2583
4.7UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 4.7UF 0.1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
4V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 4V 2 10V
X5R 2 CERM CERM CERM CERM CERM CERM CERM CERM CERM X5R 2 CERM
402 402 402 402 402 402 402 402 402 402 402 402

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

MCP 3.3V Power NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)
L2555 Apple: 1x 2.2uF 0402 (2.2 uF)
L2584
82 72
Apple: 4x 2.2uF 0402 (8.8 uF) 30-OHM-1.7A PP1V05_S0_MCP_PLL_SATA 19
58 57 53 49 47 46 45 43 41
21 20 18 17 12 7 6 PP3V3_S0 72 71 69 68 67 66 61 58 57 53
26 23 22 21 20 18 17 12 7 6 PP3V3_S0 30-OHM-1.7A PP3V3_S0_MCP_PLL_USB 19 MIN_LINE_WIDTH=0.4 MM
37 35 27 26 23 22 49 47 46 45 43 41 37 35 27 MIN_LINE_WIDTH=0.4 MM 1 2 MIN_NECK_WIDTH=0.2 MM 84 mA (A01)
71 69 68 67 66 61
450 mA (A01) 82
19 mA (A01) 1 2 MIN_NECK_WIDTH=0.2 MM 19 mA (A01) VOLTAGE=1.05V
VOLTAGE=3.3V 0402
0402
1 C2550 1 C2551 1 C2552 1 C2553 1 C2555 C2584 1 1 C2585
4.7UF 0.1UF
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 20% 20%
20% 20% 20% 20% 20% 4V 2 10V
2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V X5R 2 CERM
CERM CERM CERM CERM CERM 402 402
402-LF 402-LF 402-LF 402-LF 402-LF
B B
MCP 3.3V AUX/USB Power NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) MCP 3.3V Ethernet Power NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
L2586
30-OHM-1.7A PP1V05_S0_MCP_PLL_CORE 15
82 71 69 68 67 66
PP3V3_S5 Apple: 1x 2.2uF 0402 (2.2 uF) PP3V3_ENET Apple: 1x 2.2uF 0402 (2.2 uF) 1 2 MIN_LINE_WIDTH=0.4 MM
28 24 21 19 17 7 6 32 31 22 17 7 6 MIN_NECK_WIDTH=0.2 MM 87 mA (A01)
62 52 42 36 35 32
0402 VOLTAGE=1.05V
266 mA (A01) 83 mA (A01)
1 C2560 1 C2564 C2586 1 1 C2587
2.2UF 2.2UF 4.7UF 0.1UF
20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM
4V
X5R 2 2 10V
CERM
402-LF 402-LF 402 402

MCP 3.3V/1.5V HDA Power NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
L2588
30-OHM-1.7A PP1V05_S0_MCP_PLL_NV 20
82 72
58 57 53 49 47 46 45 43 41
PP3V3_S0 Apple: 1x 2.2uF 0402 (2.2 uF) 1 2 MIN_LINE_WIDTH=0.4 MM
21 20 18 17 12 7 6 MIN_NECK_WIDTH=0.2 MM 37 mA (A01)
37 35 27 26 23 22
0402 VOLTAGE=1.05V
71 69 68 67 66 61
7 mA (A01)
1 C2562 C2588 1 1 C2589 1 C2590
2.2UF 4.7UF 0.1UF 0.1UF
20%
2 6.3V
CERM
MCP79 Ethernet VRef 20%
4V
X5R 2
20%
2 10V
CERM
20%
2 10V
CERM
402-LF 402 402 402
32 31 22 17 7 6 PP3V3_ENET

R25911 MCP Standard Decoupling

1.47K
1%
SYNC_MASTER=T18_MLB SYNC_DATE=02/05/2009
A L2595
1/16W
MF-LF
402 2
NOTICE OF PROPRIETARY PROPERTY
A
32 31 22 17 7 6 PP1V05_ENET 30-OHM-1.7A PP1V05_ENET_MCP_PLL_MAC 17 MCP_MII_VREF 17
OUT
1 2 MIN_LINE_WIDTH=0.4 MM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
5 mA (A01) 5 mA (A01)
MIN_NECK_WIDTH=0.2 MM PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
VOLTAGE=1.05V AGREES TO THE FOLLOWING
0402
R25901 1 C2591 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
C2595 1 1 C2596 1.47K
1% 0.1UF II NOT TO REPRODUCE OR COPY IT
4.7UF 0.1UF 1/16W 20%
20% 20% 10V
4V MF-LF 2 CERM III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
X5R 2 2 10V
CERM 402 2 402
402 402 SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 22 83
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)
Apple: 2x 2.2uF 0402 (4.4 uF)
66 53 17 7 6 PP1V8_S0 PP3V3_S0_MCP_DAC 17
MIN_LINE_WIDTH=0.4 MM
190 mA (A01, 1.8V) MIN_NECK_WIDTH=0.2 MM 206 mA (A01)
VOLTAGE=3.3V
1 C2610
2.2UF 1
R2651
20%
2 6.3V
CERM 0
5%
D
402-LF 1/16W
MF-LF
2 402
D

21 19 17 16 13 12 11 10 9 7 6
67 66 65 61 35 22
PP1V05_S0
95 mA (A01)

C2615 1 1 C2616
4.7UF 2.2UF
20% 20%
4V 6.3V
X5R 2 2 CERM
402 402-LF

23 17 NC_MCP_RGB_RED NC_MCP_RGB_RED 17 23
MAKE_BASE=TRUE NO_TEST=TRUE
23 17 NC_MCP_RGB_GREEN NC_MCP_RGB_GREEN 17 23
MAKE_BASE=TRUE NO_TEST=TRUE
23 17 NC_MCP_RGB_BLUE NC_MCP_RGB_BLUE 17 23
MAKE_BASE=TRUE NO_TEST=TRUE
23 17 NC_MCP_RGB_HSYNC NC_MCP_RGB_HSYNC 17 23
MAKE_BASE=TRUE NO_TEST=TRUE
23 17 NC_MCP_RGB_VSYNC NC_MCP_RGB_VSYNC 17 23
77 17 MCP_HDMI_RSET 77 17 MCP_IFPAB_RSET MAKE_BASE=TRUE NO_TEST=TRUE
77 17 MCP_HDMI_VPROBE 77 17 MCP_IFPAB_VPROBE NO STUFF
1 1 77 23 17 NC_CRT_IG_R_C_PR NC_CRT_IG_R_C_PR 17 23 77
NO STUFF NO STUFF
C C2620 1
R2620
1K
1%
C2630 1 1%
R2630
1K 77 23 17 NC_CRT_IG_G_Y_Y
MAKE_BASE=TRUE
NC_CRT_IG_G_Y_Y
MAKE_BASE=TRUE
NO_TEST=TRUE

NO_TEST=TRUE
17 23 77
C
0.1UF 1/16W 0.1UF 1/16W
20% MF-LF 20% MF-LF 77 23 17 NC_CRT_IG_B_COMP_PB NC_CRT_IG_B_COMP_PB 17 23 77
10V 10V NO_TEST=TRUE
CERM 2 2 402 CERM 2 2 402 MAKE_BASE=TRUE
402 402
77 23 17 NC_CRT_IG_HSYNC NC_CRT_IG_HSYNC 17 23 77
MAKE_BASE=TRUE NO_TEST=TRUE
77 23 17 NC_CRT_IG_VSYNC NC_CRT_IG_VSYNC 17 23 77
MAKE_BASE=TRUE NO_TEST=TRUE

WF: Checklist says 0-ohm resistor placeholder for ferrite bead. 23 17 NC_MCP_RGB_DAC_RSET NC_MCP_RGB_DAC_RSET 17 23
MAKE_BASE=TRUE NO_TEST=TRUE
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
NC_MCP_RGB_DAC_VREF NC_MCP_RGB_DAC_VREF 17 23
L2640 Apple: ???
23 17
MAKE_BASE=TRUE NO_TEST=TRUE
82 72 71 69 68 67 66 61 58
27 26 22 21 20 18 17 12 7 6 PP3V3_S0 30-OHM-1.7A PP3V3_S0_MCP_VPLL 17
57 53 49 47 46 45 43 41 37 35
1 2 MIN_LINE_WIDTH=0.4 MM
16 mA (A01) MIN_NECK_WIDTH=0.2 MM 16 mA (A01) 77 23 17 NC_MCP_TV_DAC_RSET NC_MCP_TV_DAC_RSET 17 23 77
0402 VOLTAGE=3.3V MAKE_BASE=TRUE NO_TEST=TRUE
77 23 17 NC_MCP_TV_DAC_VREF NC_MCP_TV_DAC_VREF 17 23 77
C2640 1 1 C2641 MAKE_BASE=TRUE NO_TEST=TRUE
4.7UF 0.1uF
20% 20%
6.3V 2 2 10V 23 17 NC_MCP_CLK27M_XTALIN NC_MCP_CLK27M_XTALIN 17 23
CERM CERM MAKE_BASE=TRUE NO_TEST=TRUE
603 402
23 17 NC_MCP_CLK27M_XTALOUT NC_MCP_CLK27M_XTALOUT 17 23
MAKE_BASE=TRUE NO_TEST=TRUE

B B

MCP Graphics Support

A SYNC_MASTER=K19_MLB

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=02/05/2009
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 23 83
Current numbers from email Xiaowei Lin provided 11/12/2007 3:22pm (no official document number).

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

Platform Reset Connections

RTC Power Source LPC Reset (Unbuffered)
PP3V42_G3H 6 7 20 21 24 38 40 41 42 43 45

43 42 41 40 38 24 21 20 7 6 PP3V42_G3H
48 59 60 67
R2881
67 60 59 48 45 PLACEMENT_NOTE=Place close to U1400 33
78 18 IN LPC_RESET_L 1 2 DEBUG_RESET_L OUT 42

C2800 1 C2801 1 1 C2802 5%

D
D 4.7UF
20%
6.3V
4.7UF
20%
6.3V
0.1UF
10%
16V
1/16W
MF-LF
402
R2883
33
X5R 2 X5R 2 2 X5R 1 2 SMC_LRESET_L OUT 40
402 402 402 PLACEMENT_NOTE=Place close to U1400 5%
1/16W
MF-LF
402

PCIE Reset (Unbuffered)

RTC Crystal C2810
R2810 12pF
0 1 2 35 24 16 IN PCIE_RESET_L PCIE_RESET_L OUT 16 24 35
20 IN RTC_CLK32K_XTALOUT 1 2 RTC_CLK32K_XTALOUT_R MAKE_BASE=TRUE
5% 5%
1/16W 50V R2891
MF-LF CERM
402
402 1
0 2 PCA9557D_RESET_L OUT 25
NO STUFF
1 CRITICAL 5%
R2811 1/16W

4
MF-LF
10M Y2810 R2893 402
5% 1
0 2 BKLT_PLT_RST_L
1/16W 32.768K OUT 73
MF-LF 7X1.5X1.4-SM C2811 5%

1
402 2
12pF 1/16W
MF-LF
20 OUT RTC_CLK32K_XTALIN 1 2 402 R2894
0
5%
1 2 MINI_RESET_L OUT 29
50V 5%
CERM 1/16W
402
C MCP 25MHz Crystal C2815
R2895
1
0 2
MF-LF
402

CARDREADER_PLT_RST_L OUT 30
C
R2815 12pF 5%
0 1 2 1/16W
20 IN MCP_CLK25M_XTALOUT 1 2 MCP_CLK25M_XTALOUT_R MF-LF
402
5% 5%
1/16W 50V
MF-LF CERM
402
402
NO STUFF
R28161 CRITICAL
3
1M

2 4
5% Y2815 NC
1/16W 25.0000M NC
MF-LF SM-3.2X2.5MM C2816
1
402 2
12pF R2870
20 MCP_CLK25M_XTALIN 1 2 33
OUT MEM_VTT_EN_R 1 2 MEM_VTT_EN
18 IN OUT 8 63 68
5% 5%
50V 1/16W
CERM MF-LF
402 402

R2825
LPC_CLK33M_SMC_R PLACEMENT_NOTE=Place close to U1400 1 33 2 LPC_CLK33M_SMC
78 18 IN OUT 40 78

5%
1/16W
MF-LF R2826
402 33 LPC_CLK33M_LPCPLUS
MCP S0 PWRGD & CPU_VLD 1
5%
1/16W
MF-LF
2
PLACEMENT_NOTE=Place close to U1400
OUT 42 78

402
36 35 32 28 22 21 19 17 7 6 PP3V3_S5
82 71 69 68 67 66 62 52 42

B B
1 C2850
0.1UF
20%
10V
2 CERM
402 R2829
22
78 20 IN PM_CLK32K_SUSCLK_R 1 2 PM_CLK32K_SUSCLK OUT 40 78

PLACEMENT_NOTE=Place close to U1400 5%

5 TC7SZ08AFEAPE
1/16W
MF-LF
67 66 65 64 62 40 IN ALL_SYS_PWRGD 2
A
SOT665 402
U2850Y 4 MCP_PS_PWRGD OUT 20

61 IN VR_PWRGOOD_DELAY 1
B

R2850
0
20 IN MCP_CPUVDD_EN 1 2 MCP_CPU_VLD OUT 20

PLACEMENT_NOTE=Place close to U1400 5%

1/16W
MF-LF
402

System Reset Circuit

PM_SYSRST_L
40 IN
XDP
SB Misc
R2896 R2899 10K pull-up to 3.3V S0 inside MCP SYNC_MASTER=WFERRY_K19I SYNC_DATE=01/06/2009
A 12 9 XDP_DBRESET_L 1
0 2 1
33 2 PM_SYSRST_DEBOUNCE_L 20 NOTICE OF PROPRIETARY PROPERTY
A
IN OUT
5%
1/16W
OMIT 5%
1/16W
NO STUFF
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
MF-LF
402 R28971 MF-LF
402
1 C2899 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
0 1UF
5% 10% I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1/16W 2 10V
X5R
MF-LF 402 II NOT TO REPRODUCE OR COPY IT
402 2
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SILK_PART=SYS RST
PLACEMENT_NOTE=Place R2897 on BOTTOM SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 24 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
Page Notes
Power aliases required by this page: MEM A VREF DQ MEM A VREF CA MEM B VREF DQ MEM B VREF CA CPU FSB VREF
- =PP3V3_S3_VREFMRGN
DAC channel A B A B C
- =PP3V3_S5_VREFMRGN
Min DAC code 0x00 0x00 0x00 0x00 0x00
- =PPVTT_S3_DDR_BUF
Max DAC code 0x87 0x87 0x87 0x87 0x55
Signal aliases required by this page: Max sink I -3.75 mA -3.75 mA -3.75 mA -3.75 mA -0.91 mA
- =I2C_VREFDACS_SCL Max source I 5 mA 5 mA 5 mA 5 mA 0.52 mA
SO-DIMM A and SO-DIMM B Vref settings should be margined separately
- =I2C_VREFDACS_SDA Nominal Vref 0.75 V 0.75 V 0.75 V 0.75 V 0.70 V (i.e. not simultaneously) due to current limitation of TPS51116 regulator.
- =I2C_PCA9557D_SCL Min Vref 0.375 V 0.375 V 0.375 V 0.375 V 0.091 V
- =I2C_PCA9557D_SDA Max Vref 1.250 V 1.250 V 1.250 V 1.250 V 1.044 V PPVTTDDR_S3
63 7

D BOM options provided by this page:

Vref Stepping
(per DAC LSB)
6.5 mV 6.5 mV 6.5 mV 6.5 mV 11.2 mV
10mA max load D
VREFMRGN
NO_VREFMRGN R2903 VREFMRGN

1
200 2
1%
1/16W
MF-LF PP0V75_S3_MEM_VREFDQ_A
402
VREFMRGN A2
B1 U2902 MIN_LINE_WIDTH=0.3 mm
26

1 C2903 V+
MAX4253
UCSP
R2904 VREFMRGN MIN_NECK_WIDTH=0.2 mm

0.1UF A1 VREFMRGN_DQ_SODIMMA_BUF 1
100 2
20% VREFMRGN
10V 1%
2 CERM A3 A4 Place close to J3100.1
PP3V3_S3 402 V- 1/16W
68 50 48 43 30 29 20 7 6 25 VREFMRGN_DQ_SODIMMA_EN MF-LF
B4 402
VREFMRGN VREFMRGN R2905 VREFMRGN
R2901

2
C2900 1 C2901 1
200 2
2.2UF 0.1UF 100K VREFMRGN
20% 20% 5% 1%
6.3V 2 10V 1/16W 1/16W
CERM CERM MF-LF MF-LF PP0V75_S3_MEM_VREFDQ_B

1
402-LF 402 402 402
C2
B1 U2902 MIN_LINE_WIDTH=0.3 mm
27

V+
MAX4253
UCSP R2906 VREFMRGN MIN_NECK_WIDTH=0.2 mm

C1 100
VREFMRGN VREFMRGN VREFMRGN_DQ_SODIMMB_BUF 1 2

8 U2900
1%
C3 C4 1/16W Place close to J3200.1
V- VREFMRGN_DQ_SODIMMB_EN MF-LF
VDD B4
25
402
SMBUS_SMC_MGMT_SCL 6 SCL 1 VREFMRGN_DQ_SODIMM
81 43 40 37 25 IN MSOP VOUTA
R2902 R2909

2
DAC5574
VREFMRGN
81 43 40 37 25 SMBUS_SMC_MGMT_SDA 7 SDA VOUTB 2 VREFMRGN_CA_SODIMM
BI 200
100K VREFMRGN 1 2
9 A0 VOUTC 4 VREFMRGN_CPUFSB 5%
1/16W 1%
MF-LF 1/16W
ADDR=0x98(WR)/0x99(RD)

1
10 A1 VOUTD 5
C NC
VREFMRGN A2
B1 U2903
402 MF-LF
402
PP0V75_S3_MEM_VREFCA_A
MIN_LINE_WIDTH=0.3 mm
26 C
GND 1 C2904 V+
MAX4253
UCSP
R2910 VREFMRGN MIN_NECK_WIDTH=0.2 mm

3 0.1UF A1 1
100 2
VREFMRGN VREFMRGN_CA_SODIMMA_BUF
20%
10V 1%
2 CERM A3 A4 Place close to J3100.126
1/16W
402 V- 25 VREFMRGN_CA_SODIMMA_EN MF-LF
B4 402

R2907 R2911 VREFMRGN

2
1
200 2
100K VREFMRGN
5% 1%
1/16W 1/16W
MF-LF MF-LF PP0V75_S3_MEM_VREFCA_B

1
402 402
C2
B1 U2903 MIN_LINE_WIDTH=0.3 mm
27

V+
MAX4253
UCSP R2912 VREFMRGN MIN_NECK_WIDTH=0.2 mm

C1 1
100 2
VREFMRGN VREFMRGN_CA_SODIMMB_BUF
1%
C3 C4 1/16W Place close to J3200.126
V- 25 VREFMRGN_CA_SODIMMB_EN MF-LF
B4 402

R2908

2
100K VREFMRGN
5%
1/16W
MF-LF

1
402
VREFMRGN A2
B1 U2904
MAX4253
1 C2905 V+ UCSP
0.1UF VREFMRGN A1
20% NC
2 10V
CERM A3 A4
402 V-
B4

B B

C2
B1 U2904
VREFMRGN V+
MAX4253
UCSP
R2914 VREFMRGN
1 C2902 VREFMRGN 100
16

VREFMRGN C1 VREFMRGN_CPUFSB_BUF 1 2 CPU_GTLREF

0.1UF OUT 9 75
20% VCC 1%
2 10V C3 C4 1/16W Place close to U1000.AD26
CERM
402 U2901 V-
B4
25 VREFMRGN_CPUFSB_EN MF-LF
402
PCA9557
QFN
6
P0 R2913

2
NC VREFMRGN_CPUFSB_EN
3 A0 P1 7 25
VREFMRGN_CA_SODIMMA_EN 100K VREFMRGN
4 A1 P2 9 5%
ADDR=0x30(WR)/0x31(RD) VREFMRGN_DQ_SODIMMA_EN
25
1/16W
5 A2 P3 10 25 MF-LF

1
VREFMRGN_CA_SODIMMB_EN 402
P4 11 25
VREFMRGN_DQ_SODIMMB_EN
P5 12 25

SMBUS_SMC_MGMT_SCL 1 SCL P6 13
81 43 40 37 25 IN NC
81 43 40 37 25 BI SMBUS_SMC_MGMT_SDA 2 SDA P7 14
NC
PCA9557D_RESET_L
THRM RESET* 15 IN 24
PAD GND
17

FSB/DDR3 Vref Margining

SYNC_MASTER=K24_MLB SYNC_DATE=02/05/2009
A NOTICE OF PROPRIETARY PROPERTY
A
Required zero ohm resistors when no VREF margining circuit stuffed THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
116S0004 1 RES,MTL FILM,0,5%,0402,SM,LF R2903 CRITICAL NO_VREFMRGN
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
116S0004 1 RES,MTL FILM,0,5%,0402,SM,LF R2905 CRITICAL NO_VREFMRGN
SIZE DRAWING NUMBER REV.
116S0004 1 R2909 CRITICAL NO_VREFMRGN
RES,MTL FILM,0,5%,0402,SM,LF
D 051-7903 A
116S0004 1 RES,MTL FILM,0,5%,0402,SM,LF R2911 CRITICAL NO_VREFMRGN APPLE INC. SCALE SHT OF
NONE 25 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
Page Notes DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)
GND
Power aliases required by this page:

- =PP1V5_S0_MEM_A

- =PP1V5_S3_MEM_A 68 63 28 27 7 6 PP1V5_S3 1 C3110 1 C3111 1 C3112 1 C3113 1 C3114 1 C3115 1 C3116 1 C3117 1 C3118 1 C3119 1 C3120 1 C3121 1 C3122 1 C3123
- =PP0V75_S0_MEM_VTT_A
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
- =PPSPD_S0_MEM_A (2.5 - 3.3V) 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
402 402 402 402 402 402 402 402 402 402 402 402 402 402
Signal aliases required by this page:
1 C3100 1 C3101
- =I2C_SODIMMA_SCL
10UF 10UF
- =I2C_SODIMMA_SDA
20% 20%
2 6.3V
X5R 2 6.3V
X5R

D BOM options provided by this page:

(NONE)
603 603
25 PP0V75_S3_MEM_VREFDQ_A D
1 C3130 1 C3131
2.2UF 0.1UF
20% 20%
2 6.3V
CERM 2 10V
CERM
402-LF 402

1 VREFDQ VSS 2
3 VSS DQ4 4 MEM_A_DQ<4> 14 76
KEY
BI
76 14 MEM_A_CKE<0> 73 CKE0 CKE1 74 MEM_A_CKE<1> 14 76 76 14 MEM_A_DQ<0> 5 DQ0 DQ5 6 MEM_A_DQ<5> 14 76
IN IN BI BI
75 76 MEM_A_DQ<1> 7 CRITICAL 8
VDD VDD 76 14 BI DQ1 VSS
77 78 NC_MEM_A_A<15> 9 10 MEM_A_DQS_N<0>
MEM_A_BA<2> 79
NC J3100 A15
80 MEM_A_A<14>
IN 8

MEM_A_DM<0> 11
VSS
J3100
DQS0*
12 MEM_A_DQS_P<0>
BI 14 76

76 14 IN BA2 F-RT-THB A14 IN 14 76 76 14 IN DM0 DQS0 BI 14 76

81 82 13 F-RT-THB 14

(SYMBOL 2 OF 2)
DDR3-SODIMM-DUAL-M97-3
VDD VDD VSS VSS

DDR3-SODIMM-DUAL-M97-3
(SYMBOL 1 OF 2)
76 14 MEM_A_A<12> 83 A12/BC* A11 84 MEM_A_A<11> 14 76 76 14 MEM_A_DQ<3> 15 DQ2 DQ6 16 MEM_A_DQ<6> 14 76
IN IN BI BI
76 14 MEM_A_A<9> 85 A9 A7 86 MEM_A_A<7> 14 76 76 14 MEM_A_DQ<2> 17 DQ3 DQ7 18 MEM_A_DQ<7> 14 76
IN IN BI BI
87 VDD VDD 88 19 VSS VSS 20
76 14 MEM_A_A<8> 89 A8 A6 90 MEM_A_A<6> 14 76 76 14 MEM_A_DQ<9> 21 DQ8 DQ12 22 MEM_A_DQ<8> 14 76
IN IN BI BI
76 14 MEM_A_A<5> 91 A5 A4 92 MEM_A_A<4> 14 76 76 14 MEM_A_DQ<13> 23 DQ9 DQ13 24 MEM_A_DQ<12> 14 76
IN IN BI BI
93 VDD VDD 94 25 VSS VSS 26
76 14 MEM_A_A<3> 95 A3 A2 96 MEM_A_A<2> 14 76 76 14 MEM_A_DQS_N<1> 27 DQS1* DM1 28 MEM_A_DM<1> 14 76
IN IN BI IN
76 14 MEM_A_A<1> 97 A1 A0 98 MEM_A_A<0> 14 76 76 14 MEM_A_DQS_P<1> 29 DQS1 RESET* 30 MEM_RESET_L 27 28
IN IN BI IN
99 VDD VDD 100 31 VSS VSS 32
76 14 MEM_A_CLK_P<0> 101 CK0 CK1 102 MEM_A_CLK_P<1> 14 76 76 14 MEM_A_DQ<11> 33 DQ10 DQ14 34 MEM_A_DQ<15> 14 76
IN IN BI BI
76 14 MEM_A_CLK_N<0> 103 CK0* CK1* 104 MEM_A_CLK_N<1> 14 76 76 14 MEM_A_DQ<14> 35 DQ11 DQ15 36 MEM_A_DQ<10> 14 76
IN IN BI BI
C 76 14 MEM_A_A<10>
105
107
VDD
A10/AP
VDD
BA1
106
108 MEM_A_BA<1> 14 76 76 14 MEM_A_DQ<16>
37
39
VSS
DQ16
VSS
DQ20
38
40 MEM_A_DQ<21> 14 76
C
IN IN BI BI
76 14 MEM_A_BA<0> 109 BA0 RAS* 110 MEM_A_RAS_L 14 76 76 14 MEM_A_DQ<18> 41 DQ17 DQ21 42 MEM_A_DQ<20> 14 76
IN IN BI BI
111 VDD VDD 112 43 VSS VSS 44
76 14 MEM_A_WE_L 113 WE* S0* 114 MEM_A_CS_L<0> 14 76 76 14 MEM_A_DQS_N<2> 45 DQS2* DM2 46 MEM_A_DM<2> 14 76
IN IN BI IN
76 14 MEM_A_CAS_L 115 CAS* ODT0 116 MEM_A_ODT<0> 14 76 76 14 MEM_A_DQS_P<2> 47 DQS2 VSS 48
IN IN BI
117 VDD VDD 118 49 VSS DQ22 50 MEM_A_DQ<17> 14 76
BI
76 14 MEM_A_A<13> 119 A13 ODT1 120 MEM_A_ODT<1> 14 76 76 14 MEM_A_DQ<23> 51 DQ18 DQ23 52 MEM_A_DQ<22> 14 76
IN IN BI BI
76 14 MEM_A_CS_L<1> 121 S1* NC 122 76 14 MEM_A_DQ<19> 53 DQ19 VSS 54
IN BI
123 VDD VDD 124 55 VSS DQ28 56 MEM_A_DQ<29> 14 76
BI
125 TEST VREFCA 126 76 14 MEM_A_DQ<24> 57 DQ24 DQ29 58 MEM_A_DQ<28> 14 76
BI BI
127 VSS VSS 128 76 14 MEM_A_DQ<30> 59 DQ25 VSS 60
BI
76 14 MEM_A_DQ<33> 129 DQ32 DQ36 130 MEM_A_DQ<36> 14 76
61 VSS DQS3* 62 MEM_A_DQS_N<3> 14 76
BI BI BI
76 14 MEM_A_DQ<32> 131 DQ33 DQ37 132 MEM_A_DQ<37> 14 76 76 14 MEM_A_DM<3> 63 DM3 DQS3 64 MEM_A_DQS_P<3> 14 76
BI BI IN BI
133 VSS VSS 134 65 VSS VSS 66
76 14 MEM_A_DQS_N<4> 135 DQS4* DM4 136 MEM_A_DM<4> 14 76 76 14 MEM_A_DQ<27> 67 DQ26 DQ30 68 MEM_A_DQ<26> 14 76
BI IN BI BI
76 14 MEM_A_DQS_P<4> 137 DQS4 VSS 138 76 14 MEM_A_DQ<25> 69 DQ27 DQ31 70 MEM_A_DQ<31> 14 76
BI BI BI
139 VSS DQ38 140 MEM_A_DQ<38> 14 76
71 VSS VSS 72
BI
76 14 MEM_A_DQ<34> 141 DQ34 DQ39 142 MEM_A_DQ<39> 14 76 KEY
BI BI
76 14 MEM_A_DQ<35> 143 DQ35 VSS 144
BI
145 VSS DQ44 146 MEM_A_DQ<47> 14 76 516-0196
BI
76 14 MEM_A_DQ<44> 147 DQ40 DQ45 148 MEM_A_DQ<40> 14 76
BI BI
76 14 MEM_A_DQ<41> 149 DQ41 VSS 150
BI
151 VSS DQS5* 152 MEM_A_DQS_N<5> 14 76
BI
76 14 MEM_A_DM<5> 153 DM5 DQS5 154 MEM_A_DQS_P<5> 14 76
IN BI
155 VSS VSS 156

B 76 14

76 14
BI
BI
MEM_A_DQ<45>
MEM_A_DQ<42>
157
159
DQ42
DQ43
DQ46
DQ47
158
160
MEM_A_DQ<46>
MEM_A_DQ<43>
BI
BI
14 76

14 76
B
161 VSS VSS 162
76 14 MEM_A_DQ<52> 163 DQ48 DQ52 164 MEM_A_DQ<48> 14 76
BI BI
76 14 MEM_A_DQ<51> 165 DQ49 DQ53 166 MEM_A_DQ<53> 14 76
BI BI
167 VSS VSS 168
76 14 MEM_A_DQS_N<6> 169 DQS6* DM6 170 MEM_A_DM<6> 14 76
BI IN
76 14 MEM_A_DQS_P<6> 171 DQS6 VSS 172
BI
173 VSS DQ54 174 MEM_A_DQ<50> 14 76
BI
76 14 MEM_A_DQ<55> 175 DQ50 DQ55 176 MEM_A_DQ<49> 14 76 PP0V75_S3_MEM_VREFCA_A 25
BI BI
76 14 MEM_A_DQ<54> 177 DQ51 VSS 178
BI
179 VSS DQ60 180 MEM_A_DQ<57> 14 76
BI
76 14 BI MEM_A_DQ<61> 181 DQ56 DQ61 182 MEM_A_DQ<56> BI 14 76
1 C3135 1 C3136
76 14 BI MEM_A_DQ<60> 183 DQ57 VSS 184 2.2UF 0.1UF
20% 20%
185 VSS DQS7* 186 MEM_A_DQS_N<7> BI 14 76 2 6.3V
CERM 2 10V
CERM
76 14 MEM_A_DM<7> 187 DM7 DQS7 188 MEM_A_DQS_P<7> 14 76
402-LF 402
IN BI
189 VSS VSS 190
76 14 MEM_A_DQ<58> 191 DQ58 DQ62 192 MEM_A_DQ<62> 14 76
BI BI
76 14 MEM_A_DQ<59> 193 DQ59 DQ63 194 MEM_A_DQ<63> 14 76
BI BI
195 VSS VSS 196
MEM_A_SA<0> 197 SA0 EVENT* 198 MEM_EVENT_L
82 72 OUT 20 27 40
53 49 47 46 45
20 18 17 12 7 6 PP3V3_S0 199 VDDSPD SDA 200 SMBUS_MCP_0_DATA 12 20 43 78 "Factory" (top) slot
43 41 37 35 27 23 22 21 BI
71 69 68 67 66 61 58 57 MEM_A_SA<1> 201 SA1 SCL 202 SMBUS_MCP_0_CLK 12 20 27 43 78
IN
203 VTT VTT 204 PP0V75_S0_DDRVTT 6 7 27 63 68

1 1 DDR3 SO-DIMM Connector A

1 C3140 R3140 R3141
10K 10K
A 2.2UF
20%
2 6.3V
5%
1/16W
MF-LF
5%
1/16W
MF-LF
516-0196
SPD ADDR=0xA0(WR)/0xA1(RD)
SYNC_MASTER=K19_MLB

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=02/05/2009

A
CERM
402-LF 2 402 2 402
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 26 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
Page Notes DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)
GND
Power aliases required by this page:

- =PP1V5_S0_MEM_B

- =PP1V5_S3_MEM_B 68 63 28 26 7 6 PP1V5_S3 1 C3210 1 C3211 1 C3212 1 C3213 1 C3214 1 C3215 1 C3216 1 C3217 1 C3218 1 C3219 1 C3220 1 C3221 1 C3222 1 C3223
- =PP0V75_S0_MEM_VTT_B
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
- =PPSPD_S0_MEM_B (2.5 - 3.3V) 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
402 402 402 402 402 402 402 402 402 402 402 402 402 402
Signal aliases required by this page:
1 C3200 1 C3201
- =I2C_SODIMMB_SCL
10UF 10UF
- =I2C_SODIMMB_SDA
20% 20%
2 6.3V
X5R 2 6.3V
X5R

D BOM options provided by this page:

(NONE)
603 603
25 PP0V75_S3_MEM_VREFDQ_B D
1 C3230 1 C3231
2.2UF 0.1UF
20% 20%
2 6.3V
CERM 2 10V
CERM
402-LF 402

1 VREFDQ VSS 2
3 VSS DQ4 4 MEM_B_DQ<4> 14 76
KEY
BI
76 14 MEM_B_CKE<0> 73 CKE0 CKE1 74 MEM_B_CKE<1> 14 76 76 14 MEM_B_DQ<0> 5 DQ0 DQ5 6 MEM_B_DQ<5> 14 76
IN IN BI BI
75 76 MEM_B_DQ<1> 7 CRITICAL 8
VDD VDD 76 14 BI DQ1 VSS
77 NC A15 78 NC_MEM_B_A<15> 8
9 VSS DQS0* 10 MEM_B_DQS_N<0> 14 76
IN BI
76 14 IN MEM_B_BA<2> 79 BA2 J3200 A14 80 MEM_B_A<14> IN 14 76 76 14 IN MEM_B_DM<0> 11 DM0 J3200 DQS0 12 MEM_B_DQS_P<0> BI 14 76
81 VDD F-RT-BGA3 VDD 82 13 F-RT-BGA3 14
VSS VSS

DDR3-SODIMM
(1 OF 2)
(2 OF 2)
MEM_B_A<12> 83 84 MEM_B_A<11> MEM_B_DQ<2> 15 16 MEM_B_DQ<6>

DDR3-SODIMM
76 14 IN A12/BC* A11 IN 14 76 76 14 BI DQ2 DQ6 BI 14 76

76 14 MEM_B_A<9> 85 A9 A7 86 MEM_B_A<7> 14 76 76 14 MEM_B_DQ<3> 17 DQ3 DQ7 18 MEM_B_DQ<7> 14 76

IN IN BI BI
87 VDD VDD 88 19 VSS VSS 20
76 14 MEM_B_A<8> 89 A8 A6 90 MEM_B_A<6> 14 76 76 14 MEM_B_DQ<28> 21 DQ8 DQ12 22 MEM_B_DQ<29> 14 76
IN IN BI BI
76 14 MEM_B_A<5> 91 A5 A4 92 MEM_B_A<4> 14 76 76 14 MEM_B_DQ<24> 23 DQ9 DQ13 24 MEM_B_DQ<25> 14 76
IN IN BI BI
93 VDD VDD 94 25 VSS VSS 26
76 14 MEM_B_A<3> 95 A3 A2 96 MEM_B_A<2> 14 76 76 14 MEM_B_DQS_N<3> 27 DQS1* DM1 28 MEM_B_DM<3> 14 76
IN IN BI IN
76 14 MEM_B_A<1> 97 A1 A0 98 MEM_B_A<0> 14 76 76 14 MEM_B_DQS_P<3> 29 DQS1 RESET* 30 MEM_RESET_L 26 28
IN IN BI IN
99 VDD VDD 100 31 VSS VSS 32
76 14 MEM_B_CLK_P<0> 101 CK0 CK1 102 MEM_B_CLK_P<1> 14 76 76 14 MEM_B_DQ<31> 33 DQ10 DQ14 34 MEM_B_DQ<26> 14 76
IN IN BI BI
76 14 MEM_B_CLK_N<0> 103 CK0* CK1* 104 MEM_B_CLK_N<1> 14 76 76 14 MEM_B_DQ<30> 35 DQ11 DQ15 36 MEM_B_DQ<27> 14 76
IN IN BI BI
C 76 14 MEM_B_A<10>
105
107
VDD
A10/AP
VDD
BA1
106
108 MEM_B_BA<1> 14 76 76 14 MEM_B_DQ<9>
37
39
VSS
DQ16
VSS
DQ20
38
40 MEM_B_DQ<13> 14 76
C
IN IN BI BI
76 14 MEM_B_BA<0> 109 BA0 RAS* 110 MEM_B_RAS_L 14 76 76 14 MEM_B_DQ<8> 41 DQ17 DQ21 42 MEM_B_DQ<12> 14 76
IN IN BI BI
111 VDD VDD 112 43 VSS VSS 44
76 14 MEM_B_WE_L 113 WE* S0* 114 MEM_B_CS_L<0> 14 76 76 14 MEM_B_DQS_N<1> 45 DQS2* DM2 46 MEM_B_DM<1> 14 76
IN IN BI IN
76 14 MEM_B_CAS_L 115 CAS* ODT0 116 MEM_B_ODT<0> 14 76 76 14 MEM_B_DQS_P<1> 47 DQS2 VSS 48
IN IN BI
117 VDD VDD 118 49 VSS DQ22 50 MEM_B_DQ<14> 14 76
BI
76 14 MEM_B_A<13> 119 A13 ODT1 120 MEM_B_ODT<1> 14 76 76 14 MEM_B_DQ<15> 51 DQ18 DQ23 52 MEM_B_DQ<11> 14 76
IN IN BI BI
76 14 MEM_B_CS_L<1> 121 S1* NC 122 76 14 MEM_B_DQ<10> 53 DQ19 VSS 54
IN BI
123 VDD VDD 124 55 VSS DQ28 56 MEM_B_DQ<20> 14 76
BI
125 TEST VREFCA 126 76 14 MEM_B_DQ<21> 57 DQ24 DQ29 58 MEM_B_DQ<16> 14 76
BI BI
127 VSS VSS 128 76 14 MEM_B_DQ<17> 59 DQ25 VSS 60
BI
76 14 MEM_B_DQ<32> 129 DQ32 DQ36 130 MEM_B_DQ<33> 14 76
61 VSS DQS3* 62 MEM_B_DQS_N<2> 14 76
BI BI BI
76 14 MEM_B_DQ<37> 131 DQ33 DQ37 132 MEM_B_DQ<36> 14 76 76 14 MEM_B_DM<2> 63 DM3 DQS3 64 MEM_B_DQS_P<2> 14 76
BI BI IN BI
133 VSS VSS 134 65 VSS VSS 66
76 14 MEM_B_DQS_N<4> 135 DQS4* DM4 136 MEM_B_DM<4> 14 76 76 14 MEM_B_DQ<18> 67 DQ26 DQ30 68 MEM_B_DQ<19> 14 76
BI IN BI BI
76 14 MEM_B_DQS_P<4> 137 DQS4 VSS 138 76 14 MEM_B_DQ<22> 69 DQ27 DQ31 70 MEM_B_DQ<23> 14 76
BI BI BI
139 VSS DQ38 140 MEM_B_DQ<38> 14 76
71 VSS VSS 72
BI
76 14 MEM_B_DQ<34> 141 DQ34 DQ39 142 MEM_B_DQ<39> 14 76 KEY
BI BI
76 14 MEM_B_DQ<35> 143 DQ35 VSS 144
BI
145 VSS DQ44 146 MEM_B_DQ<44> 14 76 516s0704
BI
76 14 MEM_B_DQ<41> 147 DQ40 DQ45 148 MEM_B_DQ<45> 14 76
BI BI
76 14 MEM_B_DQ<40> 149 DQ41 VSS 150
BI
151 VSS DQS5* 152 MEM_B_DQS_N<5> 14 76
BI
76 14 MEM_B_DM<5> 153 DM5 DQS5 154 MEM_B_DQS_P<5> 14 76
IN BI
155 VSS VSS 156

B 76 14

76 14
BI
BI
MEM_B_DQ<43>
MEM_B_DQ<42>
157
159
DQ42
DQ43
DQ46
DQ47
158
160
MEM_B_DQ<47>
MEM_B_DQ<46>
BI
BI
14 76

14 76
B
161 VSS VSS 162
76 14 MEM_B_DQ<55> 163 DQ48 DQ52 164 MEM_B_DQ<48> 14 76
BI BI
76 14 MEM_B_DQ<49> 165 DQ49 DQ53 166 MEM_B_DQ<54> 14 76
BI BI
167 VSS VSS 168
76 14 MEM_B_DQS_N<6> 169 DQS6* DM6 170 MEM_B_DM<6> 14 76
BI IN
76 14 MEM_B_DQS_P<6> 171 DQS6 VSS 172
BI
173 VSS DQ54 174 MEM_B_DQ<53> 14 76
BI
76 14 MEM_B_DQ<52> 175 DQ50 DQ55 176 MEM_B_DQ<50> 14 76 PP0V75_S3_MEM_VREFCA_B 25
BI BI
76 14 MEM_B_DQ<51> 177 DQ51 VSS 178
BI
179 VSS DQ60 180 MEM_B_DQ<60> 14 76
BI
76 14 BI MEM_B_DQ<56> 181 DQ56 DQ61 182 MEM_B_DQ<61> BI 14 76
1 C3235 1 C3236
76 14 BI MEM_B_DQ<57> 183 DQ57 VSS 184 2.2UF 0.1UF
20% 20%
185 VSS DQS7* 186 MEM_B_DQS_N<7> BI 14 76 2 6.3V
CERM 2 10V
CERM
1 MEM_B_DM<7> 187 188 MEM_B_DQS_P<7> 402-LF 402
R3240 76 14 IN
189
DM7 DQS7
190
BI 14 76

10K VSS VSS

5% 191 192
1/16W 76 14 BI MEM_B_DQ<63> DQ58 DQ62 MEM_B_DQ<58> BI 14 76
MF-LF 193 194
2 402 76 14 BI MEM_B_DQ<59> DQ59 DQ63 MEM_B_DQ<62> BI 14 76
195 VSS VSS 196
MEM_B_SA<0> 197 SA0 EVENT* 198 MEM_EVENT_L OUT 20 26 40
61 58 57 53 49 47
21 20 18 17 12 7 6 PP3V3_S0 199 VDDSPD SDA 200 =I2C_SODIMMB_SDA 43
BI
46 45 43 41 37 35 26 23 22
201 202 "Expansion" (bottom) slot
82 72 71 69 68 67 66 MEM_B_SA<1> SA1 SCL SMBUS_MCP_0_CLK IN 12 20 26 43 78
203 VTT VTT 204 PP0V75_S0_DDRVTT 6 7 26 63 68

1 205
MTG PINS
206 DDR3 SO-DIMM Connector B
1 C3240 R3241 207
MTG PIN MTG PIN
208
10K
A 2.2UF
20%
2 6.3V
5%
1/16W
MF-LF
209
MTG PIN
MTG PIN
MTG PIN
MTG PIN 210
SYNC_MASTER=K19_MLB

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=02/05/2009

A
CERM 211 212
402-LF 2 402 MTG PIN MTG PIN
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
516s0704 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
SPD ADDR=0xA2(WR)/0xA3(RD) II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 27 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

DDR3 RESET Support

Required becaues MCP79 does not meet DDR3 spec power-up reset timing requirement.

R3309
MCP_MEM_RESET_L 2
0 1 MEM_RESET_L
15 IN OUT 26 27

5%
1/16W
MF-LF
68 63 27 26 7 6 PP1V5_S3 402

C R33101 Q3305 C
1K PP3V3_S5 6 7 17 19 21 22 24 32 35 36 42
5% DMB53D0UDW 52 62 66 67 68 69 71 82
1/16W SOT-363
1 MF-LF 1
R3300 402 2 R3305 3.3V S5 is used because MEM_RESET

Q1
10K 100K

S
6

1
5% 5% must be high before 1.5V starts to
1/16W 1/16W
MF-LF MF-LF rise to avoid glitch on MEM_RESET_L.
402 2 402 2

G
5

2
MEM_RESET_RC_L MEM_RESET

R33011 C3300

Q2
1

C
4

3
20K 0.1UF
5% 20%
1/16W 10V
MF-LF 2 CERM
402 2 402

B B

DDR3 Support
SYNC_MASTER=T18_MLB SYNC_DATE=02/05/2009
A NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 28 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

PCIE_MINI_PRSNT_L
16 OUT
5V S3 WLAN FET
3 D Q3401 Part TPCP8102
D SSM6N15FEAPE
SOT563 Type P-Channel
D
Rds(on) 14 mOhm @4.5V
4 S G 5
Loading 0.8 A (EDP)
AP_PWR_EN IN 20 32
CRITICAL
PLACEMENT_NOTE=Place close to J3401.
L3404 Q3450
1000 mA peak FERR-120-OHM-1.5A XW3450
SM
TPCP8102
MINI_CLKREQ_L 750 mA nominal max 2 1 PP5V_WLAN_F 1 2 PP5V_WLAN_R
16 OUT 51 23V1K-SM

8
MIN_LINE_WIDTH=1 mm MIN_LINE_WIDTH=1 mm
0402-LF PP5V_S3

3
MIN_NECK_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm 6 7 8 29 37 38 39 41 49 51 53

6 7
VOLTAGE=5V VOLTAGE=5V 62 63 68

2
D
6 D Q3401 C3421 1 1 C3420 XW3451 XW3452

1
SSM6N15FEAPE 0.1uF 10UF

5
20% 20% SM SM 1
R3451

4 G
SOT563
10V
CERM 2
10V
2 X5R C3451 1
10K
402 805 0.033UF

1
10% 5%
16V 2 1/16W
1 S G 2 C3450 X5R
402 R3450
MF-LF
2 402
PLACEMENT_NOTEs: 0.1UF
1 2 P5VWLAN_SS 1
100K 2 PM_WLAN_EN_L IN 32
Place close to Q3450. 5%
(C3420 & C3421) 10% 1/16W
16V MF-LF
X5R

C3431
AIRPORT ISNS_AIRPORT_P OUT 51 82
402
402

ISNS_AIRPORT_N OUT 51 82
0.1uF PLACEMENT_NOTE=Place close to J3401.
CRITICAL 1 2 PCIE_MINI_R2D_C_P IN 16 77
J3401 C3430 10%
20347-325E-12 0.1uF 16V
X5R PP3V3_S3
C F-RT-SM
31
1 2 402 PCIE_MINI_R2D_C_N
PLACEMENT_NOTE=Place close to J3401.
IN 16 77
6 7 20 25 29 30 43 48 50 68
R34531
33K
C
10% 5%
16V
1 PCIE_MINI_D2R_P
X5R
402
U3402 5 1/16W
MF-LF
OUT 6 16 77 74LVC1G17DRL 402 2 R3455
2 TC7SZ08AFEAPE 5 SOT-553
PCIE_MINI_D2R_N OUT 6 16 77 CRITICAL 1
3
SOT665
A
2 WLAN_SMIT_BUF 4 2 WLAN_SMIT_RC 1 2 WLAN_SMIT_DISCHRG
4 82
77 6 PCIE_MINI_R2D_P
L3401
90-OHM-100MA
4
U3401
Y NC 5%
1/16W Q3455
1 1
5 82
77 6 PCIE_MINI_R2D_N
DLP11S
SYM_VER-1
B
3 1 1 C3453 R3454
62K
MF-LF
402 3 D SSM3K15FV
SOD-VESM-HF
6 4 3 PCIE_CLK100M_MINI_P IN 16 77
3 1UF 5%
7 NC 10% 1/16W
82 6 PCIE_CLK100M_MINI_CONN_P 2 6.3V
CERM MF-LF
8 402 402 2
82 6 PCIE_CLK100M_MINI_CONN_N
9
1 2 PCIE_CLK100M_MINI_N IN 16 77
2 S G 1
10 PLACEMENT_NOTE=Place close to J3401.
6 MINI_CLKREQ_Q_L
11 PCIE_WAKE_L 6 16
OUT
12 6 MINI_RESET_CONN_L
13 MINI_RESET_L IN 24
6 PP5V_WLAN
14 MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.5 mm
15 VOLTAGE=5V L3406
NC
16 PP3V3_S3_BT_F 2 1 PP3V3_S3 6 7 20 25 29 30 43 48 50 68
17 MIN_LINE_WIDTH=0.5 mm
6 PP5V_S3_BTCAMERA_F MIN_NECK_WIDTH=0.25 mm FERR-120-OHM-1.5A
18 MIN_LINE_WIDTH=0.5 mm VOLTAGE=3.3V
SMBUS_SMC_A_S3_SDA BI 6 40 43 49 81 MIN_NECK_WIDTH=0.25 mm 275 mA peak 0402-LF
19 SMBUS_SMC_A_S3_SCL VOLTAGE=5V
206 mA nominal max PLACEMENT_NOTE=Place close to J3401.
C3462 1
IN 6 40 43 49 81
0.1uF
20
21
22
USB_CAMERA_CONN_P ALS L3405
FERR-120-OHM-1.5A
20%
10V
CERM 2
402
USB_CAMERA_CONN_N CRITICAL 2 1 PP5V_S3 6 7 8 29 37 38 39 41 49 51 53

B
23
24
25
CONN_USB2_BT_P
L3402
90-OHM
DLP0NS
CAMERA 1 C3452
0402-LF
62 63 68

B
CONN_USB2_BT_N SYM_VER-1
0.1uF
4 3 USB_CAMERA_P BI 6 19 78
20%
10V
26 2 CERM
402
27 1 C3422 1 2 USB_CAMERA_N
28 0.1uF BI 6 19 78
20% PLACEMENT_NOTE=Place close to J3401.
29 10V
2 CERM
30 402

CRITICAL
32
L3403
90-OHM
DLP0NS
BLUETOOTH
518S0610 SYM_VER-1

4 3 USB_BT_P BI 6 19 78

1 2 USB_BT_N BI 6 19 78

PLACEMENT_NOTE=Place close to J3401.

Right Clutch Connector

SYNC_MASTER=K19_MLB SYNC_DATE=03/04/2009
A NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 29 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

R3511 PLACEMENT_NOTE=PLACE 402 NEAR EACH PIN

0
68 50 48 43 29 25 20 7 6 PP3V3_S3 1 2 30 PP3V3_S3_CARDREADER_DVDD
MIN_LINE_WIDTH=0.40MM MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM 5% MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V 1/16W VOLTAGE=3.3V
MF-LF 1 C3500 1 C3501 1 C3502 1 C3503
402
10UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20%
6.3V 10V 10V 10V
2 X5R 2 CERM 2 CERM 2 CERM

D
603 402 402 402
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION D
516-0225 1 CONN,SD CARD, OPTN B J3500 CRITICAL
L3500
PLACEMENT_NOTE=PLACE 402 NEAR EACH PIN 0.22UH
PP3V3_S3_CARDREADER_AVDD 1 2
MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM 0805-1
1 1 1
VOLTAGE=3.3V MAX CURRENT = 250MA
C3514 C3504 C3508 PLACEMENT_NOTE=KEEP THIS NET AS SHORT AS POSSIBLE
10UF 0.1UF 0.1UF PP3V3_SW_SD_PWR
20% 20% 20% MIN_LINE_WIDTH=0.30MM
2 6.3V
X5R 2 10V
CERM 2 10V
CERM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
603 402 402 1
1 C3507 1 C3505 R3505
2.2UF 0.1UF 39K
20% 20% 5%
6.3V 10V 1/16W
2 CERM1 2 CERM MF-LF
603 402 2 402
PP1V8_S3_CARDREADER
MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=1.8V
1 C3506
0.1UF
20% OMIT
2 10V
CERM
402 J3500
SD-CARD-K19

11

15
26
35

25

36
F-RT-TH

6
4
3

VDD18O

AVDD

DVDD

VDD5V

PMOSO
VSS
6
VSS
SD_CLK 5
82 6 CLK
SD_CMD 2

78 19 USB_CARDREADER_N 7 DM U3500 D0 40
82 6

82 6 SD_D<0> 7
CMD
DAT0
BI
GL137
C 78 19 BI USB_CARDREADER_P 8 DP
LQFP D1
D2
43
37
82 6

82 6
SD_D<1>
SD_D<2>
8
9
DAT1 C
CARDREADER_GPIO1 48 GPIO1 DAT2
30
D3 29 82 6 SD_D<3> 1
CARDREADER_GPIO2 47 GPIO2 CD/DAT3
30
D4 28 82 6 SD_D<4> 10
46 GPIO3 DAT4
NC D5 30 82 6 SD_D<5> 11
DAT5
19
SK D6 32 82 6 SD_D<6> 12
NC DAT6
20 CS D7 38 82 6 SD_D<7> 13
NC DAT7
21 DO 6 SD_CD_L 14
NC 39 SD_CLK_R CARD_DETECT_SW
22 DI /IPD SD_CLK/MS_SCLK/SM_ALE 15
NC IPD/ SD_WP/SM_WPDZ
3 CARD_DETECT_GND
6 SD_WP 16
CARDREADER_XTAL1 13 X1 41 WRITE_PROTECT_SW
IPD/ SD_CMD/SM_REZ 4
NO STUFF 14 X2 2 VDD
R3503 CARDREADER_XTAL2 IPU/ SM_CDZ CARDREADER_PDMOD
1M 23 17
1 2 CARDREADER_RREF 10 RREF IPU/ SD_CDZ SHLD_PIN
18
5% 1 SHLD_PIN
1/16W CARDREADER_TEST_MOD 17 TEST_MOD IPU/ XD_CDZ NC R3504 19
MF-LF
/IPD 31 0 SHLD_PIN
SM_CE NC 20
402 1 2 SHLD_PIN
CARDREADER_RESET_L 18 EXTRSTZ* /IPU IPD/ SM_WEZ
42
NC
44 5%
CRITICAL IPD/ SM_RBZ 1/16W NO STUFF
NC MF-LF
45 402 1 C3515
IPD/ SM_WPZ NC
Y3500 10PF
12.000M-100PPM IPU/ MS_INS
24 5%
1 2 NC 50V
2 CERM
33
IPD/ MS_BS/SM_CLE NC 402-1
8X4.5X1.4-SM
1 NO STUFF
1
R3506 R3502 AGND DGND
C3511 C3512 0 1 C3513
33PF 33PF 715 PDMOD: POWER DOWN MODES

34
5% 0.1UF

5
9
12

16
27
1 2 1 2 1% 1/16W 20%
1/16W MF-LF 10V NC = DISABLE (DEFAULT)
MF-LF 2 402 2 CERM
5% 5% 2 402 402 10K LOW = POWER SAVING MODE ENABLE
50V 50V 10K HIGH = REMOTE WAKE UP ENABLE
B CERM
402
CERM
402 30 PP3V3_S3_CARDREADER_DVDD B
Q3500 D 3 1
R3512
SSM6N15FEAPE 10K
SOT563 5%
1/16W
MF-LF
2 402
5 G S 4
16 IN CARDREADER_RESET (PDMOD)
CARDREADER_PLT_RST
D 6 NO STUFF
Q3500 1
R3513
SSM6N15FEAPE 10K
SOT563 5%
1/16W
MF-LF
2 402
2 G S 1
24 IN CARDREADER_PLT_RST_L

30 PP3V3_S3_CARDREADER_DVDD

1 1 NO STUFF
R3507 R3508
10K 10K
5%
1/16W
5%
1/16W
SECUREDIGITAL CARD READER
MF-LF MF-LF

A 30 CARDREADER_GPIO1
2 402 2 402
CARDREADER_GPIO2 30
SYNC_MASTER=K19_MLB

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=03/23/2009
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1NO STUFF 1 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
R3509 R3510 AGREES TO THE FOLLOWING
10K 10K I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
5% 5%
1/16W 1/16W II NOT TO REPRODUCE OR COPY IT
MF-LF MF-LF
2 402 2 402 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 30 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

PP1V05_ENET 6 7 17 22 32

(221mA typ - 1000base-T)

D ( 7mA typ - Energy Detect) D
C3710 1 C3711 1 1 WF: Marvell numbers, update for Realtek
0.1UF 0.1UF CRITICAL
10% 10%
PP3V3_ENET
16V 2
X5R
16V 2
X5R L3715
32 22 17 7 6 402 402 FERR-120-OHM-1.5A
(43mA typ - 1000base-T) 0402-LF
(19mA typ - Energy Detect)
WF: Marvell numbers, update for Realtek 1 1 C3700 1 C3701 1 C3702 2
CRITICAL 0.1UF 0.1UF 0.1UF
10% 10% 10% PP1V05_ENET_PHYAVDD
L3705 2 16V
X5R 2 16V
X5R
16V
2 X5R MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
FERR-120-OHM-1.5A 402 402 402 VOLTAGE=1.05V
0402-LF C3714 1 C3715 1 C3716 1
0.1UF 0.1UF 0.1UF
10% 10% 10%
2 16V 2 16V 2 16V 2
X5R X5R X5R
402 402 402
PP3V3_ENET_PHYAVDD
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V 1 C3705 1 C3706
0.1UF 0.1UF
10% 10% RTL8211_VDDREG 8
2 16V
X5R
16V
2 X5R
402 402 If internal switcher is used, must place 1x 22uF &
1x 0.1uF caps within 5mm of U3700 pins 44 & 45.
NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.
R37501 1
R3751 R37521
NC_RTL8211_REGOUT

41

15
21
37

44
45

28
36

10
40
4.7K 4.7K 4.7K 8

3
5% 5% 5%
1/16W 1/16W 1/16W If internal switcher is used, must place inductor within 5mm
R37201

AVDD33

DVDD33

VDDREG

FB12

DVDD12

AVDD12
MF-LF MF-LF MF-LF
10K 402 2 2 402 402 2 of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.
C Alias to =PP3V3_ENET_PHY for internal switcher.
Alias to GND for external 1.05V supply.
5%
1/16W
MF-LF
402 2
If internal switcher is not used, VDDREG and REGOUT can float. C
GND 39 ENSWREG
U3700 REGOUT 48
IN RTL8211CLGR
TQFP
R3796 OMIT
79 17 IN ENET_CLK125M_TXCLK 1 2 ENET_CLK125M_TXCLK_R 22 TXC CRITICAL RXC 19 79 ENET_CLK125M_RXCLK_R R3790 22 1 2 ENET_CLK125M_RXCLK OUT 17 79
22 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402
PLACEMENT_NOTE=Place R3796 close to U1400,pin D24
79 17 IN ENET_TXD<0> 23 TXD[0] RXD[0] 14 79 ENET_RXD_R<0> R3791 22 1 2 ENET_RXD<0> OUT 17 79
5% 1/16W MF-LF 402
79 17 IN ENET_TXD<1> 24 TXD[1] RXD[1]/TXDLY 16 79 ENET_RXD_R<1> R3792 22 1 2 ENET_RXD<1> OUT 17 79
25 RGMII/MII 17 R3793 22 5% 1/16W MF-LF 402
79 17 IN ENET_TXD<2> TXD[2] RXD[2]/AN0 79 ENET_RXD_R<2> 1 2 ENET_RXD<2> OUT 17 79
5% 1/16W MF-LF 402
79 17 IN ENET_TXD<3> 26 TXD[3] RXD[3]/AN1 18 79 ENET_RXD_R<3> R3794 22 1 2 ENET_RXD<3> OUT 17 79
5% 1/16W MF-LF 402

79 17 IN ENET_TX_CTRL 27 TXCTL RXCTL 13 ENET_RXCTL_R R3795 22 1 2 ENET_RX_CTRL OUT 17 79

5% 1/16W MF-LF 402

79 17 ENET_MDC 30 MDC MDI+[0] 1 ENET_MDI_P<0> 33 79

IN BI
31 MANAGEMENT 2
79 17 BI ENET_MDIO MDIO MDI-[0] ENET_MDI_N<0> BI 33 79

MDI+[1] 4 ENET_MDI_P<1> 33 79
BI
MDI-[1] 5 ENET_MDI_N<1> 33 79
79 17 ENET_RESET_L 29 PHYRSTB* RESET MEDIA DEPENDENT BI
IN
MDI+[2] 8 ENET_MDI_P<2> 33 79
BI
MDI-[2] 9 ENET_MDI_N<2> 33 79
BI
RTL8211_RSET 46 RSET REFERENCE
MDI+[3] 11 ENET_MDI_P<3> 33 79
BI
MDI-[3] 12 ENET_MDI_N<3> 33 79
BI
R37301
B 2.49K
1%
8 RTL8211_CLK125 32 CLK125 B
1/16W 34
MF-LF CLOCK LED0/PHYAD0 RTL8211_PHYAD0
402 2 42 35
79 32 IN RTL8211_CLK25M_CKXTAL1 CKXTAL1 LED LED1/PHYAD1 RTL8211_PHYAD1
TP_RTL8211_CKXTAL2 43 CKXTAL2 LED2/RXDLY 38 RTL8211_RXDLY
GND NO STUFF
C3790 1 R37551 R37561 1
R3757

7
20
33
47
10PF 4.7K 4.7K 4.7K
5% 5% 5% 5%
50V 1/16W 1/16W 1/16W
CERM 2 MF-LF MF-LF MF-LF
402 402 2 402 2 2 402

Reserved for EMI

per RealTek request.

Ethernet PHY (RTL8211CL)

SYNC_MASTER=(K19I_MLB) SYNC_DATE=02/05/2009
A NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
Configuration Settings: SIZE DRAWING NUMBER REV.
PHYAD = 01 (PHY Address 00001)
AN[1:0] = 11 (Full auto-negotiation)
D 051-7903 A
RXDLY = 0 (RXCLK transitions with data) APPLE INC. SCALE SHT OF
TXDLY = 0 (No TXCLK Delay) NONE 31 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

3.3V ENET FET

@ 2.5V Vgs: CRITICAL
Rds(on) = 90mOhm max Q3810
I(max) = 1.7A (85C) NTR4101P
SOT-23-HF
35 32 28 24 22 21 19 17 7 6
82 71 69 68 67 66 62 52 42 36
PP3V3_S5 PP3V3_ENET 6 7 17 22 31
2 S D 3

D D
R38001 1 C3811 G
10K 0.033UF
5% 10% 1
1/16W 16V
2 X5R
MF-LF
402 2 R3810 402 C3810
100K 2 0.01UF
P3V3ENET_EN_L 1 P3V3ENET_SS 2 1
5% 10%
1/16W 16V
D 3 MF-LF
Q3801 402 CERM
402
SSM6N15FEAPE
SOT563

5 G S 4
32 20 8 IN PM_SLP_RMGT_L
MOBILE:

Recommend aliasing PM_SLP_RMGT_L and

=P3V3ENET_EN. Nets separated on
ARB for alternate power options.

WLAN Enable Generation

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))

NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.

PM_WLAN_EN_L OUT 29

C Pull-up is with power FET.

1.05V ENET FET C
Q3805 D 6
SSM6N15FEAPE
SOT563 66 22 21 7 6 PP1V05_S5

1.8V Vgs
2 G S 1
C3840 1 3
29 20 IN AP_PWR_EN AC_OR_S0_L 0.1UF CRITICAL
20%
10V D
CERM 2
D 3 6 D 35 32 28 24 22 21 19 17 7 6 PP3V3_S5 R3840 402 Q3840
Q3805 Q3801 82 71 69 68 67 66 62 52 42 36
1
100K 2
P1V05ENET_SS 1 G SI2312BDS
SSM6N15FEAPE SSM6N15FEAPE S
SOT23
SOT563 SOT563 5%
1/16W
MF-LF D 6
R38421 402 Q3841 2
PP1V05_ENET
5 G S 4 G 2 69.8K SSM6N15FEAPE 6 7 17 22 31
1 S 1% SOT563
1/16W
41 40 35 20 IN SMC_ADAPTER_EN MF-LF
402 2
R3841 2 G S 1 1 C3841
10K 0.01UF
P1V05ENET_EN_L 1 2 10%
71 67 40 35 20 6 IN PM_SLP_S3_L 2 16V
CERM
1% 402
1/16W
D 3 MF-LF
Q3841 402 P1V05ENET_EN_L_RC
SSM6N15FEAPE
SOT563

5 G S 4

B 32 20 8 IN PM_SLP_RMGT_L
B
Non-ARB:

Recommend aliasing PM_SLP_RMGT_L and

=P1V05ENET_EN. Nets separated on
ARB for alternate power options.

RTL8211 25MHz Clock

NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered.
Ethernet & AirPort Support
A Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal. SYNC_MASTER=K19_MLB

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=02/05/2009
A
R3895 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
22 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
79 17 IN MCP_CLK25M_BUF0_R 1 2 RTL8211_CLK25M_CKXTAL1 OUT 31 79 AGREES TO THE FOLLOWING
5% I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1/16W
MF-LF II NOT TO REPRODUCE OR COPY IT
402
PLACEMENT_NOTE=Place close to U1400 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 32 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
Page Notes
Power aliases required by this page:
(NONE)
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
(NONE)

D D

Place one of 0.1uf cap close to each centertap pin of transformer

ENETCONN_CTAP
1 C3900 1 C39021 C39041 C3906
0.1UF 0.1UF 0.1UF 0.1UF
10% 10% 10% 10%
2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R
402 402 402 402

CRITICAL
T3900
SM
79 31 BI ENET_MDI_P<0> 1 82 12 ENETCONN_P<0>
79 31 BI ENET_MDI_N<0> 2 82 11 ENETCONN_N<0> CRITICAL
3 10 ENET_CTAP0 J3900
RJ45-M97-3
TX F-RT-TH
C 4
TLA-6T213HF
9 ENET_CTAP1
9
10
C
79 31 BI ENET_MDI_N<1> 5 8 82 ENETCONN_N<1> 1
2
79 31 BI ENET_MDI_P<1> 6 7 82 ENETCONN_P<1> 3
RX 4
5
CRITICAL 6
T3901
SM
7
79 31 BI ENET_MDI_N<2> 1 82 12 ENETCONN_N<2> 8

79 31 BI ENET_MDI_P<2> 2 82 11 ENETCONN_P<2> 11
12
3 10 ENET_CTAP2
TX 514-0636
TLA-6T213HF
4 9 ENET_CTAP3
79 31 BI ENET_MDI_N<3> 5 8 82 ENETCONN_N<3>
79 31 BI ENET_MDI_P<3> 6 7 82 ENETCONN_P<3>
RX

Transformers should be
mirrored on opposite
sides of the board
R3900
75
1R39011
75
1
R3902
75
1R3903
75
B 5% 5%
1/16W 1/16W
5%
1/16W
5%
1/16W
CRITICAL B
MF-LF
4022
MF-LF
4022
MF-LF
2402
MF-LF
2402
C3908
1000PF
CRITICAL CRITICAL CRITICAL CRITICAL ENET_BOB_SMITH_CAP1 2
1C3910 1C3920 1C3930
1 C3940 MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
10PF 10PF 10PF 10PF
5%
10%
2KV
5% 5% 5% 2 50V CERM
2 50V
CERM 2 50V
CERM 2 50V
CERM
CERM
402-1
1206
402-1 402-1 402-1
CRITICAL CRITICAL CRITICAL CRITICAL
1C3911 1C3921 1 C3931 1 C3941
10PF
5%
10PF
5%
10PF
5%
10PF
5%
2 50V
CERM 2 50V
CERM 2 50V
CERM 2 50V
CERM
402-1 402-1 402-1 402-1

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

Ethernet Connector
SYNC_MASTER=K19_MLB SYNC_DATE=03/13/2009
A NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 33 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

PP3V3_FW 7 34 35 36
7 mA I/O
138 mA

C4120 1 C4121 1 C4122 1 C4123 1 C4124 1

1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10%
6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2
CERM CERM CERM CERM CERM
402 402 402 402 402

L4130
120-OHM-0.3A-EMI
D 114 mA FireWire PHY PP3V3_FW_FWPHY_VDDA 1 2 D
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION MIN_LINE_WIDTH=0.4 MM 0402-LF
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
114S0556 1 RES,549mOHM,1%,1/16W,0402 R4100 CRITICAL C4130 1 C4131 1 C4132 1
1UF 1UF 1UF
10% 10% 10%
6.3V 2 6.3V 2 6.3V 2
CERM CERM CERM
402 402 402
OMIT
R4100 L4110 L4135
PP1V05_FW 1
0.2 2 PP1V0_FW_R 120-OHM-0.3A-EMI 120-OHM-0.3A-EMI
35 7
MIN_LINE_WIDTH=0.4 MM 1 2 PP1V0_FW_FWPHY_AVDD 25 mA PCIe SerDes 17 mA PCIe SerDes PP3V3_FW_FWPHY_VP25 1 2
135 mA 1%
1/16W
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.0V 0402-LF MIN_LINE_WIDTH=0.4 MM MIN_LINE_WIDTH=0.4 MM 0402-LF
MF-LF MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM
402 VOLTAGE=1.0V VOLTAGE=3.3V
1 C4110 1 C4111 C4135 1 C4136 1
1UF 1UF 1UF 1UF
10% 10% 10% 10%
2 6.3V
CERM 2 6.3V
CERM
6.3V 2
CERM
6.3V 2
CERM
402 402 402 402

110 mA Digital Core 0 mA VReg PWR

1 C4100 1 C4101 1 C4102 1 C4103 1 C4104 1 C4105 1 C4106 C4141 1 1 C4140

1UF 1UF 1UF 1UF 1UF 1UF 1UF 0.1UF 1UF
10% 10% 10% 10% 10% 10% 10% 20% 10%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
10V
CERM 2 2 6.3V
CERM
402 402 402 402 402 402 402 402 402

C PLACEMENT_NOTE=Place C4170 close to U1400

PLACEMENT_NOTE=Place C4171 close to U1400
C

B12
C13

E10

H12

M12

N11

C12

G12

L11

A12

L10

K12
C4170 PCIE_FW_R2D_C_N

A1
B1

E2

H2

K2
L1

N3

C1

F1

J1
L3

M2

D5
D6
D8

L5

L6
L9
1 2 16 77
IN
0.1UF 10% 16V X5R 402
VDD10 VDD33 VDDH VP VP25 VREG_PWR C4171 1 2 PCIE_FW_R2D_C_P IN 16 77
B13 ATBUSB OMIT N8 PCIE_FW_R2D_N 0.1UF 10% 16V X5R 402
NC PCIE_RXD0N 77

A13 ATBUSH CRITICAL N7 PCIE_FW_R2D_P

PCIE_RXD0P 77
NC
A11 ATBUSN
U4100 PCIE_TXD0N N5 77 PCIE_FW_D2R_C_N C4175 1 2 PCIE_FW_D2R_N
NC OUT 16 77

FW643E PCIE_TXD0P N6 77 PCIE_FW_D2R_C_P 0.1UF 10% 16V X5R 402

36 IN FWPHY_DS0 F12 DS0 (IPD) NT-2 C4176
BGA
1 2 PCIE_FW_D2R_P OUT 16 77
36 IN FWPHY_DS1 E12 DS1 (IPD) NT-3 0.1UF
REFCLKN N9 PCIE_CLK100M_FW_N IN 16 77
10% 16V X5R 402
36 IN FWPHY_DS2 E13 DS2 (IPD) NT-4 PCI EXPRESS PHY PLACEMENT_NOTE=Place C4175 close to U4100
REFCLKP N10 PCIE_CLK100M_FW_P IN 16 77 PLACEMENT_NOTE=Place C4176 close to U4100
80 36 BI NC_FW0_TPAN B8 TPA0N
80 36 BI NC_FW0_TPAP A8 TPA0P
NT-21 (IPU) TCK M4 TP_FW643_TCK
80 36 BI FW_PORT1_TPA_N B5 TPA1N
NT-20 (IPU) TDI N2 TP_FW643_TDI
80 36 BI FW_PORT1_TPA_P A5 TPA1P TEST CONTROLLER PP3V3_FW 7 34 35 36
(IPU) TDO M1 TP_FW643_TDO
36 BI NC_FW2_TPAN B3 TPA2N
NT-18 (IPU) TMS M3 TP_FW643_TMS
36 BI NC_FW2_TPAP A3 TPA2P 1394 PHY FW643_LDO
80 36 BI NC_FW0_TPBN B9 TPB0N NT-19 (IPU) TRST* N1 FW643_TRST_L R41651 1
R4166
80 36 BI NC_FW0_TPBP A9 TPB0P 10K 10K
5% 5%
80 36 BI FW_PORT1_TPB_N B6 TPB1N 1/16W 1/16W
FW_PORT1_TPB_P A6 (OD) MF-LF MF-LF
80 36 BI TPB1P 402 2 2 402
NT-10 (IPD)WAKE* C2 FW643_WAKE_L OUT 8 35
36 BI NC_FW2_TPBN B4 TPB2N
36 PPVP_FW_CPS FIXME!!! - TYPO IN SYMBOL REGCTL REGCLT D13 FW643_REGCTL
36 BI NC_FW2_TPBP A4 TPB2P
POWER MANAGEMENT VAUX_DETECT E1 FW643_VAUX_DETECT
R41601 36 BI NC_FW0_TPBIAS B7 TPBIAS0 NT-12 (IPD) VAUX_DISABLE D2 TP_FW643_VAUX_ENABLE
B 200K
1%
1/16W
36 35

36
BI
BI
FW_P1_TPBIAS
NC_FW2_TPBIAS
C3 TPBIAS1
A2 TPBIAS2
NT-13 (OD) CLKREQN L2 FW_CLKREQ_PHY_L OUT 35
1
R4164
10K
NOTE: FW_PME_L and FW_CLKREQ_L are
isolated for systems that use
B
MF-LF 5%
402 2
FW643_R0 B11 R0 1/16W 1394B physical plug detect.
MF-LF
FW643_TPCPS B10 TPCPS 2 402 WITH PLUG DETECT:
NT-16 (IPD) SCIFCLK G2 TP_FW643_SCIFCLK
G1 TP_FW643_SCIFDAIN - Gate CLKREQ# based on PHY power
TP_FW643_NAND_TREE K1 SCIF NT-14 (IPD) SCIFDAIN
C4150 NAND_TREE NT-OUT H1 TP_FW643_SCIFDOUT - TP (or NC) PME#
R4150 FW643_REXT L8 NT-17 SCIFDOUT
22PF REXT F2 TP_FW643_SCIFMC
1 2 412 NOTE: NT-xx notes show NT-15 (IPD) SCIFMC WITHOUT PLUG DETECT:
FW_CLK24P576M_XO 1 2 FW_CLK24P576M_XO_R F13 XO
FW_CLK24P576M_XI G13 NAND tree order. - Alias both signals to drop = prefix
5% CRITICAL 1%
1/16W
XI NT-9
50V Y4150 MF-LF
1

CERM 402 TP_FW643_SE M13 SE (IPD)

402 NC 24.576MHZ R41611 1
R4170 SERIAL EEPROM NT-7 SCL N12 FW643_SCL
2

SM-3.2X2.5MM TP_FW643_SM N13 SM (IPD)

C4151 NC 2.94K 191 CONTROLLER NT-6 SDA M11 TP_FW643_SDA
4

1% 1% TP_FW643_MODE_A J2 MODE_A (IPD) NT-1

3

22PF 1/16W 1/16W

TP_FW643_CE L13
1 2 MF-LF MF-LF CE (IPD)
402 2 2 402 TP_FW643_FW620_L D12 FW620* (IPU) MISCELLANEOUS
5% TP_FW643_JASI_EN D1 JASI_EN (IPD) NT-11
50V
CERM TP_FW643_AVREG A10 AVREG CHIP RESET NT-5 PERST* N4 FW_RESET_L 35
402 IN
TP_FW643_VBUF H13 VBUF
FW643_PU_RST_L K13 1
FW_RESET* (IPU) NT-8 R4163
TP_FW643_OCR10_CTL J12 OCR_CTL_V10 10K
5%
R41621 1 C4162 NC
J13 OCR_CTL_V12 (Reserved)
1/16W
MF-LF
470K 0.33UF 2 402
5% 10% VSS VREG_VSS
1/16W
MF-LF 2 6.3V
B2
D4
D7
D9
D10
E4
E5
E9
F4
F6
F7
F8
F10
G4
G6
G7
G8
G10
H4
H6
H7
H8
H10
J4
J5
J9
J10
K4
K5
K7
K8
K9
L7
K6
K10

L12
402 2 CERM-X5R
402
FireWire LLC/PHY (FW643E)
SYNC_MASTER=T18_MLB SYNC_DATE=02/05/2009
A NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 34 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
Page Notes
Power aliases required by this page: 3.3V FW FET
- =PPBUS_S5_FWPWRSW (system supply for bus power) @ 2.5V Vgs:
CRITICAL
- =PP3V3_FW_LATEVG_ACTIVE
Rds(on) = 90mOhm max Q4291
72 71 69 68 67 66 61 58 57
26 23 22 21 20 18 17 12 7 6 PP3V3_S0
- =PPVP_FW_SUMNODE (power passthru summation node) 53 49 47 46 45 43 41 37 35 27
82
72 71 69 68 67 66 61 58 57 PP3V3_S0 I(max) = 1.7A (85C) NTR4101P 1
Signal aliases required by this page:
26 23 22 21 20 18 17 12 7 6
53 49 47 46 45 43 41 37 35 27 SOT-23-HF R4281
82
PP3V3_FW 100K
(NONE)
2 S D 3
7 34 35 36
R4280 5%
1/16W
10K MF-LF
BOM options provided by this page: R4290 1 35 34 7 PP1V05_FW 1 2
2 402
10K 1%
5%
1/16W
1 C4290 G 1/16W
MF-LF
MF-LF 0.033UF 402
402 2 10% 1 3 CRITICAL
D P3V3FW_EN_L R4291
2 16V
X5R
402 C4291 P1V0_FW_RC 5 Q4299 D
0.01UF DMB53D0UV
1
100K 2
P3V3FW_SS 2 1 C4281 1 SOT-563
PP3V3_FW 1UF 4
36 35 34 7 Q4290 D 3 5%
1/16W 10%
10%
6.3V 2
SSM6N15FEAPE MF-LF 16V
CERM
CERM
402
SOT563 402
402
FW_PLUG_DET_L 8 18 35
PCIE_FW_PRSNT_L
OUT 8 16
R42771 1
R4276 5 G S 4 MAKE_BASE=TRUE
10K 100K
5% 5% FW_PWR_EN
1/16W
MF-LF
1/16W
MF-LF
35 18 IN
Q4264 D 3
P1V0_RESET_GATE
402 2 2 402
SSM6N15FEAPE
SOT563
3 CRITICAL R4283
FW_CLKREQ_L 16 10K
FW_WAKE 5 Q4276 1.05V FW FET OUT 1 2 PCIE_RESET_L IN 16 24

DMB53D0UV 5 G S 4 5%
1/16W
SOT-563 PP1V05_S0
NOSTUFF 21 19 17 16 13 12 11 10 9 7 6 MF-LF
4 67 66 65 61 35 23 22 CRITICAL 6 402
1 C4276 C4296 1 Q4264 D 6
0.1UF D Q4299
10% 0.1UF SSM6N15FEAPE
2 16V 20% SOT563 DMB53D0UV
X5R
402
R4297 10V
CERM 2
3
CRITICAL SOT-563
PP3V3_FW 1
220K 2 402 D 2 G
36 35 34 7
Q4295 FW_RESET_L OUT 34
CRITICAL 6 5%
1/16W
2 G S 1
MF-LF P1V05FW_SS 1 G SI2312BDS
D Q4276 402 S
SOT23
DMB53D0UV S
SOT-563
Q4293 D 6 2 FW_PWR_EN 1
34 8 FW643_WAKE_L 2 G 82 71 69 68 67 66
24 22 21 19 17 7 6
62 52 42 36 35 32 28
PP3V3_S5 SSM6N15FEAPE 35 18
PP1V05_FW PGOOD/FW_RESET_L
SOT563
R42951 PP1V05_FW 7 34 35

C S 10K
5%
1/16W
2 G S 1
NOSTUFF 35 34 FW_CLKREQ_PHY_L 35
34 FW_CLKREQ_PHY_L
C
1 IN
MF-LF MAKE_BASE=TRUE
402 2 R4296 1 C4295 FireWire Port Power Switch
100K 2 0.068UF
P1V05_FW_EN_L 1 10%
2 10V
CERM
5% 402
1/16W P1V05_FW_EN_L_RC
D 3 MF-LF
Q4293 402
SSM6N15FEAPE
SOT563

5 G S 4
35 18 FW_PWR_EN
CRITICAL
Q4260 CRITICAL
CRITICAL
NDS9407 F4260 D4260
SOI-HF 1.1A-24V SM
8 PPBUS_FW_FWPWRSW_F 1 2 PPBUS_FW_FWPWRSW_D 1 2 PPVP_FW 7 36
73 64 63 62 60 59 45 44 7 6 PPBUS_G3H 3
7 MIN_LINE_WIDTH=0.5 mm MIN_LINE_WIDTH=0.5 mm
2 MIN_NECK_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm
6 VOLTAGE=12.6V MINISMDC110H24 VOLTAGE=12.6V CRS08-1.5A-30V
1 1
CRITICAL R4260 C4260 1 5
Q4262 470K 0.1UF
5% 10%
DMB54D0UV 1/16W 25V 2
SOT-563 MF-LF X5R 4
2 402 402
Late-VG Event Detection FWPWR_EN_L_DIV
PP3V3_S0 53 57 58 61 66 67 68 69 71 72
6 7 12 17 18 20 21 22 23
26 27 35 37 41 43 45 46 47 49
82
4

3
E

C
Q2

R4265
B 2
10K 1 LATEVG_FAULT_EVENT_PNP
1
R4261
330K PP1V05_S0
1
R4274
B
5% 21 19 17 16 13 12 11 10 9 7 6
5

2
B

NOSTUFF 5% 1/16W 67 66 65 61 35 23 22 100K

R4263 1/16W
MF-LF
MF-LF
2 402
5%
1/16W
100 402 LATEVG_FAULT_EVENT MF-LF
LATEVG_RETRY_RC 1 2
2 402
FWPWR_EN_L
6

1
D

S
Q1

1 1 1
NOSTUFF
1%
1/16W R4275 R4270 R4271
MF-LF 1K 330K 56K FW_PLUG_DET_L 8 18 35
C4263 1 402
Q4261 D 6 5%
1/16W
5%
1/16W
5%
1/16W
OUT
1UF Q4261 D 3 MF-LF MF-LF MF-LF
10% SSM6N15FEAPE
10V SOT563 SSM6N15FEAPE 2 402 2 402 2 402 3 CRITICAL
X5R 2 SOT563
402-1
FW_DET_MIRROR FW_PLUG_DET 5 Q4275
FW_PWR_EN_L DMB53D0UV
2 G S 1 SOT-563
5 G S 4
SMC_ADAPTER_EN CRITICAL 3 6 CRITICAL 1 C4270 4
40 32 20
41 IN Q4270 5 2
Q4270 0.1UF
BC847CDXV6TXG BC847CDXV6TXG
71 67 40 32 20 6 IN PM_SLP_S3_L SOT563 SOT563
10%
16V
82 71 69
2 X5R
52 42 36 35
21 19 17 7 6
32 28 24 22
PP3V3_S5 4 1 402
68 67 66 62 PP2V4_FW_LATEVG Enables port power when machine

is running or on AC. FW_P1_TPBIAS_R FW_DET_EMIT

R42111 1
R4212 1 C4210 1 1
10K 10K 0.1UF
20%
R4272 R4273
5% 1% 1K 12K
1/16W 1/16W 2 10V
CERM CRITICAL 6 5% 5%
MF-LF MF-LF 402 1/16W 1/16W
402 2 2 402 MF-LF MF-LF
2 U4210 D Q4275 2 402 2 402
FWLATEGV_3V_REF 4
LMC7211 DMB53D0UV
V+ SM-HF SOT-563
1 LATEVG_EVENT FW_PWR_EN 2 G FireWire Port Power
35 18 IN

A P2V4_FWLATEVG_RC 3 V-
5
SYNC_MASTER=K19_MLB

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=03/18/2009
A
1 S
C4211 1 R4213 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
100pF 80.6K 1 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
5% 1% AGREES TO THE FOLLOWING
50V 1/16W
CERM 2 MF-LF I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
402 2 402 R4210 FWLATEVG Hysteresis: II NOT TO REPRODUCE OR COPY IT
1
200K 2
3.08V when port power is on III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
2.91V when late Vg event and port power is off
1%
1/16W 36 34 IN
FW_P1_TPBIAS SIZE DRAWING NUMBER REV.
MF-LF
402
D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 35 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
Page Notes
Power aliases required by this page:

36 35 34 7 PP3V3_FW
- =PPVP_FW_PORT1
- =PP3V3_FW_LATEVG R43821 R43801
10K 10K
1% 1%
1/16W 1/16W
MF-LF MF-LF
- =GND_CHASSIS_FW_PORT1 402 2 402 2
- =GND_CHASSIS_FW_EMI_R
36 34 FWPHY_DS0 FWPHY_DS0 34 36
Signal aliases required by this page:
(NONE)
FireWire PHY Config Straps 36 34
MAKE_BASE=TRUE
FWPHY_DS2 FWPHY_DS2
D
D NOTE: This page is expected to contain
Configures PHY for:
MAKE_BASE=TRUE
34 36

the necessary aliases to map the 36 34 FWPHY_DS1 FWPHY_DS1 34 36

MAKE_BASE=TRUE
FireWire TPA/TPB pairs to their - 1-port Portable Power Class (0)
appropriate connectors and/or to
properly terminate unused signals. - Port "1" Bilingual (1394B) R43811
10K
1%
BOM options provided by this page: 1/16W
MF-LF
(NONE) 402 2

NOTE: FireWire TPA/TPB pairs are NOT

constrained on this page. It is
assumed that FireWire PHY page will
provide the appropriate constraints 36 34 NC_FW0_TPBIAS NC_FW0_TPBIAS MAKE_BASE=TRUE 34 36

to apply to entire TPA/TPB XNets. 36 34 NC_FW2_TPBIAS NC_FW2_TPBIAS MAKE_BASE=TRUE 34 36

80 36 34 NC_FW0_TPAN NC_FW0_TPAN MAKE_BASE=TRUE 34 36 80

1394b implementation based on Apple
80 36 34 NC_FW0_TPAP NC_FW0_TPAP MAKE_BASE=TRUE 34 36 80
FireWire Design Guide (FWDG 0.6, 5/14/03)
36 34 NC_FW2_TPAN NC_FW2_TPAN MAKE_BASE=TRUE 34 36

36 34 NC_FW2_TPAP NC_FW2_TPAP MAKE_BASE=TRUE 34 36

80 36 34 NC_FW0_TPBN NC_FW0_TPBN MAKE_BASE=TRUE 34 36 80

80 36 34 NC_FW0_TPBP NC_FW0_TPBP MAKE_BASE=TRUE 34 36 80

Termination 36 34 NC_FW2_TPBN
NC_FW2_TPBP
NC_FW2_TPBN
NC_FW2_TPBP
MAKE_BASE=TRUE 34 36

36 34 MAKE_BASE=TRUE 34 36
Place close to FireWire PHY

BSS8402DW
TI PHYs require 1uF even though
FW_P1_TPBIAS

Q4300
35 34
FW spec calls out 0.33uF

SOT-363
(SYM-VER2)
C 1 C4360 C
0.33UF
10%
2 6.3V
CERM-X5R Cable Power
PPVP_FW

D
402

3
36 35 7
36 34PPVP_FW_CPS MAKE_BASE=TRUE PPVP_FW_CPS 34 36 CRITICAL
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
L4310 Note: Trace PPVP_FW_PORT1 must handle up to 5A
VOLTAGE=12.6V FERR-250-OHM
R43111 36 35 7 PPVP_FW

G
470K 1 2 PPVP_FW_PORT1_F
"Snapback" & "Late VG" Protection

5
5% SM MIN_LINE_WIDTH=0.5 mm
1/16W MIN_NECK_WIDTH=0.25 mm
MF-LF VOLTAGE=33V
402 2 36 35 PP2V4_FW_LATEVG CRITICAL 1 C4314
DP4310 0.01UF
10%
CPS_EN_L_DIV BAV99DW-X-G 2 50V
X7R
SOT-363
C4311 1 5
402
0.01uF
R43121
1
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
R4360 R43611
330K
5% CRITICAL
10%
50V 2
X7R
402
3 PORT 1
1/16W 4
56.2
1%
56.2
1%
MF-LF
402 2
DP4310 BILINGUAL
1/16W 1/16W CPS_EN_L BAV99DW-X-G
MF-LF MF-LF SOT-363
2 402 402 2 C4310 1
2
0.01uF
80 36 34 FW_PORT1_TPA_P FW_PORT1_TPA_P 34 36 80 6 10% CRITICAL
MAKE_BASE=TRUE 50V 2 6
FW_PORT1_TPA_N FW_PORT1_TPA_N D
X7R
402 J4310
80 36 34 34 36 80
1 1394B-M97
MAKE_BASE=TRUE Q4300 F-RT-TH
80 36 34 FW_PORT1_TPB_P FW_PORT1_TPB_P 34 36 80
2 G BSS8402DW TPB- TPB(R)
MAKE_BASE=TRUE 36 35 34 7 PP3V3_FW 80 36 34 FW_PORT1_TPB_N 1 TPB-
SOT-363
80 36 34 FW_PORT1_TPB_N FW_PORT1_TPB_N 34 36 80
S (SYM-VER1) (FW_PORT1_BREF) 9 TPB<R> OUTPUT
MAKE_BASE=TRUE
SIGNAL_MODEL=EMPTY 1 80 36 34 FW_PORT1_TPB_P 2 TPB+ TPB+
VP

SIGNAL_MODEL=EMPTY 8 VP
1
R4362 R43631
B 56.2
1%
56.2
1% (GND_FW_PORT1_VG)
NC 7
6
NCSC/NC

VG
B
1/16W 1/16W
MF-LF MF-LF 80 36 34 FW_PORT1_TPA_N 3 TPA- TPA-
VG
2 402 402 2
FW_PORT1_AREF 5 TPA<R> INPUT
80 36 34 FW_PORT1_TPA_P 4 TPA+ TPA(R)
TPA+
FW_PORT1_TPB_C CRITICAL
DP4311 10
BAV99DW-X-G 11
SOT-363
1 C4364 R4364
1
2 CRITICAL C4319 1 12 CHASSIS
4.99K DP4311 0.1uF GND
220pF 1% 10% 13
5% 1/16W 6 BAV99DW-X-G 50V 2
2 25V
CERM MF-LF
402 2
C4312 1 SOT-363 X7R
603-1
402 0.01uF 1 5
10%
50V 2 1
X7R 3 R4319 AREF needs to be isolated from all
402 C4313 1 1M
5% local grounds per 1394b spec 514S0605
0.01uF 4 1/16W
10% MF-LF
50V 2
X7R 2 402 When a bilingual device is connected to a
402 beta-only device, there is no DC path
between them (to avoid ground offset issue)
PLACEMENT_NOTE=Place C4319 close to connector pin 5.

BREF should be hard-connected to logic

ground for speed signaling and connection

Late-VG Protection Power FireWire Ports

A R4390 SYNC_MASTER=K19_MLB SYNC_DATE=02/05/2009
35 32 28 24 22 21 19 17 7 6
82 71 69 68 67 66 62 52 42
PP3V3_S5
1
332 2
PP2V4_FW_LATEVG
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm
35 36

NOTICE OF PROPRIETARY PROPERTY

A
VOLTAGE=2.4V
1%
1/16W ESD and late-VG rail THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
MF-LF
402
3 CRITICAL PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
for snap-back diodes AGREES TO THE FOLLOWING
D4390 (Common to all ports) I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
PP2V4_FWLATEVG needs to be biased MMBZ5227BLT1H II NOT TO REPRODUCE OR COPY IT
SOT23
to at least 2.1V for FW signal integrity 1 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
and should be biased to 2.4V for margin
SIZE DRAWING NUMBER REV.
R4390 should be 390 Ohms max for a 3.3V rail
D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 36 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

ODD Power Control

CRITICAL
Q4590
TPCP8102
23V1K-SM PP5V_SW_ODD_R
PP5V_S3

8
53 51 49 41 39 38 37 29 8 7 6 MIN_LINE_WIDTH=0.6mm

3
68 63 62 MIN_NECK_WIDTH=0.4mm

6 7
VOLTAGE=5V
D

D
D

1
R45961

5
NOTE: 3.3V must be S0 if 5V is S3 or S5 to 1 C4595

G
100K 0.068UF

4
ensure the drive is unpowered in S3/S5. 5% 10%
1/16W
MF-LF 2 10V
CERM C4596
72 71 69 68 67 66 61 58 57
26 23 22 21 20 18 17 12 7 6 PP3V3_S0 402 2 R4595 402
53 49 47 46 45 43 41 37 35 27
82 100K 2 0.01UF
ODD_PWR_EN_LS5V_L 1 ODD_PWR_SS 1 2
R45971 5% 10% XW4504
100K 1/16W
16V SM
5% D 6 MF-LF
1/16W
MF-LF
Q4596 402 CERM
402
1 2 ISNS_ODD_P OUT 51 82

402 2 SSM6N15FEAPE
SOT563
XW4503

2
ODD_PWR_EN
SM
2 G S 1
Q4596 D 3 XW4505

1
SSM6N15FEAPE SM
SOT563 1 2 ISNS_ODD_N OUT 51 82

5 G S 4
20 IN ODD_PWR_EN_L

51 6 PP5V_SW_ODD
MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.4mm
VOLTAGE=5V

C C
SATA ODD Port
FL4520
90-OHM-100MA PLACEMENT_NOTE=PLACE C4520 CLOSE TO MCP79
DLP11S PLACEMENT_NOTE=PLACE C4521 NEXT TO C4520
CRITICAL SYM_VER-1

3 4 82 SATA_ODD_R2D_UF_P 1 2 C4521 SATA_ODD_R2D_C_P IN 19 77

0.01UF 10% 16V CERM 402

J4500 2 1 82 SATA_ODD_R2D_UF_N 1 2 C4520 SATA_ODD_R2D_C_N IN 19 77

CRITICAL 54722-0164 0.01UF 10% 16V CERM 402

F-ST-SM
1 2 PLACEMENT_NOTE=Place FL4520 close to J4500
3 4 77 6 SATA_ODD_R2D_P
72 71 69 68 67 66 61 58 57
26 23 22 21 20 18 17 12 7 6 PP3V3_S0 5 6 77 6 SATA_ODD_R2D_N
53 49 47 46 45 43 41 37 35 27
82 7 8
9 10 SATA_ODD_D2R_C_N
R45901 11 12 SATA_ODD_D2R_C_P PLACEMENT_NOTE=PLACE C4526 CLOSE TO J4500 FL4525
90-OHM-100MA
33K 13 14 PLACEMENT_NOTE=PLACE C4525 NEXT TO C4526 DLP11S
5% 15 16
SYM_VER-1

1/16W C4526 1 2 82 6 SATA_ODD_D2R_UF_N 4 CRITICAL

3 SATA_ODD_D2R_N
MF-LF OUT 19 77
402 2 10% 16V CERM 402
0.01UF
516S0616 C4525 1 2 82 6 SATA_ODD_D2R_UF_P 1 2 SATA_ODD_D2R_P 19 77
OUT
40 6 SMC_ODD_DETECT 0.01UF 10% 16V CERM 402
OUT

PLACEMENT_NOTE=Place FL4525 close to J4500

Indicates disc presence

B B

1 C4501 1 C4502
L4502 0.1UF 0.1UF

PP1V5_S0
FERR-220-OHM
1 2 PP1V5_S0_HDD_FLT
20%
2 10V
CERM
402 CRITICAL
20%
2 10V
CERM
402
PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4501
PLACEMENT_NOTE=PLACE C4502 CLOSE TO J4501 SATA HDD Port
68 67 66 22 15 11 10 7 6
82
0402
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.6mm
MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.4mm
L4500 XW4500
MIN_NECK_WIDTH=0.3mm VOLTAGE=5V FERR-70-OHM-4A SM
1 C4503 6 PP5V_S0_HDD_FLT 1 2 PP5V_S0_HDD_R 1 2 PP5V_S0
1UF MIN_LINE_WIDTH=0.6mm
6 7 42 47 49 61 64 65 67 68
70 72
10% 0603 CRITICAL MIN_NECK_WIDTH=0.4mm
2 6.3V
CERM PLACEMENT_NOTE=PLACE L4500 CLOSE TO J4501 FL4501 VOLTAGE=5V PLACEMENT_NOTE=Place C4510 close to MCP79
XW4501 XW4502

2
402 90-OHM-100MA PLACEMENT_NOTE=Place C4511 next to C4510
PLACEMENT_NOTE=PLACE C4503 CLOSE TO J4501 DLP11S
SYM_VER-1 SM SM
77 6 SATA_HDD_R2D_P 3 4 82 SATA_HDD_R2D_UF_P C4510 1 2 SATA_HDD_R2D_C_P IN 19 77

1
77 6 SATA_HDD_R2D_N 0.01UF 10% 16V CERM 402
ISNS_HDD_P OUT 51 82
2 1 82 SATA_HDD_R2D_UF_N C4511 1 2 SATA_HDD_R2D_C_N IN 19 77
10% 16V CERM 402 ISNS_HDD_N OUT 51 82
0.01UF
PLACEMENT_NOTE=Place FL4501 close to J4501 FL4502
21 22 90-OHM-100MA
19 20
77 6 SATA_HDD_D2R_C_N DLP11S
SATA_HDD_D2R_C_P CRITICAL
SYM_VER-1

17 18
77 6
C4515 1 2 82 SATA_HDD_D2R_UF_N 4 3 SATA_HDD_D2R_N
15 16 0.01UF 10% 16V CERM 402
OUT 19
77 SATA Connectors
SMBUS_SMC_MGMT_SCL 13 14
C4516 1 SYNC_MASTER=K19_MLB SYNC_DATE=03/23/2009
A 81 43 40 25

81 43 40 25
IN

SMBUS_SMC_MGMT_SDA
11 12
0.01UF
2 82 SATA_HDD_D2R_UF_P
10% 16V CERM 402
1 2 SATA_HDD_D2R_P OUT 19 77

NOTICE OF PROPRIETARY PROPERTY

A
BI 9 10 PLACEMENT_NOTE=PLACE FL4502 CLOSE TO J4501
7 8 6 39 PLACEMENT_NOTE=Place C4515 next to C4516 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
OUT
5 6 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
R4532 R4531 PLACEMENT_NOTE=Place C4516 close to J4501 AGREES TO THE FOLLOWING
3 4
IR_RX_OUT
10 4.7 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
53 51 49 41 39 38 37 29 8 7 6PP5V_S3 2 1 6 PP5V_S3_IR_R 1 2
6 SYS_LED_ANODE_R 2 1 SYS_LED_ANODE 41
68 63 62 402 1/16W 402 II NOT TO REPRODUCE OR COPY IT
5% 5% 1/16W
MF-LF 1 C4532 F-ST-SM 1 C4531 MF-LF III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
0.1UF 54722-0224 0.001UF
10%
16V
516S0687
J4501 10%
50V SIZE DRAWING NUMBER REV.
2 X7R-CERM 2 CERM
402 402
D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 37 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

Port Power Switch Left USB Port A

CRITICAL CRITICAL
Q4690 L4605
FERR-220-OHM-2.5A
TPS2064DGN
C 62 53 51 49 41 39 37 29 8 7 6
68 63
PP5V_S3 2 IN
MSOP
OUT1
7 PP5V_S3_RTUSB_A_ILIM
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
1 2
0603
PP5V_S3_RTUSB_A_F
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
C
67 41 40 20 6 PM_SLP_S4_L 19 USB_EXTA_OC_L 8 OC1* VOLTAGE=5V VOLTAGE=5V CRITICAL
OUT
3 OUT2 6 PP5V_S3_RTUSB_B_ILIM C4605 1 J4600
EN1
MIN_LINE_WIDTH=0.5 mm 0.01uF USB
1 USB_EXTB_OC_L 5 20%
R4690 19 OUT OC2* MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V 16V
CERM 2
CRITICAL F-RT-TH-M97-4
5.1K 4 EN2 402 L4600
90-OHM-100MA
5
5% 6
1/16W DLP11S
MF-LF USB_PWR_EN GND TPAD SYM_VER-1

2 402 1 9 CRITICAL CRITICAL 82 USB2_EXTA_MUXED_N 4 3 82 USB2_LT1_N 1

C4690 1 1 C4691 C4695 1
10UF 0.1UF
10UF
1
C4696 C4617
10UF
1 1
C4616 2
C4692 1 20%
6.3V 2
20%
2 10V 20%
100UF
20% 20%
100UF
20%
82 USB2_EXTA_MUXED_P 1 2 82 USB2_LT1_P 3
0.47UF X5R CERM 6.3V 2 2 6.3V 6.3V 2 2 6.3V 4
10% 603 402 X5R POLY-TANT X5R POLY-TANT
10V 2 603 CASE-B2-SM 603 CASE-B2-SM
X5R 2 5 3 4
402 7

NC
IO
NC
IO
6 VBUS 8

1 GND

514-0606
D4600
RCLAMP0502N
SLP1210N6
CRITICAL
CRITICAL
We can add protection to 5V if we want, but leaving NC for now
L4615
FERR-220-OHM-2.5A
1 2 Place L4600 and L4605 at connector pin
PP5V_S3_RTUSB_B_F
0603 MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V
B 1 C4615 B
0.01uF
20%
2 16V
CERM
402
CRITICAL
J4610
USB/SMC Debug Mux USB
F-RT-TH-M97-4
5
SMC_DEBUG_YES CRITICAL 6
67 60
PP3V42_G3H
L4610
90-OHM-100MA
40 24 21 20 7 6 SIGNAL_MODEL=USB_MUX
59 48 45 43 42 41 DLP11S 1
SYM_VER-1

1 USB_EXTB_N 4 3 USB_LT2_N 2
SMC_DEBUG_YES R4650 78 19 BI 82

C4650 1 10K 82 USB_LT2_P 3

9

0.1UF 5% 4
20% 1/16W 1 2
10V VCC MF-LF 78 19 BI USB_EXTB_P
CERM 2 2 402
42 41 40 SMC_RX_L 402 5 M+ Y+ 1 7
IN
SMC_TX_L 4 M- Y- 2 2 5 3 4 8
42 41 40 OUT U4650

NC
IO
NC
IO
PI3USB102ZLE 6 VBUS
78 19 USB_EXTA_P 7 D+ TQFN
BI
USB_EXTA_N 6 D- CRITICAL 1 GND
78 19 BI

8 OE* SEL 10 USB_DEBUGPRT_EN_L IN 40

GND SEL=0 Choose SMC

D4610
RCLAMP0502N
SEL=1 Choose USB SLP1210N6
3

CRITICAL External USB Connectors

A SMC_DEBUG_NO
SYNC_MASTER=K19_MLB

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=02/05/2009
A
R4651
1
0 2 Left USB Port B THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
5%
1/16W
SMC_DEBUG_NO AGREES TO THE FOLLOWING
MF-LF
402 R4652 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

1
0 2 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
5%
1/16W
MF-LF SIZE DRAWING NUMBER REV.
402
D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 38 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

IR SUPPORT
D 62 53 51 49 41 38 37 29 8 7 6PP5V_S3
D
68 63

1 C4801
0.1UF
10%
2 16V
X7R-CERM
402

14
VCC

U4800
CY7C63803-LQXC
QFN
78 19 BI USB_IR_P 12 P1.0/D+ P0.0 7
DIFFERENTIAL_PAIR=USB2_IR
78 19 BI USB_IR_N 13 P1.1/D- P0.1 6
DIFFERENTIAL_PAIR=USB2_IR
IR_VREF_FILTER
15 P1.2/VREG INT0/P0.2 5
16 P1.3/SSEL INT1/P0.3 4
17 P1.4/SCLK INT2/P0.4 3 R4800
1 C4803 18 P1.5/SMOSI TIO0/P0.5 2 IR_RX_OUT_RC 1
100 2 IR_RX_OUT
1UF IN 6 37
10% 19 P1.6/SMISO TIO1/P0.6 1 5%
2 10V
X5R 1/16W
402-1 MF-LF
8 CRITICAL 402
9 OMIT
10 P/N 338S0633
1 C4804
0.001UF
20 10%
21 NC 2 50V
CERM
402
22
C 23
24
C
THRML
PAD VSS

25

11

B B

Front Flex Support

A SYNC_MASTER=K19_MLB

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=02/05/2009
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 39 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
NOTE: Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.

41 6 PP3V3_S5_AVREF_SMC
45 43 42 41 38 24 21 20 7 6 PP3V42_G3H
D
67 60 59 48
D
C4902 1 1 C4903 1 C4904 1 C4905 1 C4906
22UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20%
6.3V 2 2 10V 2 10V 2 10V 2 10V
CERM CERM CERM CERM CERM
805 402 402 402 402
TP_SMC_EXCARD_PWR_EN
U4900 SMC_PM_G2_EN PLACEMENT_NOTE=Place C4907 close to U4900 pin F1
41 OUT B12 P10 H8S2117 P60 L13 OUT 6 8 62 67

41 OUT TP_SMC_RSTGATE_L A13 P11 LGA-HF P61 K12 NC

R4999 SMC_VCL
67 66 65 64 62 24 IN ALL_SYS_PWRGD A12 P12 (1 OF 3) P62 K11 NC 4.7
67 RSMRST_PWRGD B13 P13 P63 J12 NC 1 2 PP3V3_S5_SMC_AVCC
IN
OMIT SMC_ADAPTER_EN MIN_LINE_WIDTH=0.25 MM C4907 1

M12

H10

L11
NC D11 P14 P64 K13 OUT 20 32 35 41 5% MIN_NECK_WIDTH=0.20 MM 0.47UF

B1
M1

E1
1/16W VOLTAGE=3.3V
20 OUT PM_RSMRST_L C13 P15 P65 J10 NC MF-LF
402
C4920 1 10%
6.3V
61 IMVP_VR_ON C12 P16 P66 J11 SMC_PROCHOT_3_3_L 41
0.1UF CERM-X5R 2
OUT IN 20% 402
PM_PWRBTN_L SMC_BIL_BUTTON_L 10V AVCC VCC VCL AVREF
20 OUT D10 P17 P67 H12 IN 6 41 59 CERM 2
402
U4900 R49091 1
R4901
41 OUT TP_ESTARLDO_EN D13 P20 P70 N10 SMC_CPU_ISENSE IN 45 NC E5 NC 10K 10K
E11 P21 P71 M11 SMC_CPU_VSENSE PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15 H8S2117 5%
1/16W
5%
1/16W
NC IN 44
PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15 LGA-HF MF-LF MF-LF
NC D12 P22 P72 L10 TP_SMC_GPU_ISENSE IN 41 402 2 2 402
(3 OF 3)
NC F11 P23 P73 N11 TP_SMC_GPU_VSENSE IN 41
MD1 D1 SMC_MD1 IN 42
41 TP_SMC_P24 E13 P24 P74 N12 SMC_DCIN_ISENSE IN 45 OMIT
MD2 H1 SMC_KBC_MDE
NC E12 P25 P75 M13 SMC_PBUS_VSENSE IN 44 42 41 IN SMC_RESET_L D3 RES*
45 41 SMC_BMON_MUX_SEL F13 P26 P76 N13 SMC_BATT_ISENSE IN 45
41 SMC_XTAL A3 XTAL
NC E10 P27 P77 L12 TP_SMC_CPU_HI_ISENSE IN 41
41 SMC_EXTAL A2 EXTAL NMI E3 SMC_NMI IN 42

78 42 18 BI LPC_AD<0> A9 P30 P80 A7 SMC_WAKE_SCI_L OUT 20

78 42 18 BI LPC_AD<1> D9 P31 P81 B6 NC

78 42 18 BI LPC_AD<2> C8 P32 P82 C7 PM_CLKRUN_L OUT 18 42
ETRST H3 SMC_TRST_L IN 42
LPC_AD<3> LPC_PWRDWN_L
C 78 42 18

78 42 18
BI
IN LPC_FRAME_L
B7
A8
P33
P34
P83
P84
D5
A6 SMC_TX_L
IN
OUT
18 42

38 40 41 42 AVSS L9 1 1 1
NO STUFF C
24 IN SMC_LRESET_L D8 P35 P85 B5 SMC_RX_L IN 38 40 41 42 VSS R4902 R4998 R4903
LPC_CLK33M_SMC 10K 10K 0
78 24 IN D7 P36 P86 C6 (OC) SMBUS_SMC_MGMT_SCL BI 25 37 43 81 5% 5% 5%
1/16W 1/16W 1/16W
XW4900

D2
L3
F10
B11
C5
42 18 BI LPC_SERIRQ D6 P37 MF-LF MF-LF MF-LF
P90 J4 SMC_ONOFF_L IN 41 48 SM 2 402 2 402 2 402
NC D4 P40 P91 G3 SMC_BC_ACOK IN 41 59 60 2 1
41 TP_SMC_P41 A5 P41 P92 H2 SMC_BS_ALRT_L IN 41

81 43 37 25 BI SMBUS_SMC_MGMT_SDA(OC) B4 P42 P93 G1 PM_SLP_S3_L IN 6 20 32 35 67 71

50 OUT SMS_PWRDN A1 P43 P94 H4 PM_SLP_S4_L IN 6 20 38 40 41 67

NC C2 P44 P95 G4 PM_SLP_S4_L IN 6 20 38 40 41 67 NOTE: P94 and P95 are shorted, P95 could be spare. GND_SMC_AVSS 41 44 45
NC B2 P45 P96 F4 PM_CLK32K_SUSCLK IN 24 78

41 20 OUT SMC_IG_THROTTLE_L C1 P46 P97 F1 (OC) SMBUS_SMC_0_S0_SDA BI 43 46 51 81

49 OUT SMC_SYS_KBDLED C3 P47

42 41 40 38 OUT SMC_TX_L G2 P50

42 41 40 38 IN SMC_RX_L F3 P51
81 51 46 43 BI SMBUS_SMC_0_S0_SCL(OC) E4 P52

SMC_PA0
U4900 SMC_CASE_OPEN
(DEBUG_SW_1) 41 N3 PA0 H8S2117 PE0 K1 IN 41

(DEBUG_SW_2) 41 SMC_PA1 N1 PA1 LGA-HF PE1 J3 SMC_TCK IN 41 42

24 OUT PM_SYSRST_L (OC) M3 PA2 (2 OF 3) PE2 K2 SMC_TDI IN 41 42

38 OUT USB_DEBUGPRT_EN_L (OC) M2 PA3 PE3 J1 SMC_TDO OUT 41 42

MEM_EVENT_L OMIT SMC_TMS

27 26 20 BI (OC) N2 PA4 PE4 K4 IN 41 42

B 59 BI
41 SMC_PA5
SYS_ONEWIRE
(OC)
(OC)
L1
K3
PA5
PA6
PF0 K5 NC B
PF1 N5 SMC_SYS_LED OUT 41
20 OUT PM_BATLOW_L (OC) L2 PA7
PF2 M6 SMC_LID IN 41 48 59

NC B8 PB0 PF3 L5 NC
20 OUT SMC_RUNTIME_SCI_L C9 PB1 PF4 M5 NC
37 6 IN SMC_ODD_DETECT B9 PB2 PF5 N4 SMC_MCP_SAFE_MODE OUT 41

41 TP_SMC_PB3
(See below) A10 PB3 PF6 L4 NC
41 IN SMC_EXCARD_CP C10 PB4 PF7 M4 NC
NC B10 PB5
PG0 M8 NC
41 IN SMC_EXCARD_OC_L C11 PB6
PG1 N7 SMS_INT_L IN 41 NOTE: SMS Interrupt can be active high or low, rename net accordingly.
41 IN SMC_GFX_OVERTEMP_L A11 PB7
PG2 K8 (OC) SMBUS_SMC_BSA_SDA BI 6 43 59 60 81 If SMS interrupt is not used, pull up to SMC rail.
47 OUT SMC_FAN_0_CTL G11 PC0 PG3 K7 (OC) SMBUS_SMC_BSA_SCL BI 6 43 59 60 81

41 OUT TP_SMC_FAN_1_CTL G13 PC1 PG4 K6 (OC) SMBUS_SMC_A_S3_SDA BI 6 29 43 49 81

41 OUT NC_SMC_FAN_2_CTL F12 PC2 PG5 N6 (OC) SMBUS_SMC_A_S3_SCL BI 6 29 43 49 81

41 OUT NC_SMC_FAN_3_CTL H13 PC3 PG6 M7 (OC) SMBUS_SMC_B_S0_SDA BI 43 46 81

47 IN SMC_FAN_0_TACH G10 PC4 PG7 L6 (OC) SMBUS_SMC_B_S0_SCL BI 43 46 81

41 IN TP_SMC_FAN_1_TACH G12 PC5

PH0 E2 SMC_PROCHOT OUT 41
41 IN NC_SMC_FAN_2_TACH H11 PC6
PH1 F2 SMC_THRMTRIP OUT 41
41 IN NC_SMC_FAN_3_TACH J13 PC7
PH2 J2 SMC_PH2 41

50 IN SMS_X_AXIS M10 PD0 PH3 A4 TP_ALS_GAIN OUT 41

50 IN SMS_Y_AXIS N9 PD1 PH4 B3 NC

50 IN SMS_Z_AXIS K10 PD2 PH5 C4 NC
TP_SMC_GPU_1V8_ISENSE
41

45 41
IN
IN SMC_MCP_CORE_ISENSE
L8
M9
PD3
PD4
SMC
SMC_MCP_DDR_ISENSE N8 SYNC_MASTER=T18_MLB SYNC_DATE=02/05/2009
A 45 41

44 41
IN
IN SMC_MCP_VSENSE K9
PD5
PD6
NOTICE OF PROPRIETARY PROPERTY
A
45 41 IN SMC_CPU_FSB_ISENSE L7 PD7
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
SMC_PB3:
II NOT TO REPRODUCE OR COPY IT
SMC_IG_THROTTLE_L for MG systems. III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
Otherwise, TP/NC okay (was ISENSE_CAL_EN)
SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 40 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
SMC Aliases SMC FSB to 3.3V Level Shifting
SMC Reset "Button" / Brownout Detect 60 59 41 40 IN SMC_BC_ACOK SMC_BC_ACOK OUT 40 41 59 60
MAKE_BASE=TRUE 82 72 71 69 68 67 66 61 58 57
26 23 22 21 20 18 17 12 7 6 PP3V3_S0
53 49 47 46 45 43 41 37 35 27
43 42 41 40 38 24 21 20 7 6 PP3V42_G3H
67 60 59 48 45
44 41 40 SMC_MCP_VSENSE SMC_MCP_VSENSE OUT 40 41 44
1 1
MAKE_BASE=TRUE R5061 R5060
1 45 41 40 SMC_CPU_FSB_ISENSE SMC_CPU_FSB_ISENSE OUT 40 41 45 100K 10K
CRITICAL R5000 MAKE_BASE=TRUE 5% 5%
1/16W 1/16W
1K 45 41 40 SMC_MCP_CORE_ISENSE SMC_MCP_CORE_ISENSE OUT 40 41 45 MF-LF MF-LF
U5000 5%
1/16W
MAKE_BASE=TRUE
SMC_MCP_DDR_ISENSE SMC_MCP_DDR_ISENSE
2 402 2 402 TO SMC
NCP303LSN MF-LF 45 41 40 OUT 40 41 45
SMC_PROCHOT_3_3_L
SOT23-5-HF 2 402 MAKE_BASE=TRUE OUT 40

41 40 TP_SMC_CPU_HI_ISENSE TP_SMC_CPU_HI_ISENSE 40 41

D
SMC_MANUAL_RST_L
OMIT NC
5
4
CD
NC
OUT
IN
1
2
SMC_RESET_L OUT 40 42

41 40
MAKE_BASE=TRUE
TP_SMC_GPU_1V8_ISENSE TP_SMC_GPU_1V8_ISENSE
OUT

OUT 40 41
CPU_PROCHOT_BUF
6 D
GND MAKE_BASE=TRUE
1
R5001 C5001 1 3 TP_SMC_GPU_ISENSE TP_SMC_GPU_ISENSE
D Q5060
0
5% 0.01UF
1 C5000 41 40
MAKE_BASE=TRUE
OUT 40 41
DMB53D0UV
1/10W 10% 0.1uF 41 40 TP_SMC_GPU_VSENSE TP_SMC_GPU_VSENSE OUT 40 41
SOT-563
16V 20% TO CPU 2 G
MF-LF
2 603
CERM 2
402 2 10V
CERM
MAKE_BASE=TRUE R5062 3

SILK_PART=SMC_RST 402 41 40 20 IN SMC_IG_THROTTLE_L SMC_IG_THROTTLE_L OUT 20 40 41 75 61 13 9 BI CPU_PROCHOT_L 1

3.3K 2 CPU_PROCHOT_L_R 5 Q5060
MAKE_BASE=TRUE DMB53D0UV
5% SOT-563
PLACEMENT_NOTE=Place R5001 on BOTTOM side SMC_BMON_MUX_SEL SMC_BMON_MUX_SEL
1/16W
MF-LF S
45 41 40 IN OUT 40 41 45 4
D 3 MAKE_BASE=TRUE 402
Q5032 6 D Q5059 1
SSM6N15FEAPE SMS_INT_L SMS_INT_L
43 42 41 40 38 24 21 20 7 6 PP3V42_G3H SOT563
41 40
MAKE_BASE=TRUE
40 41
SSM6N15FEAPE
67 60 59 48 45 SOT563

5 U5001 R5096
SMC_TPAD_RST_L 1 SN74LVC1G02 5 G S 4
48 IN SOT553-5 SMC_MCP_SAFE_MODE 1
0 2 MCP_SPKR 1 S G 2
40 IN OUT 20
4 SMC_TPAD_RST
2 5% SMC_PROCHOT IN 40
48 41 40 IN SMC_ONOFF_L 02 1/16W
MF-LF
3 PLACEMENT_NOTE=Place next to U5000 (shares C5000) 402
75 13 9 OUT PM_THRMTRIP_L

Unused Pins 3 D Q5059

41 40 IN TP_SMC_FAN_1_CTL TP_SMC_FAN_1_CTL 40 41 SSM6N15FEAPE
MAKE_BASE=TRUE SOT563
TP_SMC_FAN_1_TACH TP_SMC_FAN_1_TACH
SMC AVREF Supply 41 40
MAKE_BASE=TRUE
OUT 40 41

NC_SMC_FAN_2_CTL NC_SMC_FAN_2_CTL 4 S G 5
CRITICAL 41 40 IN 40 41
MAKE_BASE=TRUE NO_TEST=TRUE
SMC_THRMTRIP
VR5020 41 40 NC_SMC_FAN_2_TACH NC_SMC_FAN_2_TACH OUT 40 41
IN 40

C 42 41 40 38 24 21 20 7 6
67 60 59 48 45 43
PP3V42_G3H
1 IN
REF3333
SOT23-3
OUT 2
PP3V3_S5_AVREF_SMC
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
6 40

41 40
MAKE_BASE=TRUE
NC_SMC_FAN_3_CTL
NO_TEST=TRUE
NC_SMC_FAN_3_CTL 40 41
C
IN
GND
VOLTAGE=3.3V
NC_SMC_FAN_3_TACH
MAKE_BASE=TRUE
NC_SMC_FAN_3_TACH
NO_TEST=TRUE
SMC Pull-ups
3
1 C5026 41 40
MAKE_BASE=TRUE NO_TEST=TRUE
OUT 40 41

PP3V42_G3H
0.01UF 43 42 41 40 38 24 21 20 7 6
67 60 59 48 45
10%
2 16V
CERM 41 40 IN TP_ALS_GAIN TP_ALS_GAIN 40 41
402 MAKE_BASE=TRUE R5091 100K
40 SMC_PA0 1 2
1 C5020 C5025 1 41 40 IN TP_ESTARLDO_EN TP_ESTARLDO_EN
MAKE_BASE=TRUE
40 41
SMC_PA1 R5092 100K 1 2 5% 1/16W MF-LF 402
0.47UF 10uF 40
5% 1/16W MF-LF 402
10% 20% TP_SMC_EXCARD_PWR_EN TP_SMC_EXCARD_PWR_EN SMC_PH2 R5072 10K 1 2
2 6.3V 6.3V 2 41 40 IN 40 41 40
CERM-X5R X5R MAKE_BASE=TRUE 5% 1/16W MF-LF 402
402 603 41 40 TP_SMC_RSTGATE_L TP_SMC_RSTGATE_L 40 41
IN
MAKE_BASE=TRUE R5070 10K
48 41 40 SMC_ONOFF_L 1 2
GND_SMC_AVSS 40 44 45 41 40 IN TP_SMC_P24 TP_SMC_P24 40 41
R5071 100K 5% 1/16W MF-LF 402
TABLE_ALT_HEAD

MIN_LINE_WIDTH=0.4 mm MAKE_BASE=TRUE 59 48 40 SMC_LID 1 2

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: MIN_NECK_WIDTH=0.2 mm R5073 10K 5% 1/16W MF-LF 402
PART NUMBER VOLTAGE=0V 41 40 IN TP_SMC_P41 TP_SMC_P41 40 41 42 40 38 SMC_TX_L 1 2
MAKE_BASE=TRUE R5074 100K 5% 1/16W MF-LF 402
TABLE_ALT_ITEM

42 40 38 SMC_RX_L 1 2
353S1381 353S1912 ALL Intersil ISL60002-33 41 40 IN TP_SMC_PB3 TP_SMC_PB3 40 41 5% 1/16W MF-LF 402
MAKE_BASE=TRUE

42 40 SMC_TMS R5077 10K 1 2

R5078 10K 5% 1/16W MF-LF 402
SMC_TDO 1 2
Debug Power "Buttons" 42 40

42 40 SMC_TDI R5079 10K 1 2 5% 1/16W MF-LF 402

SMC_ONOFF_L 42 40 SMC_TCK R5080 10K 1 2

5% 1/16W MF-LF 402
OUT 40 41 48
R5081 10K 5% 1/16W MF-LF 402
59 40 6 SMC_BIL_BUTTON_L 1 2
OMIT OMIT SMC_BC_ACOK R5087 470K 1 2 5% 1/16W MF-LF 402
60 59 41 40
R50141 1
R5015 41 40 SMS_INT_L R5093 10K 1 2 5% 1/16W MF-LF 402
0 0 R5094 10K 5% 1/16W MF-LF 402
5% 5% 40 SMC_GFX_OVERTEMP_L 1 2
1/10W 1/10W 5% 1/16W MF-LF 402
MF-LF MF-LF 40 SMC_EXCARD_OC_L R5095 10K 1 2
603 2 2 603 5% 1/16W MF-LF 402

B SILK_PART=PWR_BTN SILK_PART=PWR_BTN SMC Crystal Circuit B

PLACEMENT_NOTEs: 82 72 71 69 68 67 66 61 58 57
26 23 22 21 20 18 17 12 7 6 PP3V3_S0
R5010 C5010 53 49 47 46 45 43 41 37 35 27

Place R5014 on TOP side 15pF

SMC_XTAL 1
0 2 SMC_XTAL_R 1 2
Place R5015 on BOTTOM side 40
SMC_PA5 R5089 10K 1 2
40
5% 5% 5% 1/16W MF-LF 402
1/16W 50V
MF-LF CERM
402 402
CRITICAL
System (Sleep) LED Circuit Y5010 1
20.00MHZ
5X3.2-SM
SMC Pull-downs
2
49 39 38 37 29 8 7 6 PP5V_S3 C5011 R5076 100K
68 63 62 53 51 40 SMC_BS_ALRT_L 1 2
15pF SMC_ADAPTER_EN R5085 10K 1 2 5% 1/16W MF-LF 402
40 35 32 20
SMC_EXTAL 1 2
1 1
40
40 SMC_CASE_OPEN R5086 10K 1 2 5% 1/16W MF-LF 402
R5031 R5030 5%
50V
5% 1/16W MF-LF 402
523 20 CERM SMC_EXCARD_CP R5088 10K 1 2
1% 1% 402 40
1/16W 1/16W 5% 1/16W MF-LF 402
MF-LF MF-LF
402 2 2 402 67 41 40 38 20 6 PM_SLP_S4_L R5090 100K 1 2
5% 1/16W MF-LF 402
SYS_LED_ILIM 67 41 40 38 20 6 PM_SLP_S4_L

SYS_LED_L_VDIV

R50321
1.47K
1%
1/16W
6
D
5
B
4
E Q5030
SMC Support
MF-LF
SYNC_MASTER=(K19_MLB) SYNC_DATE=(11/25/2008)
A 402 2 DMB54D0UV
SOT-563
NOTICE OF PROPRIETARY PROPERTY
A
SYS_LED_L
Q2 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
Q1 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

S G C I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT
1 2 3
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

40 IN SMC_SYS_LED SYS_LED_ANODE OUT 37 D 051-7903 A

APPLE INC. SCALE SHT OF
NONE 41 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

LPC+SPI Connector
CRITICAL
LPCPLUS
J5100
55909-0374
M-ST-SM
43 42 41 40 38 24 21 20 7 6 PP3V42_G3H 31 32
67 60 59 48 45
68 67 65 64 61 49 47 37 7 6 PP5V_S0
D
72 70
1 2
4
LPC_CLK33M_LPCPLUS IN 24 78 D
78 40 18 BI LPC_AD<0> 3 LPC_AD<2> BI 18 40 78

78 40 18 LPC_AD<1> 5 6 LPC_AD<3> 18 40 78
BI BI
7 8
42 SPI_ALT_MOSI 9 10 SPIROM_USE_MLB 20 42
IN OUT
42 SPI_ALT_MISO 11 12 SPI_ALT_CLK 42
OUT IN
78 40 18 LPC_FRAME_L 13 14 SPI_ALT_CS_L 42
IN IN
40 18 PM_CLKRUN_L 15 16 LPC_SERIRQ 18 40
OUT BI
41 40 SMC_TMS 17 18 LPC_PWRDWN_L 18 40
OUT IN
24 DEBUG_RESET_L 19 20 SMC_TDI 40 41
IN OUT
41 40 SMC_TDO 21 22 SMC_TCK 40 41
OUT OUT
40 SMC_TRST_L 23 24 SMC_RESET_L 40 41
IN OUT
40 SMC_MD1 25 26 SMC_NMI 40
OUT OUT
SMC_TX_L 27 28 SMC_RX_L 38 40 41
IN OUT

Alternate SPI ROM Support 29

33
30 LPCPLUS_GPIO OUT 17

34

43 42 41 40 38 24 21 20 7 6 PP3V42_G3H
PP3V3_S5
67 60 59 48 45
LPCPLUS
35 32 28 24 22 21 19 17 7 6
82 71 69 68 67 66 62 52 42 36
1 C5114 516S0573
0.1UF
R51901 20%
10K LPCPLUS 2 10V
CERM

9
5% 402
1/16W
MF-LF VCC
402 2
78 42 20 SPI_CLK_R 1 Y+ M+ 5 SPI_ALT_CLK 42
IN OUT
SPI_MOSI_R 2 Y- M- 4 SPI_ALT_MOSI
C 78 42 20 IN U5110
PI3USB102ZLE
OUT 42
C
TQFN D+ 7 SPI_CLK_MUX 42 52
OUT
R51911 D- 6 SPI_MOSI_MUX OUT 42 52
10K CRITICAL
5%
1/16W 10 SEL
MF-LF OE* 8
402 2
GND
3

SEL HIGH OUTPUTS TO D (ON BOARD ROM)

SEL LOW OUTPUTS TO M (FRANKCARD ROM)
67 60 59
38 24 21 20 7 6 PP3V42_G3H LPCPLUS
48 45 43 42 41 40

1 C5124
0.1UF
LPCPLUS 20%
2 10V
9

CERM SPI_ALT_MISO 42
402 IN
VCC
R51401 1 Y+
100K 78 42 20 OUT SPI_MISO M+ 5 Pull-up on debug card
5% 2 Y-
1/16W 78 20 IN SPI_CS0_R_L U5120 M- 4 SPI_ALT_CS_L OUT 42
MF-LF
402 2 PI3USB102ZLE
TQFN D+ 7 SPI_MISO_MUX 42 52
IN
D- 6
CRITICAL
42
42 20 BI SPIROM_USE_MLB 20 SPIROM_USE_MLB 10 SEL OE* 8 SPI_MLB_CS_L OUT 52
MAKE_BASE=TRUE
GND
1 PP3V3_S5
R5144 6 7 17 19 21 22 24 28 32 35 36

B B
3

42 52 62 66 67 68 69 71 82
20K
5%
LPCPLUS_NOT 1/16W
MF-LF
R5146 402 2
1
0 2
5% PLACEMENT_NOTE=PLACE NEXT TO U1400
1/16W
MF-LF
402

SPI MUX BYPASS

LPCPLUS_NOT
R5156
0
52 42 OUT SPI_CLK_MUX 1 2 SPI_CLK_R IN 20 42 78

5%
1/16W
MF-LF
LPCPLUS_NOT
402 R5157
0
52 42 OUT SPI_MOSI_MUX 1 2 SPI_MOSI_R IN 20 42 78

5%
LPCPLUS_NOT 1/16W
MF-LF
R5158 402
0
SPI_MISO_MUX 1 2 SPI_MISO
52 42 IN
5%
OUT 20 42 78
LPC+SPI Debug Connector
1/16W
MF-LF
A 402
SYNC_MASTER=K19_MLB

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=02/05/2009
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 42 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
MCP79 SMBUS "0" CONNECTIONS SMC "0" SMBus Connections SMC "A" SMBus Connections
NOTE: SMC RMT bus remains powered and may be active in S3 state
72 71 69 68 67 66 61 58 57
26 23 22 21 20 18 17 12 7 6 PP3V3_S0 72 71 69 68 67 66 61 58 57
26 23 22 21 20 18 17 12 7 6 PP3V3_S0 68 50 48 43 30 29 25 20 7 6 PP3V3_S3
53 49 47 46 45 43 41 37 35 27 53 49 47 46 45 43 41 37 35 27
82 82

MCP79 R52001 1
R5201 SO-DIMM "A" SMC R52501 1
R5251 MCP Temp SMC R52701 1
R5271 TRACKPAD
1K 1K 4.7K 4.7K 1K 1K
U1400 5% 5% J3100 U4900 5% 5% EMC1403-5: U5535 U4900 5% 5% J5800
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
(MASTER) MF-LF MF-LF (Write: 0xA0 Read: 0xA1) (MASTER) MF-LF MF-LF (Write: 0x98 Read: 0x99) (MASTER) MF-LF MF-LF (Write: 0x90 Read: 0x91)
402 2 2 402 81
402 2 2 402 402 2 2 402
51

D 27 26 20 12
78 43
SMBUS_MCP_0_CLK
MAKE_BASE=TRUE
SMBUS_MCP_0_CLK 12 20 26
27 43 78
51 46 43 40
81
SMBUS_SMC_0_S0_SCL 46 43

81 51
40

46 43
SMBUS_SMC_0_S0_SCL
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SCL 40 43 46
51 81
43 40 29 6
81 49
SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SCL
MAKE_BASE=TRUE
SMBUS_SMC_A_S3_SCL 6 29 40
43 49 81 D
43 26 20 12 SMBUS_MCP_0_DATA SMBUS_MCP_0_DATA 12 20 26 51 46 43 40 SMBUS_SMC_0_S0_SDA 40 SMBUS_SMC_0_S0_SDA SMBUS_SMC_0_S0_SDA 40 43 46 43 40 29 6 SMBUS_SMC_A_S3_SDA SMBUS_SMC_A_S3_SDA SMBUS_SMC_A_S3_SDA 6 29 40
78 MAKE_BASE=TRUE 43 78 81 MAKE_BASE=TRUE 51 81 81 49 MAKE_BASE=TRUE 43 49 81

SO-DIMM "B" Sensor ADCs ALS

J3200 U5930 J3401
(Write: 0xA2 Read: 0xA3) (Write: 0x10 Read: 0x11) (Write: 0x52 Read: 0x53)

SMBUS_MCP_0_CLK 12 20 26
27 43 78
SMBUS_SMC_0_S0_SCL 40 43 46
51 81
SMBUS_SMC_A_S3_SCL 6 29 40
43 49 81
NBC
=I2C_SODIMMB_SDA 27 SMBUS_SMC_0_S0_SDA 40 43 46 SMBUS_SMC_A_S3_SDA 6 29 40
51 81 43 49 81

MCP79 SMBUS "1" CONNECTIONS SMC "Battery A" SMBus Connections SMC "B" SMBus Connections
72 71 69 68 67 66 61 58 57
26 23 22 21 20 18 17 12 7 6
53 49 47 46 45 43 41 37 35 27
PP3V3_S0
72 71 69 68 67 66 61 58 57
26 23 22 21 20 18 17 12 7 6 PP3V3_S0 45 42 41 40 38 24 21 20 7 6 PP3V42_G3H 82
53 49 47 46 45 43 41 37 35 27 67 60 59 48
82

SMC R52601 1
R5261 CPU Temp
MCP79
U1400
R52301
2.0K
5%
1
R5231
5%
2.0K Mikey
U6860
SMC
U4900
R52801
2.61K
1%
1
R5281
2.61K
1%
BATTERY & BIL
J6950 & J6955
U4900
(MASTER)
4.7K
5%
1/16W
MF-LF
4.7K
5%
1/16W
MF-LF
EMC1403-5: U5515
(Write: 0x98 Read: 0x99)
1/16W 1/16W 1/16W 1/16W 402 2 2 402
(MASTER/SLAVE) MF-LF MF-LF (WRITE: 0X72 READ: 0X73) (MASTER) MF-LF MF-LF (See Table) 81
402 2 2 402 402 2 2 402 46 43
SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SCL
C 72 58 43 20
78
SMBUS_MCP_1_CLK
MAKE_BASE=TRUE
SMBUS_MCP_1_CLK 20 43 58
72 78
59 43 40 6
81 60
SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SCL
MAKE_BASE=TRUE
SMBUS_SMC_BSA_SCL 6 40 43
59 60 81
81 46 43 40

81 46 43 40 SMBUS_SMC_B_S0_SDA
81
40
MAKE_BASE=TRUE
46 43
40 SMBUS_SMC_B_S0_SDA SMBUS_SMC_B_S0_SDA
40 43 46
81

40 43 46
C
MAKE_BASE=TRUE 81
72 58 43 20 SMBUS_MCP_1_DATA SMBUS_MCP_1_DATA 20 43 58 59 43 40 6 SMBUS_SMC_BSA_SDA SMBUS_SMC_BSA_SDA SMBUS_SMC_BSA_SDA 6 40 43
78 MAKE_BASE=TRUE 72 78 81 60 MAKE_BASE=TRUE 59 60 81

LP8543 (Bklt) Battery Charger

U9700 (DEFAULT) ISL6258A - U7000
(Write: 0x58 Read: 0x59)
Battery (Write: 0x12 Read: 0x13)

SMBUS_MCP_1_CLK Battery Manager - (Write: 0x16 Read: 0x17) SMBUS_SMC_BSA_SCL

20 43 58 6 40 43
72 78 Battery LED Driver - (Write: 0x36 Read: 0x37) 59 60 81

SMBUS_MCP_1_DATA 20 43 58 Battery Temp - (Write: 0x90 Read: 0x91) SMBUS_SMC_BSA_SDA 6 40 43

72 78 59 60 81

SMC "Management" SMBus Connections

The bus formerly known as "Battery B"
68 50 48 43 30 29 25 20 7 6 PP3V3_S3

SMC R52901 1
R5291 Vref DACs
4.7K 4.7K
U4900 5% 5% U2900
1/16W 1/16W
(MASTER) MF-LF MF-LF (Write: 0x98 Read: 0x99)
402 2 2 402
B 43 40 37 25 SMBUS_SMC_MGMT_SCL
81
43
40 37
25 SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SCL 25 37 40
B
81
81 43 MAKE_BASE=TRUE 43 81
40 37
43 40 37 25 SMBUS_SMC_MGMT_SDA 25 SMBUS_SMC_MGMT_SDA SMBUS_SMC_MGMT_SDA 25 37 40
81 MAKE_BASE=TRUE 43 81

Margin Control
U2901
(Write: 0x30 Read: 0x31)

SMBUS_SMC_MGMT_SCL 25 37 40
43 81

SMBUS_SMC_MGMT_SDA 25 37 40
43 81

HDD Margin Ctrl.

J4501
(Write: 0xXX Read: 0xXX)

SMBUS_SMC_MGMT_SCL 25 37 40
43 81

SMBUS_SMC_MGMT_SDA 25 37 40
43 81

K19i SMBus Connections

SYNC_MASTER=WFERRY_K19I SYNC_DATE=12/12/2008
A NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 43 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

CPU Voltage Sense / Filter

XW5309 R5309
61 11 10 7 6 PPVCORE_S0_CPU SM
4.53K
1 2 CPUVSENSE_IN 1 2 SMC_CPU_VSENSE OUT 40

PLACEMENT_NOTE=Place near U1000 center 1%

1/16W
MF-LF
402
1
C5309
0.22UF
20%
6.3V
2 X5R
402

D GND_SMC_AVSS 40 41 44 45 D
Place RC close to SMC

MCP Voltage Sense / Filter

PPVCORE_S0_MCP
XW5359 R5359
64 22 21 7 6 SM
4.53K
1 2 MCPVSENSE_IN 1 2 SMC_MCP_VSENSE OUT 40 41

PLACEMENT_NOTE=Place near U1400 center 1%

1/16W
MF-LF
402
1
C5359
0.22UF
20%
6.3V
2 X5R
402

GND_SMC_AVSS 40 41 44 45

Place RC close to SMC

C C
PBUS VOLTAGE SENSE ENABLE & FILTER

Q5315
NTUD3127CXXG
SOT-963
N-CHANNEL
6 PBUSVSENS_EN_L

D
R5316 1
100K
68 67 PM_SLP_S3_L_BUF 2 G 1%
IN
S 1/16W
MF-LF
Enables PBUS VSense 402
2
1
divider when high. 3 PPBUS_G3HRS5_VSENSE
MIN_LINE_WIDTH=0.20 mm
MIN_NECK_WIDTH=0.20 mm
D VOLTAGE=18.5V
R5385 1
27.4K
5 G 1%
S 1/16W
73 64 63 62 60 59 45 35 7 6 PPBUS_G3H MF-LF
402
2
RTHEVENIN = 4573 OHMS
4
P-CHANNEL SMC_PBUS_VSENSE 40

B R53151
1
OUT
B
100K R5386
1%
1
C5385
1/16W 5.49K 0.22UF
MF-LF 1%
20%
402 1/16W
2 MF-LF 2
6.3V
X5R
402 402
PBUSVSENS_EN_L_DIV 2

GND_SMC_AVSS 40 41 44 45

Place RC close to SMC

VOLTAGE SENSING
A SYNC_MASTER=K24_MLB

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=02/05/2009
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 44 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

MCP MEM VDD Current Sense / Filter MCP VCore Current Sense Filter
82 72 71 69 68 67 66 61 58 57
26 23 22 21 20 18 17 12 7 6 PP3V3_S0
53 49 47 46 45 43 41 37 35 27
R5416
4.53K2
64 IN MCPCORES0_IMON 1 SMC_MCP_CORE_ISENSE OUT 40 41

C5400 1 1%
1/16W
0.1uF C5472
D 20%
10V
CERM 2
MF-LF
402
1
0.22UF
20%
D
402 U5400 PLACEMENT_NOTEs:
2 6.3V
68 P1V5_S0_KELVIN 1 5 OPA348 X5R
IN 402
SC70-5 Place close to SMC
4 P1V5_S0_SENSE_AMP (For R and C) GND_SMC_AVSS 40 41 44 45

68 IN P1V5_S0_SENSE 3
2

R54101
0
5%
1/16W R54112
MF-LF 0
402 2 5%
1/16W
MF-LF
P1V5_S0_SENSE_E 402 1

1 C5434
0.1UF
Q5401 10%
2 2SA2154MFV-YAE 2 16V
X5R
SOD 402
1 P1V5_S0_SENSE_B

3 R5417
P1V5_S0_SENSE_C 1
4.53K2 SMC_MCP_DDR_ISENSE OUT 40 41

1%
1/16W
R5412 1 MF-LF
402
1 C5435
118 0.22UF
1% PLACEMENT_NOTEs: 20%
1/16W 6.3V
2 X5R
MF-LF 402
402 2 Place close to SMC
C (For R and C) GND_SMC_AVSS 40 41 44 45 C

MCP/CPU 1.05V AND CPU VCore High-Side Current Sense / Filter CPU VCore Load Side Current Sense / Filter
82 72 71 69 68 67 66 61 58 57
26 23 22 21 20 18 17 12 7 6
53 49 47 46 45 43 41 37 35 27
PP3V3_S0 R5471
6.19K2
61 IN IMVP6_IMON 1 SMC_CPU_ISENSE OUT 40

73 64 63 62 60 59 44 35 7 6 PPBUS_G3H 1%
1/16W
1
1 C5417 MF-LF
402 R5480 1 C5470

3
CRITICAL 0.1uF 17.4K 0.22UF
R5492 V+ 1%
1
3

20% PLACEMENT_NOTEs: 1/16W 20%

0.01 2 10V MF-LF 6.3V
2 X5R
0.5%
1W U5402 CERM
402 R5418 Place close to SMC
402 2 402
MF
INA213 4.53K2
0612-1
82 ISNS_CPUVTT_N 5 IN- SC70 OUT 6 CPUVTT_IOUT 1 SMC_CPU_FSB_ISENSE OUT 40 41 (For R’s and C)
2
4

1% GND_SMC_AVSS 40 41 44 45
1/16W
82 ISNS_CPUVTT_P 4 IN+ REF 1 MF-LF
402
1 C5436
65 61 7 PPBUS_CPU_IMVP_ISNS 0.22UF
PLACEMENT_NOTEs: 20%
GND 2 6.3V
X5R
402
2

Place close to SMC

(For R and C) GND_SMC_AVSS 40 41 44 45

B B

Battery (BMON) Current Sense, MUX & Filter DC-IN (AMON) Current Sense Filter
43 42 41 40 38 24 21 20 7 6 PP3V42_G3H R5481
67 60 59 48
4.53K2
60 IN CHGR_AMON 1 SMC_DCIN_ISENSE OUT 40
BMON_ENG BMON_ENG 1%
PLACEMENT_NOTE=Place near sense resistor 1 C5418 C5459 1 1/16W
3

0.1uF 0.1uF BMON_ENG MF-LF

402
1 C5487
V+ 20% 20% 0.22UF
2 10V 10V
CERM 2 U5413 PLACEMENT_NOTEs: 20%
Charger/Load side U5403 CERM
402 402 NC7SB3157P6XG 2 6.3V
X5R
INA213 SC70 Place close to SMC 402
82 60 CHGR_CSO_R_P 5 IN- SC70 OUT 6 BMON_INA_OUT 1 B1 SEL 6 SMC_BMON_MUX_SEL 40 41
IN IN GND_SMC_AVSS
(For R and C) 40 41 44 45
BMON_ENG 1
82 60 IN CHGR_CSO_R_N 4 IN+ REF 1 2 GND
(50V/V) VCC 5
Battery side GND R5401
0
3 4 4.53K2
BMON_AMUX_OUT SMC_BATT_ISENSE
2

1 OUT 40
NOTE: Monitoring current from B0 A
1%
battery to PBUS (battery discharge) VER 1 BMON_ENG 1/16W
across R7008 BMON_PROD 1 MF-LF 1 C5490
R5423 402 0.22UF
20%
100K
R5431
0
5%
1/16W
PLACEMENT_NOTEs:
2 6.3V
X5R
402
Current Sensing
60 IN CHGR_BMON 2 1 MF-LF Place close to SMC
SYNC_MASTER=WFERRY_K19I SYNC_DATE=12/16/2008
A From charger
For engineering, stuff BMON_ENG
5%
1/16W
MF-LF
2 402 (For R and C) GND_SMC_AVSS 40 41 44 45

NOTICE OF PROPRIETARY PROPERTY

A
402
For production, stuff BMON_PROD
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PLACEMENT_NOTE=Place R5431 next to U5413 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 45 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

CPU T-Diode Thermal Sensor

INTERNAL DIODE IN U5515 DETECTS CPU PROXIMITY TEMPERATURE
82 72 71 69 68 67 66 61 58 57
26 23 22 21 20 18 17 12 7 6 PP3V3_S0 R5515
53 49 47 46 45 43 41 37 35 27 47
1 2 PP3V3_S0_CPUTHMSNS_R
MIN_LINE_WIDTH=0.25 mm
5% MIN_NECK_WIDTH=0.25 mm

D
1/16W
MF-LF
402
VOLTAGE=3.3V
1 1 C5515 R5516 1 1
R5517 D
VDD 0.1uF 10K 10K
1% 5%

82 9 CPU_THERMD_P U5515 2
20%
10V 1/16W
MF-LF
1/16W
MF-LF
BI EMC1413 CERM
402 402 402
2 2
SIGNAL_MODOL=EMPTY DFN
C5521 1 2 DP1 THERM*/ADDR 7 CPUTHMSNS_THERM_L
DETECT CPU DIE TEMPERATURE 0.0022uF
10% 3 DN1CRITICAL 8
50V ALERT* CPUTHMSNS_ALERT_L
CERM 2
402 4 DP2/DN3 SMDATA 9 SMBUS_SMC_B_S0_SDA 40 43 81
CPU_THERMD_N BI
82 9 BI
5 DN2/DP3 SMCLK 10 SMBUS_SMC_B_S0_SCL 40 43 81
BI
GND THRM_PAD
6 11

82 CPUTHMSNS_D2_P
3 SIGNAL_MODOL=EMPTY
1 PLACEMENT NOTE: PLACE U5515 NEAR CPU
C5520
DETECT FIN-STACK TEMPERATURE
Q5501 1
0.0022uF
BC846BMXXH 10%
50V
SOT732-3 2
CERM
2 402
82 CPUTHMSNS_D2_N

C C

MCP T-Diode Thermal Sensor

INTERNAL DIODE IN U5535 DETECTS MCP PROXIMITY TEMPERATURE
82 72 71 69 68 67 66 61 58 57
26 23 22 21 20 18 17 12 7 6 PP3V3_S0 R5535
53 49 47 46 45 43 41 37 35 27 47
1 2 PP3V3_S0_MCPTHMSNS_R
MIN_LINE_WIDTH=0.25 mm
5% MIN_NECK_WIDTH=0.25 mm
1/16W VOLTAGE=3.3V
R5536 1
MF-LF 1
402 1 1
C5535 R5537
VDD 0.1uF 10K 10K
1% 5%

82 20 MCP_THMDIODE_P U5535 2
20%
10V 1/16W
MF-LF
1/16W
MF-LF
BI EMC1413 CERM
402 2
402 2 402
SIGNAL_MODOL=EMPTY DFN
C5522 1 2 DP1 THERM*/ADDR 7 MCPTHMSNS_THERM_L
DETECT MCP DIE TEMPERATURE 0.0022uF
10% 3 DN1 CRITICAL ALERT* 8 MCPTHMSNS_ALERT_L
50V
CERM 2
4 DP2/DN3 9
B 82 20 BI MCP_THMDIODE_N
402

5 DN2/DP3
SMDATA
10
SMBUS_SMC_0_S0_SDA BI 40 43 51 81
B
SMCLK SMBUS_SMC_0_S0_SCL BI 40 43 51 81
GND THRM_PAD
CRITICAL
6 11
J5590
78171-0002
M-RT-SM NOSTUFF 82 MCPTHMSNS_D2_P
3
SIGNAL_MODOL=EMPTY
DETECT HEAT-PIPE TEMPERATURE
1
C5540 1
PLACEMENT NOTE: PLACE U5535 NEAR MCP
0.0022uF
2 10%
50V
NOSTUFFCERM 2
402
4 82 MCPTHMSNS_D2_N

REPLACED 518S0521 WITH 518S0519

Thermal Sensors
A SYNC_MASTER=K24_MLB

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=02/05/2009
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 46 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

68 67 65 64 61 49 42 37 7 6
72 70
PP5V_S0
82 72 71 69 68 67 66 61 58
26 23 22 21 20 18 17 12 7 6
57 53 49 46 45 43 41 37 35 27
PP3V3_S0
CRITICAL

R5660 1 J5601
78171-0004
C 47K
5%
M-RT-SM
NC 5
C
R5665 1/16W
MF-LF
402 2
1 5V DC
40 SMC_FAN_0_TACH 147K2 FAN_RT_TACH
6 2 TACH
5% 3
1/16W
MF-LF 4 MOTOR CONTROL
402 GND
NC 6

R5661 1
100K 518S0521
5% Q5660

1
1/16W
MF-LF SSM3K15FV

G
402 2 SOD-VESM-HF
FAN_RT_PWM

D
6

3
SMC_FAN_0_CTL

2
40

B B

Fan
SYNC_MASTER=K24_MLB SYNC_DATE=02/05/2009
A NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 47 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

KEYBOARD CONNECTOR
PSOC USB CONTROLLER IC PIN NAME CURRENT R_SNS V_SNS POWER
CRITICAL
J5713
TMP102 V+ 10UA 2.55 KOHM 0.0255 V 0.255E-6 W
80UA 0.204 V 16.32E-6 W APN 518S0637
3V3 LDO VDD 60MA MAX 10 OHM 0.6 V 36E-3 W NC 32
USB INTERFACES TO MLB TRACKPAD PICK BUTTONS VOUT 60MA MAX 0.2 OHM 0.012 V 0.72E-3 W
VDD PP3V3_S3
SPI HOST TO Z2 KEYBOARD SCANNER PSOC 8MA (TYP) 1.5 OHM 0.012 V 96E-6 W IN

D 14MA (MAX) 0.021 V 294E-6 W

WS_KBD1
30

29
D
PP3V3_S3_PSOC 48 48 6
28
18V BOOSTER VIN 4MA (MAX) 4.7 OHM 0.0188 V 75.2E-6 W
48 6 WS_KBD2
27

48

48

48

48

48

48
48 6 WS_KBD3
26
PICKB_L

6
49 6
48 6 WS_KBD4

WS_KBD23
WS_KBD22
WS_KBD21
WS_KBD20
WS_KBD19
WS_KBD18
25
48 BUTTON_DISABLE
48 6 WS_KBD5
24
49 6 Z2_HOST_INTN
48 6 WS_KBD6
23
48 WS_LEFT_SHIFT_KEY
48 6 WS_KBD7
22
48 WS_LEFT_OPTION_KEY
48 6 WS_KBD8
21
48 6 WS_KBD9
20

56
55
54
53
52
51
50
49
48
47
46
45
44
43
48 6 WS_KBD10
19

P2_5
P2_7
P0_1
P0_3
P0_5
P0_7
VSS
VDD
P0_6
P0_4
P0_2
P0_0
P2_6
P2_4
R5714 48 6 WS_KBD11
18
470 48 6 WS_KBD12
48 WS_CONTROL_KEY 1
P2_3 P2_2 42 WS_KBD17 6 48 48 WS_KBD15_C 1 2 17
48 6 WS_KBD13
2 41 16
49 6 Z2_KEY_ACT_L P2_1 P2_0 WS_KBD16N 48 1%
1/16W 48 6 WS_KBD14
3 CRITICAL 40 WS_KBD15_C 48 MF-LF 15
NC P4_7 P4_6 402 6 WS_KBD15_CAP
4 39 14
TP_P4_5
5
P4_5 U5701 P4_4
38
WS_KBD14 6 48
6 WS_KBD16_NUM
13
49 6 Z2_DEBUG3 P4_3 CY8C24794 P4_2 WS_KBD13 6 48
48 6 WS_KBD17
6 37 12
49 6 Z2_RESET P4_1 MLF P4_0 WS_KBD12 6 48
R5715 48 6 WS_KBD18
49 6 PSOC_MISO 7
P3_7 (SYM-VER2) P3_6 36 WS_KBD11 6 48 11
10K 48 6 WS_KBD19
49 6 PSOC_F_CS_L 8
P3_5 APN 337S2983 P3_4 35 WS_KBD10 6 48 48 WS_KBD16N 1 2 10
48 6 WS_KBD20
9 P3_3 34 9
49 6 PSOC_MOSI P3_2 WS_KBD9 6 48 1%
OMIT 1/16W 48 6 WS_KBD21
10 33 8
49 6 PSOC_SCLK P3_1 P3_0 WS_KBD8 6 48 MF-LF
402 48 6 WS_KBD22
49 6 Z2_MISO 11
P5_7 P5_6 32 WS_KBD7 6 48 R5710 7
48 6 WS_KBD23
Z2_CS_L 12 31 WS_KBD1 6 48 6
49 6 P5_5 P5_4 41 40 SMC_ONOFF_L 1
1K
2 6 WS_KBD_ONOFF_L
OUT 5
Z2_MOSI 13 30 WS_KBD2 6 48
49 6 P5_3 P5_2 5% 42 41 40 38
67
24 21 20 7 6 PP3V42_G3H
14 29 4
49 6 Z2_SCLK P5_1 P5_0 WS_KBD3 6 48 1/16W 60 59 48 45 43
P7_7
P7_0
P1_0
P1_2
P1_4
P1_6 48 6 WS_LEFT_SHIFT_KBD
15 P1_7
16 P1_5
17 P1_3
18 P1_1

C MF-LF
3
C
19 VSS

22 VDD

402
THRML 1
C5710 48 6 WS_LEFT_OPTION_KBD
20 D+
21 D-

57 2
PAD 0.1UF
48 6 WS_CONTROL_KBD
20% 1
23
24
25
26
27
28

10V
2 CERM
402
PLACEMENT_NOTE=NEAR J5713 NC

TP_PSOC_SCL WS_KBD4
ISOLATION CIRCUIT 31
F-RT-SM
FF14-30A-R11B-B-3H
6 48

WS_KBD5 6 48 C5725
WS_KBD6 6 48 0.1UF
PP3V42_G3H 2 1
6 NC_PSOC_SDA
NC_ISSP_SDATA_P1_0 6
43 42 41 40 38 24 21 20 7 6
67 60 59 48 45

CRITICAL 20%
SMC_MANUAL_RESET LOGIC
10V
ISSP SDATA/I2C SDA 5 TC7SZ08AFEAPE
CERM
PP3V3_S3 2 SOT665
68 50 48 43 30 29 25 20 7 6 A 402 43 42 41 40 38 24 21 20 7 6 PP3V42_G3H
NC_PSOC_P1_3 4 WS_LEFT_SHIFT_KEY 48 67 60 59 48 45
1
6
Z2_CLKIN 6 49 U5725 Y C5758
48 6 WS_LEFT_SHIFT_KBD 1 0.1UF
B
10%
16V
3 2 X7R-CERM
402
NC_P7_7 6
6 NC_ISSP_SCLK_P1_1
ISSP SCLK/I2C SCL C5726
0.1UF
PP3V42_G3H 2 1
43 42 41 40 38 24 21 20 7 6
67 60 59 48 45
APN 311S0406
20%
DIFFERENTIAL_PAIR=USB2_TPAD CRITICAL
5 TC7SZ08AFEAPE 10V CRITICAL
R5701 68 50 48 43 30 29 25 20 7 6
PP3V3_S3 2 SOT665
CERM
402
5
SN74LVC1G10
24 A 48 6 WS_LEFT_SHIFT_KBD 1 A SC70
78 19 USB_TPAD_P 1 2 USB_TPAD_R_P 4 WS_LEFT_OPTION_KEY 48
U5726 Y 48 6 WS_LEFT_OPTION_KBD 3 B 4 41
5% PP3V3_S3_PSOC 48 WS_LEFT_OPTION_KBD 1 U5703 Y
48 6 B
1/16W 48 6 WS_CONTROL_KBD 6
C SMC_TPAD_RST_L
MF-LF
402 3
B TO MLB CONNECTOR
2
B
R5702
24
78 19 USB_TPAD_N 1 2 USB_TPAD_R_N
C5727 1
5% R5769 1 1
1/16W PP3V42_G3H
0.1UF R5770 R5771
MF-LF 2 1 33K 33K
45 43 42 41 40 38 24 21 20 7 6 5%
33K
402 67 60 59 48 5% 5%
1/16W
DIFFERENTIAL_PAIR=USB2_TPAD 1/16W 1/16W
20% MF-LF
CRITICAL MF-LF MF-LF
10V 2 402
5 TC7SZ08AFEAPE
CERM 2 402 402
68 50 48 43 30 29 25 20 7 6
PP3V3_S3 2 SOT665
402
2
A
4 WS_CONTROL_KEY 48
U5727 Y
48 6 WS_CONTROL_KBD 1
B

3
U5701 CHIP DECOUPLING
Alternate Parts
PLACE C5701, C5702 & C5703 PLACE C5704, C5705 & C5706 TABLE_ALT_HEAD

CLOSE TO U5701 VDD PIN 22 CLOSE TO U5701 VDD PIN 49 PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
TPAD BUTTONS DISABLE 311S0406
PART NUMBER

311S0447 ALL NXP PART AS ALTERNATE

TABLE_ALT_ITEM

R5704 BUTTON_DISABLE
1.5 PP3V3_S3 48 PLACE THESE COMPONENTS CLOSE TO J5800
48 PP3V3_S3_PSOC MIN_LINE_WIDTH=0.50MM 1 2 6 7 20 25 29 30 43 48 50 68
MIN_NECK_WIDTH=0.20MM
5%
THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB
1/16W
MF-LF
1 C5701 1 C5702 1 C5703 1 C5704 1 C5705 1 C5706 402
4.7UF 100PF 0.1UF 100PF 0.1UF 4.7UF
20% 5% 10% 5% 10% 20% Q5701
2
6.3V
X5R
603
2
50V
CERM
402
2
16V
X7R-CERM
402
2
50V
CERM
402
2
16V
X7R-CERM
402
6.3V
2 X5R
603
SSM3K15FV
SOD-VESM-HF
D 3 WELLSPRING 1
A SYNC_MASTER=K24_MLB

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=02/05/2009
A
THE TPAD BUTTONS WILL BE DISABLE
1 G S 2 WHEN THE LID IS CLOSED THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
SMC_LID LID OPEN => SMC_LID_LC ~ 3.42V PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
59 41 40
AGREES TO THE FOLLOWING
IN
LID CLOSE => SMC_LID_LC < 0.50V I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 48 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

BOOSTER +18.5VDC FOR SENSORS

BOOSTER DESIGN CONSIDERATION:
- POWER CONSUMPTION
- DROOP LINE REGULATION
- RIPPLE TO MEET ERS
- 100-300 KHZ CLEAN SPECTRUM
- STARTUP TIME LESS THAN 2MS

D 53 51 49 41 39 38 37 29 8 7 6
PP5V_S3
APN 152S0504

CRITICAL
- R5812,R5813,C5818 MODIFIED
D
CRITICAL
68 63 62
L5801
3.3UH-870MA D5802 R5806
SOD-323
0 PP18V5_S3 IPD FLEX CONNECTOR

2
INPUT_SW BOOST_SW PP18V5_S3_SW

R5805
MIN_LINE_WIDTH=0.50MM 1 2 6 49

1/16W
MF-LF
MIN_NECK_WIDTH=0.20MM

402
VLF3010AT-SM-HF MIN_LINE_WIDTH=0.50MM

5%
5%

0
0.50MM
MIN_NECK_WIDTH=0.20MM 1/16W
0.20MM B0520WSXG MF-LF
SWITCH_NODE=TRUE APN 371S0313 402

1
1
1
C5818 R5812 APN 516S0689
MIN_LINE_WIDTH=0.50MM PP5V_S3_BOOSTER 39PF
1M
MIN_NECK_WIDTH=0.20MM 1%
5%
1/16W
2
50V
MF-LF CRITICAL
CERM
APN 353S1401 2 402 J5800

2
402

55560-0228
VIN 0.50MM M-ST-SM
1 C5819 0.20MM

U5805 1UF 2 1
1 L FB 4 BOOST_FB 10%
1 TPS61045 25V 48 6 Z2_CS_L 4 3 Z2_KEY_ACT_L 6 48
C5800 QFN
2 X5R
6 5 Z2_RESET 6 48
0.1UF 3 5 Z2_BOOST_EN 603-1 48 6 Z2_DEBUG3
DO CTRL 6 49
20%
10V 48 6 Z2_MOSI
8 7 PSOC_F_CS_L 6 48
2 CERM CRITICAL 1
48 6 Z2_MISO
R5813 10 9 PICKB_L
402
SW 8 6 48
71.5K PSOC_MISO

7 PGND
PLACEMENT_NOTE=NEAR J5800 48 6 Z2_SCLK
12 11 6 48

6 GND
1%
THRML
PAD 1
1/16W
49 6 Z2_BOOST_EN
14 13 PSOC_MOSI 6 48
1 C5816 1 C5817 R5811 MF-LF
16 15 PSOC_SCLK
48 6 Z2_HOST_INTN
402
2 6 48

9
100K
0.1UF 2.2UF
10% 10%
1%
1/16W
NC 18 17 SMBUS_SMC_A_S3_SDA 6 29 40 43 81
16V 16V
2 X7R-CERM
2 X5R
MF-LF
48 6
Z2_CLKIN 20 19 SMBUS_SMC_A_S3_SCL 6 29 40 43 81
402 603 402
2
49 6 PP3V3_S3_LDO 0.50MM
22 21 0.50MM PP18V5_S3 6 49
0.20MM 0.20MM

C C

3V3 LDO FOR IPD

R5873
PP5V_S3 1
10 2 PP5V_S3_VR
53 51 49 41 39 38 37 29 8 7 6
68 63 62
1%
1/16W
MF-LF
402
49 6 PP3V3_S3_LDO

CRITICAL

2
APN 353S1364

R5836

402-HF
0.2

1/6W
1%

MF
VDD 1 C5838 1 C5854
1 C5853 VR5802 0.1UF 4.7UF
2.2UF

1
MM3243DRRE 10% 20%
10% 16V 6.3V
MLF 2 X7R-CERM 2
2 X5R
16V
1 CE VOUT 3 PP3V3_S3_LDO_R 402
X5R
603
603 GND

B B

KEYBOARD BACKLIGHT DRIVNG AND DETECTION

KB_BL
82 72 71 69 68 67 66 61 58
26 23 22 21 20 18 17 12 7 6
PP3V3_S0 68 67 65 64 61 47 42 37 7 6 PP5V_S0 CRITICAL
57 53 47 46 45 43 41 37 35 27 72 70 APN 518S0691
L5850 J5815 pin 1 is grounded
10UH-0.58A-0.35OHM
KB_BL
CRITICAL on keyboard backlight flex
To detect Keyboard backlight, SMC will R5853 1 1 2 KBDLED_SW
MIN_LINE_WIDTH=0.3 MM J5815
470K 1098AS-SM
KB_BL MIN_NECK_WIDTH=0.25 MM FF18-4A-R11AD-B-3H
5% SWITCH_NODE=TRUE F-RT-SM
tristate SMC_SYS_KBDLED: 1/16W C5850 1
1

MF-LF
402 1UF VIN 49 6
SMC_KDBLED_PRESENT_L 1
LOW = keyboard backlight present 2 10%
10V 2
X5R 2
SW 3
HIGH= keyboard backlight not present 402-1 3
SMC_SYS_KBDLED 6 CTRL LED 5 6 KBDLED_ANODE 4
IN
BOM OPTION: KBDLED_YES KB_BL MIN_LINE_WIDTH=0.25 MM
WELLSPRING 2
40

MIN_NECK_WIDTH=0.25 MM
TURNED ON FOR BEST MLB CONFIG CRITICAL 1 KB_BL
NO STUFF U5850 R5855
A R5853 ALWAYS PRESENT
KB_BL
R5854 1 R5852 1 LT3491
DFN
10
1%
1/16W
SYNC_MASTER=K24_MLB

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=02/25/2009
A
4.7K 10K MF-LF
5%
1/16W
MF-LF
5%
1/16W
MF-LF
2
402
KBD BACKLIGHT CONNECTOR THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
402 402
2
CAP 4 KBDLED_CAP AGREES TO THE FOLLOWING
2 MIN_LINE_WIDTH=0.25 MM
THRML MIN_NECK_WIDTH=0.25 MM KB_BL I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
GND PAD 1
C5855 II NOT TO REPRODUCE OR COPY IT
7
2

1UF
10%
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
35V
2 X5R
603 SIZE DRAWING NUMBER REV.
SMC_KDBLED_PRESENT_L
49 6
D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 49 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

C C

Analog SMS
R5921 PULLS UP SMS_PWRDN TO TURN OFF SMS WHEN PIN IS NOT BEING DRIVEN BY SMC

68 48 43 30 29 25 20 7 6 PP3V3_S3
Desired orientation when
1 C5922 1 C5926 placed on board top-side:
14

0.1UF 10UF
B R59211 VDD
10%
2 16V
X5R
20%
2 4V
X5R
B
10K 402 603
5%
1/16W U5920
MF-LF
402 2
AP344ALH +Y
LGA
1 FS VOUTX 12 SMS_X_AXIS OUT 40
Front of system
50 40 IN SMS_PWRDN 50 40 SMS_PWRDN 5 PD CRITICAL +X
MAKE_BASE=TRUE VOUTY 10 SMS_Y_AXIS OUT 40
SMS_SELFTEST2 ST +Z (up)
VOUTZ 8 SMS_Z_AXIS OUT 40

15 RES
NC 4 RES
1
R5922 NC 3 NC NC 11 NC
10K 6 NC Circle indicates pin 1 location when placed
5% NC NC 13 NC
1/16W in correct orientation
MF-LF NC 9 NC NC 16 NC 1 C5923 1 C5924 1 C5925
2 402 GND 0.01UF 0.01UF 0.01UF
10% 10% 10%
2 16V 2 16V 2 16V
7

CERM CERM CERM

402 402 402

Sudden Motion Sensor (SMS)

A SYNC_MASTER=K19_MLB

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=02/05/2009
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 50 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
PLACEMENT_NOTE=PLACE NEAR Q4590 53 51 49 41 39 38 37 29 8 7 6 PP5V_S3 53 51 49 41 39 38 37 29 8 7 6 PP5V_S3
PLACEMENT_NOTE=PLACE NEAR Q3450 68 63 62 68 63 62

XW6010
SM
XW6020
SM
DEBUG_ADC DEBUG_ADC DEBUG_ADC DEBUG_ADC
PP5V_WLAN_F 1 2 PP5V_WLAN_F_XW PP5V_SW_ODD 1 2 PP5V_SW_ODD_XW
1 C6000 1 C6001 1 C6002 1 C6003
29 37 6
0.1UF 10UF 0.1UF 10UF
20% 20% 20% 20%
DEBUG_ADC DEBUG_ADC 2 10V
CERM 2 6.3V
X5R 2 10V
CERM 2 6.3V
X5R
1 1 402 603 402 603
R6010 R6020
PLACEMENT_NOTE=PLACE RC NEAR U6000 PLACEMENT_NOTE=PLACE RC NEAR U6000

12
13

21
1M 1M
1% 1%
1/16W DEBUG_ADC 1/16W DEBUG_ADC
MF-LF MF-LF AVDD DVDD
2 402 R6012 2 402 R6022 DEBUG_ADC
226K 2 226K 2 U6000 R6001 PLACEMENT_NOTE=PLACE CLOSE TO U4900
D
D PP5V_WLAN_F_DIV
DEBUG_ADC
1
1%
ADC_CH0 51 PP5V_SW_ODD_DIV
DEBUG_ADC
1
1%
ADC_CH1 51

51 ADC_CH0 22 CH0
LTC2309
QFN AD0 14 1
0 2 SMBUS_SMC_0_S0_SDA BI 40 43 46
1
1/16W DEBUG_ADC 1
1/16W DEBUG_ADC ADC_CH1 23
81

R6011 MF-LF R6021 MF-LF CH1 AD1 15 5%

681K
402 1 C6012 681K
402 1 C6022 51

ADC_CH2 24 CH2
DEBUG_ADC 1/16W
MF-LF
DEBUG_ADC
2.2UF 2.2UF 51
402
1%
1/16W 10% 1%
1/16W 10% 51 ADC_CH3 1 CH3 SDA 17 ADC_SDA R6002 PLACEMENT_NOTE=PLACE CLOSE TO U4900

MF-LF 2 6.3V
X5R MF-LF 2 6.3V
X5R 0 SMBUS_SMC_0_S0_SCL
2 402 402 2 402 402 51 ADC_CH4 2 CH4 SCL 16 ADC_SCL 1 2 IN 40 43 46 81

51 ADC_CH5 3 CH5 5%
1/16W
51 ADC_CH6 4 CH6 VREF 7 ADC_VREF MF-LF
402
51 ADC_CH7 5 CH7
6 COM REFCOMP 8 ADC_REFCOMP
DIVIDER: ~ 2/5 DEBUG_ADC DEBUG_ADC DEBUG_ADC
DIVIDER: ~ 2/5
I2C ADDRESS: 0X10 / 0X11 GND
THRM
PAD
1 C6004 1 C6005 1 C6006
ADC RANGE: 0V TO 4.096V 0.1UF 10UF 2.2UF
20% 20% 20%

9
10
11
18
19
20

25
LSB: 0.001V 2 10V
CERM 2 6.3V
X5R 2 6.3V
CERM
402 603 402-LF

53 51 49 41 39 38 37 29 8 7 6
68 63 62
PP5V_S3
DEBUG_ADC DEBUG_ADC
1 C6030 1 C6040
0.1UF 0.1UF
DEBUG_ADC 20% DEBUG_ADC 20%
2 10V
CERM 2 10V
CERM
R6030 402 R6050 402
ISNS_AIRPORT_P 243 PLACEMENT_NOTE=PLACE RC NEAR U6000 499 PLACEMENT_NOTE=PLACE RC NEAR U6000
82 29 IN 1 2 82 ISNS_AIRPORT_R_P DEBUG_ADC 82 37 IN ISNS_ODD_P 1 2 82 ISNS_ODD_R_P DEBUG_ADC
1%
1/16W
U6030 DEBUG_ADC 1%
1/16W
U6040 DEBUG_ADC
OPA2330 OPA2330
C MF-LF
402 3
V+
8 DFN
1 ISNS_AIRPORT_IOUT
R6034
1
226K 2
ADC_CH2 51
MF-LF
402 3
V+
8 DFN
1 ISNS_ODD_IOUT
R6054
1
226K 2
ADC_CH4 51
C
DEBUG_ADC 2 1%
DEBUG_ADC 2 1%
V- 1/16W DEBUG_ADC V- 1/16W DEBUG_ADC
R6031 THRM 4 MF-LF R6051 THRM 4 MF-LF
ISNS_AIRPORT_N 1
243 2 82 ISNS_AIRPORT_R_N 9 GAIN: 1239X 402 1 C6034 ISNS_ODD_N 1
499 2 82 ISNS_ODD_R_N 9 GAIN: 561X 402 1 C6054
82 29 IN 2.2UF 82 37 IN 2.2UF
1% 10% 1% 10%
1/16W 2 6.3V
X5R 1/16W 2 6.3V
X5R
MF-LF MF-LF
402 402 402 402
DEBUG_ADC DEBUG_ADC
DEBUG_ADC DEBUG_ADC
1 DEBUG_ADC DEBUG_ADC
1
C6032 1 R6032 R6033 C6052 1 R6052 R6053
470PF 301K 1
301K 2 470PF 280K 1
280K 2
10% 1% 10% 1%
50V 1/16W 50V 1/16W
CERM 2 MF-LF 1% DEBUG_ADC CERM 2 MF-LF 1% DEBUG_ADC
402 2 402 1/16W 402 2 402 1/16W
MF-LF C6033 MF-LF C6053
402 402
470PF 470PF
1 2 1 2

10% 10%
50V 50V
CERM CERM
DEBUG_ADC 402 DEBUG_ADC 402

R6040 R6060
ISNS_1V5_S3_P 3.65K2 ISNS_1V5_S3_R_P PLACEMENT_NOTE=PLACE RC NEAR U6000 ISNS_HDD_P 412 PLACEMENT_NOTE=PLACE RC NEAR U6000
82 63 IN
1 82 82 37 IN
1 2 82 ISNS_HDD_R_P
1%
1/16W
U6030 DEBUG_ADC 1%
1/16W
U6040 DEBUG_ADC
OPA2330 OPA2330
MF-LF
402 5 8 DFN R6044 MF-LF
402 5 8 DFN R6064
V+ 7 ISNS_1V5_S3_IOUT 226K 2 V+ 7 ISNS_HDD_IOUT 226K 2
1 ADC_CH3 51 1 ADC_CH5 51
DEBUG_ADC 6 1%
DEBUG_ADC 6 1%
V- 1/16W DEBUG_ADC V- 1/16W DEBUG_ADC
R6041 THRM 4 MF-LF R6061 THRM 4 MF-LF
ISNS_1V5_S3_N
3.65K2
1 82 ISNS_1V5_S3_R_N 9 GAIN: 273X 402 1 C6044 ISNS_HDD_N 1
412 2 82 ISNS_HDD_R_N 9 GAIN: 845X 402 1 C6064
82 63
2.2UF 82 37
2.2UF
B IN
1%
1/16W
10%
2 6.3V
X5R
IN
1%
1/16W
10%
2 6.3V
X5R
B
MF-LF MF-LF
402 402 402 402
DEBUG_ADC DEBUG_ADC
DEBUG_ADC DEBUG_ADC
1 DEBUG_ADC DEBUG_ADC
1
C6042 1 R6042 R6043 C6062 1 R6062 R6063
470PF 1M 1
1M 2 470PF 348K 1
348K 2
10% 1% 10% 1%
50V 1/16W 50V 1/16W
CERM 2 MF-LF 1%
1/16W
DEBUG_ADC CERM 2 MF-LF 1% DEBUG_ADC
1/16W
402 2 402 402 2 402 MF-LF
MF-LF
402 C6043 402 C6063
470PF 470PF
1 2 1 2

10% 10%
50V 50V
CERM CERM
402 PLACEMENT_NOTE=PLACE NEAR D9701 402
53 51 49 41 39 38 37 29 8 7 6 PP5V_S3
68 63 62 DEBUG_ADC
1 C6050 XW6080
SM
0.1UF PPVOUT_S0_LCDBKLT
20% 74 72 69 6 1 2 PPVOUT_S0_LCDBKLT_XW
2 10V
CERM
402 DEBUG_ADC
1
R6080
3

PLACEMENT_NOTE=PLACE RC NEAR U6000 1M PLACEMENT_NOTE=PLACE RC NEAR U6000

V+ 1%
DEBUG_ADC 1/16W DEBUG_ADC
MF-LF
U6050 R6074 2 402 R6082
INA210 226K 2 226K 2
82 72 IN ISNS_LCDBKLT_N 5 IN- SC70 OUT 6 ISNS_LCDBKLT_IOUT 1 ADC_CH6 51 PPVOUT_S0_LCDBKLT_DIV 1 ADC_CH7 51

DEBUG_ADC 1% DEBUG_ADC 1%
ISNS_LCDBKLT_P 4 IN+ REF 1
1/16W
MF-LF
DEBUG_ADC 1
R6081
1/16W
MF-LF
DEBUG_ADC DEBUG SENSORS AND ADC
82 72 IN
GAIN: 200X 402 1 C6074 47.0K
402 1 C6082
A GND
2.2UF
10%
2 6.3V
1%
1/16W
MF-LF
2.2UF
10%
2 6.3V
SYNC_MASTER=K19_MLB

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=03/25/2009
A
X5R X5R
2

402 2 402 402

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
DIVIDER: ~ 1/22
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 51 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

35 32 28 24 22 21 19 17 7 6
82 71 69 68 67 66 62 42 36
PP3V3_S5

NO STUFF
R61901 R61001 1
R6101 C6100 1 CRITICAL

8
10K 3.3K 3.3K 0.1UF VCC
5% 5% 5% 20%
1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF 10V
CERM 2 U6100
C R6150
0
402 2 402 2 2 402 402 32MBIT
SOP
R6152
0
C
42 SPI_CLK_MUX 1 2 78 SPI_CLK 6 SCLK SI/SIO0 5 78 SPI_MOSI 1 2 SPI_MOSI_MUX 42
IN IN
PLACEMENT_NOTE=PLACE CLOSE TO U6100 5% MX25L3205DM2I-12G 5% PLACEMENT_NOTE=PLACE CLOSE TO U6100
1/16W R6105 1/16W
SPI_MLB_CS_L
MF-LF
1 CE* OMIT MF-LF
42 IN 402 0 402
SO/SIO1 2 SPI_MISO_R
78 1 2 SPI_MISO_MUX OUT 42
SPI_WP_L 3 WP*/ACC
NO STUFF 5%
SPI_HOLD_L 7 HOLD*
1
1/16W PLACEMENT_NOTE=PLACE CLOSE TO U6100
R6191 MF-LF
402
GND 10K
5%

4
1/16W
MF-LF
2 402

MCP79 SPI Frequency Select

Frequency SPI_MOSI SPI_CLK

B 31 MHz 0 0
B
42 MHz 0 1

25 MHz 1 0

1 MHz 1 1

25MHz is selected with R5190 and R5191

Any of the 4 frequencies can be selected
with R6190, R6191, R5190 and R5191

SPI ROM
A SYNC_MASTER=K19_MLB

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=02/05/2009
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 52 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
AUDIO CODEC
CRITICAL APPLE P/N 353S2355
L6201
FERR-220-OHM PP5V_S3 6 7 8 29 37 38 39 41 49 51 53
62 63 68
66 23 17 7 6 PP1V8_S0 1 2 PP1V8_S0_AUDIO_DIG
IN
0402 VOLTAGE=1.8V
CRITICAL MIN_LINE_WIDTH=0.10MM
PP3V3_S0 58 61 66 67 68 69 71 72 82
MIN_NECK_WIDTH=0.10MM 6 7 12 17 18 20 21 22 23 26 27
C6210 1 1 C6211 35 37 41 43 45 46 47 49 53 57

4.7UF 0.1UF
20% 10% PP4V5_AUDIO_ANALOG IN
4V 2 2 16V CRITICAL VOLTAGE=4.5V
6 53
X5R X5R CRITICAL CRITICAL MIN_LINE_WIDTH=0.15MM
402 402
1 C6216 1 C6215 1 C6214 1 1 C6213 MIN_NECK_WIDTH=0.10MM
C6219 1UF 0.1UF
D 10UF
20% C6218 1 C6217
10%
1CRITICAL10V
X5R 2
10%
16V 2
X5R
0.1UF
10%
16V 2
10UF
20%
D
57 55 53 GND_AUDIO_HP_AMP 16V
TANT-POLY 2 0.1UF 10UF 402-1 402 X5R 2 6.3V
X5R
53 6 PP4V5_AUDIO_ANALOG 2012-LLP 10% 20% 402 603
IN 16V 2

24

46

25
CRITICAL CRITICAL X5R 2 16V

9
6 PP3V3_S0 GND_AUDIO_HP_AMP
69 68 67 66 61 58 57 TANT-POLY
26 23 22 21 20 18 17 12 7
53 49 47 46 45 43 41 37 35
82 72 71
27
K19
C6221 1 1 C6220 VD VA_REF VA_HP VA
402 2012-LLP
GND_AUDIO_CODEC
53 55 57

1
R6210 10UF 10UF 53 54 58
1 20% 20% VBIAS_DAC
R6218 2.67K 6.3V
X5R 2 2 6.3V
X5R
29 VBIAS_DAC
10K 1% 603-1 603-1 HPOUT_L 38 MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM AUD_HP_PORT_L OUT 55
5% 1/16W CS4206_FP 44 VHP_FILT+
1/16W MF-LF HPOUT_R 40 MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM AUD_HP_PORT_R OUT 55
MF-LF 2 402 CS4206_FN 41 VHP_FILT-
2 402 HPREF 39 MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM AUD_HP_PORT_REF 57
IN

NC TP_AUD_GPIO_0 2 GPIO0/DMIC_SDA1 LINEOUT_L1+ 35 NC_AUD_LO1_P_L NC 6

AUD_GPIO_1 12 GPIO1/DMIC_SDA2 LINEOUT_L1- 34 NC_AUD_LO1_N_L NC 6
/SPDIF_OUT2
NC TP_AUD_GPIO_2 14 GPIO2 LINEOUT_R1+ 36 AUD_LO1_P_R OUT 56
56 OUT AUD_GPIO_3 15 GPIO3 LINEOUT_R1- 37 AUD_LO1_N_R OUT 56
58 IN AUD_SENSE_A 13 SENSE_A LINEOUT_L2+ 31 AUD_LO2_P_L OUT 56

CS4206_FLYP LINEOUT_L2- 30 AUD_LO2_N_L OUT 56

K19I CS4206_FLYC AUD_LO2_P_R
1 LINEOUT_R2+ 32 OUT 56
R6219 CRITICAL CRITICAL 45 FLYP
AUD_LO2_N_R
LINEOUT_R2- 33
5%
10K C6222 1 1 C6223 43 FLYC OUT 56

1/16W 2.2UF 2.2UF 42 FLYN

MF-LF 20% 20%
6.3V 6.3V 16 AUD_CODEC_MICBIAS
2 402 CERM 2 2 CERM U6201 MICBIAS OUT 58
402-LF 402-LF
CS4206_FLYN
3 VL_HD CS4206ACNZC
QFN
VCOM 28 CS4206_VCOM
CRITICAL
1 VL_IF

AUD_LI_P_L
C 78 20 IN HDA_BIT_CLK 6 BITCLK
LINEIN_L+
LINEIN_C-
21
22 AUD_LI_REF
IN
IN
54

54
C
78 20 IN HDA_SYNC LINEIN_R+ 23 AUD_LI_P_R IN 54

R6211 10 SYNC
39
78 20 OUT HDA_SDIN0 1 2 AUD_SDI_R 8 SDI MICIN_L+ 18 AUD_MIC_INP_L IN 58

5% 5 SDO MICIN_L- 17 AUD_MIC_INN_L IN 58

1/16W
MF-LF MICIN_R+ 19 AUD_MIC_INP_R IN 58
402 11 RESET*
78 20 IN HDA_SDOUT MICIN_R- 20 AUD_MIC_INN_R IN 58

78 20 IN HDA_RST_L
57 IN AUD_SPDIF_IN 47 SPDIF_IN
AUD_SPDIF_OUT_CHIP 48 SPDIF_OUT
VREF+_ADC 27 CS4206_VREF_ADC NC
R6212
39
57 OUT AUD_SPDIF_OUT 1 2 DMIC_SCL 4 TP_AUD_DMIC_CLK NC
5%
1/16W
MF-LF
402 DGND THRM_PAD AGND

49

26
CRITICAL CRITICAL
C6224 1 1
C6225
1UF 10UF 1
20%
16V
20%
2 16V
R6213
TANT 2 POLY-TANT 100K
0603-SM CASE-B2-SM 5%
1/16W
MF-LF
2 402

MIN_LINE_WIDTH=0.5MM
58 54 53 GND_AUDIO_CODEC MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V

B B

4.5V POWER SUPPLY FOR CODEC

APPLE P/N 353S2234
CRITICAL CRITICAL MIN_LINE_WIDTH=0.15MM
L6200 MIN_LINE_WIDTH=0.15MM
FERR-220-OHM MIN_NECK_WIDTH=0.10MM
U6200
MIN_NECK_WIDTH=0.10MM
VOLTAGE=4.5V NOTES ON CODEC I/O
VOLTAGE=5V MAX8840-4.5V
53 51 49 41 39 38 37 29 8 7 6 PP5V_S3 1 2 4V5_REG_IN 1 IN UDFN
OUT 6 PP4V5_AUDIO_ANALOG 6 53
DIFF FSINPUT= 2.45VRMS
IN OUT
68 63 62
0402 SE FSINPUT= 1.22VRMS
R6200 BP 4 4V5_NR
DAC1 FSOUTPUT= 1.34VRMS
71 69 68 67 66 61 58 57 53
PP3V3_S0 1
2.21K2 4V5_REG_EN 3 SHDN*
CRITICAL
DAC2/3 FSOUTPUTDIFF= 2.67VRMS
26 23 22 21 20 18 17 12 7 6
49 47 46 45 43 41 37 35 27 IN
GND NC 5 C6202 DAC2/3 FSOUTPUTSE= 1.34VRMS
82 72 1%
1/16W
0.1UF 1 C6203
1UF
2

MF-LF
402
1 C6200 CRITICAL 1 2
10%
1UF 1 C6201 2 10V
X5R
10% 10%
10V
2 X5R 1UF 16V 402-1
10% X7R-CERM
402-1 XW6200
SM
2 10V
X5R
402
402-1
1 2 GND_AUDIO_CODEC 53 54 58
VOLTAGE=0V
NOSTUFF
R6201
AUDIO: CODEC/REGULATOR
0
A 1
5%
2
NOTICE OF PROPRIETARY PROPERTY
A
1/16W
MF-LF
402 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
XW6201
SM MIN_LINE_WIDTH=0.15MM I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
MIN_NECK_WIDTH=0.10MM
1 2 GND_AUDIO_HP_AMP 53 55 57 II NOT TO REPRODUCE OR COPY IT
VOLTAGE=0V
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 53 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

LINE INPUT VOLTAGE DIVIDER

CODEC RIN = 20K OHMS
NET RIN = 20K OHMS
FC = 8 HZ
VIN = 2VRMS, CODEC VIN = 1.21 VRMS

CRITICAL
R6301 C6301
3.3UF
AUD_LI_L 6.04K2
1 AUD_LI_L_DIV 1 2 AUD_LI_P_L
57 IN OUT 53
MIN_LINE_WIDTH=.1MM MIN_LINE_WIDTH=.1MM MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM 1% MIN_NECK_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
1/16W 10%
MF-LF 10V
402 CERM-X5R
805-1
C CRITICAL
NOSTUFF
C
1
R6302 1 C6303
16.5K 15PF
1% 5%
1/16W 2 50V
CERM
MF-LF 402
2 402 CRITICAL
C6302
3.3UF
1 2

10%
10V
CERM-X5R
805-1

AUD_LI_REF OUT 53
57 IN AUD_LI_GND MIN_LINE_WIDTH=.1MM
MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
1
R6300
10
1% CRITICAL
1/16W
MF-LF
2 402
C6312
3.3UF
1 2

58 53 GND_AUDIO_CODEC 10%
IN 10V
CERM-X5R
805-1
CRITICAL
1
R6312 NOSTUFF
B 16.5K
1%
1 C6313
15PF
B
1/16W 5%
MF-LF
2 402 2 50V
CERM
402
CRITICAL
R6311 C6311
3.3UF
6.04K2 1 2
57 IN AUD_LI_R 1 AUD_LI_R_DIV AUD_LI_P_R OUT 53
MIN_LINE_WIDTH=.1MM MIN_LINE_WIDTH=.1MM MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM 1% MIN_NECK_WIDTH=.1MM 10% MIN_NECK_WIDTH=.1MM
1/16W 10V
MF-LF CERM-X5R
402
805-1

AUDIO: LINE INPUT FILTER

A NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 54 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER

R6501
0
AUD_HP_PORT_L 1 2 AUD_HP_L OUT
C 53 IN

CRITICAL
5%
1/10W
57
C
MF-LF
C6500 1 603
0.1UF NO STUFF
10% 1
16V
X7R-CERM 2
CRITICAL R6502
402 C6501 1 2.21K
1%
NC AUD_HP_ZOBEL_L 0.0022UF 1/16W
10% MF-LF
50V
1 CERM 2 2 402
R6500 402
39
5%
1/16W
MF-LF
402 2

57 53 IN GND_AUDIO_HP_AMP

R65101
39
5%
1/16W
MF-LF NO STUFF
402 2 CRITICAL 1
C6511 1 R6512
NC AUD_HP_ZOBEL_R 0.0022UF 2.21K
1%
CRITICAL 10% 1/16W
50V
C6510 1 CERM 2 MF-LF
402 2 402
0.1UF
10%
16V
X7R-CERM 2
402 R6511
AUD_HP_PORT_R 1
0 2 AUD_HP_R
53 IN OUT 57

5%
B 1/10W
MF-LF
603
B

AUDIO: HEADPHONE FILTER

A SYNC_MASTER=K19_MLB

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=02/05/2009
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 55 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

3X MONO SPEAKER AMPLIFIERS (SSM2315)

APN: 353S2500
GAIN = 6DB
1ST ORDER FC (L&R) = 120 HZ +/- 30%
1ST ORDER FC (SUB) = 58HZ +/- 30%

D PLACE C6610 CLOSE TO VDD PIN

D
56 8 PP5V_S3_AUDIO_AMP

CRITICAL
CRITICAL 1 C6613
C6612 1 0.1UF SPEAKER CHECKPOINTS
47UF 10%
20% 2 16V
X5R
6.3V
TANT-POLY 2 402
CASE-A4

B1

B2
VDD PVDD
CRITICAL
L6610 C6610 U6610
FERR-1000-OHM CRITICAL 0.033UF SSM2315
MIN_LINE_WIDTH=0.30 mm R6610 MIN_LINE_WIDTH=0.30 mm
1 2 1 2 WLCSP OUT+ C3 MIN_NECK_WIDTH=0.20 MM MIN_NECK_WIDTH=0.20 MM
53 IN AUD_LO2_P_L AUD_SPKRAMP_INP_L SSM2315L_P C1 IN- SPKRAMP_L_OUT_P 56 82 0
CRITICAL SPKRAMP_L_OUT_P 2 1 SPKRCONN_L_OUT_P
L6611 0402 C6611 10% SSM2315L_N A1 IN+ OUT_ A3 SPKRAMP_L_OUT_N 56 82
82 56 OUT 6 57 82

FERR-1000-OHM CRITICAL 16V

0.033UF X5R CRITICAL
5%
1/16W
C2 SD* MF-LF
53 AUD_LO2_N_L 1 2 AUD_SPKRAMP_INN_L 1 2 402 402
IN
L6601 0402
10%
GND
FERR-1000-OHM CRITICAL 16V MIN_LINE_WIDTH=0.30 mm R6611 MIN_LINE_WIDTH=0.30 mm

B3
A2
X5R MIN_NECK_WIDTH=0.20 MM MIN_NECK_WIDTH=0.20 MM
53 AUD_GPIO_3 1 2 402 0
IN SPKRAMP_L_OUT_N 2 1 SPKRCONN_L_OUT_N
82 56 OUT 6 57 82
0402
R66011 5%
1/16W
AUD_SPKRAMP_SHUTDOWN_L 100K MF-LF
402
56 5%
1/16W
MF-LF
402 2

C C

PLACE C6620 CLOSE TO VDD PIN MIN_LINE_WIDTH=0.30 mm R6620 MIN_LINE_WIDTH=0.30 mm

56 8 PP5V_S3_AUDIO_AMP MIN_NECK_WIDTH=0.20 MM MIN_NECK_WIDTH=0.20 MM
0
82 56 SPKRAMP_R_OUT_P 2 1 SPKRCONN_R_OUT_P OUT 6 57 82

CRITICAL 5%
1/16W
C6622 1 CRITICAL MF-LF
402
47UF
20%
1 C6623
6.3V 0.1UF MIN_LINE_WIDTH=0.30 mm R6621 MIN_LINE_WIDTH=0.30 mm

B1

B2
TANT-POLY 2 10% MIN_NECK_WIDTH=0.20 MM MIN_NECK_WIDTH=0.20 MM
CASE-A4 2 16V
X5R 0
CRITICAL VDD PVDD 402 82 56 SPKRAMP_R_OUT_N 2 1 SPKRCONN_R_OUT_N OUT 6 57 82

L6620 C6620 U6620 5%

FERR-1000-OHM CRITICAL 0.033UF SSM2315
1/16W
MF-LF
1 2 1 2 WLCSP OUT+ C3 402
53 IN AUD_LO2_P_R AUD_SPKRAMP_INP_R SSM2315R_P C1 IN- SPKRAMP_R_OUT_P 56 82
0402 CRITICAL 10% SSM2315R_N A1 IN+ OUT_ A3 SPKRAMP_R_OUT_N 56 82

L6621 C6621 16V

X5R C2 SD* CRITICAL
FERR-1000-OHM CRITICAL 0.033UF 402
53 AUD_LO2_N_R 1 2 AUD_SPKRAMP_INN_R 1 2 GND
IN
0402

B3
A2
10%
16V
X5R
402
56 AUD_SPKRAMP_SHUTDOWN_L

MIN_LINE_WIDTH=0.30 mm R6630 MIN_LINE_WIDTH=0.30 mm

B 82 56
MIN_NECK_WIDTH=0.20 MM
SPKRAMP_S_OUT_P 2
0 1
MIN_NECK_WIDTH=0.20 MM
SPKRCONN_S_OUT_P OUT 6 57 82
B
5%
1/16W
MF-LF
402
MIN_LINE_WIDTH=0.30 mm R6631 MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM MIN_NECK_WIDTH=0.20 MM
SPKRAMP_S_OUT_N 2
0 1 SPKRCONN_S_OUT_N
82 56 OUT 6 57 82
PLACE C6630 CLOSE TO VDD PIN
5%
56 8 PP5V_S3_AUDIO_AMP 1/16W
MF-LF
402

CRITICAL
CRITICAL
C6632 1 1 C6633
100UF 0.1UF
20%
B1

B2

6.3V 2 10%
TANT
CASE-AL1 2 16V
X5R
CRITICAL VDD PVDD 402
L6630 C6630 U6630
FERR-1000-OHM CRITICAL 0.068UF SSM2315
53 AUD_LO1_P_R 1 2 AUD_SPKRAMP_INP_SUB 1 2 SSM2315S_P C1 IN- WLCSP OUT+ C3 SPKRAMP_S_OUT_P 56 82
IN
0402
10% SSM2315S_N A1 IN+ OUT_ A3 SPKRAMP_S_OUT_N 56 82

L6631 CRITICAL 10V

C6631 CERM C2 SD*
CRITICAL
FERR-1000-OHM CRITICAL 0.068UF 402
53 AUD_LO1_N_R 1 2 AUD_SPKRAMP_INN_SUB 1 2 GND
IN
0402
A2
B3

10%
10V
CERM
402 AUDIO:SPEAKER AMP
AUD_SPKRAMP_SHUTDOWN_L
A 56 SYNC_MASTER=K19_MLB

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=02/05/2009
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 56 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

AUDIO JACK 1 LO/HP JACK, SPDIF TX

D
AUD_SPDIF_OUT IN 53
MIC CONNECTOR D
L6703
FERR-1000-OHM CRITICAL CRITICAL
1 2 HS_MIC_HI OUT 58
J6780
78171-0003
0402 APN: 518S0520 M-RT-SM
L6702 4
82 72
61 58 57 53 FERR-1000-OHM CRITICAL
41 37 35 27
18 17 12 7 6 PP3V3_S0 1 2
26 23 22 21 20
49 47 46 45 43
HS_MIC_LO OUT 58 58 6 OUT BI_MIC_LO 1
71 69 68 67 66 0402 BI_MIC_SHIELD 2
APN: 514-0671 L6707
CRITICAL
58 6 OUT
BI_MIC_HI 3
FERR-220-OHM 58 6 OUT
1 2 AUD_HP_PORT_REF 53
J6700 CRITICAL 0402
BI 5
SPDIF-TXRX-K24 L6701
F-RT-TH FERR-220-OHM-2.5A
MIC 6 AUD_CONNJ1_SLEEVE2 1 2 GND_AUDIO_HP_AMP 53 55
OUT
DETECT 5 AUD_CONNJ1_SLEEVEDET 0603 CRITICAL
SWITCH 2 AUD_CONNJ1_TIPDET L6704
LEFT 1 AUD_CONNJ1_TIP FERR-220-OHM
RIGHT 3 AUD_CONNJ1_RING 1 2 AUD_HP_R 55
BI
GND 4 AUD_CONNJ1_SLEEVE 0402
AUDIO CRITICAL
7 L6706
A - VIN FERR-220-OHM
8
B - VCC 1 2 AUD_HP_L BI 55
9
C - GND 0402
OPERATING VOLTAGE 3.3 R6700
10K
C POF
10
1
5%
2 AUD_J1_SLEEVEDET_R OUT 58 C
1/16W
SHELL 11 MF-LF
12 CRITICAL 2
402
CRITICAL L6705
SHIELD
13
1 C6700 1 C6701 CRITICAL 2 DZ6704 DZ6700
2
PINS 0.1UF 2.2UF DZ6703 6.8V-100PF FERR-1000-OHM CRITICAL SPEAKER CONNECTOR
10% 20% 402 6.8V-100PF
2 16V
X5R 2 6.3V
CERM
6.8V-100PF 402 1 2 AUD_J1_TIPDET_R OUT 58
402 402-LF 402
1 CRITICAL 0402 CRITICAL
2
CRITICAL 2
1
1
DZ6706 DZ6701 J6781
78171-0002
6.8V-100PF
402
6.8V-100PF
402
1 C6705 APN: 518S0519 M-RT-SM
100PF 3
5%
1 1 2 50V
CERM
402 82 56 6 SPKRCONN_L_OUT_P 1
IN
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.10 MM GND_CHASSIS_AUDIO_JACK 8 57 82 56 6 IN SPKRCONN_L_OUT_N 2
VOLTAGE=0V
XW6701
SM 4
1 2
CRITICAL
GND PATCH XW6702
SM J6782
1 2
78171-0004
M-RT-SM
APN: 518S0521 5
R6701
0
82 72 71
57 8 GND_CHASSIS_AUDIO_JACK 1 2 82 56 6 IN SPKRCONN_S_OUT_P 1
49 47 46 45 43
20 18 17 12 7 6 PP3V3_S0 5% 82 56 6 IN SPKRCONN_S_OUT_N 2
41 37 35 27 26 23 22 21 1/16W
69 68 67 66 61 58 57 53 MF-LF 82 56 6 IN SPKRCONN_R_OUT_P 3
402
R6749 82 56 6 IN SPKRCONN_R_OUT_N 4
AUD_J2_OPT_OUT 4.7 NOSTUFF
B APN: 514-0635 1 2 AUD_SPDIF_IN OUT 53 NOSTUFF
CRITICAL CRITICAL B
5% 6
1/16W
MF-LF L6751 C6783 1 1 C6784
402 FERR-220-OHM CRITICAL 33PF 33PF
5% 5%
J6750 AUD_CONNJ2_SLEEVE 1 2 NOSTUFF 50V
NOSTUFF CERM 2 2 50V
CERM
AUDIO-RCVR-M97 CRITICAL CRITICAL 402 402
F-RT-TH5 0402
DETECT FOR PLUG TYPE 5 CRITICAL
C6781 1 1 C6782
33PF 33PF
SWITCH 2 AUD_CONNJ2_TIPDET L6754 5%
50V
5%
50V
LEFT 1 FERR-1000-OHM CERM 2 2 CERM
402 402
RIGHT 3 AUD_CONNJ2_RING 1 2 AUD_LI_R 54
BI
GROUND 4 0402
CRITICAL
AUDIO
L6756
6 FERR-1000-OHM
A - VDD
B - GND 7 AUD_CONNJ2_TIP 1 2 AUD_LI_L 54
BI
8 0402
C - VOUT
CRITICAL
OPERATING VOLTAGE 3.3 L6758
POF FERR-220-OHM
9 AUD_CONNJ2_SLEEVEDET 1 2 AUD_LI_GND 54

SHELL 10 0402
11 CRITICAL
SHIELD
PINS
12
1 C6750 CRITICAL
L6752
CRITICAL 2 FERR-1000-OHM
1UF 2 DZ6758
10%
2 10V
DZ6754 6.8V-100PF
1 2 AUD_J2_TIPDET_R OUT 58
X5R
402-1
6.8V-100PF
CRITICAL402
402 0402 AUDIO: JACKS
2
DZ6756
A 6.8V-100PF
402
1 2 CRITICAL
DZ6751
1
1 C6756
SYNC_MASTER=CASEYHARDY_K19

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=03/20/2009
A
6.8V-100PF 100PF
1 402 5% THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
50V
2 CERM PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
402 AGREES TO THE FOLLOWING
1
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
GND_CHASSIS_AUDIO_JACK 8 57
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

AUDIO JACK 2 LINE IN JACK, SPDIF RX SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 57 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
CODEC OUTPUT SIGNAL PATHS

FUNCTION VOLUME CONVERTER PIN COMPLEX MUTE CONTROL DET ASSIGNMENT PORT B LEFT(HEADSET MIC)
HP/LINE OUT 0X02 (2) 0X02 (2) 0X09 (9,A) N/A 0X09 (A) CRITICAL HP=80HZ, LP=8.82KHZ
SATELLITES 0X04 (4) 0X04 (4) 0X0B (11) GPIO_3 N/A MIKEY MIN_LINE_WIDTH=0.1MM
SUB 0X03 (3) 0X03 (03) 0X0A (10) GPIO_3 N/A L6880 MIN_NECK_WIDTH=0.1MM
SPDIF OUT N/A 0X08 (8) 0X10 (16) N/A 0X0C (B) FERR-1000-OHMVOLTAGE=3.3V
82 72 71 69 68 67 66 61 58 57
26 23 22 21 20 18 17 12 7 6 PP3V3_S0 1 2 PP3V3_S0_HS_RX
53 49 47 46 45 43 41 37 35 27
0402 DRC MIKEY
CODEC INPUT SIGNAL PATHS
CRITICAL APN:353S2256
D FUNCTION
LINE IN
CONVERTER
0X05 (5)
PIN COMPLEX
0X0C (12,C)
VREF
N/A
DET ASSIGNMENT
0X0C (12,C)
MIKEY 1
C6880 D

3
10UF MIKEY
SPDIF IN 0X07 (7) 0X0F (15) N/A N/A 6.3V 20% 2 AVDD
603 X5R
BUILT-IN MIC 0X06 (6) 0X0D (13,B,RIGHT) MIC_BIAS (80%) N/A U6880
CD3275
HEADSET MIC 0X06 (6) 0X0D (13,V22,B,LEFT) MIKEY MIKEY PULLUPS ON MCP PAGE
DRC
78 72 43 20 SMBUS_MCP_1_CLK 6 SCL MICBIAS 1 HS_MIC_BIAS
IN
MIKEY
78 72 43 20 SMBUS_MCP_1_DATA 5 SDA DETECT 2 HS_SW_DET CRITICAL
BI
1
20 OUT AUD_I2C_INT_L 7 INT* BYPASS 10 HS_RX_BP C6882
2.2UF
20%
18 8 IN AUD_IPHS_SWITCH_EN 8 ENABLE 2 6.3V
PORT A DETECT (HEADPHONES) PORT B DETECT(SPDIF DELEGATE) GND THM
TANT
402
MIKEY
R68801

4
9

11
AUD_SENSE_A MIKEY 1 GND_AUDIO_CODEC
100K
58 53 OUT
5%
1/16W
C6881 53 54 58

58 PP3V3_S0_AUDIO_F MF-LF 0.01UF MIKEY MIKEY

1 1 16V 10%
R6806 R6805 402 2 402 CERM 2
R6881 1 1
R6882
39.2K 20.0K
1 APN:376S0613 1% 1% 1K 2.2K
R6801 1/16W
MF-LF
1/16W
MF-LF
1%
1/16W
5%
1/16W
220K AUD_OUTJACK_INSERT_L 2 402 2 402 MIKEY MF-LF MF-LF
5%
AUD_PORTA_DET_L NC AUD_PORTB_DET_L NC CRITICAL 402 2 2 402
1/16W C6883 MIKEY
MF-LF
2 402 Q6800 D 3 0.1UF R6884
SSM6N15FEAPE Q6801 D 3 Q6801 D 6 53 OUT AUD_MIC_INP_L 1 2 HS_MIC_HI_RC 1 2.2K 2 HS_MIC_HI IN 57
SOT563
SSM6N15FEAPE SSM6N15FEAPE MIKEY MIKEY 5%
R6802 SOT563 SOT563 CRITICAL 10%
25V 1
1/16W
AUD_J1_TIPDET_R 1
47K 2 AUD_J1_DET_RC C6886 X5R R6883 1 MIKEYMF-LF 1 MIKEY
58 57 402
IN
5%
5 G S 4 0.1UF 402 100K
5%
C6884 C6885
1/16W 1 5 G S 4 2 G S 1 AUD_MIC_INN_L 1 2 1/16W 0.0082UF
MF-LF C6801 53 OUT
MF-LF 25V 10%
2 X7R 27PF
402 402 2 5% 50V
0.1UF 10% 2 402 CRITICAL CERM 402
C 2 20% 10V
CERM 402
25V
X5R
402 XW6880
SM
CRITICAL C
58 54 53 GND_AUDIO_CODEC
58 54 53 GND_AUDIO_CODEC 1 2 HS_MIC_LO IN 57
R6803
220K 2
58 PP3V3_S0_AUDIO_F 1 AUD_J1_SLEEVEDET_INV
1 5%
R6804 1/16W
MF-LF
220K 402 D 6
5%
1/16W
Q6800 58 57 AUD_J1_SLEEVEDET_R
MF-LF SSM6N15FEAPE
2 402
SOT563 PORT B RIGHT(BUILT-IN MIC)
58 57 IN AUD_J1_SLEEVEDET_R
R6850 R6851
1 C6802 2 G S 1 AUD_CODEC_MICBIAS 1
100 2 MIC_BIAS_FILT 1 2.4K 2
0.01UF 53 IN
10% 1% CRITICAL 1%
2 16V
CERM 1/16W
1
1/16W
58 54 53 GND_AUDIO_CODEC 402 MF-LF
402 C6852 MF
402-1
2.2UF
20%
2 6.3V
TANT
402
58 54 53 GND_AUDIO_CODEC
CRITICAL
C6850 L6850
0.1UF FERR-1000-OHM
53 AUD_MIC_INP_R 1 2 BI_MIC_HI_F 1 2 BI_MIC_HI 6 57
OUT IN
EXTRACT_BUFF 0402
R6865 CRITICAL 10%
1
100K 2 C6851 25V
X5R
1
R6852 CRITICAL
1 1 CRITICAL
0.1UF
EXTRACT_BUFF 5% AUD_MIC_INN_R 1 2
402 100K C6853 C6854
R6864 1/16W
53 OUT 5%
1/16W 0.001UF 27PF
PP3V3_S0_AUDIO_F 1 220K 2 AUD_J1_TIPDET_INV 402
MF-LF
10% MF-LF 50V 10%
402 CERM 2 2 5% 50V
CERM 402 L6851
58
2 402 FERR-1000-OHM
B 5%
1/16W
25V
X5R
402
R6853
2.4K 2 BI_MIC_LO_F 1 2 BI_MIC_LO IN 6 57
B
MF-LF EXTRACT_BUFF 58 54 53 GND_AUDIO_CODEC 1
0402
402
Q6803 EXTRACT_BUFF 1%
1/16W
SSM6N15FEAPE
EXTRACT_BUFF SOT563
D 6 Q6803 D 3 XW6851
SM
MF
402-1
SSM6N15FEAPE
R6860 SOT563 1 2 BI_MIC_SHIELD IN 6 57
15K
58 57 AUD_J1_TIPDET_R1 2 TIPDET_FILT
5%
HP=80HZ
1/16W 1 2 G S 1 5 G S 4
MF-LF
402 C6860
0.1UF
2 20% 10V
CERM 402
GND_AUDIO_CODEC EXTRACT_BUFF
58 54 53

PORT C DETECT (LINE-IN)

MIN_LINE_WIDTH=0.1MM
MIN_NECK_WIDTH=0.1MM EXTRACTION NOTIFICATION AUD_SENSE_A
58 53 OUT
58 PP3V3_S0_AUDIO_F APN:353S2401
VOLTAGE=3.3V
CRITICAL
L6862 R68131
FERR-1000-OHM 58 PP3V3_S0_AUDIO_F 10K
1%
71 69 68 67 66 61 58 57 53
PP3V3_S0 1 2 EXTRACT_DEBOUNCE 1/16W
26 23 22 21 20 18 17 12 7 6 IN MF-LF
49 47 46 45 43 41 37 35 27
0402 1 402 2
82 72
R6811
4 TPS3801E18DCK 270K AUD_INJACK_INSERT_L
NC
5%
VDD R6861 1/16W
MF-LF Q6802
U6860 100 2 402 SSM3K15FV
58 57 AUD_J1_TIPDET_R 5
MR*RST*
3 AUD_PERPH_DET_R
1 2 AUD_IP_PERIPHERAL_DET
OUT 16
SOD-VESM-HF
D 3 AUDIO: JACK TRANSLATORS
1 SC-70-1 5%
1/16W R6812
A C6861
0.1UF 1
GND
2
MF-LF
402
57 AUD_J2_TIPDET_R 1
47K 2 AUD_J2_DET_RC
APN:376S0612
SYNC_MASTER=K19_MLB

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=03/17/2009
A
10V 20% 2 IN
402 CERM 5% 1 G S 2
1/16W 1 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
GND_AUDIO_CODEC
MF-LF
402
C6811 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
58 54 53
0.1UF
2 20% 10V I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
CERM 402
PLACE L6800/C6800 CLOSE TO U6800 II NOT TO REPRODUCE OR COPY IT
58 54 53 GND_AUDIO_CODEC
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 58 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

MagSafe DC Power Jack

CRITICAL
CRITICAL
J6900 F6905
D 78048-0573
M-RT-SM 6 PP18V5_DCIN_FUSE
6AMP-24V
1 2
PPDCIN_S5 7 59 60
D
MIN_LINE_WIDTH=1mm
1 MIN_NECK_WIDTH=0.20mm
PWR VOLTAGE=18.5V 1206-2
2
1 C6905 PP3V42_G3H 6 7 20 21 24 38 40 41 42 43 45
48 59 60 67
PWR
0.01UF
GND 3 20% PLACEMENT_NOTE=Place
2 50V
near L6900 SMC_BC_ACOK_VCC 1 C6908
GND 4 CERM 0.1UF
603 20% PLACEMENT_NOTE=PLACE NEAR U6900 and U6901
SIG 5 1
R6929 2 10V
CERM

1
2.0K VCC TC7SZ08AFEAPE 402
5% SOT665
1/16W 5
MF-LF U6900 A
2 SMC_BC_ACOK IN 40 41 60
2 402 MAX9940 4

3
SC70-5 Y U6901
40 BI SYS_ONEWIRE 4 INT EXT 5 B
1

SC-75 CRITICAL 3
RCLAMP2402B
D6900 GND NC

2
CRITICAL

3
NO STUFF NC

PP3V42_G3H
BIL CONNECTOR
43 42 41 40 38 24 21 20 7 6
67 60 59 48 45
516S0523
C6951 1

1-Wire OverVoltage Protection 0.1UF

10%
25V
CRITICAL
J6955
X5R 2 CPB6312-0101F
6 ADAPTER_SENSE 402
F-ST-SM
14 13

The chassis ground will otherwise float and can 2 1

send transients onto ADAPTER_SENSE when AC is 4 3
C connected. R6961
100 NC
6 5
NC C
48 41 40 SMC_LID 2 1 6 SMC_LID_R 8 7
OUT 402 1/16W
81 60
SMBUS_SMC_BSA_SDA 10 9
5%
MF-LF
43 40 6
59
81
BI TO SMC
43 40 6 SMBUS_SMC_BSA_SCL 12 11 SMC_BIL_BUTTON_L 6 40 41
60 59 BI OUT

C6955 1 C6953 1
C6952 1
C6954 1
16 15
0.001UF 47PF 47PF 0.001UF
10% 5% 5% 10%
50V 50V 50V 50V
CERM 2 CERM 2 CERM 2 CERM 2
402 402 402 402

3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator
R6905 D6905
47 HN2D01JEAPE
60 59 7 PPDCIN_S5 1 2
SOT665
5%
1/8W
MF-LF PPDCIN_S5_P3V42G3H 1 5
805 MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm PPVIN_G3H_P3V42G3H
VOLTAGE=18.5V 3 4 MIN_LINE_WIDTH=0.3 mm P3V42G3H_BOOST
MIN_NECK_WIDTH=0.3 mm
VOLTAGE=18.5V
PPBUS_G3H

3
73 64 63 62 60 45 44 35 7 6
2 C6990 1
VIN BOOST
C6994 1
NC NC 10UF 0.22UF CRITICAL
10% 20%
25V 2
X5R U6990 6.3V 2
X5R L6995
805 LT3470A 402 33UH PP3V42_G3H
518-0358 8 SHDN*
DFN
SW 4 P3V42G3H_SW 1 2
6 7 20 21 24 38 40 41 42 43 45
48 59 60 67

B CRITICAL CRITICAL BIAS 2

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm CDPH4D19FHF-SM Vout = 3.425
B
J6950 BATTERY CONNECTOR NC 7 NC SWITCH_NODE=TRUE DIDT=TRUE
250mA max output
BAT-K19 FB 1 <Ra>
1 (Switcher limit)
M-RT-TH THRM R6995
1
PPVBAT_G3H_CONN GND PAD C6995 1 348K
P1 6 60
22pF

9
2 5% 1%
P2 50V 1/16W
3 CERM 2 MF-LF
P3 402 2 402 1 C6999
4 SMBUS_SMC_BSA_SCL
P4 6 40 43 59 60 81
P3V42G3H_FB 22UF
5 6 SYS_DETECT_L 20%
P5 <Rb> 2 6.3V
6 SMBUS_SMC_BSA_SDA X5R-CERM
P6 6
1 603
7
CRITICAL 40 43 59 60 81
R6996
P7
8
D6950 C6950
200K
R6950 1
1
1%
1

P8 RCLAMP2402B 1/16W
9 SC-75 10K 0.1UF MF-LF
P9 10%
5%
1/16W
25V
2 2 402
10 X5R
SHLD_PIN MF-LF 402
402 2
SHLD_PIN 11
3

SHLD_PIN 12 8 6 GND_BATT_CHGND
13
Vout = 1.25V * (1 + Ra / Rb)
SHLD_PIN

DC-In & Battery Connectors

A SYNC_MASTER=K19_MLB

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=03/18/2009
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 59 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
FROM ADAPTER
59 7 PPDCIN_S5 Inrush Limiter Reverse-Current Protection
PPDCIN_S5_CHGR_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
2 1 VOLTAGE=18.5V
D7005 R7060 C7060 1 R70651
1SS418 470K 0.1UF 100K
5% 10%
3 2 1 5%
SOD-723-HF 1/16W 25V 2
1 2 3 1/16W PP3V42_G3H 6 7 20 21 24 38 40 41 42 43 45
1 MF-LF X5R CRITICAL CRITICAL MF-LF 48 59 60 67

2 402 402 402 2

CHGR_AGATE_DIV S
Q7060 Q7065 S
G 4
CHGR_SGATE_DIV
MIN_LINE_WIDTH=0.3 mm
MIN_LINE_WIDTH=0.3 mm 4
G HAT1128R01 MIN_NECK_WIDTH=0.3 mm
C7070 R70701 1
R7074
D 1
MIN_NECK_WIDTH=0.3 mm
R7061
SOI HAT1128R01 D
R70661
1
0.1uF
10%
57.6K
1%
1M
5%
D
SOI 1/16W 1/16W
330K D 62K 2 16V
X5R MF-LF MF-LF
5% 5% 402 402 2 2 402
1/16W
MF-LF 5 6 7 8
8 6 7 5 1/16W
MF-LF U7070 5
1
2 402 402 2 TL331 CHGR_AMON 45 60
SOT23-5 VCC
4 R7075 clamps CHGR_AMON when charger is
PPDCIN_S5_INRUSH CHGR_SGATE
MIN_LINE_WIDTH=0.6 mm MIN_LINE_WIDTH=0.3 mm not powered to counter TL331 bias current.
MIN_NECK_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm GND 3 D
VOLTAGE=18.5V 3 SGATE_P0V1_VREF Q7074
2 SSM6N15FEAPE
SOT563 6 D
R7071 1 Q7074
1.82K SSM6N15FEAPE
1% SOT563
1/16W 4 S G 5
MF-LF
402 2 AMON_CLAMP
1 S G 2

PP5V1_CHGR_VDD 60

TO SYSTEM
NOSTUFF
(CHGR_AGATE)
D7040 PPBUS_G3H 6 7 35 44 45 59 62 63 64 73

(CHGR_DCIN) 1 2
R7021 1SS418
1
10 2
SOD-723-HF
CRITICAL
5%
CHGR_CSI_R_P 3 1 1 CRITICAL
1 C7020 1/16W
MF-LF
82
R7020 F7040
0.047UF 402 0.02
10%
0.5% 8AMP-24V
1W 1206-2
2 10V CHGR_CSI_R_N MF
C 43 42 41 40 38 24 21 20 7 6
67 60 59 48 45
PP3V42_G3H R7001
4.7
CERM
402
R7022
1
10 2
82
4 2 0612-1
2
C
60 PP5V1_CHGR_VDD 1 2 PP5V1_CHGR_VDDP
MIN_LINE_WIDTH=0.2 mm MIN_LINE_WIDTH=0.2 mm 5% PPDCIN_S5_FET_CHGR
MIN_NECK_WIDTH=0.2 mm 5% MIN_NECK_WIDTH=0.2 mm 1/16W MIN_LINE_WIDTH=0.6 mm
VOLTAGE=5.1V 1/16W VOLTAGE=5.1V MF-LF MIN_NECK_WIDTH=0.4 mm CRITICAL CRITICAL
ACIN pin threshold C7002 1 MF-LF
C7001 1 402 VOLTAGE=18.5V 1 1
is 3.2V, +/- 50mV 1UF 30mA max load 402 C7030 C7031
10%
10V 2
1UF C7022 1 1 C7021 22UF 22UF
10% 20% 20%
Divider sets ACIN X5R 10V 2 0.1UF 0.1UF 25V
2 POLY-TANT 25V
2 POLY-TANT
402-1 X5R 10% 10%
threshold at 13.07V 402-1 25V 2 2 25V CASE-D2-SM CASE-D2-SM
19

20
X5R X5R
402 402
Input impedance of ~40K meets 5
VDD VDDP
sparkitecture requirements 12 VHST CRITICAL AGATE 1 CHGR_AGATE CRITICAL
1
R7010 81 59 43 40 6 IN SMBUS_SMC_BSA_SCL 11 SCL U7000
CSIP 28 81 CHGR_CSI_P Q7030 1 C7032 1 C7033 1 C7034
30.1K QFN 1UF 1UF 0.001UF
1% SMBUS_SMC_BSA_SDA 10 SDA CSIN 27 CHGR_CSI_N 4 RJK0305DPB
ISL6258A

81 59 43 40 6 81
BI 10% 10% 10%
1/16W
MF-LF LFPAK-HF 2 25V 2 25V 2 50V
402 2
VREF = 3.2V, < 300uA 4 VREF BGATE 16 CHGR_BGATE 1 C7035 X5R
603-1
X5R
603-1
X7R
402
NC DCIN 2 CHGR_DCIN 0.1UF CRITICAL
CHGR_ACIN 3 ACIN 10%
2 25V
X5R L7030
BOOT 25 CHGR_BOOT 402 3
1 2 3 4.7UH-10.2A
R70111 CHGR_ICOMP 5 ICOMP UGATE 24 CHGR_UGATE
DIDT=TRUE
2
9.31K CHGR_VCOMP 7 VCOMP OMIT PHASE 23 CHGR_PHASE PPVBAT_G3H_CHGR_REG
1% MIN_LINE_WIDTH=0.6 mm FDA1254F-SM MIN_LINE_WIDTH=0.6 mm
1/16W CHGR_VNEG 8 VNEG MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.4 mm
MF-LF 1 LGATE 21 CHGR_LGATE SWITCH_NODE=TRUE VOLTAGE=12.6V CRITICAL
402 2 R7015 81 CHGR_CSO_P 18 CSOP DIDT=TRUE 5
56.2K 81 CHGR_CSO_N 17 CSON
(OD) TRKL* 13 TP_CHGR_TRKL 1 C7040 1 1 C7041
1% 20V/V AMON 9 CHGR_AMON OUT 45 60 CRITICAL 22UF 0.001UF
1/16W 20% 10%
THRM_PAD

MF-LF 32V/V BMON 15 CHGR_BMON Q7035 25V

POLY-TANT 2 2 50V
2 402
1 C7050 (OD) ACOK 14 SMC_BC_ACOK
OUT 45

4
CRITICAL CASE-D2-SM
X7R
402 CRITICAL
0.1uF OUT 40 41 59 RJK0305DPB R7050 Q7055
6 AGND

22 PGND

10% DIDT=TRUE
CHGR_VCOMP_R LFPAK-HF
0.01
2 16V
X5R 0.5% SI7137DP
402 SO-8
B C7015 1
1W
B
29

26

152S0542 MF
0612-1
0.001UF

S
10%
2 1 PPVBAT_G3H_CHGR_R

3
50V 1 2 3 MIN_LINE_WIDTH=0.6 mm

D
4 3 PPVBAT_G3H_CONN 6
CERM 2 MIN_NECK_WIDTH=0.4 mm 59

2
VOLTAGE=12.6V MIN_LINE_WIDTH=0.6 mm

5
402 C7057 1 MIN_NECK_WIDTH=0.4 mm

1
0.01uF VOLTAGE=12.6V
XW7000

G
10%
SM C7055 1 16V
CERM 2
R70161 Max Current = 8.5A

4
1 2 1UF 402
3.01K (L7030 limit) 10%
1% 25V 2
1/16W
MF-LF
f = 400 kHz X5R
603-1
1 C7056
0.1UF
402 2 R7051 10%
10 2 16V
X5R
CHGR_VNEG_R 1 2 82 45 CHGR_CSO_R_P 402
5% R7052
1/16W
1 C7016 MF-LF
402 1
10 2 82
45 CHGR_CSO_R_N
470PF (CHGR_CSO_P)
10% 5%
50V
2 CERM (CHGR_CSO_N) 1/16W
402 MF-LF
402
(PPVBAT_G3H_CHGR_R)

1 C7042 C7000 1 1 C7011 C7005 1 1 C7026

0.033UF 1UF 0.01UF 0.1UF 0.001UF
10% 10% 10% 10% 10%
2 16V
X5R
10V
X5R 2 2 16V
CERM
25V 2
X5R
50V
2 CERM
402 402-1 402 402 402
GND_CHGR_AGND
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm PBus Supply & Battery Charger
VOLTAGE=0V

A SYNC_MASTER=K19_MLB

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=03/18/2009
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION SIZE DRAWING NUMBER REV.

353S1811 1 IC,ISL6258,BAT CHARGER,28P,4X4,QFN,L U7000 CRITICAL ISL6258 2S Battery Default D 051-7903 A

353S1832 1 IC,ISL6258A,BAT CHARGER,4X4MM,QFN28 U7000 CRITICAL ISL6258A 3S Battery Default APPLE INC. SCALE SHT OF
NONE 60 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
65 45 7 PPBUS_CPU_IMVP_ISNS These caps are for Q7100 These caps are for Q7102

R7120 CRITICAL CRITICAL CRITICAL

1
10 2 PPVIN_S5_IMVP6_VIN C7108 1 1
C7117 1 C7109 1
C7155 C7152 1 1
C7153 1 C7154
MIN_LINE_WIDTH=0.25 MM 0.001UF 68UF 1UF 68UF 0.001UF 68UF 1UF
1% MIN_NECK_WIDTH=0.2 MM 10% 20% 10% 20% 10% 20% 10%
1/16W
MF-LF
VOLTAGE=12.6V C7196 1 50V 2
X7R 2 16V
POLY-TANT
2 25V
X5R 2 16V
POLY-TANT
50V 2
X7R 2 16V
POLY-TANT
2 25V
X5R
402 0.1UF 402 CASE-D2E-SM 603-1 CRITICAL CASE-D2E-SM 402 CASE-D2E-SM 603-1
10%
16V 2
X5R
402
Q7100
49 47 42 37 7 6 PP5V_S0 IRF6710
72 70 68 67 65 64 S1
1
R7112 DPRSLPVR DPRSTP* PSI* Operation Mode D
10 2
1 2 PP5V_S0_IMVP6_VDD
D 1%
1/16W
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V C7126 1
0 1 1 2-Phase CCM
4 G
5
6
D
MF-LF 1UF 0 1 0 1-Phase CCM DIDT=TRUE CRITICAL PPVCORE_S0_CPU 6 7 10 11 44
402 S
10%
10V 2 1 0 1 1-Phase DCM
3 L7100 44A MAX CURRENT
R7121 X5R
402-1
0.36UH-26A-1.05MOHM
82 72 71 69 68
47 46 45 43 41 37
PP3V3_S0 10 PP3V3_S0_IMVP6_3V3 1 2
20 18 17 12 7 6 1 2 1 0 0 1-Phase DCM (IMVP6_PHASE1)
35 27 26 23 22 21
67 66 58 57 53 49
MIN_LINE_WIDTH=0.25 MM DIDT=TRUE
MPCG1040-SM
1% MIN_NECK_WIDTH=0.2 MM
1/16W VOLTAGE=3.3V
MF-LF
402 1 C7135 XW7103
SM
XW7104
SM
C7156 1
67 66 65 35
PP1V05_S0 1 2 6 7 0.001UF
13 12 11 10 9 7 6
23 22 21 19 17 16 4.7UF 1 2 2 1 10%
1 C7130 1 1
R7197 20%
2 6.3V D CRITICAL 50V 2
X7R
R7199 0.1uF
10% 10K X5R-CERM
402 Q7101 61 IMVP6_VSUM1 61 IMVP6_VO1 402
68 16V 2 5%
5% X5R 1/16W 5 G IRF6795
1/16W 402 MF-LF DIRECTFET-MX 1
R7119
MF-LF
2 402
2 402 DIDT=TRUE S R7104
1
PM_DPRSLPVR 1
499 2 3 4 5%
75 20 IN 20 22 31 1/16W
MF-LF
1% VIN VDD PVCC 2 402
1/16W R7198 C7103
MF-LF
402 0 IMVP6_VID<6> 43 VID6 BOOT1
36 61 IMVP6_BOOT1 C7127 1 1 C7115 R7100 0.22UF
75 41 13 9 OUT CPU_PROCHOT_L 1 2
75 8 IN 0.22UF 0.22UF 10K
IMVP6_VID<5> 42 VID5 26 IMVP6_BOOT2 20% 20% 1 2 1 2
5%
1/16W
75 8

75 8
IN
IMVP6_VID<4> 41 VID4
U7100 BOOT2 61
25V 2
X5R 2 25V
X5R 1%
MF-LF IN QFN 603 603 1/16W 10%
IMVP6_VID<3> 40 UGATE1 35 IMVP6_UGATE1 10V

ISL9504BCRZ
LAYOUT NOTE: 402 75 8 IN VID3 61 MF-LF CERM
39 402 402
Place R7126 in hot (IMVP6_NTC) 75 8 IN IMVP6_VID<2> VID2
38 PHASE1 34 61 IMVP6_PHASE1 1
R7101
spot of reg circuit. 75 8 IN IMVP6_VID<1> VID1
37 3.65K
1 75 8 IN IMVP6_VID<0> VID0 LGATE1 32 61 IMVP6_LGATE1 1%
CRITICAL 1/10W
MF-LF
R7126 46 PGND1 33 (GND) 2 603
CPU_DPRSTP_L DPRSTP*
470K C7110 1 75 13 9 IN
75 IMVP_DPRSLPVR 45 DPRSLPVR ISEN1 24 61 IMVP6_ISEN1 (IMVP6_ISEN1)
0.01uF
402 10% 9 CPU_PSI_L 2 PSI*
16V IN
C 2 CERM 2
402 45 OUT IMVP6_IMON 3 IMON (PGD_IN)
(ISL9504A)
UGATE2
27 61 IMVP6_UGATE2 C
IMVP6_NTC_R 48 PHASE2 28 61 IMVP6_PHASE2
3V3
8 TP_IMVP6_CLKEN_L 47 CLK_EN* LGATE2 30 61 IMVP6_LGATE2
OUT
R71271 61 IN IMVP_VR_ON_R 44 VR_ON
4.02K 1 PGND2 29 (GND)
1% 24 OUT VR_PWRGOOD_DELAY PGOOD CRITICAL
1/16W 5
MF-LF IMVP6_VR_TT_L VR_TT* 23 Q7102
1 402 2 6 ISEN2 61 IMVP6_ISEN2 IRF6710
R7108 IMVP6_NTC NTC
C7105 1 147K (GND_IMVP6_SGND)
S1
1
0.015UF 1% VSUM
19 IMVP6_VSUM D
10% 1/16W 61 IMVP6_SOFT 7 SOFT 2
16V 2 MF-LF OCSET
8 61 IMVP6_OCSET
X7R 5
402 2 402 61 IMVP6_RBIAS 4 RBIAS VO 18 IMVP6_VO 61
OUT 4 6
16 IMVP6_DROOP NO STUFF G
(GND_IMVP6_SGND) DROOP CRITICAL
IMVP6_VDIFF 13 VDIFF
OUT 61
C7116 1 DIDT=TRUE
3 S
L7101
61
R7117 0.001uF 0.36UH-26A-1.05MOHM
DFB 17 61 IMVP6_DFB 4.12K2 10%
50V
1
1 C7106 1 IMVP6_FB2 12 CERM 2 1 2
0.001UF
R7113 61
11
FB2
1% 402 (IMVP6_PHASE2)
10% 1K 61 IMVP6_FB FB VSEN 14 1/16W DIDT=TRUE MPCG1040-SM
1% MF-LF
2 50V
CERM 1/16W
MF-LF
61 IMVP6_COMP 10 COMP RTN
15 402 XW7101
SM
XW7102
SM C7157 1
402 402 2 61 IMVP6_VW 9 VW C7131 1 1
R7118 1 C7129
1
R7116 1 2 6 7
1 2 2 1 0.001UF
IMVP6_VDIFF_RC 0.01UF 1K 13.3K CRITICAL 10%
10% 1% 180pF 1% D 50V 2
25 NC 16V 5% IMVP6_VSUM2 IMVP6_VO2 X7R
1 1
CERM 2
402
1/16W
MF-LF 2 50V
CERM
1/16W
MF-LF Q7103 61 61
402
R7111 R7109 GND TPAD 2 402 402 2 402 5 G IRF6795
DIRECTFET-MX 1
255 1K DIDT=TRUE S R7107
1% 1% 21 49 (IMVP6_VO)
1/16W 1/16W 1
MF-LF MF-LF 3 4 5%
402 2 2 402
GND_IMVP6_SGND 1 1 1/16W
MIN_LINE_WIDTH=0.50 MM
MIN_NECK_WIDTH=0.20 MM 1 C7134 R7115 R7130 MF-LF
2 402
(IMVP6_FB) VOLTAGE=0V 0.068UF 11K 2.61K C7104
1% 1% R7105
B 1 C7114 C7113 1
10%
10V
2 CERM
402
1/16W
MF-LF
2 402
1/16W
MF-LF
402 2 1
10K 2
0.22UF
1 2 B
470PF 220PF 1%
10% 10% IMVP6_VO_R 1/16W 10%
2 50V
CERM
50V
X7R-CERM 2 MF-LF 10V
CERM
402 402 402 402
1 1
IMVP6_COMP_RC (IMVP6_VW) CRITICAL R7106
3.65K
R7131 1%
1/10W
R71141 C7107 1
1
R7110 C7128 1 10KOHM-5% MF-LF
97.6K 6.81K 0.22UF 2 603
1% 0.001UF 1% 10% 0603-LF
1/16W 10% 1/16W 6.3V
MF-LF 50V CERM-X5R 2 2 (IMVP6_ISEN2)
402 2 CERM 2 MF-LF 402
402 2 402
(IMVP6_VSUM)
(IMVP6_COMP)
Place R7131 Between L7100,L7101 and CPU
(IMVP6_VO)

R7122
0
75 61 IMVP6_VSEN_P 1 2 CPU_VCCSENSE_P IN 10 75

5%
1/16W
MF-LF R7123
402 0
75 61 IMVP6_VSEN_N 1 2 CPU_VCCSENSE_N IN 10 75

NO STUFF 5%
1/16W
C7121 1 C7133 1 1 C7132 MF-LF
402
0.22UF 0.01uF 0.01uF
R7160 20% 10% 10%
40 IMVP_VR_ON 1
0 2 IMVP_VR_ON_R 61
XW7100
SM
6.3V 2
X5R
16V
CERM 2 2 16V
CERM
402 402 402
5%
1/16W
1 2 IMVP6 CPU VCore Regulator
MF-LF
402
A 61 IMVP6_OCSET MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM
SYNC_MASTER=K19_MLB

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=02/05/2009
A
61 IMVP6_VO MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
61 IMVP6_DROOP MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
61 IMVP6_DFB MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
61 IMVP6_SOFT MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM 61 IMVP6_PHASE1 MIN_LINE_WIDTH=1.5 MM MIN_NECK_WIDTH=0.2 MM 61 IMVP6_PHASE2 MIN_LINE_WIDTH=1.5 MM MIN_NECK_WIDTH=0.2 MM
II NOT TO REPRODUCE OR COPY IT
61 IMVP6_RBIAS MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM 61 IMVP6_BOOT1 MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM 61 IMVP6_BOOT2 MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
61 IMVP6_VDIFF MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM 61 IMVP6_UGATE1 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM 61 IMVP6_UGATE2 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM
61 IMVP6_FB2 MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM 61 IMVP6_LGATE1 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM 61 IMVP6_LGATE2 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM SIZE DRAWING NUMBER REV.
IMVP6_FB IMVP6_ISEN1 IMVP6_ISEN2
61

61 IMVP6_COMP
MIN_LINE_WIDTH=0.25
MIN_LINE_WIDTH=0.25
MM
MM
MIN_NECK_WIDTH=0.20
MIN_NECK_WIDTH=0.20
MM
MM
61

61 IMVP6_VSUM1
MIN_LINE_WIDTH=0.25 MM
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.25 MM
61

61 IMVP6_VSUM2
MIN_LINE_WIDTH=0.25 MM
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.25 MM
D 051-7903 A
61 IMVP6_VW MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM 61 IMVP6_VO1 MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM 61 IMVP6_VO2 MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM APPLE INC. SCALE SHT OF
75 61 IMVP6_VSEN_P MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM I849 75 61 IMVP6_VSEN_N MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM I848
NONE 61 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

73 64 63 60 59 45 44 35 7 6 PPBUS_G3H

CRITICAL CRITICAL
1
C7240 1 C7241 1 C7243 P5VP3V3_VREG5 1
C7280 1 C7281 1 C7282
68UF 1UF 0.001UF 68UF 1UF 0.001UF
20% 10% 10% P5VP3V3_VREG3 20% 10% 10%
2 16V
POLY-TANT
2 25V
X5R 2 50V
CERM 2 16V
POLY-TANT
2 25V
X5R 2 50V
CERM
CASE-D2E-SM 603-1 402 CASE-D2E-SM 603-1 402
C7203 1 1 C7205
10UF 10UF
P5VP3V3_VREF 20% 20%
6.3V 2 2 6.3V
X5R X5R
603 603
P5VS5_VBST_R C7201 1
5 0.22UF P3V3S5_VBST_R
C7200 1 10%
10V
C7224 1 1UF CERM 2
CRITICAL R72242

16
10% 402 2 1 C7264

3
D
0.1UF 0 25V 2 R7264
53 51 49 41 39 38 37 29 8 7 6 PP5V_S3 Q7220 10%
50V 2 5% X5R
603-1
VIN
14 SKIPSEL
VREF
0 0.1UF 9 4 3 2 PP3V3_S5 6 7 17 19 21 22 24 28 32 35 36
68 63
STL11NH3LL G 4
X7R 1/16W VREG3 8 5% 10% 42 52 66 67 68 69 71 82
MF-LF 1/16W 2 50V
Vout = 5.0V PWRFLAT-SM 603-1 X7R Vout = 3.3V C
C 13A max output
402 1 4 TONSEL
U7201
VREG5 17
MF-LF
1 402
603-1
1 CRITICAL
5.5A max output
CRITICAL S
P5VS5_VBST 22 VBST1 QFN VBST2 9 P3V3S5_VBST Q7260 CRITICAL
(Q7220 limit) L7220 MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm TPS51125
21 DRVH1
MIN_LINE_WIDTH=0.6
MIN_NECK_WIDTH=0.2
mm
mm FDMS9600S L7260 (L7260 limit)
4.7UH-13A-15MOHM 3 2 1 P5VS5_DRVH DRVH2 10 P3V3S5_DRVH MLP 4.7UH-5.5A
MIN_LINE_WIDTH=0.6 mm GATE_NODE=TRUE DIDT=TRUE GATE_NODE=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.6 mm
f=365KHz 1 2 MIN_NECK_WIDTH=0.2 mm
P5VS5_LL 20 LL1 LL2 11 P3V3S5_LL MIN_NECK_WIDTH=0.2 mm Q1
10 1 2 f=460KHz
PCMB104E4R7-SM MIN_LINE_WIDTH=0.6 mm SWITCH_NODE=TRUE DIDT=TRUE SWITCH_NODE=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.6 mm SW IHLP2525CZ
CRITICAL MIN_NECK_WIDTH=0.2 mm 19 DRVL1 MIN_NECK_WIDTH=0.2 mm NO STUFF CRITICAL
NO STUFF NO STUFF P5VS5_DRVL DRVL2 12 P3V3S5_DRVL 8
C7250 1 5 MIN_LINE_WIDTH=0.6 mm GATE_NODE=TRUE DIDT=TRUE GATE_NODE=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.6 mm R7262 1 1 C7290 1
C7292
C7252 1 10UF R72221 MIN_NECK_WIDTH=0.2 mm
(P5VS5_VO1) 24 VO1 VO2 7 (P3V3S5_V02)
MIN_NECK_WIDTH=0.2 mm
10 10UF 150UF-.025-OHM
150UF 20%
10V 2 10 CRITICAL 5% 20% 20%
20% X5R 5% D 2 VFB1 1/16W 2 6.3V 2 6.3V
6.3V
POLY-TANT 2 805 1/16W Q7225 P5VS5_VFB VFB2 5 P3V3S5_VFB Q2 MF-LF X5R
603
TANT
CASE-B2-SM
CASE-B2-SM MF-LF G 4 402 2
402 2 STL15N3LLH5 1 ENTRIP1
P5VS5_ENTRIP ENTRIP2 6 P3V3S5_ENTRIP
CRITICAL 1 C7251 P5VS5_RC
P3V3S5_RC C7291 1
1
C7253 VCLK 18 NO STUFF 0.001UF
0.001UF NO STUFF S 7 6 5 10%
150UF
20%
10%
2 50V C7222 1 PGOOD 23
1 C7262 50V
CERM 2
2 6.3V CERM PWRFLAT-SM 100PF 402
POLY-TANT 402 100PF 3 2 1 5%
CASE-B2-SM 5%
50V EN0 13 P5V3V3_EN0 NO STUFF 2 50V
CERM
2 CERM 2
402
R72001 GND THRM_PAD C7208 1
1
R7206 402 2
XW7220 86.6K 220PF 75K

15

25
SM 1%
1/16W 5%
25V
1%
1/16W XW7260
SM
MF-LF CERM 2 MF-LF
1 402 2 402 2 402 1
PLACEMENT_NOTE=Place XW7220 next to L7220. PLACEMENT_NOTE=Place XW7200 next to U7200 pin 15. PLACEMENT_NOTE=Place XW7260 next to L7260.
P5VS5_REG_XW GND_P5VP3V3_SGND
MIN_LINE_WIDTH=0.6 mm P3V3S5_REG_XW
MIN_NECK_WIDTH=0.2 mm
1 VOLTAGE=0V XW7200
R7220 SM R72732 R72601
15K 1 2 100K
5% 5% 6.49K
1/16W 1/16W 1%
MF-LF MF-LF 1/16W
2 402 402 1 MF-LF
402 2
B B
1
R7221 R72611
10K
1% 10K
1/16W 1%
MF-LF 1/16W
2 402 MF-LF
402 2

One master PGOOD for both 5V and 3V3

67 66 65 64 40 24 OUT ALL_SYS_PWRGD

Q7210 D 6 Q7210 D 3
SSM6N15FEAPE SSM6N15FEAPE
SOT563 SOT563

2 G S 1 5 G S 4
67 IN PM_SLP_S3_L_INVERT 67 IN PM_G2_P3V3S5_EN_L

67 40 8 6 IN SMC_PM_G2_EN

TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

PART NUMBER
TABLE_ALT_ITEM
5V / 3.3V Power Supply
152S0778 152S0693 ALL Cyntec alternate to MagLayers

A SYNC_MASTER=WFERRY_K19I

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=01/13/2009
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 62 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

68 63 28 27 26 7 6 PP1V5_S3

73 64
PPBUS_G3H
1 C7355 44 35 7 6
62 60 59 45

10UF
20% CRITICAL CRITICAL
2 6.3V
X5R
603 C7330 1 C7331 1 1 C7332 1 C7333
22UF 22UF 1UF 0.001UF
20% 20% 10% 10%
53 51 49 41 39 38 37 29 8 7 6 PP5V_S3 R7305 25V
POLY-TANT 2
25V
POLY-TANT 2 2 25V
X5R 2 50V
X7R
68 62
1
4.7 2 PP5V_S3_DDRREG_V5FILT CASE-D2-SM CASE-D2-SM 603-1 402
MIN_LINE_WIDTH=0.6 mm
5% MIN_NECK_WIDTH=0.17 mm
1/16W VOLTAGE=5V
MF-LF
402
ISNS_1V5_S3_P OUT 51 82

CRITICAL
C7300 1 C7305 1
DDRREG_VDDQSNS
D
Q7330 ISNS_1V5_S3_N

15

14

23
4.7UF 1UF OUT 51 82
20% 10% (DDRREG_DRVH) SI7110DN
6.3V 2 10V 2 DIDT=TRUE G
CERM X5R V5IN V5FILT VLDOIN PWRPK-1212-8-HF
R73101 MIN_LINE_WIDTH=0.6 mm XW7331 XW7332

2
603 402-1 MIN_NECK_WIDTH=0.17 mm
10K S
SM SM
C 6 COMP
CRITICAL
VDDQSNS 8 1%
1/16W
MF-LF
CRITICAL
L7330 VOLTAGE=1.5V
C
MODE 4 402 2 C7325 MIN_NECK_WIDTH=0.1 MM

1
68 24 8 IN MEM_VTT_EN 10 S3 VTT Enable
0.1UF 1.0UH-13A-5.6MOHM MIN_LINE_WIDTH=0.8 MM XW7330
SM
67 IN DDRREG_EN 11 S5 VDDQ/VTTREF Enable 1 2 1 2
PPDDR_S3_REG_R PP1V5_S3
VBST 22 DDRREG_VBST (DDRREG_VBST) 1 2 6 7 26 27 28 63 68
67 OUT TP_DDRREG_PGOOD 13 PGOOD VDDQ PGOOD U7300 MIN_LINE_WIDTH=0.6 mm PCMB065T-SM
MIN_NECK_WIDTH=0.17 mm 10% CRITICAL Vout = 1.5V
25 7 PPVTTDDR_S3 TPS51116 DRVH 21 DDRREG_DRVH 50V 1
C7340 15A max output
10mA max load QFN GATE_NODE=TRUE X7R
5 VTTREF 603-1 CRITICAL 270UF (Q7335 limit)
68 27 26 7 6 PP0V75_S0_DDRVTT SYM (2 OF 2) 20%
MIN_LINE_WIDTH=2 mm Vout = VDDQSNS/2 LL 20 DDRREG_LL (DDRREG_LL) D 2 2V f = 400 kHz
MIN_NECK_WIDTH=0.17 mm 24 VTT SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
DIDT=TRUE Q7335 TANT
CASE-B4-SM
Vout = VTTREF SI7108DN
PLACEMENT_NOTE=Place next to C7360
XW7360
SM
DRVL 19 DDRREG_DRVL
GATE_NODE=TRUE
(DDRREG_DRVL)
MIN_LINE_WIDTH=0.6 mm
G
PWRPK-1212-8-HF CRITICAL
1 2 DDRREG_VTTSNS 2 VTTSNS
MIN_NECK_WIDTH=0.17 mm
DIDT=TRUE S C7341 1 1 C7345 1 C7346 2
CS 16 DDRREG_CS 270UF 10UF
20% 0.001UF
CRITICAL CRITICAL NC 7 NC0
20%
2V 2 2 6.3V
X5R
10%
50V
XW7345
SM
TANT 2 X7R
C7360 1 1 C7361 NC 12 NC1 VDDQSET 9 DDRREG_FB CASE-B4-SM 603
402 1
PLACEMENT_NOTE=Place next to C7345
22UF 22UF
20% 20% VTTGND THRM_PAD GND PGND CS_GND
6.3V 2 6.3V
X5R-CERM 2 X5R-CERM 1 XW7335

25

18

17
603 603 PLACEMENT_NOTE=Place next to Q7335
SM
DDRREG_CSGND (DDRREG_CSGND) 1 2 NO STUFF 1
MIN_LINE_WIDTH=0.1 mm
MIN_NECK_WIDTH=0.1 mm C7320 1 R7320
100PF 15.0K
5% 1%
50V 1/16W
(DDRREG_VDDQSNS) CERM 2 MF-LF
MIN_LINE_WIDTH=0.2 mm 402 2 402
MIN_NECK_WIDTH=0.17 mm
C7350 1 2
(DDRREG_FB)
<Ra>
0.033UF XW7300
10%
16V 2
SM Vout = 0.75V * (1 + Ra / Rb) 1
X5R
402 1 R7321
15.0K
1%
B 1/16W
MF-LF
2 402
B
GND_DDRREG_SGND <Rb>
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=0V

1.5V DDR3 Supply

SYNC_MASTER=K19_MLB SYNC_DATE=02/04/2009
A NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 63 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

73 63 62 60 59 45 44 35 7 6 PPBUS_G3H
R7560
D 5V_S0_MCPREG_VIN 1
2.2 2 PP5V_S0 1
CRITICAL
C7540
CRITICAL D
VOLTAGE=5V
MIN_LINE_WIDTH=0.6 mm 5%
6 7 37 42 47 49 61 65 67 68
70 72
68UF C7563 1 1
C7560 1 C7561
MIN_NECK_WIDTH=0.2 MM 1/10W 20% 0.001UF 68UF 1UF
MF-LF 2 16V 10% 20% 10%
603 POLY-TANT 50V 2 2 25V
R7593 CASE-D2E-SM X7R 2 16V
POLY-TANT X5R
MCPCORES0_IMON 1
0 2 C7550 1 1 C7562 5
402 CASE-D2E-SM 603-1
45
1UF 1UF
5% 10% 10%
16V 2 2 16V

16

22
1/16W
1 X5R X5R D
CRITICAL
MF-LF
402 R7561 402 402
Q7560
1K VDD PVCC 4 G
5% (MCPCORES0_UGATE) FDMC8676
R7590 1/16W
MF-LF
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM POWER33-SM
0 2 402
20 IN MCP_VID<0> 1 2
MCPCORES0_RBIAS 1 RBIAS
U7500 VIN 14
GATE_NODE=TRUE
DIDT=TRUE
S
5%
1/16W
QFN
R7565 C7564 CRITICAL
R7591 0.22UF

ISL6263D
MF-LF MCPCORES0_SOFT 2 SOFT 0
MCP_VID<1>
402
1
0 2
UGATE 18 MCPCORES0_UGATE 1 2
0.25 MM
1
MCPCORES0_BOOT_R2 1 2 3
CRITICAL
R7525 MAX CURRENT: 15.5A
20 IN 5% 0.2 MM 0.001
R7592 5%
1/16W
MCPCORES0_IMON_R 28 IMON BOOT 17 MCPCORES0_BOOT 1/10W
0.2 MM MF-LF
CERM-X7R
10V L7560 1%
1W (Q7560 Limit)
0 MF-LF
67
66 0.25 MM 603
603 1.0UH-17A-5M-OHM MF
20 MCP_VID<2> 1 2 402 62
ALL_SYS_PWRGD 31 PGOOD PHASE 19 5% 0612
IN 24 OUT
40 MCPCORES0_PHASE (MCPCORES0_PHASE) 1 2 PPMCPCORE_S0_R 1 2 PPVCORE_S0_MCP 6 7 21 22 44 64
5% 65 MCP_VID0_R 25 VID0 MIN_LINE_WIDTH=0.5 MM SWITCHNODE NO STUFF HAHF651R0AP-SM
MIN_LINE_WIDTH=0.5 MM 3 4
1/16W MIN_NECK_WIDTH=0.2 MM 1 MIN_NECK_WIDTH=0.2 MM
MF-LF MCP_VID1_R 26 VID1 SWITCH_NODE=TRUE R7589 VOLTAGE=1V
402
MCP_VID2_R 27 VID2 DIDT=TRUE 5 1
C7566 1
5% 10UF
MCPCORES0_OS0 23 OFFSET0 CRITICAL 1/10W 20%
D 4V
1NOSTUFF 1NOSTUFF MCPCORES0_OS1 24
MF-LF X5R 2
R7580 R7581 OFFSET1
(MCPCORES0_LGATE) Q7565 2 603 603 f = 300 kHz
20.0K 20.0K 67 IN MCPCORES0_EN 29 VR_ON MCPCORE_SNUBBER CRITICAL
1% 1%
MCPCORES0_FDE MCPCORES0_LGATE G FDMC8678S CRITICAL
1/16W
MF-LF
1/16W
MF-LF
30 AF_EN LGATE 21 DIDT=TRUE
MIN_LINE_WIDTH=0.5 MM
4
MICROFET3X3
1
C7565 1
C7568
2 402 2 402
32 FDE MIN_NECK_WIDTH=0.2 MM S NO STUFF 270UF
MCPCORES0_VSEN 8 VSEN
GATE_NODE=TRUE C7589 1 1 C7567 20%
2 2V
270UF
20%
1 2 3 0.001UF 10UF TANT 2 2V
MCPCORES0_RTN 9 RTN 10% 20% CASE-B4-SM TANT
50V 2 2 4V
C MCPCORES0_VW 4 VW
X7R
402
X5R
603
CASE-B4-SM
C
1
R7582 1R7583 1 C7569
20.0K 20.0K 0.001UF
1% 1% VO 12 MCPCORES0_VO (MCPCORES0_VO) 10%
1/16W 1/16W 2 50V
X7R
MF-LF
2 402
MF-LF
2 402
MCPCORES0_COMP 5 COMP OCSET 3 R7569 402
11.3K2
6 MCPCORES0_OCSET 1
MCPCORES0_FB 6 FB ISP 13 MCPCORES0_ISP 1%
1/16W
ISN 11 MCPCORES0_ISN MF-LF
1
MCPCORES0_VDIFF 7 VDIFF 402 R7573
ICOMP 10 MCPCORES0_ICOMP 10K C7573 1
1% 47PF
64 44 22 21 7 6 PPVCORE_S0_MCP PGND VSS THRM_PAD 1/16W 5%
MF-LF 50V
1 2 402 CERM 2

20

15

33
R7563 1
R7572 402
100
1%
C7576 1 150K R7500
1/16W 0.1UF 1% 100
MF-LF 10% 1/16W 1 2 MCPCORES0_ISP_R
XW7562
SM R7566 2 402
16V
X7R-CERM 2 MF-LF
1%
20 (MCPCORES0_VSEN) 402 2 402 1/16W
64 44 22 21 7 6 PPVCORE_S0_MCP1 2 82 MCPCORES0_RSEN_P
1 2 MF-LF
402
PLACE XW NEAR THE MCP, OMIT 1%
CONNECT SENSE LINES TO CLOSEST
MCPCORE AND GND BALL
1/16W
MF-LF
1 C7570 XW7561
OF MCP 402 0.001UF SM (MCPCORES0_ISN)
XW7563
SM R7568 10%
50V
2 X7R 1 2
20
1 2 82 MCPCORES0_RSEN_N
1 2 402
(MCPCORES0_RTN) GND_MCPCORES0_AGND
1
R7575 1 C7575
OMIT 1% VOLTAGE=0V 47.0K 47PF
1/16W MIN_LINE_WIDTH=0.6 mm 1% 5%
MF-LF MIN_NECK_WIDTH=0.2 MM 1/16W 2 50V
CERM
402 1 MF-LF 402
R7571 2 402
100 (MCPCORES0_ICOMP)
1%
1/16W
B 2
MF-LF
402 B
(MCPCORES0_VW)

C7579 1
0.001UF
C7580 10%
50V 2
68PF X7R 1
1 2 402 R7576
6.98K
5% 1%
50V 1/16W
R7577 CERM
402-1
C7581 MF-LF
2 402
560PF
1
133K 2 MCPCORES0_COMP_C
1 2
(MCPCORES0_COMP)
1%
1/16W 10%
MF-LF 50V
402 CERM
402 (MCPCORES0_FB)
R7578 C7582 VID<2:0> VOLTAGE
560PF
1
100 2 1
MCPCORES0_VDIF_C 2
1%
000 1.05V
1/16W 10%
MF-LF R7579 50V
CERM 001 1.00V
402
1
2.21K2 402
1%
(MCPCORES0_VDIFF) 010 0.95V
1/16W
MF-LF 011 0.90V
MCP CORE REGULATOR
402
A 100 0.85V
SYNC_MASTER=K19_MLB

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=02/03/2009
A
101 0.80V
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
110 0.75V PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
111 0.70V I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 64 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

61 45 7 PPBUS_CPU_IMVP_ISNS

CRITICAL
C7690 1 1 C7695
22UF 1UF
20% 10% CRITICAL
25V
POLY-TANT 2 2 25V
X5R
CASE-D2-SM 603-1 Q7660 9 4 3 2
FDMS9600S
68 67 64 61 49 47 42 37 7 6 PP5V_S0 MLP
72 70
1

R7601 CRITICAL
1
200 2 PP5V_S0_CPUVTTS0_V5FILT L7660
1 2.2UH-8.0A PP1V05_S0
1%
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm R7679 Q1
10
6 7 9 10 11 12 13 16 17 19 21
22 23 35 61 66 67

10
1/16W VOLTAGE=5V 226K 1 2
C7601 1 C7600

4
MF-LF 1 1% Vout = 1.052V
SW PCMB065T-SM
402 1/16W
2.2UF 1UF 8 1 C7665
C 10%
16V 2
X5R
V5FILT
CRITICAL
V5DRV
2
10%
10V
X5R
MF-LF
402 2 10UF
20%
8A max output C
603 402-1 6.3V
2 X5R (Q7660 limit?)
U7600 603
TPS51117RGY_QFN14 Q2 f = 360 kHz
CPUVTTS0_EN
SYM (2 OF 2)
1 EN_PSV
QFN
TON 2 CPUVTTS0_TON C7680 1 CRITICAL
67 IN 0.1UF
10%
67 66 64 62 40 24 OUT ALL_SYS_PWRGD 6 PGOOD VBST 14 CPUVTTS0_VBST 50V 2
X7R 7 6 5
C7660 1
MIN_LINE_WIDTH=0.6MM 603-1 2 330UF
MIN_NECK_WIDTH=0.2MM 20%
(=PPCPUVTT_S0_REG) 3 VOUT DRVH 13 CPUVTTS0_DRVH XW7665 2.0V 2
GATE_NODE=TRUE MIN_LINE_WIDTH=0.6MM POLY-TANT
MIN_NECK_WIDTH=0.2MM DIDT=TRUE SM B2-SM
CPUVTTS0_VFB 5 VFB LL 12 CPUVTTS0_LL
SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.6MM DIDT=TRUE 1
MIN_NECK_WIDTH=0.2MM
CPUVTTS0_TRIP 11 TRIP DRVL 9 CPUVTTS0_DRVL CPUVTTS0_VSNS
GATE_NODE=TRUE MIN_LINE_WIDTH=0.6MM DIDT=TRUE
GND THRM_PAD PGND MIN_NECK_WIDTH=0.2MM PLACEMENT_NOTE=Place XW7665 next to L7660
1

15
R7670

8
1 8.06K
R7685 1%
1/16W
8.87K MF-LF
1% 2 402
1/16W
MF-LF
XW7600
SM <Ra>
2 402 1 2 (GND)
1
R7671
20.0K
1%
1/16W
MF-LF
2 402
GND_CPUVTTS0_SGND <Rb>
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
Vout = 0.75V * (1 + Ra / Rb)
B (CPUVTTS0_VFB)
B
(=PPCPUVTT_S0_REG)

CPU VTT Power Supply

A SYNC_MASTER=(K19_MLB)

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=(12/05/2008)
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
M99 differences from last sync on 12/03/07 to T18 MLB:
II NOT TO REPRODUCE OR COPY IT
1. Tied THERMAL_PAD to PGND. GND and THERMAL_PAD disconnected.
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 65 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

1.8V S0 SWITCHER D
D

82 72 71 69 68 67 66 61 58 57
26 23 22 21 20 18 17 12 7 6
53 49 47 46 45 43 41 37 35 27
PP3V3_S0

1 CRITICAL
CRITICAL
VI
C7760 1
U7760 L7760
10uF TPS62202 10UH-0.55A-330MOHM
20% PCAA031B-SM
6.3V 4
SOT23-5 MAX CURRENT = 200MA
X5R 2 FB
603
67 P1V8S0_EN 3 EN SW 5 P1V8S0_SW 1 2 PP1V8_S0 6 7 17 23 53
DIDT=TRUE
GND
C7762 1
2
10uF
20%
6.3V
X5R 2
603

1.05V S0 PLL LDO

C PP3V3_S0
R7743
100
C
82 72 71 69 68 67 66 61 58 57
26 23 22 21 20 18 17 12 7 6 1 2 PP3V3_S0_MCP_PLL_VLDO_BIAS
53 49 47 46 45 43 41 37 35 27
5%
1/16W
LDO_YES MF-LF
402
LDO_NO
C7740 1 LDO_YES R7745
1UF PP1V05_S0 1
0 2
19 17 16 13 12 11 10 9 7 6
10% 67 65 61 35 23 22 21
6.3V 2 5%
CERM 1/16W
402 MF-LF
LDO_YES VOUT = 0.8V * (1 + RA / RB) 402 PP1V05_S0_MCP_PLL_UF 7 22

4
CRITICAL
BIAS R7744 Vout = 1.05V
PP1V5_S0 1 9 PP1V05_S0_MCP_PLL_UF_LDO 1
0 2 MAX CURRENT = 0.5A
82 68 67 37 22 15 11 10 7 6 IN0 OUT0
2 IN1 OUT1 10 MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
<Ra> 5%
1/16W
TPS74701 DIDT=TRUE
1
R7746 MF-LF
402
C7741 1 5 EN
SON
FB 8 1.37K
1% 1 C7742 LDO_YES
1UF 1/16W
10% MF-LF 4.7UF
MCP 1.05V S5 (AUXC) SUPPLY LDO_YES 6.3V
CERM 2 P1V05S0_LDO_SS U7740 2 402
LDO_YES
20%
4V
2 X5R
402 7 SS PG 3 P1V05S0_LDO_FB 402
C7743 1 GND THRML_PAD 1
<Rb> LDO_YES
0.0022UF R7747
10% 4.42K

11
50V
CERM 2 1%
CRITICAL 402 1/16W
MF-LF
1 C7750 LDO_YES 2 402
PP3V3_S5 22UF LDO_YES
35 32 28 24 22 21 19 17 7 6
82 71 69 68 67 62 52 42 36 20%
2 6.3V
CERM
B 805
R7748 B
PP1V05S0_PGOOD 1
0 2 ALL_SYS_PWRGD 24 40 62 64 65 67

1 5%
CRITICAL 1/16W
VIN MF-LF
402
U7750 L7770 LDO_YES
ISL8009B 2.2UH-3.25A
IHLP1616BZ-SM
DFN
67 IN PM_G2_P1V05S5_EN 2 EN CRITICAL LX 8 1V05S5_SW 1 2 PP1V05_S5 6 7 21 22 32
DIDT=TRUE

P1V05_S5_PGOOD 3 POR VFB 6 1V05S5_FB 1 <Ra> Vout = 1.05V

67
C7776 1 R7780
4 SKIP RSI 5 47PF 255K MAX CURRENT = 0.8A
5% 1% CRITICAL
50V
GND THRM_PAD CERM 2 1/16W
MF-LF 1 C7771 FREQ = 1.6MHZ
402 2 402
7 9 22UF
1
<Rb> 2
20%
6.3V
CERM
R7781 805
806K
1%
1/16W
MF-LF
2 402

VOUT = 0.8V * (1 + RA / RB)

MISC POWER SUPPLIES
SYNC_MASTER=K24_MLB SYNC_DATE=02/25/2009
A NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 66 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

3.3V 1.05V S5 ENABLE

R7802 Power Control Signals
100K
PP3V42_G3H 2 1 67 62 PM_G2_P3V3S5_EN_L PM_G2_P3V3S5_EN_L
43 42 41 40 38 24 21 20 7 6
67 60 59 48 45 MAKE_BASE=TRUE
OUT 62 67
3.3V_S0, 1.8V_S0 ENABLE
5%
1/16W
MF-LF State SMC_PM_G2_ENABLE PM_SLP_S4_L PM_SLP_S3_L MCPDDR, CPUVTT,MCPCORES0 ENABLE
NO STUFF
402 1 C7802 1.5V S0 AND 1.05V S0 ENABLE
0.068UF Run (S0) 1 1 1
Q7800 10%

D SSM3K15FV
SOD-VESM-HF
D 3 2 10V
CERM
402
Sleep (S3) 1 1 0 D
62 40 8 6 SMC_PM_G2_EN Soft-Off (S5) 1 0 0
IN
Battery Off (G3Hot) 0 0 0
1
R7800
100K 1 G S 2
5%
1/16W
MF-LF
R7801
402 5.1K
2 2 1 PM_G2_P1V05S5_EN PM_G2_P1V05S5_EN 66 67
MAKE_BASE=TRUE
OUT
5%
1/16W
MF-LF 1
402 C7801
0.47UF
10%
6.3V
2 CERM-X5R
402
(PM_SLP_S3_L)
R7859
PM_SLP_S3_L 100
71 40 35 32 20 6 IN 2 1 68 67 44 PM_SLP_S3_L_BUF
MAKE_BASE=TRUE
5%
1/16W
MF-LF PM_SLP_S3_L_BUF 44 67 68
402
OUT

1 PM_SLP_S3_L_BUF OUT 44 67 68
R7880 R7881 R7882 R7883

2
R7879 2
5%
2
5%
2
5%
2
5%
R7884
100K 1/16W 1/16W 1/16W 1/16W 5%
S3 ENABLE 5%
1/16W
MF-LF MF-LF MF-LF MF-LF 1/16W
MF-LF
402 402 402 402
MF-LF 1 22K 1 1 0 1 10K 402
402
33K 5.1K

1
2
R7813
68K
43 42 41 40 38 24 21 20 7 6
PP3V42_G3H 2 1
67 60 59 48 45
5%
1/16W Q7813 68
MF-LF D 3 SSM3K15FV 67 62 PM_SLP_S3_L_INVERT PM_SLP_S3_L_INVERTOUT 62 67 67 P3V3S0_EN P3V3S0_EN
OUT 67 68
402 SOD-VESM-HF
MAKE_BASE=TRUE MAKE_BASE=TRUE
NO STUFF
1 C7813 67 66 P1V8S0_EN P1V8S0_EN
OUT 66 67
41 40 38 20 6 PM_SLP_S4_L
IN MAKE_BASE=TRUE

C
MAKE_BASE=TRUE

2
0.068UF
10%
10V
CERM
68 67 MCPDDR_EN
MAKE_BASE=TRUE
MCPDDR_EN
OUT 67 68 C
1 1 G S 2 402 67 65 CPUVTTS0_EN CPUVTTS0_EN 65 67
R7810 OUT
(PM_S4_STATE_L) MAKE_BASE=TRUE
100K
5%
67 64 MCPCORES0_EN MCPCORES0_EN OUT 64 67
1/16W MAKE_BASE=TRUE
MF-LF
402
2

NO STUFF
C7810
1 1 1 1
R7811 0.47UF C7880 C7881 C7882 C7883 1 C7884
5.1K 1 2 0.47UF 0.47UF 0.47UF 0.47UF 0.47UF
10% 10% 10% 10%
1 2 10%
6.3V 6.3V 6.3V 6.3V
5% 2 2 2 2 6.3V
1/16W 10%
CERM-X5R CERM-X5R CERM-X5R CERM-X5R 2 CERM-X5R
402 402 402 402
MF-LF 6.3V 402
402 CERM-X5R
402

67
63 DDRREG_EN DDRREG_EN OUT 63 67
MAKE_BASE=TRUE
DDRREG_EN OUT 63 67

NO STUFF
C7812
R7812 0.47UF
0
1 2
1 2 VOLTAGE MONITOR
5%
1/16W 10%
MF-LF 6.3V
402 CERM-X5R
402 43 42 41 40 38 24 21 20 7 6 PP3V42_G3H
67 60 59 48 45
68 67 P3V3S3_EN P3V3S3_EN
OUT 67 68
MAKE_BASE=TRUE

35 32 28 24 22 21 19 17 7 6 PP3V3_S5
82 71 69 68 66 62 52 42 36

C7840 1
0.1uF 1
B 20%
10V
CERM
2
R7840
100K
5%
B
402
1/16W
MF-LF
6 402
2
VDD
5 SENSE RESET* 1 RSMRST_PWRGD
U7840 40

TPS3808G33DBVRG4
SOT23-6
3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT PP5V_S0 CT 4 CT MR* 3 P1V05_S5_PGOOD 66
6 7 37 42 47 49 61 64 65 68 70
72
GND TPS3808 MR* HAS INTERNAL PULLUP

2
R7870
10K 1
1% C7841
1/16W 0.001UF
MF-LF 20%
402
2 OTHER S0 RAILS PGOOD 50V
CERM 2
PP3V3_VMON_VDD 402

353S2310 68 67 66 61 58 57 53 49
2
7

1
23 22 21 20 18 17 12 7 6 PP3V3_S0
C7870 1 R7871 47 46 45 43 41 37 35 27 26
VDD 82 72 71 69
20.0K
0.1uF
1%
20%
U7870 10V
CERM
2
1/16W
MF-LF
ISL88042IRTEZ 402
402
2
1
TDFN R7820
82 72 71 69 68 67 66 61 58
27 26 23 22 21 20 18 17 12 7 6 PP3V3_S0 3 V2MON MR* 1
57 53 49 47 46 45 43 41 37 35 NC 10K
PP1V5_S0 5%
82 68 66 37 22 15 11 10 7 6 5 V3MON 1/16W
67 66 65 64 62 40 24 ALL_SYS_PWRGD MF-LF
21 19 17 16 13 12 11 10 9 7 6 PP1V05_S0
6 V4MON RST* 8 402
66 65 61 35 23 22 2

GND THRM_PAD
POWER SEQUENCING
4

Unused PGOOD signal

67 66 65 64 62 40 24 IN ALL_SYS_PWRGD

A 67 66 65 64 62 40 24 IN ALL_SYS_PWRGD
67 63 TP_DDRREG_PGOOD
MAKE_BASE=TRUE
TP_DDRREG_PGOOD 63 67 SYNC_MASTER=K24_MLB

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=02/05/2009
A
V2MON THRESHOLD IS 2.866V THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
V3MON THRESHOLD IS 0.6V PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
V4MON THRESHOLD IS 0.6V 67 66 65 64 62 40 24 IN ALL_SYS_PWRGD
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
67 66 65 64 62 40 24 IN ALL_SYS_PWRGD
II NOT TO REPRODUCE OR COPY IT

ALL_SYS_PWRGD III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

OUT 24 40 62 64 65 66 67
MAKE_BASE=TRUE

(S0PGOOD_PWROK) SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 67 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
1.5V S0 FET
3.3V S3 FET (1.5V S0 FET FOR DDR3 MEM, MCP79 AND CPU)

CRITICAL
Q7910 63 28 27 26 7 6 PP1V5_S3
FDC638P_G
SM
PP3V3_S3
3.3V S3 FET
6 7 20 25 29 30 43 48 50
9 CRITICAL
66 62 52 42 36
21 19 17 7 6 PP3V3_S5
35 32 28 24 22
82 71 69 68 67
6 Q7901
ROME
D 4
5
MOSFET FDC638P D
DFN D
R7912 1
C7911 1
2
CHANNEL P-TYPE C7902 1
NC 8
0.033UF
1
0.1UF
10K RDS(ON) 48 mOhm @4.5V

45
20% 4 G
10%
5% 10V
16V
CERM 2
KELVIN 6 P1V5_S0_KELVIN OUT
1/16W
X5R
2
R7901

SENSE
MF-LF
402 3
LOADING 0.182 A (EDP) 53 51 49 41 39 38 37 29 8 7 6 PP5V_S3 402
S
402
C7910 68 63 62 10K

GND
2
R7910 0.01UF 1 2 MCPDDR_SS
47K 1 2 5%
P3V3S3_EN_L 1 2 P3V3S3_SS 7 1 2 3 5

45
1/16W
MF-LF
5%
Q7971 D 6 OUT
1/16W
10%
16V
R7903 1 402 P1V5_S0_SENSE
Q7903 MF-LF
CERM 100K SSM6N15FEAPE
402
402 5% SOT563 PP1V5_S0 6 7 10 11 15 22 37 66 67 82
SSM3K15FV D 3 1/16W
SOD-VESM-HF MF-LF
402
2

R7971 2 G S 1
1
C7903
47K 0.068UF 1.5V S0 FET
MCPDDR_EN_L 1 2 10%
10V
2
1 G S 2 5% CERM MOSFET Rome SenseFET
1/16W 402
67 P3V3S3_EN
IN MF-LF
Q7971 D 3
402 CHANNEL N-TYPE
MCPDDR_EN_L_RC
SSM6N15FEAPE
SOT563 RDS(ON) 6.3 mOHM @4.5V VGS

LOADING 5A (EDP)
5 G S 4

MCPDDR_EN
3.3V S0 FET 67 IN

CRITICAL
Q7930
C FDC606P_G
SOT-6
C
3.3V S0 FET

5 6
58 61 66 67 69 71 72 82
PP3V3_S0 6 7 12 17 18 20 21 22 23 26 27
66 62 52 42 36
21 19 17 7 6 PP3V3_S5 35 37 41 43 45 46 47 49 53 57
35 32 28 24 22
82 71 69 68 67
MOSFET FDC606P
S

D
4

2
1
CHANNEL P-TYPE
R7932 1
C7931 1
G

100K 0.033UF RDS(ON) 26 MOHM @4.5V

10%
5%
16V
3

1/16W 2
X5R
MF-LF
402
LOADING 1.431 A (EDP)
402
2
R7930 C7930
0.01UF
47K 1 2
P3V3S0_EN_L 1 2 P3V3S0_SS

5%
1/16W 10%
16V
Q7905 MF-LF
402 CERM
402
SSM3K15FV D 3
SOD-VESM-HF

MCP79 DDRVTT FET

1 G S 2
67 P3V3S0_EN
IN
MCP79 DDR PAD LEAKAGE IS HIGH ENOUGH THAT
NVIDIA RECOMMENDS UNPOWERING DURING SLEEP.
IN ORDER TO SUPPORT UNPOWERING RAIL, HARDWARE
MUST GUARANTEE MEM_CKE SIGNALS ARE LOW
BEFORE RAIL IS TURNED OFF, AND REMAINS LOW
UNTIL AFTER RAIL TURNS BACK ON OR DIMMS
WILL EXIT SELF-REFRESH PREMATURELY.

B 5.0V S0 FET
MEM_VTT_EN OUTPUT FROM MCP79 USED TO ENABLE CLAMP
ON VTT RAIL, WHICH PULLS ALL CKE SIGNALS
B
LOW THROUGH VTT TERMINATION RESISTORS.

CRITICAL
Q7940
TPCP8102 376S0778
23V1K-SM

PP5V_S0
49 61 64 65 67 70 72
6 7 37
5.0V S0 FET
7 8

38 37 29 8 7 6 PP5V_S3 42 47
Part TPCP8102 R7975
3

68 63 62 53 51 49 41 39
10
PP0V75_S0_DDRVTT 2 1 VTTCLAMP_L
1 2

63 27 26 7 6 90mA max load @ 0.9V

Type P-Channel
6

5% 81mW max power

C7941
5

R7942 1 1

Rds(on) 14 mOhm @4.5V

1/10W
G

MF-LF
47K 0.033UF 603
4

5%
10%
CKT FROM T18
1/16W
16V
X5R
2 Loading 1.7 A (EDP) 53 51 49 41 39 38 37 29 8 7 6
68 63 62
PP5V_S3
MF-LF
402
Q7975 D 6
402
2
R7940 C7940 SSM6N15FEAPE
47K
0.01UF R7976 1 SOT563
P5V0S0_EN_L 1 2 P5V0S0_SS 1 2 100K
5%
5% 1/16W
10%
1/16W MF-LF
Q7945 MF-LF 16V
CERM
402
2
2 G S 1
402
402
SSM3K15FV D 3 VTTCLAMP_EN
SOD-VESM-HF

D NO STUFF
Q7975 3
C7976 1
SSM6N15FEAPE
0.001UF
67 44 IN PM_SLP_S3_L_BUF
1 G S 2 SOT563
20%
50V
CERM 2
POWER FETS
402
SYNC_MASTER=K24_MLB SYNC_DATE=03/12/2009
A 5 G S 4
NOTICE OF PROPRIETARY PROPERTY
A
63 24 8 IN MEM_VTT_EN
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 68 83

8 7 6 5 4 3 2 .
. 1
 8 7 6 5 4 3 2 1

D D
17 8 IN LCD_PWR_EN

R90941
10K
5%
1/16W
MF-LF
LCD (LVDS) INTERFACE
402 2

CRITICAL
U9000 CRITICAL
FPF1009
1 ON MFET-2X2 L9000
FERR-250-OHM
35 32 28 24 22 21 19 17 7 6 PP3V3_S5 2 VIN_1 VOUT_1 4 PP3V3_SW_LCD_UF 1 2
82 71 68 67 66 62 52 42 36 MIN_LINE_WIDTH=0.5 mm SM
MIN_NECK_WIDTH=0.25 mm
3 VIN_2 VOUT_2 5 VOLTAGE=3.3V

GND THRM
PAD 1 C9011 1 C9012 C9001 1 C9002 1
1 C9009 0.1UF 0.001UF
6 7 0.1UF 10UF 10% 10%
0.1UF 10% 20% 16V 2 50V 2
10%
16V 2 16V
X5R 2 6.3V
X5R
X5R
402
X7R
402
2 X5R 402 603
402 CRITICAL
J9000
20474-040E-11
F-RT-SM
41
82 72 71 68 67 66 61 58 57
26 23 22 21 20 18 17 12 7 6
53 49 47 46 45 43 41 37 35 27
PP3V3_S0 42

C 1
C
100K pull-ups are for
R90101 1
R9011 6 PP3V3_SW_LCD 2
100K 100K MIN_LINE_WIDTH=0.5 mm 3
no-panel case (development). 5% 5% MIN_NECK_WIDTH=0.25 mm
1/16W 1/16W VOLTAGE=3.3V 4
Panel has 2K pull-ups MF-LF MF-LF
402 2 2 402 5
NC
17 8 6 LVDS_DDC_CLK 6
17 8 6 LVDS_DDC_DATA 7
8 6 LVDS_CONN_A_DATA_N<0> 8
C9010 1 8 6 LVDS_CONN_A_DATA_P<0> 9
0.001UF 10
10%
50V 2 LVDS_CONN_A_DATA_N<1> 11
X7R 8 6
402 8 6 LVDS_CONN_A_DATA_P<1> 12
CRITICAL 13
L9010
90-OHM-100MA LVDS_CONN_A_DATA_N<2> 14
8 6
DLP11S 15
SYM_VER-1
8 6 LVDS_CONN_A_DATA_P<2>
77 17 8 LVDS_CONN_A_CLK_N 4 3 16
82 6 LVDS_CONN_A_CLK_F_N 17
82 6 LVDS_CONN_A_CLK_F_P 18
77 17 8 LVDS_CONN_A_CLK_P 1 2
19
Place close to the connector 8 6 LVDS_CONN_B_DATA_N<0> 20
8 6 LVDS_CONN_B_DATA_P<0> 21
22
8 6 LVDS_CONN_B_DATA_N<1> 23
8 6 LVDS_CONN_B_DATA_P<1> 24
CRITICAL 25
L9011
B 90-OHM-100MA
DLP11S
SYM_VER-1
8 6

8 6
LVDS_CONN_B_DATA_N<2>
LVDS_CONN_B_DATA_P<2>
26
27 B
77 17 8 LVDS_CONN_B_CLK_N 4 3 28
LVDS_CONN_B_CLK_F_N
82 6 29
LVDS_CONN_B_CLK_F_P
82 6 30
77 17 8 LVDS_CONN_B_CLK_P 1 2
74 72 6 LED_RETURN_6 31
Place close to the connector 74 72 6 LED_RETURN_5 32
74 72 6 LED_RETURN_4 33
74 72 6 LED_RETURN_3 34
74 72 6 LED_RETURN_2 35
LED_RETURN_1 36 518S0651
74 72 6
37
NC
38
39
74 72 51 6 PPVOUT_S0_LCDBKLT 40

43
44

LVDS Display Connector

A SYNC_MASTER=K19_MLB

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=02/05/2009
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 69 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

17 =MCP_HDMI_TXC_P DP_ML_P<3> 71 82
MAKE_BASE=TRUE
17 =MCP_HDMI_TXC_N DP_ML_N<3> 71 82
MAKE_BASE=TRUE
17 =MCP_HDMI_TXD_P<0> DP_ML_P<2> 71 82
MAKE_BASE=TRUE
17 =MCP_HDMI_TXD_N<0> DP_ML_N<2> 71 82
MAKE_BASE=TRUE
17 =MCP_HDMI_TXD_P<1> DP_ML_P<1> 71 82
MAKE_BASE=TRUE
17 =MCP_HDMI_TXD_N<1> DP_ML_N<1> 71 82
MAKE_BASE=TRUE
82 71 70 17 DP_ML_P<0> DP_ML_P<0> 17 70 71 82
MAKE_BASE=TRUE
82 71 70 17 DP_ML_N<0> DP_ML_N<0> 17 70 71 82
MAKE_BASE=TRUE
71 70 17 DP_HPD DP_HPD 17 70 71

D 70 17 DP_IG_DDC_CLK DP_IG_DDC_CLK
MAKE_BASE=TRUE

MAKE_BASE=TRUE
17 70 D
70 17 DP_IG_DDC_DATA DP_IG_DDC_DATA 17 70
MAKE_BASE=TRUE

DP_AUX_CH_C_N 71 82
BI

R9300 C9300
0.1UF
70 17
DP_IG_DDC_DATA 1
33 2 1 2 82 DP_AUX_CH_SW_N
BI
5%
1/16W 10%
MF-LF 16V
402 X5R
Display Port Interoperability spec says that sources 402

or sinks which do both DP and DVI must depend on the

DP_AUX_CH_C_P 71 82
BI
external adapter for pull ups on DDC lines (since DP
AUX CH has 100K pull up/down on the MLB)..
R9301 C9301
0.1UF
70 17
DP_IG_DDC_CLK 1
33 2 1 2 82 DP_AUX_CH_SW_P
BI
5%
1/16W 10%
MF-LF 16V
402 X5R
402

C 3
SIGNAL_MODEL=DP_AUXCH_FET
D Q9300
SIGNAL_MODEL=DP_AUXCH_FET
Q9300 D 6
C
SSM6N15FEAPE SSM6N15FEAPE
SOT563 SOT563

4 S G 5 2 G S 1

77 17
DP_IG_AUX_CH_P
BI

77 17
DP_IG_AUX_CH_N
BI

PP5V_S0
64 61 49 47 42 37 7 6
72 68 67 65

1
R9302
100K
1 5%
R9306 1/16W
MF-LF
1K 2 402
5%
1/16W
MF-LF
402 2
DDC_CA_DET_LS5V_L

B B
Q9301
3 D SSM3K15FV
SOD-VESM-HF

2 S G 1

71
DP_CA_DET
IN

DP_IG_CA_DET 17
OUT

DISPLAYPORT SUPPORT
SYNC_MASTER=K24_MLB SYNC_DATE=12/19/2008
A NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 70 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

Port Power Switch

CRITICAL
DP_ESD
DP_ESD
U9480 CRITICAL
CRITICAL
TPS2051B
D 82
32 28 24 22 21 19 17 7 6 PP3V3_S5 5 IN
SOT23
OUT 1 PP3V3_S0_DPILIM D9410 D9410
RCLAMP0524P
D
69 68 67 66 62 52 42 36 35 MIN_LINE_WIDTH=0.38 MM
L9400 RCLAMP0524P SLP2510P8
PM_SLP_S3_L 4 EN MIN_NECK_WIDTH=0.20 MM SLP2510P8
67 40 35 32 20 6 IN OC* 3 TP_DPPWR_OC_L
VOLTAGE=3.3V FERR-120-OHM-3A
GND 1 2
2 PP3V3_S0_DPPWR 2 IO
MIN_LINE_WIDTH=0.38 MM IO 1
0603 MIN_NECK_WIDTH=0.20 MM 5 IO IO 4
VOLTAGE=3.3V 9 NC NC 10
1 C9400 6 NC NC 7
0.01UF

GND
GND
20%
CRITICAL 2 50V
CERM 3
C9480 1 1 C9481 C9485 1 1 C9486
603
3
10UF 0.1UF
20% 20% 0.1UF 22UF
6.3V 2 2 10V 20% 20%
X5R CERM 10V 2 6.3V
603 402 CERM 2 X5R-CERM
402 603

R94201
100K
5%
1/16W
MF-LF
402 2 NO STUFF
R9400 0 1 2
5% 1/16W MF-LF 402
NO STUFF
NO STUFF R9430 0 1 2
R9401 0 1 2 5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
HDMI_CEC CRITICAL NO STUFF
J9400 R9431 0 1 2
5% 1/16W MF-LF 402
NO STUFF DSPLYPRT-M97-1
R9403 0 1 2 F-RT-THSM FL9400
5% 1/16W MF-LF 402 12-OHM-100MA
NO STUFF
C R9413 0 1 2
5% 1/16W MF-LF 402
BOT ROW TOP ROW 82 DP_ML_CONN_P<0> 1
TCM1210-4SM
SYM_VER-2 4
82 6 DP_ML_C_P<0> C9410 1 2 DP_ML_P<0>
C
1 TH PINS SM PINS IN 17 70 82
R9425 82 DP_ML_CONN_N<0> 10% 16V X5R 402
2 HOT_PLUG_DETECT GND
1 0.1uF
1M
5%
FL9403
12-OHM-100MA 4
CONFIG1
3 FL9401
12-OHM-100MA 2 3 82 DP_ML_C_N<0> C9411 1 2 DP_ML_N<0> IN 17 70 82
1/16W ML_LANE0P 10% 16V X5R 402
MF-LF 4
TCM1210-4SM
1
6
CONFIG2 ML_LANE0N
5
1
TCM1210-4SM
4 0.1uF
2 402
SYM_VER-2
DP_ML_CONN_P<1> SYM_VER-2

82 70 IN DP_ML_P<3> C9414 1 2 DP_ML_C_P<3>

10% 16V X5R 402
82 DP_ML_CONN_P<3> 8 GND GND
7
82
82 6 DP_ML_C_P<1> C9412 1 2 DP_ML_P<1>
10% 16V X5R 402 IN 70 82

0.1uF 10 ML_LANE3P ML_LANE1P

9 0.1uF
82 70 IN DP_ML_N<3> C9415 1 2 82 DP_ML_C_N<3> 3 2 82 DP_ML_CONN_N<3> 12 ML_LANE3N 11 82 DP_ML_CONN_N<1> 2 3 FL9402
12-OHM-100MA 82 DP_ML_C_N<1> C9413 1 2 DP_ML_N<1> IN 70 82
10% 16V X5R 402 ML_LANE1N 10% 16V X5R 402
0.1uF 14 GND GND
13
1
TCM1210-4SM
SYM_VER-2 4 0.1uF
82 70 BI DP_AUX_CH_C_P 16 AUX_CHP ML_LANE2P
15 82 DP_ML_CONN_P<2> 82 6 DP_ML_C_P<2> C9416 1 2 DP_ML_P<2> IN 70 82
10% 16V X5R 402
18 AUX_CHN ML_LANE2N
17 0.1uF
82 70 BI DP_AUX_CH_C_N 20 DP_PWR RETURN
19 82 DP_ML_CONN_N<2> 2 3 82 DP_ML_C_N<2> C9417 1 2 DP_ML_N<2>
10% 16V X5R 402
IN 70 82

DP_ESD 0.1uF
68 67 66 61 58 57 53 49
26 23 22 21 20 18 17 12 7 6 PP3V3_S0
47 46 45 43 41 37 35 27
82 72 71 69
CRITICAL SHIELD PINS
R94431 R94421 D9411 22 21 NO STUFF
100K RCLAMP0524P R9402 0
5% 100K SLP2510P8
1 2
1/16W
MF-LF
5%
1/16W R94211 NO STUFF
5% 1/16W MF-LF 402
402 2 MF-LF 100K R9432 0 1 2
402 2 5%
70 OUT DP_CA_DET 1/16W 2 IO 5% 1/16W MF-LF 402
MF-LF IO 1
6 402 2 9 NC NC 10
Q9440 D

GND
2N7002DW-X-G DP_ESD
SOT-363
S G 2 DP_CA_DET_L_Q CRITICAL DP_ESD
3
D9400 CRITICAL
3
1 RCLAMP0504F
SC70-6-1
D9411
Q9440 D RCLAMP0524P
B 2N7002DW-X-G
SOT-363
S G 5 DP_CA_DET_Q 1
6
SLP2510P8
B
DP to DVI/HDMI 5 IO
4 IO 4
R94221 Cable Adapter 2 5
6 NC NC 7
1M (CA) has 100k
5%

GND
Q9440 must have Drain to Gate leakage of <500nA and Gate to Source resistance of >5MOhm 1/16W pull-up to DP_PWR. 4
MF-LF 3
402 2
3

66 61 58 57 53 49 47
26 23 22 21 20 18 17 12 7 6 PP3V3_S0
46 45 43 41 37 35 27
82 72 71 69 68 67

R94451 R94441
10K
5% 10K
1/16W 5%
MF-LF 1/16W
402 2 MF-LF
402 2
70 17 OUT DP_HPD
6

Q9441 D
2N7002DW-X-G
SOT-363 2
S G DP_HPD_L_Q
1 3

Q9441 D
2N7002DW-X-G
SOT-363
DisplayPort Connector
S G 5 DP_HPD_Q
A 4 DP Source must pull
SYNC_MASTER=K19_MLB SYNC_DATE=02/05/2009
A
R94231 down HPD input with
NOTICE OF PROPRIETARY PROPERTY
100K
5% greater than or equal THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1/16W PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
MF-LF to 100K (DPv1.1a). AGREES TO THE FOLLOWING
402 2
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 71 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
*L9701, D9701, C9796, C9797, C9799, C9712 AND C9713 SHOULD ALL BE PLACED NEAR EACHOTHER.
*PPVOUT_S0_LCDBKLT_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.
* LVDS_IG_BKL_PWM SHOULD BE AWAY FROM BOOST CIRCUIT

BKL_VLDO_EN_L

CRITICAL

Q9701
NTZD3155C
3 SOT-563-HF
P-CHN

D D
R9735
D
G 5 1
100K 2
S 1%
1/16W
4 MF-LF
402
6
PP5V_S0 6 7 37 42 47 49 61 64 65 67 68
MIN_LINE_WIDTH=0.4 MM 70

D MIN_NECK_WIDTH=0.2 MM
R9701
0
G 2 BKLT_EN_R 1 2 BKLT_EN 72
S 5%
1/16W
1 MF-LF
402
N-CHN

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
1
VOLTAGE=5V R9702
0
5%
1/16W
MF-LF
2 402 CRITICAL
CRITICAL
XW9720 L9701 D9701
SM 22UH-2.5A SOD-123
73 72 PPBUS_S0_LCDBKLT_PWR 1 2 74 PPVIN_BKL 1 2 PPBUS_S0_LCDBKLT_PWR_SW 1 2 PPVOUT_S0_LCDBKLT 6 51 69 74
CRITICAL MIN_LINE_WIDTH=0.5 MM MIN_LINE_WIDTH=0.5 MM MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.375 MM MIN_NECK_WIDTH=0.375 MM MIN_NECK_WIDTH=0.375 MM
XW9721 XW9722 1 C9712 1 C9713 C
C VOLTAGE=6V VOLTAGE=50V VOLTAGE=50V

2
IHLP2525CZ-SM RB160M-60G
10UF 0.1UF NO
SWITCH_NODE=TRUE
1 C9796 1 C9799 1 C9797
SM SM 10% 10% 1 STUFF
25V
2 X5R 25V
2 X5R R9703 220PF
10%
2.2UF
10%
2.2UF
10%
805 402 0
5% 2 50V 2 100V 2 100V
1

1
1/16W X7R-CERM X7R X7R
MF-LF 402 1210 1210
82 51 OUT ISNS_LCDBKLT_P 2 402
82 51 OUT ISNS_LCDBKLT_N

PPVIN_BKL_R
6 BKL_VLDO
82 71 69 68 67 66 61 58 57
26 23 22 21 20 18 17 12 7 6
53 49 47 46 45 43 41 37 35 27
PP3V3_S0

R97161
100K 1 C9714 1 C9710 1 C9711

22

23
5% 0.01UF 1UF 0.1UF CRITICAL

8
1/16W 10% 10% 10%
MF-LF VDDIO VLDO VIN
402 2 2 16V
CERM 2 25V
X5R 2 16V
X5R
402 603-1 402
U9701
LLP

LP8543SQX
NO STUFF
1
R9714 NC
6 ALSO SW 24
100K R9717
IF_SEL=1 FOR SMBUS 5% 5 ALSI
1/16W FB 21 10.2 2
MF-LF 1 LED_RETURN_1 OUT 6 69 74
402 2 20 ADR MIN_LINE_WIDTH=0.5 mm
OUT1 12 6 BKL_ISEN1 0.1% MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm 1/16W
MIN_NECK_WIDTH=0.20 mm TF
BKL_IF_SEL 3 IF_SEL OUT2 13 6 BKL_ISEN2 402
78 58 43 20 R9753
SMBUS_MCP_1_CLK 0 1 2
10 SCLK OMIT
5% 1/16W MF-LF 402 BKL_SCL OUT3 14 6 BKL_ISEN3 R9718
11 SDA 10.2 2
BKL_SDA OUT4 16 6 BKL_ISEN4 1 LED_RETURN_2 OUT 6 69 74
MIN_LINE_WIDTH=0.5 mm MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm 0.1% MIN_NECK_WIDTH=0.20 mm
B 78 58 43 20 R9757
SMBUS_MCP_1_DATA 0 1 2 LVDS_BKL_PWM_RC 2 PWM OUT5 17 6 BKL_ISEN5 1/16W
TF B
5% 1/16W MF-LF 402
402
TP_BKL_FAULT 7 FAULT OUT6 18 6 BKL_ISEN6
R9731 R9719
PPBUS_S0_LCDBKLT_PWR 72 BKLT_EN 4 EN OUT7 19 10.2 2
73 72
NC 1 LED_RETURN_3 OUT 6 69 74
1 2 MIN_LINE_WIDTH=0.5 mm MIN_LINE_WIDTH=0.5 mm
301K MIN_NECK_WIDTH=0.20 mm 0.1% MIN_NECK_WIDTH=0.20 mm
1% NO STUFF 1/16W

1 GND_SW
1/16W TF
R9715

9 GND_S

15 GND_L
MF-LF 1 C9723 402
2

402
0.1UF 100K THRM
10% 1% PAD R9720
2 25V 1/16W 10.2 2

25
X5R MF-LF 1 LED_RETURN_4 6 69 74
402 402 MIN_LINE_WIDTH=0.5 mm OUT
MIN_LINE_WIDTH=0.5 mm
1

MIN_NECK_WIDTH=0.20 mm 0.1% MIN_NECK_WIDTH=0.20 mm

1/16W
TF
402
R9721
R9704 10.2 2
1 LED_RETURN_5 OUT 6 69 74
LCD_BKLT_PWM 1
0 2 MIN_LINE_WIDTH=0.5 mm
0.1%
MIN_LINE_WIDTH=0.5 mm
74 73 17 8 IN MIN_NECK_WIDTH=0.20 mm MIN_NECK_WIDTH=0.20 mm
1/16W
5% TF
1/16W
MF-LF
NO STUFF 402
402 1 C9704 XW9710
SM R9722
R9704 SHOULD BE 47K IF RC FILTER IS USED 33PF 10.2 2
5% BKL_SGND 1 2 1 LED_RETURN_6 6 69 74
OUT
2 50V
CERM MIN_LINE_WIDTH=0.5 mm MIN_LINE_WIDTH=0.5 mm
402 MIN_NECK_WIDTH=0.20 mm 0.1% MIN_NECK_WIDTH=0.20 mm
PLACE XW9700 CLOSE TO C9712 AND C9713 1/16W
TF
402

LCD BACKLIGHT DRIVER

A PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
SYNC_MASTER=K19_MLB

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=02/10/2009
A
353S2670 1 IC,LP8543,WHT LED BKLT,PROD U9701 CRITICAL THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 72 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

CRITICAL
Q9806
FDC638APZ_SBMS001 PPBUS S0 LCDBkLT FET
SSOT6-HF
F9800 MOSFET FDC638APZ

6
2AMP-32V

2 5
CHANNEL P-TYPE

4
PPBUS_G3H 1 2 PPBUS_S0_LCDBKLT_FUSED
64 63 62 60 59 45 44 35 7 6

D
IN
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
RDS(ON) 43 mOhm @4.5V
D

1
1
VOLTAGE=12.6V VOLTAGE=12.6V
0402-HF
R9808 1
C9802
301K
1%
0.1UF LOADING 0.4 A (EDP)

3
10%
1/16W
16V
MF-LF 2 X5R
402
2 402

PPBUS_S0_LCDBKLT_EN_DIV

1
R9809
147K
1%
1/16W
MF-LF
402
2
PPBUS_S0_LCDBKLT_EN_L

Q9807 D 3

SSM6N15FEAPE
SOT563

5 G S PPBUS_S0_LCDBKLT_PWR 72
LVDS_BKL_ON 4 OUT
73 17 8 IN MIN_LINE_WIDTH=0.4 mm
BKLT_EN_L MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V

Q9807 D 6

SSM6N15FEAPE
SOT563

C 24 BKLT_PLT_RST_L
2 G S 1
C
IN

B B

LVDS_BKL_ON 8 17 73

LCD_BKLT_PWM 8 17 72 74

1 1
R9840 R9841
1K 1K
5% 5%
1/16W 1/16W
MF-LF MF-LF
402
2 2 402

MCP HAS INTERNAL 10K PULL-UP FOR THESE SIGNALS

LCD Backlight Support
A SYNC_MASTER=K24_MLB

NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=03/16/2009
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 73 83

8 7 6 5 4 3 2 . 1
 8 7 6 5 4 3 2 1

D D

PLACEMENT_NOTE=Place near L9910

BKLT_FS
NO STUFF
CRITICAL
NO STUFF MIN_LINE_WIDTH=0.5 MM
L9910 CRITICAL
MIN_NECK_WIDTH=0.38 MM
R9901 VOLTAGE=9V 10UH-2.1A D9910
SOD-123
PPVIN_BKL 1
0 2 PPVIN_BKL_U9900 1 2 PPVOUT_S0_LCDBKLT_SW 1 2 PPVOUT_S0_LCDBKLT
72 6 51 69 72
IHLP2020BZ11-SM
MIN_LINE_WIDTH=0.5 MM MIN_LINE_WIDTH=0.5 MM
5% BKLT_FS MIN_NECK_WIDTH=0.38 MM BKLT_FS BKLT_FS BKLT_FS MIN_NECK_WIDTH=0.375 MM
1/8W CRITICAL BKLT_FS VOLTAGE=50V RB160M-60G VOLTAGE=50V
MF-LF C9910 1 1 SWITCH_NODE=TRUE 1 C9915 1 C9916 1 C9917
805
10UF R9930 2.2UF 2.2UF 200PF
PLACEMENT_NOTEs:
10%
25V 2 10
5%
f = 600kHz 10%
2 100V
10%
2 100V
5%
2 100V
X5R X7R X7R CERM
805 1/16W 1210 1210 1206
MF-LF
Place near L9910 & pin1 of U9900 2 402 (PGND)
(C9910-C9911) LCDBKLT_VIN
MIN_LINE_WIDTH=0.3 MM

1
MIN_NECK_WIDTH=0.2 MM
WF: C9911 and C9917 not in ref schematic.
BKLT_FS VIN
1 C9911 PP2V5_S0_LCDBKLT
MIN_LINE_WIDTH=0.3 MM
20 VDC1 SWA 4
0.1UF MIN_NECK_WIDTH=0.2 MM SWB 3
10% VOLTAGE=2.5V
25V
2 X5R
PP5V5_S0_LCDBKLT 23 VDC2 VOUT 24 NO STUFF NO STUFF NO STUFF PLACEMENT_NOTEs:
402
MIN_LINE_WIDTH=0.3 MM
NO STUFF BKLT_FS 1 C9921 1 C9923 1 C9925 C
C BKLT_FS
C9900 1
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5.5V
1 C9901 BKLT_FS
CRITICAL R9915 1
5%
100PF
5%
100PF
5%
100PF Place near U9900
(C9921-C9926)
2.2UF
20%
2.2UF
20%
U9900 1%
1M 50V
2 CERM
402
50V
2 CERM
402
50V
2 CERM
402
10V 2 10V
MC34845 OVP = Vovp * (1 + Ra/Rb) 1/16W
NO STUFF NO STUFF NO STUFF
X5R-CERM 2 X5R-CERM LLP MF-LF
Vovp = 6.5V +/- 0.35V 402 2
402 402
(SGND) <Ra>
C9922 1 C9924 1 C9926 1
OVP 22 LCDBKLT_OVP 100PF 100PF 100PF
5% 5% 5%
50V 50V 50V
LCD_BKLT_PWM 16 CERM 2 CERM 2 CERM 2 R9917
73 72 17 8 IN PWM 402 402 402
18 10.2 2
WAKE CH1 7 BKL_MC_CH1 1 LED_RETURN_1 IN 6 69 72
MIN_LINE_WIDTH=0.5 mm R9918 MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm 0.1% MIN_NECK_WIDTH=0.20 mm
6 1/16W 10.2 2
EN CH2 8 BKL_MC_CH2 TF 1 LED_RETURN_2 IN 6 69 72
MIN_LINE_WIDTH=0.5 mm 402 MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm 0.1% R9919 MIN_NECK_WIDTH=0.20 mm
17 1/16W 10.2 2
LCDBKLT_COMP COMP CH3 9 BKL_MC_CH3 TF 1 LED_RETURN_3 IN 6 69 72
MIN_LINE_WIDTH=0.2 MM MIN_LINE_WIDTH=0.5 mm 402 MIN_LINE_WIDTH=0.5 mm
15 MIN_NECK_WIDTH=0.20 mm R9920 0.1% MIN_NECK_WIDTH=0.20 mm
LCDBKLT_ISET ISET 10.2 2 1/16W
MIN_LINE_WIDTH=0.2 MM CH4 10 BKL_MC_CH4 1 TF LED_RETURN_4 IN 6 69 72
BKLT_FS OMIT MIN_LINE_WIDTH=0.5 mm
0.1% R9921 402 MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm MIN_NECK_WIDTH=0.20 mm
R99051 1
R9910 CH5 11 BKL_MC_CH5
1/16W
TF 1
10.2 2 LED_RETURN_5 IN 6 69 72
6.8K NOSTUFF MIN_LINE_WIDTH=0.5 mm 402
R9922 MIN_LINE_WIDTH=0.5 mm
5% NONE MIN_NECK_WIDTH=0.20 mm 0.1% MIN_NECK_WIDTH=0.20 mm
1/16W NONE 1/16W 10.2 2
MF-LF NONE CH6 12 BKL_MC_CH6 TF 1 LED_RETURN_6 IN 6 69 72
402 2 MIN_LINE_WIDTH=0.5 mm 402 MIN_LINE_WIDTH=0.5 mm
2 402 MIN_NECK_WIDTH=0.20 mm 0.1% MIN_NECK_WIDTH=0.20 mm
LCDBKLT_COMP_RC <Riset> 1/16W
TF
402
FAIL 14 LCDBKLT_FAIL OMIT
BKLT_FS BKLT_FS
R99161

5 PGNDA
2 PGNDB
1 C9905 C9906 1 R99021

GND
0.0022UF 56PF NOSTUFF
10% 5%
THRM
PAD
NO STUFF 0 NONE
50V 50V 5% NONE
2 CERM CERM 2 1/16W NONE
XW9900

13
19
21

25
402 402 MF-LF 402 2
402 2 SM
<Rb>
B ISET = 153mA / <Riset>
GND_LCDBKLT
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
1 2
B
VOLTAGE=0V

13.3 Inch Panel (9 LEDs per string)

PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
114S0298 1 RES,MTL FILM,1/16W,6.65K,1,0402,SMD,LF R9910 ? LCD_13INCH WF: Need 6.65K 0.1% resistor?
114S0445 1 RES,MTL FILM,1/16W,226K,1,0402,SMD,LF R9916 ? LCD_13INCH
Target: ISET = 23mA, OVP = 35V
Actual: ISET = 23mA, OVP = 35.2V

15.4 Inch Panel (10/11 LEDs per string)

PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
114S0298 1 RES,MTL FILM,1/16W,6.65K,1,0402,SMD,LF R9910 ? LCD_15INCH WF: Need 6.65K 0.1% resistor?
114S0438 1 RES,MTL FILM,1/16W,191K,1,0402,SMD,LF R9916 ? LCD_15INCH
Target: ISET = 23mA, OVP = 40V
Actual: ISET = 23mA, OVP = 40.5V
LCD Backlight Driver (MC34845)
SYNC_MASTER=VEMURI_K19I SYNC_DATE=02/09/2009
A 17 Inch Panel (14 LEDs per string) NOTICE OF PROPRIETARY PROPERTY
A
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
114S0299 1 RES,MTL FILM,1/16W,6.81K,1,0402,SMD,LF R9910 ? LCD_17INCH WF: Need 6.80K 0.1% resistor? AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
114S0428 1 RES,MTL FILM,1/16W,150K,1,0402,SMD,LF R9916 ? LCD_17INCH
II NOT TO REPRODUCE OR COPY IT
Target: ISET = 22.5mA, OVP = 50V III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
Actual: ISET = 22.47mA, OVP = 49.8V
SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 74 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
FSB (Front-Side Bus) Constraints CPU / FSB Net Properties
ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

NET_TYPE
PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
FSB_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD
TABLE_PHYSICAL_RULE_ITEM
FSB_DATA_GROUP0 FSB_50S FSB_DATA FSB_D_L<15..0> 6 9 13

FSB_DSTB_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR FSB_DATA_GROUP0 FSB_50S FSB_DATA FSB_DINV_L<0> 6 9 13

FSB_DSTB0 FSB_DSTB_50S FSB_DSTB FSB_DSTB_L_P<0> 6 9 13

FSB 4X Signal Groups

TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_HEAD

FSB_DSTB0 FSB_DSTB_50S FSB_DSTB FSB_DSTB_L_N<0> 6 9 13

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM

FSB_DATA_GROUP1 FSB_50S FSB_DATA FSB_D_L<31..16> 6 9 13

FSB_DATA * =2x_DIELECTRIC ? FSB_DATA TOP,BOTTOM =4x_DIELECTRIC ?
TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM
FSB_DATA_GROUP1 FSB_50S FSB_DATA FSB_DINV_L<1> 6 9 13

FSB_DSTB * =3x_DIELECTRIC ? FSB_DSTB TOP,BOTTOM =5x_DIELECTRIC ? FSB_DSTB1 FSB_DSTB_50S FSB_DSTB FSB_DSTB_L_P<1> 6 9 13

D FSB_ADDR * =STANDARD ?
TABLE_SPACING_RULE_ITEM

FSB_ADDR TOP,BOTTOM =3x_DIELECTRIC ?

TABLE_SPACING_RULE_ITEM

FSB_DSTB1 FSB_DSTB_50S FSB_DSTB FSB_DSTB_L_N<1> 6 9 13

D
TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM

FSB_DATA_GROUP2 FSB_50S FSB_DATA FSB_D_L<47..32> 6 9 13

FSB_ADSTB * =2x_DIELECTRIC ? FSB_ADSTB TOP,BOTTOM =4x_DIELECTRIC ? FSB_DINV_L<2>
TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM
FSB_DATA_GROUP2 FSB_50S FSB_DATA 6 9 13

FSB_1X * =STANDARD ? FSB_1X TOP,BOTTOM =3x_DIELECTRIC ? FSB_DSTB2 FSB_DSTB_50S FSB_DSTB FSB_DSTB_L_P<2> 6 9 13

FSB_DSTB2 FSB_DSTB_50S FSB_DSTB FSB_DSTB_L_N<2> 6 9 13

All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.
FSB_DATA_GROUP3 FSB_50S FSB_DATA FSB_D_L<63..48> 6 9 13
FSB 4X signals / groups shown in signal table on right. FSB_DINV_L<3>
FSB_DATA_GROUP3 FSB_50S FSB_DATA 6 9 13
Signals within each 4x group should be matched within 5 ps of strobe. FSB_DSTB_L_P<3>
FSB_DSTB3 FSB_DSTB_50S FSB_DSTB 6 9 13
DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 300 ps. FSB_DSTB_L_N<3>
FSB_DSTB3 FSB_DSTB_50S FSB_DSTB 6 9 13
Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.
DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs. FSB_ADDR_GROUP0 FSB_50S FSB_ADDR FSB_A_L<16..3> 6 9 13

Signals
FSB 2X
FSB_ADDR_GROUP0 FSB_50S FSB_ADDR FSB_REQ_L<4..0> 6 9 13
FSB 2X signals / groups shown in signal table on right. FSB_ADSTB_L<0>
FSB_ADSTB0 FSB_50S FSB_ADSTB 6 9 13
Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps.
Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#. FSB_ADDR_GROUP1 FSB_50S FSB_ADDR FSB_A_L<35..17> 6 9 13

FSB_ADSTB1 FSB_50S FSB_ADSTB FSB_ADSTB_L<1> 6 9 13

FSB 1X signals shown in signal table on right.
Signals within each 1x group should be matched to CPU clock, +0/-1000 mils. FSB_1X FSB_50S FSB_1X FSB_ADS_L 6 9 13

FSB_BREQ0_L FSB_50S FSB_1X FSB_BREQ0_L 9 13

Design Guide recommends each strobe/signal group is routed on the same layer.

FSB 1X Signals
FSB_BREQ1_L FSB_50S FSB_1X FSB_BREQ1_L 13
Intel Design Guide recommends FSB signals be routed only on internal layers. FSB_BNR_L
FSB_1X FSB_50S FSB_1X 9 13

NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened. FSB_1X FSB_50S FSB_1X FSB_BPRI_L 9 13

FSB_1X FSB_50S FSB_1X FSB_DBSY_L 9 13

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2 FSB_DEFER_L
FSB_1X FSB_50S FSB_1X 9 13
SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3 FSB_DRDY_L
FSB_1X FSB_50S FSB_1X 9 13

FSB_HIT_L
CPU Signal Constraints TABLE_PHYSICAL_RULE_HEAD
FSB_1X
FSB_1X
FSB_50S
FSB_50S
FSB_1X
FSB_1X FSB_HITM_L
6 9 13

6 9 13
ALLOW ROUTE FSB_LOCK_L
C PHYSICAL_RULE_SET

CPU_50S
LAYER

*
ON LAYER?

=50_OHM_SE
MINIMUM LINE WIDTH

=50_OHM_SE
MINIMUM NECK WIDTH

=50_OHM_SE
MAXIMUM NECK LENGTH

=50_OHM_SE
DIFFPAIR PRIMARY GAP

=STANDARD
DIFFPAIR NECK GAP

=STANDARD
TABLE_PHYSICAL_RULE_ITEM
FSB_1X
FSB_CPURST_L
FSB_50S
FSB_50S
FSB_1X
FSB_1X FSB_CPURST_L
6 9 13

9 12 13
C
TABLE_PHYSICAL_RULE_ITEM
FSB_1X FSB_50S FSB_1X FSB_RS_L<2..0> 9 13

CPU_27P4S * =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE 7 MIL 7 MIL FSB_1X FSB_50S FSB_1X FSB_TRDY_L 9 13

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance. CPU_ASYNC CPU_50S CPU_AGTL CPU_A20M_L 9 13

TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_HEAD
CPU_BSEL CPU_50S CPU_AGTL CPU_BSEL<2..0> 8 9

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT CPU_FERR_L CPU_50S CPU_8MIL CPU_FERR_L 9 13
TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM

CPU_ASYNC CPU_50S CPU_AGTL CPU_IGNNE_L 9 13

CPU_AGTL * =STANDARD ? CPU_AGTL TOP,BOTTOM =2x_DIELECTRIC ?
TABLE_SPACING_RULE_ITEM
CPU_INIT_L CPU_50S CPU_AGTL CPU_INIT_L 9 13

CPU_8MIL * 8 MIL ? CPU_ASYNC_R CPU_50S CPU_AGTL CPU_INTR 9 13

TABLE_SPACING_RULE_ITEM

CPU_ASYNC_R CPU_50S CPU_AGTL CPU_NMI 9 13

CPU_COMP * 25 MIL ?
TABLE_SPACING_RULE_ITEM
CPU_PROCHOT_L CPU_50S CPU_AGTL CPU_PROCHOT_L 9 13 41 61

CPU_GTLREF * 25 MIL ? SR DG recommends at least 25 mils, >50 mils preferred CPU_PWRGD CPU_50S CPU_AGTL CPU_PWRGD 9 12 13
TABLE_SPACING_RULE_ITEM

CPU_ASYNC CPU_50S CPU_AGTL CPU_SMI_L 9 13

CPU_ITP * =2:1_SPACING ?
TABLE_SPACING_RULE_ITEM
CPU_ASYNC CPU_50S CPU_AGTL CPU_STPCLK_L 9 13

CPU_VCCSENSE * 25 MIL ? PM_THRMTRIP_L CPU_50S CPU_8MIL PM_THRMTRIP_L 9 13 41

FSB_CPUSLP_L CPU_50S CPU_AGTL FSB_CPUSLP_L 9 13

Most CPU signals with impedance requirements are 55-ohm single-ended. CPU_DPSLP_L
CPU_FROM_SB CPU_50S CPU_AGTL 9 13
Some signals require 27.4-ohm single-ended impedance. CPU_DPRSTP_L
CPU_DPRSTP_L CPU_50S CPU_AGTL 9 13 61

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2 CPU_ASYNC CPU_50S CPU_AGTL FSB_DPWR_L 9 13

SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4 MCP_CPU_COMP MCP_50S MCP_FSB_COMP MCP_BCLK_VML_COMP_VDD 13

MCP_CPU_COMP MCP_50S MCP_FSB_COMP MCP_BCLK_VML_COMP_GND 13

MCP FSB COMP Signal Constraints MCP_CPU_COMP MCP_50S MCP_FSB_COMP MCP_CPU_COMP_VCC 13

ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

MCP_CPU_COMP MCP_50S MCP_FSB_COMP MCP_CPU_COMP_GND 13

PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM

FSB_CLK_CPU CLK_FSB_100D CLK_FSB FSB_CLK_CPU_P 9 13

MCP_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD
FSB_CLK_CPU CLK_FSB_100D CLK_FSB FSB_CLK_CPU_N 9 13

B TABLE_SPACING_RULE_HEAD
FSB_CLK_ITP CLK_FSB_100D CLK_FSB FSB_CLK_ITP_P 12 13 B
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT FSB_CLK_ITP CLK_FSB_100D CLK_FSB FSB_CLK_ITP_N 12 13
TABLE_SPACING_RULE_ITEM

FSB_CLK_MCP CLK_FSB_100D CLK_FSB FSB_CLK_MCP_P 13

MCP_FSB_COMP * 8 MIL ? FSB_CLK_MCP_N
FSB_CLK_MCP CLK_FSB_100D CLK_FSB 13

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4 CPU_IERR_L

CPU_IERR_L CPU_50S 9

FSB Clock Constraints PM_DPRSLPVR CPU_50S CPU_AGTL PM_DPRSLPVR 20 61

ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

(See above) CPU_50S CPU_AGTL IMVP_DPRSLPVR 61

PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM

CPU_GTLREF CPU_50S CPU_GTLREF CPU_GTLREF 9 25

CLK_FSB_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
CPU_COMP CPU_50S CPU_COMP CPU_COMP<3> 9

TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_HEAD
CPU_COMP CPU_27P4S CPU_COMP CPU_COMP<2> 9

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT CPU_COMP CPU_50S CPU_COMP CPU_COMP<1> 9
TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM

CPU_COMP CPU_27P4S CPU_COMP CPU_COMP<0> 9

CLK_FSB * =3x_DIELECTRIC ? CLK_FSB TOP,BOTTOM =4x_DIELECTRIC ?
XDP_TDI CPU_50S CPU_ITP XDP_TDI 9 12
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5 XDP_TDO
XDP_TDO CPU_50S CPU_ITP 1 9 12

XDP_TMS CPU_50S CPU_ITP XDP_TMS 9 12

XDP_TCK CPU_50S CPU_ITP XDP_TCK 9 12

XDP_TRST_L CPU_50S CPU_ITP XDP_TRST_L 9 12

XDP_BPM_L CPU_50S CPU_ITP XDP_BPM_L<4..0> 9 12

XDP_BPM_L5 CPU_50S CPU_ITP XDP_BPM_L<5> 9 12

(FSB_CPURST_L) CPU_50S CPU_ITP XDP_CPURST_L 12

CPU_50S CPU_8MIL CPU_VID<6..0> 8 10

CPU_50S CPU_8MIL IMVP6_VID<6..0> 8 61 CPU/FSB Constraints

CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE_P 10 61
SYNC_MASTER=T18_MLB SYNC_DATE=02/05/2009
A CPU_VCCSENSE
(CPU_VCCSENSE)
CPU_27P4S
CPU_27P4S
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE_N
IMVP6_VSEN_P
10 61

61 NOTICE OF PROPRIETARY PROPERTY

A
(CPU_VCCSENSE) CPU_27P4S CPU_VCCSENSE IMVP6_VSEN_N 61
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 75 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
Memory Bus Constraints Memory Net Properties
ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

NET_TYPE
PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
MEM_40S * =40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE =STANDARD =STANDARD
TABLE_PHYSICAL_RULE_ITEM
MEM_A_CLK MEM_70D_VDD MEM_CLK MEM_A_CLK_P<5..0> 14 26

MEM_40S_VDD * =40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE =STANDARD =STANDARD MEM_A_CLK MEM_70D_VDD MEM_CLK MEM_A_CLK_N<5..0> 14 26
TABLE_PHYSICAL_RULE_ITEM

MEM_70D * =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF MEM_A_CNTL MEM_40S_VDD MEM_CTRL MEM_A_CKE<3..0> 14 26
TABLE_PHYSICAL_RULE_ITEM

MEM_A_CNTL MEM_40S_VDD MEM_CTRL MEM_A_CS_L<3..0> 14 26

MEM_70D_VDD * =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF
MEM_A_CNTL MEM_40S_VDD MEM_CTRL MEM_A_ODT<3..0> 14 26

TABLE_SPACING_RULE_HEAD

MEM_A_CMD MEM_40S_VDD MEM_CMD MEM_A_A<14..0> 14 26

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
MEM_A_CMD MEM_40S_VDD MEM_CMD MEM_A_BA<2..0> 14 26

D MEM_CLK2MEM * =4:1_SPACING ?
TABLE_SPACING_RULE_ITEM

MEM_A_CMD MEM_40S_VDD MEM_CMD MEM_A_RAS_L 14 26 D

TABLE_SPACING_RULE_ITEM

MEM_A_CMD MEM_40S_VDD MEM_CMD MEM_A_CAS_L 14 26

MEM_CTRL2CTRL * =2:1_SPACING ? MEM_A_WE_L
TABLE_SPACING_RULE_ITEM
MEM_A_CMD MEM_40S_VDD MEM_CMD 14 26

MEM_CTRL2MEM * =2.5:1_SPACING ?
TABLE_SPACING_RULE_ITEM
MEM_A_DQ_BYTE0 MEM_40S MEM_DATA MEM_A_DQ<7..0> 14 26

MEM_CMD2CMD * =1.5:1_SPACING ? MEM_A_DQ_BYTE1 MEM_40S MEM_DATA MEM_A_DQ<15..8> 14 26

TABLE_SPACING_RULE_ITEM

MEM_A_DQ_BYTE2 MEM_40S MEM_DATA MEM_A_DQ<23..16> 14 26

MEM_CMD2MEM * =3:1_SPACING ?
TABLE_SPACING_RULE_ITEM
MEM_A_DQ_BYTE3 MEM_40S MEM_DATA MEM_A_DQ<31..24> 14 26

MEM_DATA2DATA * =1.5:1_SPACING ? MEM_A_DQ_BYTE4 MEM_40S MEM_DATA MEM_A_DQ<39..32> 14 26

TABLE_SPACING_RULE_ITEM

MEM_A_DQ_BYTE5 MEM_40S MEM_DATA MEM_A_DQ<47..40> 14 26

MEM_DATA2MEM * =3:1_SPACING ?
TABLE_SPACING_RULE_ITEM
MEM_A_DQ_BYTE6 MEM_40S MEM_DATA MEM_A_DQ<55..48> 14 26

MEM_DQS2MEM * =3:1_SPACING ? MEM_A_DQ_BYTE7 MEM_40S MEM_DATA MEM_A_DQ<63..56> 14 26

TABLE_SPACING_RULE_ITEM

MEM_2OTHER * 25 MIL ? MEM_A_DQ_BYTE0 MEM_40S MEM_DATA MEM_A_DM<0> 14 26

MEM_A_DQ_BYTE1 MEM_40S MEM_DATA MEM_A_DM<1> 14 26

MEM_A_DM<2>
Memory Bus Spacing Group Assignments TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_HEAD
MEM_A_DQ_BYTE2
MEM_A_DQ_BYTE3
MEM_40S
MEM_40S
MEM_DATA
MEM_DATA MEM_A_DM<3>
14 26

14 26

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_A_DQ_BYTE4 MEM_40S MEM_DATA MEM_A_DM<4> 14 26
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_A_DQ_BYTE5 MEM_40S MEM_DATA MEM_A_DM<5> 14 26

MEM_CLK MEM_CLK * MEM_CLK2MEM MEM_CMD MEM_CLK * MEM_CMD2MEM
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DQ_BYTE6 MEM_40S MEM_DATA MEM_A_DM<6> 14 26

MEM_CLK MEM_CTRL * MEM_CLK2MEM MEM_CMD MEM_CTRL * MEM_CMD2MEM MEM_A_DQ_BYTE7 MEM_40S MEM_DATA MEM_A_DM<7> 14 26
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CLK MEM_CMD * MEM_CLK2MEM MEM_CMD MEM_CMD * MEM_CMD2CMD MEM_A_DQS0 MEM_70D MEM_DQS MEM_A_DQS_P<0> 14 26
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_A_DQS0 MEM_70D MEM_DQS MEM_A_DQS_N<0> 14 26

MEM_CLK MEM_DATA * MEM_CLK2MEM MEM_CMD MEM_DATA * MEM_CMD2MEM
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DQS1 MEM_70D MEM_DQS MEM_A_DQS_P<1> 14 26

MEM_CLK MEM_DQS * MEM_CLK2MEM MEM_CMD MEM_DQS * MEM_CMD2MEM MEM_A_DQS1 MEM_70D MEM_DQS MEM_A_DQS_N<1> 14 26

MEM_A_DQS2 MEM_70D MEM_DQS MEM_A_DQS_P<2> 14 26

TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_HEAD

MEM_A_DQS2 MEM_70D MEM_DQS MEM_A_DQS_N<2> 14 26

C NET_SPACING_TYPE1

MEM_CTRL
NET_SPACING_TYPE2

MEM_CLK
AREA_TYPE

*
SPACING_RULE_SET

MEM_CTRL2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
NET_SPACING_TYPE1

MEM_DATA
NET_SPACING_TYPE2

MEM_CLK
AREA_TYPE

*
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DATA2MEM
MEM_A_DQS3
MEM_A_DQS3
MEM_70D
MEM_70D
MEM_DQS
MEM_DQS
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
14 26

14 26
C
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_A_DQS4 MEM_70D MEM_DQS MEM_A_DQS_P<4> 14 26

MEM_CTRL MEM_CTRL * MEM_CTRL2CTRL MEM_DATA MEM_CTRL * MEM_DATA2MEM
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DQS4 MEM_70D MEM_DQS MEM_A_DQS_N<4> 14 26

MEM_CTRL MEM_CMD * MEM_CTRL2MEM MEM_DATA MEM_CMD * MEM_DATA2MEM MEM_A_DQS5 MEM_70D MEM_DQS MEM_A_DQS_P<5> 14 26
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_A_DQS5 MEM_70D MEM_DQS MEM_A_DQS_N<5> 14 26

MEM_CTRL MEM_DATA * MEM_CTRL2MEM MEM_DATA MEM_DATA * MEM_DATA2DATA
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DQS6 MEM_70D MEM_DQS MEM_A_DQS_P<6> 14 26

MEM_CTRL MEM_DQS * MEM_CTRL2MEM MEM_DATA MEM_DQS * MEM_DATA2MEM MEM_A_DQS6 MEM_70D MEM_DQS MEM_A_DQS_N<6> 14 26

MEM_A_DQS7 MEM_70D MEM_DQS MEM_A_DQS_P<7> 14 26

TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_HEAD

MEM_A_DQS7 MEM_70D MEM_DQS MEM_A_DQS_N<7> 14 26

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_B_CLK MEM_70D_VDD MEM_CLK MEM_B_CLK_P<5..0> 14 27

MEM_DQS MEM_CLK * MEM_DQS2MEM MEM_CLK * * MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_CLK MEM_70D_VDD MEM_CLK MEM_B_CLK_N<5..0> 14 27

MEM_DQS MEM_CTRL * MEM_DQS2MEM MEM_CTRL * * MEM_2OTHER

TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_CNTL MEM_40S_VDD MEM_CTRL MEM_B_CKE<3..0> 14 27

MEM_DQS MEM_CMD * MEM_DQS2MEM MEM_CMD * * MEM_2OTHER MEM_B_CNTL MEM_40S_VDD MEM_CTRL MEM_B_CS_L<3..0> 14 27

TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_B_CNTL MEM_40S_VDD MEM_CTRL MEM_B_ODT<3..0> 14 27

MEM_DQS MEM_DATA * MEM_DQS2MEM MEM_DATA * * MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_B_CMD MEM_40S_VDD MEM_CMD MEM_B_A<14..0> 14 27

MEM_DQS MEM_DQS * MEM_DQS2MEM MEM_DQS * * MEM_2OTHER
MEM_B_CMD MEM_40S_VDD MEM_CMD MEM_B_BA<2..0> 14 27

Need to support MEM_*-style wildcards! MEM_B_CMD MEM_40S_VDD MEM_CMD MEM_B_RAS_L 14 27

DDR2: MEM_B_CMD MEM_40S_VDD MEM_CMD MEM_B_CAS_L 14 27

DQ signals should be matched within 20 ps of associated DQS pair. MEM_B_CMD MEM_40S_VDD MEM_CMD MEM_B_WE_L 14 27

DQS intra-pair matching should be within 1 ps, no inter-pair matching requirement. MEM_B_DQ<7..0>
MEM_B_DQ_BYTE0 MEM_40S MEM_DATA 14 27
All DQS pairs should be matched within 100 ps of clocks. MEM_B_DQ<15..8>
MEM_B_DQ_BYTE1 MEM_40S MEM_DATA 14 27
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 140 ps. MEM_B_DQ<23..16>
MEM_B_DQ_BYTE2 MEM_40S MEM_DATA 14 27
A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement. MEM_B_DQ<31..24>
MEM_B_DQ_BYTE3 MEM_40S MEM_DATA 14 27
All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).
B DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.
MEM_B_DQ_BYTE4
MEM_B_DQ_BYTE5
MEM_40S
MEM_40S
MEM_DATA
MEM_DATA
MEM_B_DQ<39..32>
MEM_B_DQ<47..40>
14 27

14 27
B
DDR3: MEM_B_DQ_BYTE6 MEM_40S MEM_DATA MEM_B_DQ<55..48> 14 27

DQ signals should be matched within 5 ps of associated DQS pair. MEM_B_DQ_BYTE7 MEM_40S MEM_DATA MEM_B_DQ<63..56> 14 27

DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps MEM_B_DM<0>
MEM_B_DQ_BYTE0 MEM_40S MEM_DATA 14 27
No DQS to clock matching requirement. MEM_B_DM<1>
MEM_B_DQ_BYTE1 MEM_40S MEM_DATA 14 27
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps. MEM_B_DM<2>
MEM_B_DQ_BYTE2 MEM_40S MEM_DATA 14 27
A/BA/cmd signals should be matched within 5 ps of CLK pairs. MEM_B_DM<3>
MEM_B_DQ_BYTE3 MEM_40S MEM_DATA 14 27
All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate). MEM_B_DM<4>
MEM_B_DQ_BYTE4 MEM_40S MEM_DATA 14 27
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric. MEM_B_DM<5>
MEM_B_DQ_BYTE5 MEM_40S MEM_DATA 14 27

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3 MEM_B_DQ_BYTE6 MEM_40S MEM_DATA MEM_B_DM<6> 14 27

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2 MEM_B_DQ_BYTE7 MEM_40S MEM_DATA MEM_B_DM<7> 14 27

MEM_B_DQS_P<0>
MCP MEM COMP Signal Constraints TABLE_PHYSICAL_RULE_HEAD
MEM_B_DQS0
MEM_B_DQS0
MEM_70D
MEM_70D
MEM_DQS
MEM_DQS MEM_B_DQS_N<0>
14 27

14 27

PHYSICAL_RULE_SET LAYER ALLOW ROUTE

ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MEM_B_DQS1 MEM_70D MEM_DQS MEM_B_DQS_P<1> 14 27
TABLE_PHYSICAL_RULE_ITEM

MEM_B_DQS1 MEM_70D MEM_DQS MEM_B_DQS_N<1> 14 27

MCP_MEM_COMP * Y 7 MIL 7 MIL =STANDARD =STANDARD =STANDARD MEM_B_DQS_P<2>
MEM_B_DQS2 MEM_70D MEM_DQS 14 27

TABLE_SPACING_RULE_HEAD
MEM_B_DQS2 MEM_70D MEM_DQS MEM_B_DQS_N<2> 14 27

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT MEM_B_DQS3 MEM_70D MEM_DQS MEM_B_DQS_P<3> 14 27

TABLE_SPACING_RULE_ITEM

MEM_B_DQS3 MEM_70D MEM_DQS MEM_B_DQS_N<3> 14 27

MCP_MEM_COMP * 8 MIL ?
MEM_B_DQS4 MEM_70D MEM_DQS MEM_B_DQS_P<4> 14 27

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4 MEM_B_DQS4 MEM_70D MEM_DQS MEM_B_DQS_N<4> 14 27

MEM_B_DQS5 MEM_70D MEM_DQS MEM_B_DQS_P<5> 14 27

MEM_B_DQS5 MEM_70D MEM_DQS MEM_B_DQS_N<5> 14 27 Memory Constraints

MEM_B_DQS6 MEM_70D MEM_DQS MEM_B_DQS_P<6> 14 27
SYNC_MASTER=T18_MLB SYNC_DATE=02/05/2009
A MEM_B_DQS6
MEM_B_DQS7
MEM_70D
MEM_70D
MEM_DQS
MEM_DQS
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
14 27

14 27 NOTICE OF PROPRIETARY PROPERTY

A
MEM_B_DQS7 MEM_70D MEM_DQS MEM_B_DQS_N<7> 14 27
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP_VDD 15 AGREES TO THE FOLLOWING
MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP_GND 15 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 76 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
PCI-Express
ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

NET_TYPE
PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
PCIE_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
PCIE_90D PCIE PEG_R2D_P<15..0>
CLK_PCIE_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF PCIE_90D PCIE PEG_R2D_N<15..0>
PEG_R2D PCIE_90D PCIE PEG_R2D_C_P<15..0>
TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_HEAD

PCIE_90D PCIE PEG_R2D_C_N<15..0>

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM
PEG_D2R PCIE_90D PCIE PEG_D2R_P<15..0>
PCIE * =3X_DIELECTRIC ? PCIE TOP,BOTTOM =4X_DIELECTRIC ? PCIE_90D PCIE PEG_D2R_N<15..0>
TABLE_SPACING_RULE_ITEM

PCIE_90D PCIE PEG_D2R_C_P<15..0>

CLK_PCIE * 20 MIL ? PEG_D2R_C_N<15..0>
PCIE_90D PCIE
D MCP_PEX_COMP * 8 MIL ?
TABLE_SPACING_RULE_ITEM

PCIE_90D PCIE PCIE_MINI_R2D_P 6 29 82

D
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4 PCIE_90D PCIE PCIE_MINI_R2D_N 6 29 82

PCIE_MINI_R2D PCIE_90D PCIE PCIE_MINI_R2D_C_P 16 29

Analog Video Signal Constraints PCIE_90D PCIE PCIE_MINI_R2D_C_N 16 29

ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

PCIE_MINI_D2R PCIE_90D PCIE PCIE_MINI_D2R_P 6 16 29

PHYSICAL_RULE_SET LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM
PCIE_90D PCIE PCIE_MINI_D2R_N 6 16 29

CRT_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD

PCIE_90D PCIE PCIE_FW_R2D_P 34

TABLE_SPACING_RULE_HEAD TABLE_SPACING_ASSIGNMENT_HEAD
PCIE_90D PCIE PCIE_FW_R2D_N 34

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET PCIE_FW_R2D PCIE_90D PCIE PCIE_FW_R2D_C_P 16 34
TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

PCIE_90D PCIE PCIE_FW_R2D_C_N 16 34

CRT * =4:1_SPACING ? CRT CRT * CRT_2CRT
TABLE_SPACING_RULE_ITEM
PCIE_FW_D2R PCIE_90D PCIE PCIE_FW_D2R_P 16 34

CRT_2CRT * =STANDARD ? PCIE_90D PCIE PCIE_FW_D2R_N 16 34

TABLE_SPACING_RULE_ITEM

PCIE_90D PCIE PCIE_FW_D2R_C_P 34

CRT_2CLK * 50 MIL ?
TABLE_SPACING_RULE_ITEM
PCIE_90D PCIE PCIE_FW_D2R_C_N 34

CRT_2SWITCHER * 250 MIL ?

TABLE_SPACING_RULE_ITEM
PCIE_90D PCIE PCIE_EXCARD_R2D_P
CRT_SYNC * 16 MIL ? PCIE_90D PCIE PCIE_EXCARD_R2D_N
TABLE_SPACING_RULE_ITEM

PCIE_EXCARD_R2D PCIE_90D PCIE NC_PCIE_EXCARD_R2DCP 8 16

MCP_DAC_COMP * =2:1_SPACING ?
PCIE_90D PCIE NC_PCIE_EXCARD_R2DCN 8 16

CRT signal single-ended impedence varies by location: PCIE_EXCARD_D2R PCIE_90D PCIE NC_PCIE_EXCARD_D2RP 8 16

- 37.5-ohm from MCP to first termination resistor. PCIE_90D PCIE NC_PCIE_EXCARD_D2RN 8 16

- 50-ohm from first to second termination resistor. NC_PEG_CLK100MP

MCP_PE0_REFCLK CLK_PCIE_100D CLK_PCIE 8 16
- 75-ohm from output of three-pole filter to connector (if possible). NC_PEG_CLK100MN
CLK_PCIE_100D CLK_PCIE 8 16
R/G/B signals should be matched as close as possible and < 10 inches. PCIE_CLK100M_MINI_P
MCP_PE1_REFCLK CLK_PCIE_100D CLK_PCIE 16 29
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.1 & 2.5.2. PCIE_CLK100M_MINI_N
CLK_PCIE_100D CLK_PCIE 16 29

PCIE_CLK100M_FW_P
C Digital Video Signal Constraints TABLE_PHYSICAL_RULE_HEAD
MCP_PE2_REFCLK CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE PCIE_CLK100M_FW_N
16 34

16 34
C
PHYSICAL_RULE_SET LAYER ALLOW ROUTE
ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MCP_PE3_REFCLK CLK_PCIE_100D CLK_PCIE NC_PCIE_CLK100M_EXCARDP 8 16
TABLE_PHYSICAL_RULE_ITEM

CLK_PCIE_100D CLK_PCIE NC_PCIE_CLK100M_EXCARDN 8 16

DP_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
MCP_PEX_CLK_COMP MCP_PEX_COMP MCP_PEX_CLK_COMP 16

LVDS_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

TABLE_PHYSICAL_RULE_ITEM
CRT_RED CRT_50S CRT NC_CRT_IG_R_C_PR 17 23

MCP_DV_COMP * Y 20 MIL 20 MIL =STANDARD =STANDARD =STANDARD CRT_GREEN CRT_50S CRT NC_CRT_IG_G_Y_Y 17 23

CRT_BLUE CRT_50S CRT NC_CRT_IG_B_COMP_PB 17 23

TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_HEAD

CRT_SYNC CRT_50S CRT_SYNC NC_CRT_IG_HSYNC 17 23

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM
CRT_SYNC CRT_50S CRT_SYNC NC_CRT_IG_VSYNC 17 23

DISPLAYPORT * =3x_DIELECTRIC ? DISPLAYPORT TOP,BOTTOM =4x_DIELECTRIC ? MCP_DAC_RSET MCP_DAC_COMP NC_MCP_TV_DAC_RSET 17 23

TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM

MCP_DAC_VREF MCP_DAC_COMP NC_MCP_TV_DAC_VREF 17 23

LVDS * =3x_DIELECTRIC ? LVDS TOP,BOTTOM =4x_DIELECTRIC ?
TMDS_IG_TXC DP_100D DISPLAYPORT TMDS_IG_TXC_P
LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length. TMDS_IG_TXC_N
TMDS_IG_TXC DP_100D DISPLAYPORT
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps. TMDS_IG_TXD_P<2..0>
TMDS_IG_TXD DP_100D DISPLAYPORT
DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals. TMDS_IG_TXD_N<2..0>
TMDS_IG_TXD DP_100D DISPLAYPORT
Max length of LVDS/DisplayPort/TMDS traces: 12 inches.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4. DP_ML DP_100D DISPLAYPORT DP_IG_ML_P<3..0>
DP_ML DP_100D DISPLAYPORT DP_IG_ML_N<3..0>
SATA Interface Constraints DP_AUX_CH DP_100D DISPLAYPORT DP_IG_AUX_CH_P 17 70

ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

DP_AUX_CH DP_100D DISPLAYPORT DP_IG_AUX_CH_N 17 70

PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM

MCP_HDMI_RSET MCP_DV_COMP MCP_HDMI_RSET 17 23

SATA_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF MCP_HDMI_VPROBE
MCP_HDMI_VPROBE MCP_DV_COMP 17 23

TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_HEAD

LVDS_IG_A_CLK LVDS_100D LVDS LVDS_CONN_A_CLK_P 8 17 69

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM
LVDS_IG_A_CLK LVDS_100D LVDS LVDS_CONN_A_CLK_N 8 17 69

B SATA * =4x_DIELECTRIC ?
TABLE_SPACING_RULE_ITEM
SATA TOP,BOTTOM =3x_DIELECTRIC ? LVDS_IG_A_DATA
LVDS_IG_A_DATA
LVDS_100D
LVDS_100D
LVDS
LVDS
LVDS_IG_A_DATA_P<2..0>
LVDS_IG_A_DATA_N<2..0>
8 17

8 17
B
SATA_TERMP * 8 MIL ? NC_LVDS_IG_A_DATAP<3>
LVDS_IG_A_DATA3 LVDS_100D LVDS 8 17

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1. LVDS_IG_A_DATA3 LVDS_100D LVDS NC_LVDS_IG_A_DATAN<3> 8 17

LVDS_IG_B_CLK LVDS_100D LVDS LVDS_CONN_B_CLK_P 8 17 69

LVDS_IG_B_CLK LVDS_100D LVDS LVDS_CONN_B_CLK_N 8 17 69

LVDS_IG_B_DATA LVDS_100D LVDS LVDS_IG_B_DATA_P<2..0> 8 17

LVDS_IG_B_DATA LVDS_100D LVDS LVDS_IG_B_DATA_N<2..0> 8 17

LVDS_IG_B_DATA3 LVDS_100D LVDS NC_LVDS_IG_B_DATAP<3> 8 17

LVDS_IG_B_DATA3 LVDS_100D LVDS NC_LVDS_IG_B_DATAN<3> 8 17

MCP_IFPAB_RSET MCP_DV_COMP MCP_IFPAB_RSET 17 23

MCP_IFPAB_VPROBE MCP_IFPAB_VPROBE 17 23

SATA_HDD_R2D SATA_100D SATA SATA_HDD_R2D_C_P 19 37

SATA_100D SATA SATA_HDD_R2D_C_N 19 37

SATA_100D SATA SATA_HDD_R2D_P 6 37

SATA_100D SATA SATA_HDD_R2D_N 6 37

SATA_HDD_D2R SATA_100D SATA SATA_HDD_D2R_P 19 37

SATA_100D SATA SATA_HDD_D2R_N 19 37

SATA_100D SATA SATA_HDD_D2R_C_P 6 37

SATA_100D SATA SATA_HDD_D2R_C_N 6 37

SATA_ODD_R2D SATA_100D SATA SATA_ODD_R2D_C_P 19 37

SATA_100D SATA SATA_ODD_R2D_C_N 19 37

SATA_100D SATA SATA_ODD_R2D_P 6 37

SATA_100D SATA SATA_ODD_R2D_N 6 37 MCP Constraints 1

SATA_ODD_D2R SATA_100D SATA SATA_ODD_D2R_P 19 37
SYNC_MASTER=T18_MLB SYNC_DATE=02/05/2009
A SATA_100D
SATA_100D
SATA
SATA
SATA_ODD_D2R_N
SATA_ODD_D2R_C_P
19 37

6 37 NOTICE OF PROPRIETARY PROPERTY

A
SATA_100D SATA SATA_ODD_D2R_C_N 6 37
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
MCP_SATA_TERMP SATA_TERMP MCP_SATA_TERMP 19 AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 77 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
PCI Bus Constraints
ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

NET_TYPE
PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
PCI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
TABLE_PHYSICAL_RULE_ITEM
MCP_DEBUG PCI_55S PCI MCP_DEBUG<7..0> 12 18

CLK_PCI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD PCI_AD PCI_55S PCI PCI_AD<23..8>
PCI_AD24 PCI_55S PCI PCI_AD<24>
TABLE_SPACING_RULE_HEAD

PCI_AD PCI_55S PCI PCI_AD<31..25>

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_ITEM
PCI_AD PCI_55S PCI PCI_PAR
PCI * =STANDARD ? PCI_C_BE_L PCI_55S PCI PCI_C_BE_L<3..0>
TABLE_SPACING_RULE_ITEM

PCI_CNTL PCI_55S PCI PCI_IRDY_L

CLK_PCI * 8 MIL ? PCI_DEVSEL_L
PCI_CNTL PCI_55S PCI
D SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.
PCI_CNTL PCI_55S PCI PCI_PERR_L D
PCI_CNTL PCI_55S PCI PCI_SERR_L
PCI_STOP_L
LPC Bus Constraints TABLE_PHYSICAL_RULE_HEAD
PCI_CNTL
PCI_CNTL
PCI_55S
PCI_55S
PCI
PCI PCI_TRDY_L
PHYSICAL_RULE_SET LAYER ALLOW ROUTE
ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCI_CNTL PCI_55S PCI PCI_FRAME_L
TABLE_PHYSICAL_RULE_ITEM

PCI_REQ0_L PCI_55S PCI PCI_REQ0_L 18

LPC_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
TABLE_PHYSICAL_RULE_ITEM
PCI_GNT0_L PCI_55S PCI PCI_GNT0_L
CLK_LPC_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD PCI_REQ1_L PCI_55S PCI PCI_REQ1_L 18

PCI_GNT1_L PCI_55S PCI PCI_GNT1_L

TABLE_SPACING_RULE_HEAD

PCI_INTW_L PCI_55S PCI PCI_INTW_L

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_ITEM
PCI_INTX_L PCI_55S PCI PCI_INTX_L
LPC * 6 MIL ? PCI_INTY_L PCI_55S PCI PCI_INTY_L
TABLE_SPACING_RULE_ITEM

PCI_INTZ_L PCI_55S PCI PCI_INTZ_L

CLK_LPC * 8 MIL ?
MCP_PCI_CLK2 CLK_PCI_55S CLK_PCI PCI_CLK33M_MCP_R 18

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.9.1. CLK_PCI_55S CLK_PCI PCI_CLK33M_MCP 18

LPC_AD<3..0>
USB 2.0 Interface Constraints TABLE_PHYSICAL_RULE_HEAD
LPC_AD
LPC_FRAME_L
LPC_55S
LPC_55S
LPC
LPC LPC_FRAME_L
18 40 42

18 40 42

PHYSICAL_RULE_SET LAYER ALLOW ROUTE

ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP LPC_RESET_L LPC_55S LPC LPC_RESET_L 18 24
TABLE_PHYSICAL_RULE_ITEM

MCP_USB_RBIAS * =STANDARD 8 MIL 8 MIL =STANDARD =STANDARD =STANDARD MCP_LPC_CLK0 CLK_LPC_55S CLK_LPC LPC_CLK33M_SMC_R 18 24
TABLE_PHYSICAL_RULE_ITEM

CLK_LPC_55S CLK_LPC LPC_CLK33M_SMC 24 40

USB_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF
CLK_LPC_55S CLK_LPC LPC_CLK33M_LPCPLUS 24 42

TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_HEAD

USB_EXTA USB_90D USB USB_EXTA_P 19 38

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM
USB_90D USB USB_EXTA_N 19 38

USB * =2x_DIELECTRIC ? USB TOP,BOTTOM =4x_DIELECTRIC ? USB_90D USB USB_EXTA_MUXED_P

USB_EXTA_MUXED_N
C SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.10.1. USB_MINI
USB_90D
USB_90D
USB
USB NC_USB_MINIP 8 19
C
USB_90D USB NC_USB_MININ 8 19

SMBus Interface Constraints USB_EXTD USB_90D USB NC_USB_EXTDP 8 19

ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

USB_90D USB NC_USB_EXTDN 8 19

PHYSICAL_RULE_SET LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM
USB_CAMERA USB_90D USB USB_CAMERA_P 6 19 29

SMB_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD USB_90D USB USB_CAMERA_N 6 19 29

USB_BT USB_90D USB USB_BT_P 6 19 29

TABLE_SPACING_RULE_HEAD

USB_90D USB USB_BT_N 6 19 29

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_ITEM
USB_TPAD USB_90D USB USB_TPAD_P 19 48

SMB * =2x_DIELECTRIC ? USB_90D USB USB_TPAD_N 19 48

USB_IR USB_90D USB USB_IR_P 19 39

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.11.1. USB_90D USB USB_IR_N 19 39

USB_EXTB USB_90D USB USB_EXTB_P 19 38

HD Audio Interface Constraints USB_90D USB USB_EXTB_N 19 38

ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

USB_EXCARD USB_90D USB NC_USB_EXCARDP 8 19

PHYSICAL_RULE_SET LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM
USB_90D USB NC_USB_EXCARDN 8 19

HDA_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD USB_EXTC USB_90D USB NC_USB_EXTCP 8 19

USB_90D USB NC_USB_EXTCN 8 19

TABLE_SPACING_RULE_HEAD

USB_CARDREADER USB_90D USB USB_CARDREADER_P 19 30

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_ITEM
USB_90D USB USB_CARDREADER_N 19 30

HDA * =2x_DIELECTRIC ? MCP_USB_RBIAS_GND

TABLE_SPACING_RULE_ITEM
MCP_USB_RBIAS MCP_USB_RBIAS 19

MCP_HDA_COMP * 8 MIL ? SMBUS_MCP_0_CLK

SMBUS_MCP_0_CLK SMB_55S SMB 12 20 26 27 43

SMBUS_MCP_0_DATA SMB_55S SMB SMBUS_MCP_0_DATA 12 20 26 43

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.12.1. SMBUS_MCP_1_CLK
SMBUS_MCP_1_CLK SMB_55S SMB 20 43 58 72

SMBUS_MCP_1_DATA
B SIO Signal Constraints
SMBUS_MCP_1_DATA SMB_55S SMB 20 43 58 72

ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

HDA_BIT_CLK HDA_55S HDA HDA_BIT_CLK 20 53

B
PHYSICAL_RULE_SET LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM
HDA_55S HDA HDA_BIT_CLK_R 20

CLK_SLOW_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD HDA_SYNC HDA_55S HDA HDA_SYNC 20 53

HDA_55S HDA HDA_SYNC_R 20

TABLE_SPACING_RULE_HEAD

HDA_RST_L HDA_55S HDA HDA_RST_R_L 20

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_ITEM
HDA_55S HDA HDA_RST_L 20 53

CLK_SLOW * 8 MIL ? HDA_SDIN0 HDA_55S HDA HDA_SDIN0 20 53

HDA_55S HDA HDA_SDIN_CODEC

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.13. HDA_SDOUT HDA_55S HDA HDA_SDOUT 20 53

HDA_55S HDA HDA_SDOUT_R 20

SPI Interface Constraints TABLE_PHYSICAL_RULE_HEAD

MCP_HDA_PULLDN_COMP MCP_HDA_COMP MCP_HDA_PULLDN_COMP 20

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM
MCP_SUS_CLK CLK_SLOW_55S CLK_SLOW PM_CLK32K_SUSCLK_R 20 24

SPI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD CLK_SLOW_55S CLK_SLOW PM_CLK32K_SUSCLK 24 40

TABLE_SPACING_RULE_HEAD
SPI_CLK SPI_55S SPI SPI_CLK_R 20 42

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPI_55S SPI SPI_CLK 52

TABLE_SPACING_RULE_ITEM

SPI_MOSI SPI_55S SPI SPI_MOSI_R 20 42

SPI * 8 MIL ? SPI_MOSI
SPI_55S SPI 52

SPI_MISO SPI_55S SPI SPI_MISO 20 42

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.14. SPI_MISO_R
SPI_55S SPI 52

SPI_CS0 SPI_55S SPI SPI_CS0_R_L 20 42

SPI_55S SPI SPI_CS0_L

MCP Constraints 2
SYNC_MASTER=T18_MLB SYNC_DATE=02/05/2009
A NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 78 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
MCP RGMII (Ethernet) Constraints
ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

NET_TYPE
PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
MCP_MII_COMP * =STANDARD 7.5 MIL 7.5 MIL =STANDARD =STANDARD =STANDARD
TABLE_PHYSICAL_RULE_ITEM
MCP_MII_COMP MCP_MII_COMP MCP_MII_COMP_VDD 17

ENET_MII_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD MCP_MII_COMP MCP_MII_COMP MCP_MII_COMP_GND 17

TABLE_SPACING_RULE_HEAD
MCP_CLK25M_BUF0 ENET_MII_55S MCP_BUF0_CLK MCP_CLK25M_BUF0_R 17 32

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT ENET_MII_55S MCP_BUF0_CLK RTL8211_CLK25M_CKXTAL1 31 32

TABLE_SPACING_RULE_ITEM

MCP_BUF0_CLK * =3:1_SPACING ? ENET_INTR_L ENET_MII_55S ENET_MII ENET_INTR_L

TABLE_SPACING_RULE_ITEM

ENET_MDIO ENET_MII_55S ENET_MII ENET_MDIO 17 31

ENET_MII * 12 MIL ? ENET_MDC
ENET_MDC ENET_MII_55S ENET_MII 17 31

D SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4

ENET_PWRDWN_L ENET_MII_55S ENET_MII ENET_PWRDWN_L D
ENET_MII_55S ENET_MII ENET_CLK125M_RXCLK_R 31

88E1116R (Ethernet PHY) Constraints ENET_RXCLK ENET_MII_55S ENET_MII ENET_CLK125M_RXCLK 17 31

ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

ENET_MII_55S ENET_MII ENET_RXD_R<3..0> 31

PHYSICAL_RULE_SET LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM
ENET_RXD ENET_MII_55S ENET_MII ENET_RXD<0> 17 31

ENET_MDI_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF ENET_RXD_STRAP ENET_MII_55S ENET_MII ENET_RXD<3..1> 17 31

ENET_RXD ENET_MII_55S ENET_MII ENET_RX_CTRL 17 31

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT ENET_TXCLK ENET_MII_55S ENET_MII ENET_CLK125M_TXCLK 17 31

TABLE_SPACING_RULE_ITEM

ENET_TXD0 ENET_MII_55S ENET_MII ENET_TXD<0> 17 31

ENET_MDI * 25 MIL ? ENET_TXD<3..1>
ENET_TXD ENET_MII_55S ENET_MII 17 31

ENET_TXD ENET_MII_55S ENET_MII ENET_TX_CTRL 17 31

SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4
ENET_MII_55S ENET_MII ENET_RESET_L 17 31

ENET_MDI ENET_MDI_100D ENET_MDI ENET_MDI_P<3..0> 31 33

ENET_MDI_100D ENET_MDI ENET_MDI_N<3..0> 31 33

C C

B B

Ethernet Constraints
SYNC_MASTER=T18_MLB SYNC_DATE=02/05/2009
A NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 79 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
FireWire Interface Constraints FireWire Net Properties
ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

NET_TYPE
PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
FW_110D * =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF
FW_P0_TPA FW_110D FW_TP NC_FW0_TPAP 34 36

TABLE_SPACING_RULE_HEAD
FW_P0_TPA FW_110D FW_TP NC_FW0_TPAN 34 36

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT FW_P0_TPB FW_110D FW_TP NC_FW0_TPBP 34 36

TABLE_SPACING_RULE_ITEM

FW_P0_TPB FW_110D FW_TP NC_FW0_TPBN 34 36

FW_TP * =3:1_SPACING ? FW_PORT1_TPA_P
FW_P1_TPA FW_110D FW_TP 34 36

FW_P1_TPA FW_110D FW_TP FW_PORT1_TPA_N 34 36

FW_P1_TPB FW_110D FW_TP FW_PORT1_TPB_P 34 36

FW_P1_TPB FW_110D FW_TP FW_PORT1_TPB_N 34 36

D D
Port 2 Not Used

C C

B B

FireWire Constraints
SYNC_MASTER=T18_MLB SYNC_DATE=02/05/2009
A NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 80 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
SMC SMBus Net Properties
ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

NET_TYPE
PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
1TO1_DIFFPAIR * =STANDARD =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM
SMBUS_SMC_A_S3_SCL SMB_55S SMB SMBUS_SMC_A_S3_SCL 6 29 40 43 49

SMBUS_SMC_A_S3_SDA SMB_55S SMB SMBUS_SMC_A_S3_SDA 6 29 40 43 49

SMBUS_SMC_B_S0_SCL SMB_55S SMB SMBUS_SMC_B_S0_SCL 40 43 46

SMBUS_SMC_B_S0_SDA SMB_55S SMB SMBUS_SMC_B_S0_SDA 40 43 46

SMBUS_SMC_0_S0_SCL SMB_55S SMB SMBUS_SMC_0_S0_SCL 40 43 46 51

SMBUS_SMC_0_S0_SDA SMB_55S SMB SMBUS_SMC_0_S0_SDA 40 43 46 51

SMBUS_SMC_BSA_SCL SMB_55S SMB SMBUS_SMC_BSA_SCL 6 40 43 59 60

SMBUS_SMC_BSA_SDA SMB_55S SMB SMBUS_SMC_BSA_SDA 6 40 43 59 60

D SMBUS_SMC_MGMT_SCL SMB_55S SMB SMBUS_SMC_MGMT_SCL 25 37 40 43 D

SMBUS_SMC_MGMT_SDA SMB_55S SMB SMBUS_SMC_MGMT_SDA 25 37 40 43

SMBus Charger Net Properties

NET_TYPE
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING

CHGR_CSI 1TO1_DIFFPAIR CHGR_CSI_P 60

1TO1_DIFFPAIR CHGR_CSI_N 60

CHGR_CSO 1TO1_DIFFPAIR CHGR_CSO_P 60

1TO1_DIFFPAIR CHGR_CSO_N 60

C C

B B

SMC Constraints
SYNC_MASTER=T18_MLB SYNC_DATE=02/05/2009
A NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 81 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_HEAD

K19i Specific Net Properties K19i Specific Net Properties

ON LAYER? NET_TYPE NET_TYPE
TABLE_PHYSICAL_RULE_ITEM

SENSE_1TO1_55S * =1:1_DIFFPAIR =55_OHM_SE =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
TABLE_PHYSICAL_RULE_ITEM

THERM_1TO1_55S * =1:1_DIFFPAIR =55_OHM_SE =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR ENET_MDI_100D ENETCONN ENETCONN_P<3..0> 33 PCIE_90D PCIE PCIE_MINI_R2D_P 6 29 77
TABLE_PHYSICAL_RULE_ITEM

ENET_MDI_100D ENETCONN ENETCONN_N<3..0> 33 (PCIE_MINI) PCIE_90D PCIE PCIE_MINI_R2D_N 6 29 77

DIFFPAIR * =1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR
SATA_100D SATA SATA_ODD_R2D_UF_P 37 (PCIE_MINI) CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_MINI_CONN_P 6 29

SATA_100D SATA SATA_ODD_R2D_UF_N 37 CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_MINI_CONN_N 6 29

SATA_100D SATA SATA_ODD_D2R_UF_P 6 37 1TO1_DIFFPAIR CHGR_CSI_R_P 60

TABLE_SPACING_RULE_HEAD

SATA_100D SATA SATA_ODD_D2R_UF_N 6 37 1TO1_DIFFPAIR CHGR_CSI_R_N 60

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_ITEM
SATA_100D SATA SATA_HDD_D2R_UF_P 37 1TO1_DIFFPAIR CHGR_CSO_R_P 45 60

D SENSE * =2:1_SPACING ?
TABLE_SPACING_RULE_ITEM
SATA_100D
SATA_100D
SATA
SATA
SATA_HDD_D2R_UF_N
SATA_HDD_R2D_UF_P
37

37 (USB_EXTA)
1TO1_DIFFPAIR
USB_90D USB
CHGR_CSO_R_N
USB2_EXTA_MUXED_P
45 60

38
D
THERM * =2:1_SPACING ?
TABLE_SPACING_RULE_ITEM
SATA_100D SATA SATA_HDD_R2D_UF_N 37 (USB_EXTA) USB_90D USB USB2_EXTA_MUXED_N 38

AUDIO * =2:1_SPACING ? (USB_EXTA) USB_90D USB USB2_LT1_P 38

CPUTHMSNS_D2 THERM_1TO1_55S THERM CPUTHMSNS_D2_P 46
(USB_EXTA) USB_90D USB USB2_LT1_N 38
THERM_1TO1_55S THERM CPUTHMSNS_D2_N 46
(USB_TPAD) USB_90D USB USB_TPAD_R_P 48
CPU_THERMD THERM_1TO1_55S THERM CPU_THERMD_P 9 46
(USB_TPAD) USB_90D USB USB_TPAD_R_N 48
TABLE_SPACING_RULE_HEAD

THERM_1TO1_55S THERM CPU_THERMD_N 9 46

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT (USB_CAMERA) USB_90D USB USB_CAMERA_CONN_P 6 29
MCPTHMSNS_D2 THERM_1TO1_55S THERM MCPTHMSNS_D2_P 46
TABLE_SPACING_RULE_ITEM

(USB_CAMERA) USB_90D USB USB_CAMERA_CONN_N 6 29

ENETCONN * 25 MILS ? THERM_1TO1_55S THERM MCPTHMSNS_D2_N 46
USB_90D USB CONN_USB2_BT_P 6 29
MCP_THMDIODE THERM_1TO1_55S THERM MCP_THMDIODE_P 20 46
USB_90D USB CONN_USB2_BT_N 6 29
TABLE_SPACING_RULE_HEAD

THERM_1TO1_55S THERM MCP_THMDIODE_N 20 46

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT USB_90D USB USB_LT2_P 38
SENSE_DIFFPAIR SENSE_1TO1_55S SENSE ISNS_1V5_S3_P 51 63
TABLE_SPACING_RULE_ITEM

USB_90D USB USB_LT2_N 38

GND * =STANDARD ? SENSE_1TO1_55S SENSE ISNS_1V5_S3_N 51 63
DP_100D DISPLAYPORT DP_AUX_CH_SW_P 70
TABLE_SPACING_RULE_ITEM

SENSE_1TO1_55S SENSE ISNS_1V5_S3_R_P 51

PP1V8_MEM * =STANDARD ? DP_100D DISPLAYPORT DP_AUX_CH_SW_N 70
SENSE_1TO1_55S SENSE ISNS_1V5_S3_R_N 51
SPK_OUT DIFFPAIR AUDIO SPKRCONN_L_OUT_P 6 56 57
SENSE_DIFFPAIR SENSE_1TO1_55S SENSE ISNS_AIRPORT_P 29 51
TABLE_SPACING_RULE_HEAD

DIFFPAIR AUDIO SPKRCONN_L_OUT_N 6 56 57

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SENSE_1TO1_55S SENSE ISNS_AIRPORT_N 29 51
SPK_OUT DIFFPAIR AUDIO SPKRCONN_S_OUT_P 6 56 57
TABLE_SPACING_RULE_ITEM

SENSE_1TO1_55S SENSE ISNS_AIRPORT_R_P 51

GND_P2MM * 0.20 MM 1000 DIFFPAIR AUDIO SPKRCONN_S_OUT_N 6 56 57
SENSE_1TO1_55S SENSE ISNS_AIRPORT_R_N 51
TABLE_SPACING_RULE_ITEM
SPK_OUT DIFFPAIR AUDIO SPKRCONN_R_OUT_P 6 56 57
PWR_P2MM * 0.20 MM 1000 SENSE_DIFFPAIR SENSE_1TO1_55S SENSE ISNS_HDD_P 37 51
DIFFPAIR AUDIO SPKRCONN_R_OUT_N 6 56 57
SENSE_1TO1_55S SENSE ISNS_HDD_N 37 51
DIFFPAIR AUDIO SPKRAMP_L_OUT_P 56
TABLE_SPACING_ASSIGNMENT_HEAD

SENSE_1TO1_55S SENSE ISNS_HDD_R_P 51

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET DIFFPAIR AUDIO SPKRAMP_L_OUT_N 56
SENSE_1TO1_55S SENSE ISNS_HDD_R_N 51
TABLE_SPACING_ASSIGNMENT_ITEM

DIFFPAIR AUDIO SPKRAMP_R_OUT_P 56

MEM_CLK GND * GND_P2MM SENSE_DIFFPAIR SENSE_1TO1_55S SENSE ISNS_LCDBKLT_P 51 72
DIFFPAIR AUDIO SPKRAMP_R_OUT_N 56
TABLE_SPACING_ASSIGNMENT_ITEM

SENSE_1TO1_55S SENSE ISNS_LCDBKLT_N 51 72

MEM_CMD GND * GND_P2MM DIFFPAIR AUDIO SPKRAMP_S_OUT_P 56
SENSE_1TO1_55S SENSE ISNS_LCDBKLT_R_P
TABLE_SPACING_ASSIGNMENT_ITEM

DIFFPAIR AUDIO SPKRAMP_S_OUT_N 56

ISNS_LCDBKLT_R_N
C MEM_CTRL

MEM_DATA
GND

GND
*

*
GND_P2MM

GND_P2MM
TABLE_SPACING_ASSIGNMENT_ITEM

SENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE
SENSE ISNS_ODD_P 37 51
C
TABLE_SPACING_ASSIGNMENT_ITEM
SENSE_1TO1_55S SENSE ISNS_ODD_N 37 51 K19i Specific Graphics Net Properties
MEM_DQS GND * GND_P2MM SENSE_1TO1_55S SENSE ISNS_ODD_R_P 51 NET_TYPE
TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_HEAD
SENSE_1TO1_55S SENSE ISNS_ODD_R_N 51 ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET SENSE_DIFFPAIR SENSE_1TO1_55S SENSE ISNS_CPUVTT_P 45
LVDS_100D LVDS LVDS_CONN_A_CLK_F_P 6 69
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

SENSE_1TO1_55S SENSE ISNS_CPUVTT_N 45

CLK_PCIE GND * GND_P2MM CLK_FSB GND * GND_P2MM LVDS_100D LVDS LVDS_CONN_A_CLK_F_N 6 69
SENSE_DIFFPAIR SENSE_1TO1_55S SENSE MCPCORES0_RSEN_P 64
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

LVDS_100D LVDS LVDS_CONN_B_CLK_F_P 6 69

PCIE GND * GND_P2MM CPU_COMP GND * GND_P2MM SENSE_1TO1_55S SENSE MCPCORES0_RSEN_N 64
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
LVDS_100D LVDS LVDS_CONN_B_CLK_F_N 6 69

SATA GND * GND_P2MM CPU_GTLREF GND * GND_P2MM SB_POWER PP3V3_S5 68 69 71

6 7 17 19 21 22 24 28
32 35 36 42 52 62 66 67 DP_ML DP_100D DISPLAYPORT DP_ML_C_P<3..0> 6 71
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

SB_POWER PP3V3_S0 6 7 12 17 18 20 21 2246

USB GND * GND_P2MM CPU_VCCSENSE GND * GND_P2MM 23 26 27 35 37 41 43 45 DP_100D DISPLAYPORT DP_ML_C_N<3..0> 71
SB_POWER PP1V5_S0 47
6 7 10 11 15 22 37 6649
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
67 68 53 DP_ML DP_100D DISPLAYPORT DP_ML_P<3..0> 17 70 71
CLK_PCIE SB_POWER * PWR_P2MM FSB_DSTB FSB_DSTB * GND_P2MM GND GND 57
58
61 DP_100D DISPLAYPORT DP_ML_N<3..0> 17 70 71
TABLE_SPACING_ASSIGNMENT_ITEM
66
SATA SB_POWER * PWR_P2MM 67
68 DP_ML DP_100D DISPLAYPORT DP_ML_CONN_P<3..0> 71
69
TABLE_SPACING_ASSIGNMENT_ITEM
71
72 DP_100D DISPLAYPORT DP_ML_CONN_N<3..0> 71
USB SB_POWER * PWR_P2MM
SD Card Net Properties DP_AUX_CH DP_100D DISPLAYPORT DP_AUX_CH_C_P 70 71
TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_HEAD

NET_TYPE DP_AUX_CH DP_100D DISPLAYPORT DP_AUX_CH_C_N 70 71

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
LVDS GND * GND_P2MM ENET_MDI GND * GND_P2MM
SD_DATA SD_55S SD_INTERFACE SD_D<0> 6 30

SD_DATA SD_55S SD_INTERFACE SD_D<1> 6 30

Memory Constraint Relaxations SD_DATA SD_55S SD_INTERFACE SD_D<2>

SD_D<3>
6 30

SD_DATA SD_55S SD_INTERFACE 6 30

Allow 0.127 mm necks for >0.127 mm lines for GMCH fanout. SD_DATA SD_55S SD_INTERFACE SD_D<4> 6 30

ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

SD_DATA SD_55S SD_INTERFACE SD_D<5> 6 30

PHYSICAL_RULE_SET LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM
SD_DATA SD_55S SD_INTERFACE SD_D<6> 6 30

B MEM_70D BOTTOM 0.127 MM 6.35 MM SD_DATA SD_55S SD_INTERFACE SD_D<7> 6 30

B
SD_CLK SD_55S SD_INTERFACE SD_CLK 6 30

SD_CMD SD_55S SD_INTERFACE SD_CMD 6 30

SD Card Interface Constraints

MCP Fanout Constraint Relaxations PHYSICAL_RULE_SET LAYER ALLOW ROUTE
ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP
TABLE_PHYSICAL_RULE_HEAD

DIFFPAIR NECK GAP

TABLE_PHYSICAL_RULE_ITEM

ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

SD_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD

PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM

MEM_40S * 0.09 MM 5.8 MM TABLE_SPACING_RULE_HEAD

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM

MEM_40S_VDD * 0.09 MM 5.8 MM SD_INTERFACE * =3X_DIELECTRIC ?

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM

MEM_70D * 0.09 MM 5.8 MM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM

MEM_70D_VDD * 0.09 MM 100 MIL

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM

PCIE_90D * 0.09 MM 100 MIL

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM

USB_90D TOP 0.09 MM 500 MIL

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM

MCP_DV_COMP TOP 0.1 MM 500 MIL

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MCP_MEM_COMP TOP 0.1 MM 500 MIL

TABLE_PHYSICAL_RULE_ITEM

K19i Specific Constraints

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE SYNC_MASTER=WFERRY_K19I SYNC_DATE=01/08/2009
A MCP_MII_COMP TOP 0.1 MM 500 MIL
TABLE_PHYSICAL_RULE_ITEM

NOTICE OF PROPRIETARY PROPERTY

A
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
TABLE_PHYSICAL_RULE_ITEM

MCP_USB_RBIAS TOP 0.1 MM 500 MIL THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
TABLE_PHYSICAL_RULE_ITEM
AGREES TO THE FOLLOWING
MCP_DV_COMP * 0.25 MM 250 MIL I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 82 83

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1
K19i Board-Specific Physical & Spacing Constraints TABLE_BOARD_INFO

BOARD LAYERS BOARD AREAS BOARD UNITS ALLEGRO TABLE_SPACING_RULE_HEAD TABLE_SPACING_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_HEAD

(MIL or MM) VERSION SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM NO_TYPE,BGA MM 15.2 TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM

DEFAULT * 0.1 MM ? * * BGA BGA_P1MM MEM_40S BGA STANDARD

TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM

ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

STANDARD * =DEFAULT ? MEM_CLK * BGA BGA_P2MM MEM_40S_VDD BGA STANDARD

PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

BGA_P1MM * 0.1 MM ? CLK_FSB * BGA BGA_P2MM

DEFAULT * Y =50_OHM_SE 0.080 MM 12.7 MM 0 MM 0 MM TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

BGA_P2MM * 0.2 MM ? CLK_LPC * BGA BGA_P2MM

STANDARD * Y =DEFAULT =DEFAULT 12.7 MM =DEFAULT =DEFAULT TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

BGA_P3MM * 0.3 MM ? CLK_PCI * BGA BGA_P2MM

TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_ASSIGNMENT_ITEM

D PHYSICAL_RULE_SET LAYER ALLOW ROUTE

ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

TABLE_SPACING_RULE_HEAD
CLK_PCIE * BGA BGA_P2MM
TABLE_SPACING_ASSIGNMENT_ITEM
D
55_OHM_SE TOP,BOTTOM Y 0.090 MM 0.090 MM TABLE_SPACING_RULE_ITEM
CLK_SLOW * BGA BGA_P2MM
TABLE_PHYSICAL_RULE_ITEM

1.5:1_SPACING * 0.15 MM ? TABLE_SPACING_ASSIGNMENT_ITEM

55_OHM_SE * Y 0.076 MM 0.076 MM =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM

FSB_DSTB FSB_DSTB BGA BGA_P3MM
2:1_SPACING * 0.2 MM ?
TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_RULE_ITEM

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 2.5:1_SPACING * 0.25 MM ?
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM

50_OHM_SE TOP,BOTTOM Y 0.115 MM 0.115 MM 3:1_SPACING * 0.3 MM ?

TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM

50_OHM_SE * Y 0.076 MM 0.076 MM =STANDARD =STANDARD =STANDARD 4:1_SPACING * 0.4 MM ?

TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM

40_OHM_SE TOP,BOTTOM Y 0.165 MM 0.100 MM 2X_DIELECTRIC TOP,BOTTOM 0.140 MM ?

TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM

40_OHM_SE * Y 0.126 MM 0.100 MM =STANDARD =STANDARD =STANDARD 3X_DIELECTRIC TOP,BOTTOM 0.210 MM ?

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD
4X_DIELECTRIC TOP,BOTTOM 0.280 MM ?
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM

ON LAYER? 5X_DIELECTRIC TOP,BOTTOM 0.350 MM ?

TABLE_PHYSICAL_RULE_ITEM

27P4_OHM_SE TOP,BOTTOM Y 0.310 MM 0.310 MM TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM
2X_DIELECTRIC * 0.126 MM ?
27P4_OHM_SE * Y 0.222 MM 0.222 MM =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM

3X_DIELECTRIC * 0.189 MM ?
TABLE_SPACING_RULE_ITEM

4X_DIELECTRIC * 0.252 MM ?
TABLE_SPACING_RULE_ITEM

ALLOW ROUTE
TABLE_PHYSICAL_RULE_HEAD

5X_DIELECTRIC * 0.315 MM ?
PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM

70_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD

TABLE_PHYSICAL_RULE_ITEM

C 70_OHM_DIFF

70_OHM_DIFF
ISL3,ISL4,ISL9,ISL10

TOP,BOTTOM
Y

Y
0.151 MM

0.185 MM
0.151 MM

0.185 MM
=STANDARD 0.224 MM
0.200 MM
0.224 MM
0.200 MM
TABLE_PHYSICAL_RULE_ITEM
C
TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

90_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD

TABLE_PHYSICAL_RULE_ITEM

90_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y 0.095 MM 0.095 MM 0.234 MM 0.234 MM

TABLE_PHYSICAL_RULE_ITEM

90_OHM_DIFF TOP,BOTTOM Y 0.112 MM 0.112 MM 0.220 MM 0.220 MM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

100_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD

TABLE_PHYSICAL_RULE_ITEM

100_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y 0.075 MM 0.075 MM 0.244 MM 0.244 MM

TABLE_PHYSICAL_RULE_ITEM

100_OHM_DIFF TOP,BOTTOM Y 0.091 MM 0.091 MM 0.230 MM 0.230 MM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

100_OHM_DIFF_HDD * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD

TABLE_PHYSICAL_RULE_ITEM

100_OHM_DIFF_HDD ISL3,ISL4,ISL9,ISL10 Y 0.083 MM 0.083 MM 0.400 MM 0.400 MM

TABLE_PHYSICAL_RULE_ITEM

100_OHM_DIFF_HDD TOP,BOTTOM Y 0.095 MM 0.095 MM 0.400 MM 0.400 MM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

B 110_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD

TABLE_PHYSICAL_RULE_ITEM
B
110_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y 0.075 MM 0.075 MM 0.330 MM 0.330 MM
TABLE_PHYSICAL_RULE_ITEM

110_OHM_DIFF TOP,BOTTOM Y 0.077 MM 0.077 MM 0.330 MM 0.330 MM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM

1:1_DIFFPAIR * Y =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM

K19i PCB Rule Definitions

SYNC_MASTER=WFERRY_K19I SYNC_DATE=12/12/2008
A NOTICE OF PROPRIETARY PROPERTY
A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

D 051-7903 A
APPLE INC. SCALE SHT OF
NONE 83 83

8 7 6 5 4 3 2 1