Scribd
Upload
71 views

8086/8088Mp Instructor: Abdulmuttalib A. H. Aldouri

This document discusses different methods for address decoding circuits using NAND gates or decoders. It provides examples of how to connect RAM and ROM modules to an 8088 microprocessor using these address decoding techniques. Specifically, it shows how to: 1. Use NAND gates alone to decode addresses and generate chip selects for 4 RAM chips occupying addresses from C0000H to DFFFFH. 2. Use a line decoder and NAND gate to decode addresses and generate chip selects for the same 4 RAM chips. It also provides a homework example of connecting a 32Kbyte ROM module using 2764 EPROM chips to addresses from E0000H using these two address decoding methods.

Uploaded by

abdulbaset alselwi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
71 views

8086/8088Mp Instructor: Abdulmuttalib A. H. Aldouri

This document discusses different methods for address decoding circuits using NAND gates or decoders. It provides examples of how to connect RAM and ROM modules to an 8088 microprocessor using these address decoding techniques. Specifically, it shows how to: 1. Use NAND gates alone to decode addresses and generate chip selects for 4 RAM chips occupying addresses from C0000H to DFFFFH. 2. Use a line decoder and NAND gate to decode addresses and generate chip selects for the same 4 RAM chips. It also provides a homework example of connecting a 32Kbyte ROM module using 2764 EPROM chips to addresses from E0000H using these two address decoding methods.

Uploaded by

abdulbaset alselwi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 5

8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H.

ALDOURI

01
8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

Address Decoding Circuits Using Only NAND Gates

 A single NAND gate is used to decode each memory device. The inputs of
the NAND gate can be connected on the address lines either directly, or
through inverters, according to the required memory map.
 This method has the advantage that it adds a short time delay in the memory
path.
 The disadvantage of this circuit is that too many gates (NAND and NOT) are
needed for memory systems that have a few memory chips. This increases
the cost of the system, adds to the complexity of the PCB board (too many
chips and lines).
The figure below shows a memory map of two memory chips. Lines A 0 – A14
are connected to each chip and lines A15 – A19 are connected to NAND gates to
generate the CS signal.

Address Decoding Circuits Using decoders and a NAND Gate


 One or more line decoders such as the 74LS139 (2 x 4 decoder) or the
74LS138 (3 x 8 decoder) are used to decode(enable) one out of a number
of memory device. The CS inputs of the decoders are enabled by a NAND
gate, according to the required memory map.
 This decoding circuit has the disadvantage that it adds at least three gate
delays in the memory path.
 The advantage of this circuit is that less gates (NAND, NOT and
decoders) are needed for memory systems that have a number memory
chips.
The figure below shows a memory map of 8 memory chips. The decoding
circuit has one decoder, one inverter and one NAND gate.

02
8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

Example: Show how a 128 Kbyte RAM module can be connected on an


8088µP using SRAM chips 32K x 8, occupying the address range starting from
the address C0000H. Use the following address decoding circuits:
1. NAND gates 2. Line decoders
Solution:
Number of chips needed: 128K / 32K = 4 chips
Number of address lines: 32K = 25 * 210 = 215 → 15 address lines (A0 - A14)
Lines A15 – A19 are used to generate the CS signals
The final address = the starting address + memory size - 1
RAM1 : final address=C0000H + 8000H - 1H=C7FFFH
RAM2 : final address=C8000H + 8000H - 1H=CFFFFH
RAM3 : final address=D0000H + 8000H - 1H=D7FFFH
RAM4 : final address=D8000H + 8000H - 1H=DFFFFH

03
8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

1. Using NAND gates


In this case the lines A15 – A19 are connected to four NAND gates with ̅
control signal sent by the 8088µP to generate the CS signal as shown below.
RAM4 RAM3 RAM2 RAM1

2. Using a line decoder and a NAND GATE


In this case, the lines A15 and A16 are input to the decoder to select one of
the four chips, while the lines A17 – A19 and ̅ signal are connected to
a NAND gate to enable the decoder.
RAM4 RAM3 RAM2 RAM1

H.W.
Show how a 32Kbyte ROM module can be connected on an 8088 system using
2764 EPROM chips (8K x 8), occupying the address range starting from the
address E0000H. Use the following address decoding circuits:
1. NAND gates
2. A line decoder and a NAND gate

04
8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

Example:
Design an 8K x 8 RAM module using 2K x 8 RAM chips. The module should
be connected on an 8-bit processor with a 16-bit address bus, and occupy the
address range starting from the address A000. Show the circuit and the memory
map.
Solution:
Number of memory devices needed = 8K / 2K = 4
Decoder needed = 2 x 4
Number of address lines on each 2K x 8 memory chip = 11
2m = 2K = 21 x 210 = 211 → (A0 - A10)

Two address lines are needed for the decoder → (A11 , A12)
Number of address lines needed for the address selection circuit
= 16 - 11 - 2 = 3 → (A13, A14 , A15)

05

You might also like