VLSI

DESIGN

A. Albert Raj
T. Latha
VLSI DESIGN

A. ALBERT RAJ T. LATHA

Assistant Professor Assistant Professor
Department of Electronics and Instrumentation Engineering
Noorul Islam College of Engineering
Kanyakumari

New Delhi-110001
2008
VLSI DESIGN
A. Albert Raj and T. Latha

© 2008 by PHI Learning Private Limited, New Delhi. All rights reserved. No part of this book may be
reproduced in any form, by mimeograph or any other means, without permission in writing from the
publisher.

ISBN-978-81-203-3431-1

The export rights of this book are vested solely with the publisher.

Published by Asoke K. Ghosh, PHI Learning Private Limited, M-97, Connaught Circus,
New Delhi-110001 and Printed by Mudrak, 30-A, Patparganj, Delhi-110091.
 Contents

Preface xiii

1. INTRODUCTION 1– 4
1.1 Evolution of VLSI Device Technology 1
1.2 Metal Oxide Semiconductor (MOS) and VLSI Technology 3
Summary 4

2. BASIC MOS STRUCTURE 5–33

2.1 Introduction 5
2.2 Basic MOS Transistor Operation 6
2.2.1 Enhancement Mode Transistor Action 7
2.2.2 Depletion Mode Transistor Action 10
2.3 MOS Transistor Switches 10
2.3.1 Complementary CMOS Switch 11
2.4 NMOS Fabrication 12
2.5 Basic CMOS Technology 15
2.5.1 The p-well CMOS Process 15
2.5.2 The n-well CMOS Process 16
2.5.3 The Twin-Well Process 19
2.5.4 Silicon-On-Insulator Process 19
2.6 CMOS Process Enhancements 21
2.6.1 Interconnect 22
2.6.2 Circuit Elements 25
2.7 BiCMOS Technology 29
2.7.1 BiCMOS Fabrication in an n-well Process 32
2.7.2 Some Aspects of Bipolar and CMOS Devices 32
Summary 32
Review Questions 33
Short Answer Questions 33

iii
iv • Contents

3. MOS DEVICE CHARACTERISTICS 34–62

3.1 Introduction 34
3.2 Static Behaviour of the MOS Transistor 35
3.2.1 The Threshold Voltage 35
3.2.2 Current–Voltage Relations 39
3.2.3 A Model for Manual Analysis 42
3.2.4 MOS Transistor Transconductance gm and Output Conductance gds 42
3.2.5 MOS Transistor Figure of Merit, w0 43
3.3 Dynamic Behaviour of MOS Transistor 43
3.3.1 MOS Structure Capacitances 43
3.3.2 Channel Capacitance 44
3.3.3 Junction Capacitance 45
3.3.4 Capacitive Device Model 46
3.4 The Actual MOS Transistor—Secondary Effects 46
3.4.1 Threshold Variations 46
3.4.2 Source–Drain Resistance 47
3.4.3 Variation in I-V Characteristics 48
3.4.4 Subthreshold Conduction 49
3.4.5 CMOS Latchup 50
3.5 NMOS Inverter 50
3.6 Determination of Pull-up to Pull-down Ratio (Zp.u/Zp.d) for an
NMOS Inverter Driven by Another NMOS Inverter 52
3.7 Pull-up to Pull-down Ratio for an NMOS Inverter Driven Through One
or More Pass Transistors 54
3.8 Device Models for Simulation 56
3.8.1 MOS Models 56
3.8.2 DC MOSFET Model 56
3.8.3 High Frequency MOSFET Model 57
3.8.4 SPICE Models 60
Summary 62
Review Questions 62
Short Answer Questions 62

4. CMOS INVERTER DESIGN 63–89

4.1 Introduction 63
4.2 CMOS Inverter—DC Characteristics 65
4.3 Design Parameters of CMOS Inverter 75
4.3.1 Symmetric CMOS Inverter 76
4.3.2 Noise Margins of CMOS Inverter 77
4.3.3 Temperature Dependence of VTC of CMOS Inverter 78
4.3.4 Supply Voltage Scaling in CMOS Inverters 78
4.3.5 Power and Area Considerations 79
4.4 Switching Characteristics of CMOS Inverter 80
4.4.1 Estimation of CMOS Inverter Delay 81
4.5 CMOS—Gate Transistor Sizing 85
4.6 Stage Ratio 86
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4.7 Power Dissipation 86

4.7.1 Static Dissipation 87
4.7.2 Dynamic Dissipation 87
4.7.3 Short-circuit Dissipation 87
4.7.4 Total Power Dissipation 87
4.7.5 Power Economy 88
Summary 88
Review Questions 88
Short Answer Questions 88

5. MOS CIRCUIT DESIGN PROCESSES 90–115

5.1 Introduction 90
5.2 Why Design Rules 90
5.3 MOS Layers 91
5.4 Stick Diagrams 91
5.4.1 Stick Layout Using NMOS Design 94
5.4.2 Stick Layout Using CMOS Design 95
5.5 Design Rules and Layout 96
5.5.1 Lambda (l) Based Design Rules 97
5.5.2 Double Metal MOS Process Rules 101
5.5.3 CMOS Lambda-based Design Rules 102
5.6 Elements of Physical Design 109
5.6.1 Basic Concepts 110
5.6.2 Design Hierarchies 111
Summary 114
Review Questions 114
Short Answer Questions 114

6. SPECIAL CIRCUIT LAYOUTS 116–136

6.1 Introduction 116
6.2 Tally Circuits 117
6.3 NAND–NAND, NOR–NOR, and AOI Logic 119
6.4 Exclusive-OR Structures 122
6.5 Barrel Shifter 127
6.6 Transmission Gates 130
6.7 Latches and Flip-flops 131
6.7.1 CMOS Static Latches 132
6.7.2 CMOS Dynamic Latches 132
6.8 Fan-in and Fan-out of CMOS Logic Design 134
Summary 136
Review Questions 136
Short Answer Questions 136
vi • Contents

7. SUPER BUFFERS, BiCMOS AND STEERING LOGIC 137–157

7.1 Introduction 137
7.2 RC Delay Lines 138
7.3 Super Buffers 139
7.3.1 NMOS Super Super Buffer 141
7.3.2 NMOS Tristate Super Buffers and Pad-Drivers 142
7.3.3 CMOS Super Buffers 143
7.3.4 BiCMOS Gates 144
7.4 Dynamic Ratioless Inverters 146
7.5 Large Capacitive Loads 147
7.6 Pass-Transistor Logic 148
7.7 General Function Blocks 152
7.7.1 NMOS Function Blocks 153
7.7.2 CMOS Function Blocks 155
Summary 156
Review Questions 156
Short Answer Questions 156

8. CMOS COMBINATIONAL LOGIC CIRCUITS 158–178

8.1 Introduction 158
8.2 Static CMOS Design 159
8.2.1 Complementary CMOS 159
8.2.2 Ratioed Logic 163
8.2.3 Pass-Transistor Logic 164
8.3 Dynamic CMOS Design 166
8.3.1 Dynamic Logic: Basic Principles 166
8.3.2 Speed and Power Dissipation of Dynamic Logic 167
8.3.3 Signal Integrity Issues in Dynamic Design 168
8.3.4 Cascading Dynamic Gates 171
8.4 Complex Logic Gates in CMOS 172
Summary 177
Review Questions 177
Short Answer Questions 178

9. CMOS SEQUENTIAL LOGIC CIRCUITS 179–197

9.1 Introduction 179
9.2 Timing Metrics for Sequential Circuits 180
9.3 Classification of Memory Elements 181
9.4 Static Latches and Registers 183
9.4.1 Bistability Principle 183
9.4.2 Multiplexer-Based Latches 183
9.4.3 Master–Slave Edge-Triggered Register 185
9.4.4 Low Voltage Static Latches 187
9.5 Dynamic Latches and Registers 187
9.5.1 Dynamic Transmission-Gate Edge-Triggered Registers 188
9.5.2 C2MOS—A Clock Skew Insensitive Approach 189
9.5.3 True Single-Phase Clocked Register (TSPCR) 190
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9.6 Alternative Register Styles 192

9.6.1 Pulse Registers 192
9.6.2 Sense Amplifier-Based Registers 192
9.7 Non-bistable Sequential Circuits 193
9.7.1 The Schmitt Trigger 193
9.7.2 Monostable Sequential Circuits 194
9.7.3 Astable Circuits 195
Summary 196
Review Questions 196
Short Answer Questions 197

10. DESIGN OF ARITHMETIC BUILDING BLOCKS 198–225

10.1 Introduction 198
10.2 Datapaths 199
10.3 The Adder 200
10.3.1 The Binary Adder: Definitions 200
10.3.2 The Full-Adder: Circuit Design Considerations 202
10.3.3 The Binary Adder: Logic Design Considerations 207
10.4 The Multiplier 217
10.4.1 Multiplier: Definitions 218
10.4.2 Partial-Product Generation 219
10.4.3 Partial-Product Accumulation 220
10.4.4 Final Addition 223
Summary 224
Review Questions 224
Short Answer Questions 225

11. PROGRAMMABLE LOGIC DEVICES 226–258

11.1 Introduction 226
11.2 NMOS PLAs 227
11.2.1 NMOS PLA Layouts 227
11.3 Other Programmable Logic Devices 232
11.3.1 Field Programmable Logic Array (FPLA) 232
11.3.2 Programmable Array Logic (PAL) 233
11.3.3 Dynamic Logic Arrays (DLAs) 233
11.4 The Finite-State Machine as a PLA Structure 235
11.5 Complex Programmable Logic Devices (CPLDs) 237
11.5.1 CPLD Packaging and Programming 239
11.6 Field Programmable Gate Arrays (FPGAs) 242
11.6.1 FPGA Packaging and Programming 243
11.6.2 The XILINX Programmable Gate Array 250
11.6.3 Implementation in FPGAs 256
11.6.4 Design Flow 256
Summary 257
Review Questions 258
Short Answer Questions 258
viii • Contents

12. CMOS CHIP DESIGN 259– 284

12.1 Introduction 259
12.2 Design Strategies 260
12.2.1 Structured Design Strategies 260
12.2.2 Hierarchy 261
12.2.3 Regularity 261
12.2.4 Modularity 261
12.2.5 Locality 261
12.3 CMOS Chip Design Options 262
12.3.1 Application Specific Integrated Circuits (ASICs) 262
12.3.2 Types of ASICs 262
12.3.3 Economics of ASICs 272
12.3.4 CMOS Chip Design with Programmable Logic 277
Summary 283
Review Questions 283
Short Answer Questions 284

13. ROUTING PROCEDURES 285–307

13.1 Introduction 285
13.2 Global Routing 285
13.2.1 Goals and Objectives 285
13.2.2 Measurement of Interconnect Delay 286
13.2.3 Global Routing Methods 289
13.2.4 Global Routing Between Blocks 289
13.2.5 Global Routing Inside Flexible Blocks 291
13.2.6 Timing-Driven Methods 293
13.2.7 Back-Annotation 294
13.3 Detailed Routing 294
13.3.1 Goals and Objectives 298
13.3.2 Measurement of Channel Density 298
13.3.3 Algorithms 299
13.3.4 Left-Edge Algorithm 299
13.3.5 Constraints and Routing Graphs 299
13.3.6 Area-Routing Algorithms 302
13.3.7 Multilevel Routing 303
13.3.8 Timing-driven Detailed Routing 303
13.3.9 Final Routing Steps 304
13.4 Special Routing 304
13.4.1 Clock Routing 304
13.4.2 Power Routing 305
Summary 306
Review Questions 306
Short Answer Questions 306
 Contents • ix

14. CMOS TESTING 308–351

14.1 Introduction 308
14.2 Need for Testing 308
14.2.1 Functionality Tests 309
14.2.2 Manufacturing Tests 309
14.2.3 Test Process 310
14.3 General Concepts of Testing 310
14.3.1 Reliability 311
14.3.2 Reliability Modelling 312
14.4 Manufacturing Test Principles 314
14.4.1 Fault Models 314
14.4.2 Gate Level Testing 317
14.4.3 Observability 321
14.4.4 Controllability 321
14.4.5 Fault Coverage 321
14.4.6 Automatic Test Pattern Generation (ATPG) 322
14.4.7 Fault Grading and Fault Simulation 326
14.4.8 Delay Fault Testing 327
14.4.9 Statistical Fault Analysis 328
14.4.10 Fault Sampling 329
14.5 Design Strategies for Test 330
14.5.1 Design for Testability 330
14.5.2 Ad hoc Testing 330
14.5.3 Scan-Based Test Techniques 333
14.5.4 Self-Test Techniques 339
14.5.5 IDDQ Testing 342
14.6 Chip-Level Test Techniques 343
14.6.1 Regular Logic Arrays 343
14.6.2 Memories 343
14.6.3 Random Logic 344
14.7 System-Level Test Techniques 344
14.7.1 Boundary Scan 344
14.8 Layout Design for Improved Testability 350
Summary 350
Review Questions 350
Short Answer Questions 350

15. VERILOG HDL 352–365

15.1 Introduction 352
15.2 Basic Concepts 352
15.3 Structural Gate-Level Modelling 354
15.3.1 Verilog by Example 354
15.4 Switch-Level Modelling 359
15.5 Design Hierarchies 363
Summary 365
Review Questions 365
Short Answer Questions 365
 Vlsi Design

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Author : RAJ, A.
Publisher : PHI Learning ISBN : 9788120334 311
ALBERT, LATHA, T.

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