Scribd
Upload
71 views2 pages

Bannari Amman Institute of Technology: Regulation: 2018

This document contains a 10 question formative assessment on memory and I/O units and memory management for a 7th semester B.E. in Electrical and Electronics Engineering course. The assessment covers topics like delays affecting algorithm accuracy, required DIMM voltages, low-level buffer filling, memory package pin configurations, data writing registers, parallel port inputs, parallel port control registers, tri-state ports, parallel port buffer enabling, and chip select functions. The assessment is 10 minutes long and carries a maximum of 10 marks.

Uploaded by

veerakumars
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
71 views2 pages

Bannari Amman Institute of Technology: Regulation: 2018

This document contains a 10 question formative assessment on memory and I/O units and memory management for a 7th semester B.E. in Electrical and Electronics Engineering course. The assessment covers topics like delays affecting algorithm accuracy, required DIMM voltages, low-level buffer filling, memory package pin configurations, data writing registers, parallel port inputs, parallel port control registers, tri-state ports, parallel port buffer enabling, and chip select functions. The assessment is 10 minutes long and carries a maximum of 10 marks.

Uploaded by

veerakumars
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
You are on page 1/ 2

18EE405

Regulation: 2018
Reg.No.:

BANNARI AMMAN INSTITUTE OF TECHNOLOGY


(An Autonomous Institution Affiliated to Anna University, Chennai)
SATHYAMANGALAM – 638 401

FORMATIVE ASSESSMENT I - FEB 2020


VII Semester
Degree & Branch : B.E & EEE 15EE704

Unit/Topic : II/ Memory and I/O units, memory management


Name of the Faculty : S.Veerakumar,M.Srinivasan, Mrs.Andril Alagusabai
Date/Day of the Class (Google Classroom):
Date /Day of the Assessment:
Time Duration of Assessment :
Department/semester : EEE/VIISemester

Time : 10 minutes Maximum : 10 Marks

Q.No Questions
A1 (i) Which of the following can destroy the accuracy in the algorithms?
a) delays
b) error signal
c) interrupt
d) mmu (1 Marks – [R /C,1])
(ii) What is the required voltage of DIMM?
a) 2V
b) 2.2V
c) 5V
d) 3.3V (1 Marks – [R/C,1])
(iii) Which of the following have low-level buffer filling?
a) output
b) peripheral
c) dma controller
d) input (1 Marks – [An /C,1])
(iv) Which memory package has a single row of pins?
a) SIMM
b) DIP
c) SIP
d) zig-zag (1 Marks – [U/C,1])
(v) In which register does the data is written in the master device?
a) index register
b) accumulator
c) SPDR
d) status registe (1 Marks – [R /C,1])
(vi) Which of the following are interfaced as inputs to the parallel ports?
a) LEDs
b) switch

Page 1 of 2
18EE405
c) alphanumeric display
d) seven segmented display (1 Marks – [C/U,1])
(vii) How many registers are there to control the parallel port in the basic form?
a) 1
b) 3
c) 2
d) 5 (1 Marks – [An /C,1])
(viii) Which of the following is also known as tri-state?
a) output port
b) input port
c) parallel port
d) output-input port (1 Marks – [An/C,1])
(ix) How buffers are enabled in the parallel ports?
a) by the data register
b) by data direction register
c) by individual control register
d) by data and individual control register (1Marks – [U/C,1])
(x) Which of the following can be used as a chip select?
a) multifunction I/O port
b) parallel port
c) DMA port
d) memory port (1 Marks – [C/U,1])

***End of Question Paper***

Page 2 of 2

You might also like