ARM and STM32F4xx

Operating Modes & Interrupt Handling

ARM Cortex-M4 User Guide (Interrupts, exceptions, NVIC)

STM32F4xx Microcontrollers Technical Reference Manual

1
 Cortex-M structure

Nested Vectored
Interrupt Controller

2
CMSIS = Cortex Microcontroller Software Interface Standard
 Cortex CPU core registers
• Two processor modes:
• Thread mode for User tasks
• Handler mode for O/S tasks and exceptions
• Stack-based exception model
• Vector table contains addresses

Process SP (handler or thread mode – select in CONTROL reg.)

Main SP (selected at reset – always used in handler mode)
Convention:
PSP in thread mode,
MSP in O/S & handler mode

3
 Cortex-M4 processor operating modes

• Thread mode – normal processing

• Handler mode – interrupt/exception processing
• Privilege levels = User and Privileged
• Supports basic “security” & memory access protection
• Supervisor/operating system usually privileged
4
 Cortex-M4 interrupts/exceptions
 Interrupts/exceptions managed by NestedVectored Interrupt
Controller (NVIC)
 CPU state/context (subset of registers) saved on the stack
R0-R3, R12, LR, PC, PSR

Exception
stack frame

 PC loaded from a vector table, located at 0x0000_0000

 Vector fetched (Flash memory) while saving state (SRAM)
 Typical latency = 12 cycles
5
 Exception states
 Each exception is in one of the following states:
 Inactive: The exception is not active and not pending.
 Pending: The exception is waiting to be serviced by the processor.
 Active: The exception is being serviced by the processor but has not
completed.
 Active and pending - The exception is being serviced by the
processor and there is a pending exception from the same source.

 An interrupt request from a peripheral or from software can

change the state of the corresponding interrupt to pending.
 An exception handler can interrupt (preempt) the execution of
another exception handler. In this case both exceptions are in the
active state.

6
 Cortex-M CPU and peripheral exceptions
Priority1 IRQ#2 Notes
Reset -3 Power-up or warm reset
NMI -2 -14 Non-maskable interrupt from peripheral or software
HardFault -1 -13 Error during exception processing or no other handler
CPU Exceptions

MemManage Config -12 Memory protection fault (MPU-detected)

BusFault Config -11 AHB data/prefetch aborts
UsageFault Config -10 Instruction execution fault - undefined instruction, illegal
unaligned access
SVCcall Config -5 System service call (SVC) instruction
DebugMonitor Config Break points/watch points/etc.
PendSV Config -2 Interrupt-driven request for system service
SysTick Config -1 System tick timer reaches 0
IRQ0 Config 0 Signaled by peripheral or by software request
IRQ1 (etc.) Config 1 Signaled by peripheral or by software request

Vendor peripheral interrupts 1 Lowest priority # = highest priority

7 2 IRQ# used in CMSIS function calls
IRQ0 .. IRQ44
 Vector table
• 32-bit vector(handler address)
loaded into PC, while saving
CPU context.
• Reset vector includes
initial stack pointer

• Peripherals use
positive IRQ #s
• CPU exceptions use
negative IRQ #s
• IRQ # used in CMSIS function
calls
• Cortex-M4 allows up to
240 IRQs

• IRQ priorities user-programmable

• NMI & HardFault priorities fixed
8
STM32F4
Vector
Table
(partial)

Tech. Ref.
Table 61

(Refer to
Startup
Code)

9
 STM32F4 vector table from startup code (partial)
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
……
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler

; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD via EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper/TimeStamps via EXTI
DCD RTC_WKUP_IRQHandler ; RTC Wakeup via EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
10 DCD EXTI2_IRQHandler ; EXTI Line2
 Special CPU registers
ARM instructions to “access special registers”
MRS Rd,spec ;move from special register (other than R0-R15) to Rd
MSR spec,Rs ;move from register Rs to special register
Use CMSIS1 functions to clear/set PRIMASK
__enable_irq(); //enable interrupts (set PRIMASK=0)
__disable_irq(); //disable interrupts (set PRIMASK=1)
(double-underscore at beginning)
Special Cortex-M Assembly Language Instructions
CPSIE I ;Change Processor State/Enable Interrupts (sets PRIMASK = 0)
CPSID I ;Change Processor State/Disable Interrupts (sets PRIMASK = 1)

Prioritized Interrupts Mask Register (PRIMASK)

PRIMASK

PRIMASK = 1 prevents (masks) activation of all exceptions with configurable priority

PRIMASK = 0 permits (enables) exceptions

Processor Status Register (PSR)

# of current
exception
(lower priority
cannot
1
11 Cortex Microcontroller Software Interface Standard – Functions for all interrupt)
ARM Cortex-M CPUs, defined in project header files: core_cmFunc.h, core_cm3.h
 Prioritized interrupts

• Up to 256 priority levels

• 8-bit priority value
• Implementations may use fewer bits
STM32F4xx uses upper 4 bits of each
priority byte => 16 levels
• STM32F4xx uses 4 bits => 16 levels
12 • NMI & HardFault priorities are fixed
 “Tail-chaining” interrupts

• NVIC does not unstack registers and then stack them again, if
going directly to another ISR.
• NVIC can halt stacking (and remember its place) if a new IRQ is
received.
13
 Exception return
 The exception mechanism detects when the processor has
completed an exception handler.
 Exception return occurs when:
1. Processor is in Handler mode
2. EXC_RETURN loaded to PC
3. Processor executes one of these instructions:
 LDM or POP that loads the PC
 LDR with PC as the destination
 BX using any register
 EXC_RETURN value loaded into LR on exception entry (after
stacking original LR)
 Lowest 5 bits of EXC_RETURN provide information on the return
stack and processor mode.

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 Interrupt signal: from device to CPU Peripheral Device
Registers:
In each peripheral device: Enable Flag
 Each potential interrupt source has a separate arm (enable) bit xIE xF
 Set for devices from which interrupts, are to be accepted
 Clear to prevent the peripheral from interrupting the CPU
&
 Each potential interrupt source has a separate flag bit
 hardware sets the flag when an “event” occurs Peripheral
 Interrupt request = (flag & enable) IRQn
 ISR software must clear the flag to acknowledge the request
 test flags in software if interrupts not desired
Nested Vectored Interrupt Controller (NVIC)
 Receives all interrupt requests
NVIC
 Each has an enable bit and a priority within the VIC
 Highest priority enabled interrupt sent to the CPU
Within the CPU: PRIMASK

 Global interrupt enable bit in PRIMASK register

&
 Interrupt if priority of IRQ < that of current thread CPU
15  Access interrupt vector table with IRQ#
Interrupt
 Nested Vectored Interrupt Controller
 NVIC manages and prioritizes external interrupts in Cortex-M
 82 IRQ sources from STM32F4xx peripherals
 NVIC interrupts CPU with IRQ# of highest-priority IRQ signal
 CPU uses IRQ# to access the vector table & get intr. handler start address

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 NVIC registers (one bit for each IRQ#)
 NVIC_ISERx/NVIC_ICERx
 Each IRQ has its own enable bit within NVIC EnableK
 Interrupt Set/Clear Enable Register
 1 = Set (enable) interrupt/Clear (disable) interrupt PendK
 NVIC_ISPRx/NVIC_ICPRx
 Interrupt Set/Clear Pending Register PriorityK
 Read 1 from ISPR if interrupt in pending state
 Write 1 to set interrupt to pending or clear from pending state
 NVIC_IABRx – Interrupt Active Bit Register
 Read 1 if interrupt in active state

x = 0..7 for each register type, with 32 bits per register, to support
up to 240 IRQs (82 in STM32F4xx)
 Each bit controls one interrupt, identified by its IRQ# (0..239)
 Register# x = IRQ# DIV 32
 Bit n in the register = IRQ# MOD 32
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 NVIC registers (continued)
 NVIC_IPRx (x=0..59) – Interrupt Priority Registers
 Supports up to 240 interrupts: 0..239 (82 in STM32F4)
 8-bit priority field for each interrupts (4-bit field in STM32F4)
 4 priority values per register (STM32F4 – upper 4 bits of each byte)
 0 = highest priority
 Register# x = IRQ# DIV 4
 Byte offset within the register = IRQ# MOD 4
 Ex. IRQ85:
o 85/4 = 21 with remainder 1 (register 21, byte offset 1)
Write priority<<8 to NVIC_IPR2
o 85/32 = 2 with remainder 21: write 1<<21 to NVIC_SER2

 STIR – Software Trigger Interrupt Register

 Write IRQ# (0..239) to trigger that interrupt from software
 Unprivileged access to this register enabled in system control register
(SCR)
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 NVIC example (assembly language)
NVIC_ISER0/1/2 = 0xE000E100/104/108
NVIC_ICER0/1/2 = 0xE000E180/184/188
NVIC_IPR0/1/2/…/20 = 0xE00E400/404/408/40C/…./500

;Example – Enable EXTI0 with priority 5 (EXTI0 = IRQ6)

NVIC_ISER0 EQU 0xE000E100 ;bit 6 enables EXTI0
NVIC_IPR1 EQU 0xE000E404 ;3rd byte = EXTI0 priority
ldr r0,=NVIC_ISER0
mov r1,#0x0040 ;Set bit 6 of ISER0 for EXTI0
str r1,[r0]
ldr r0,=NVIC_IPR1 ;IRQ6 priority in IPR1[23:16]
ldr r1,[r0] ;Read IPR1
bic r1,#0x00FF0000 ;Clear [23:16] for IRQ6
orr r1,#0x00500000 ;Bits [23:20] = 5
str r1,[r0] ;Upper 4 bits of byte = priority
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CMSIS: Cortex Microcontroller Software Interface Standard
Vendor-independent hardware abstraction layer for Cortex-M
(Facilitates software reuse)
•Core Peripheral Access Layer provides name definitions, address
definitions, and helper functions to access core registers and core
peripherals.
•Device Peripheral Access Layer (MCU specific) offers name
definitions, address definitions, and driver code to access peripherals.
•Access Functions for Peripherals (MCU specific and optional)
implements additional helper functions for peripherals.

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 CMSIS functions
Available when CMSIS Core is included in the project

 NVC_EnableIRQ(IRQn_Type IRQn)
 NVIC_DisableIRQ(IRQn_Type IRQn)
 Set bit IRQn in NVIC_ISERx/NVIC/ICERx
 NVIC_SetPendingIRQ(IRQn_Type IRQn)
 NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 NVIC_GetPendingIRQ(IRQn_Type IRQn)
 Set/read/read bit IRQn in NVIC_ISPRx/NVIC_ICPRx
 NVIC_SetPriority(IRQn_Type IRQn,unit32_t priority)
 NVIC_GetPriority(IRQn_Type IRQn)
 Set/get IRQn priority in NVIC_IPRxI
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 NVIC CMSIS example: enable interrupts

 Interrupt Set Enable Register: each bit enables one interrupt

NVIC_EnableIRQ(n); //set bit to enable IRQn
 Interrupt Clear Enable Register: each bit disables one interrupt
NVIC_DisableIRQ(n); //set bit to disable IRQn

 For convenience, stm32f4xx.h defines a symbol for each IRQn

Examples: EXTI0_IRQn = 6 ; //External interrupt EXTI0 is IRQ #6
TIM3_IRQn = 29 ; //Timer TIM3 interrupt is IRQ #29
Usage:
NVIC_EnableIRQ(EXTI0_IRQn); //enable external interrupt EXTI0
NVIC_DisableIRQ(TIM3_IRQn); //disable interrupt from timer TIM3
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 STM32F4 external interrupt/event controller
23 edge detectors to trigger events and interrupts signaled by
240 GPIO pins and 7 internal events.

PR IMR RTSR FTSR

IRQ
to
NVIC
External
interrupt
signal
(GPIO pin)

23
 STM32F4xx external interrupt sources
(select in System Configuration Module – SYSCFG)
• 16 multiplexers select GPIO pins as external interrupts EXTI0..EXTI15
• Mux inputs selected via 4-bit fields of EXTICR[k] registers (k=0..3)
• EXTIx = 0 selects PAx, 1 selects PBx, 2 selects PCx, etc.
• EXTICR[0] selects EXTI3-EXTI0; EXTICR[1] selects EXTI7-EXTI4, etc
15 12 11 8 7 4 3 0
SYSCFG_EXTICR1 is
SYSCFG->EXTICR[0] EXTI3 EXTI2 EXTI1 EXTI0

Example: Select pin PC2 as external interrupt EXTI2

SYSCFG->EXTICR[0] &= 0xF0FF; //clear EXTI2 bit field
24 SYSCFG->EXTICR[0] |= 0x0200; //set EXTI2 = 2 to select PC2
 STM32F4 external interrupt sources

Sixteen external interrupts

EXTI0 – EXTI15

Seven “event” triggers:

EXTI16 = PVD output
EXTI17 = RTC Alarm event
EXTI18 = USB OTG FS Wakeup event
EXTI19 = Ethernet Wakeup event
EXTI20 = USB OTG HS Wakeup event
EXTI21 = RTC Tamper and TimeStamp events
EXTI22 = RTC Wakeup event

25
 STM32F4 EXTI Registers
23 bits per register - control 23 interrupts/events
 EXTI_IMR – interrupt mask register
 0 masks (disables) the interrupt
 1 unmasks (enables) the interrupt
 EXTI_RTSR/FTSR – rising/falling trigger selection register
 1 to enable rising/falling edge to trigger the interrupt/event
 0 to ignore the rising/falling edge
 EXTI_PR – interrupt/event pending register
 read 1 if interrupt/event occurred
 clear bit by writing 1 (writing 0 has no effect)
 write 1 to this bit in the interrupt handler to clear the pending state
of the interrupt

 EXTI_SWIER – software interrupt event register

 1 to set the pending bit in the PR register
 Triggers interrupt if not masked
26
27
 Project setup for interrupt-driven applications
 Write the interrupt handler for each peripheral
 Clear the flag that requested the interrupt (acknowledge the intr. request)
 Perform the desired actions, communicating with other functions via shared global
variables
 Use function names from the vector table
Example: void EXTI4_IRQHandler () { statements }
 Perform all initialization for each peripheral device:
 Initialize the device, “arm” its interrupt, and clear its “flag”
Example: External interrupt EXTIn
 Configure GPIO pin as a digital input
 Select the pin as the EXTIn source (in SYSCFG module)
 Enable interrupt to be requested when a flag is set by the desired event (rising/falling edge)
 Clear the pending flag (to ignore any previous events)
 NVIC
 Enable interrupt: NVIC_EnableIRQ (IRQn);
 Set priority: NVIC_SetPriority (IRQn, priority);
 Clear pending status: NVIC_ClearPendingIRQ (IRQn);
 Initialize counters, pointers, global variables, etc.
 Enable CPU Interrupts: __enable_irq();
28 (diagram on next slide)
 Example: Enable EXTI0 as rising-edge triggered
;System Configuration Registers
SYSCFG EQU 0x40013800
EXTICR1 EQU 0x08
;External Interrupt Registers
EXTI EQU 0x40013C00
IMR EQU 0x00 ;Interrupt Mask Register
RTSR EQU 0x08 ;Rising Trigger Select
FTSR EQU 0x0C ;Falling Trigger Select
PR EQU 0x14 ;Pending Register

;select PC0 as EXTI0

ldr r1,=SYSCFG ;SYSCFG selects EXTI sources
ldrh r2,[r1,#EXTICR1] ;EXTICR1 = sources for EXTI0 - EXTI3
bic r2,#0x000f ;Clear EXTICR1[3-0] for EXTI0 source
orr r2,#0x0002 ;EXTICR1[3-0] = 2 to select PC0 as EXTI0 source
strh r2,[r1,#EXTICR1] ;Write to select PC0 as EXTI0
;configure EXTI0 as rising-edge triggered
ldr r1,=EXTI ;EXTI register block
mov r2,#1 ;bit #0 for EXTI0 in each of the following registers
str r2,[r1,#RTSR] ;Select rising-edge trigger for EXTI0
str r2,[r1,#PR] ;Clear any pending event on EXTI0
29 str r2,[r1,#IMR] ;Enable EXTI0
 EXTI example – accessing registers directly (in C)
#include "STM32F4xx.h"
/*------------------------------------------------------------------------------
Intialize the GPIO and the external interrupt
*------------------------------------------------------------------------------*/
void Init_Switch(void){

//Enable the clock for GPIO

RCC->AHB1ENR| = RCC_AHB1ENR_GPIOAEN; /*-------------------------------------------------------------------
Interrupt Handler – count button presses
//Pull-up pin 0 *--------------------------------------------------------------------*/
GPIOA->PUPDR |= GPIO_PUPDR_PUPDR0_1; void EXTI0_IRQHandler(void) {

//Connect the portA pin0 to external interrupt line0 //Make sure the Button is really pressed
SYSCFG->EXTICR[0] &= SYSCFG_EXTICR1_EXTI0_PA; if (!(GPIOA->IDR & (1<<0)) )
{
//Interrupt Mask count++;
EXTI->IMR |= (1<<0); }

//Falling trigger selection //Clear the EXTI pending bits

EXTI->FTSR |= (1<<0); NVIC_ClearPendingIRQ(EXTI3_IRQn);
EXTI->PR|=(1<<0);
//Enable interrupt }
__enable_irq();

//Set the priority

NVIC_SetPriority(EXTI0_IRQn,0);

//Clear the pending bit

NVIC_ClearPendingIRQ(EXTI0_IRQn);

//Enable EXTI0
NVIC_EnableIRQ(EXTI0_IRQn);}
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 Supervisor Call Instruction (SVC)
 Access system resources from O/S (“privileged operations”)
 SVC_Handler is defined in the interrupt vector table
 SVC interrupt handler written as a C function:
void SVC_Handler()
{ your code }
 SVC interrupt handler as an assembly language function:
EXTERN SVC_Handler
SVC_Handler
your code
bx lr

31
 Supervisor Call instruction (SVC)
 To execute SVC_Handler as a software interrupt
 Assembly language syntax: SVC #imm
 C syntax: __svc (imm)
 imm is an “SVC number” (0-255), which indicates a particular
“service” to be performed by the handler
 imm is encoded into the instruction, but ignored by the CPU
 Handler can retrieve imm by using stacked PC to read the SVC
instruction code (examples provided later)
 Since this is an “interrupt”, R0-R3 are pushed onto the stack:
 Arguments can be passed to the handler in R0-R3
 SVC handler can retrieve the arguments from the stack
 SVC handler can also return results by replacing R0-R3 values in the
stack, which will be restored to R0-R3 on return from interrupt.

32
 Access SVC arguments in C

// Stack contains eight 32-bit values:

// r0, r1, r2, r3, r12, r14, return address, xPSR
// 1st argument = r0 = svc_args[0]
// 2nd argument = r1 = svc_args[1]
// 7th argument = return address = svc_args[6]

void SVC_Handler(unsigned int * svc_args) {

int a,b,c;

a = svc_args[0]; //get first argument from stack

b = svc_args[1]; //get second argument from stack
c = a + b;
svc_args[0] = c; //replace R0 value in stack with result to “return” result in R0

}
}

33
 Access SVC arguments in assembly language

; Stack contains: r0, r1, r2, r3, r12, r14, return address, xPSR
; The saved r0 is the top entry in the stack
EXPORT SVC_Handler
SVC_Handler
TST LR,#0x04 ;Test bit 2 of EXC_RETURN
ITE EQ ;Which stack pointer was used?
MRSEQ R4,MSP ;Copy Main SP to R4
MRSNE R4,PSP ;Copy Process SP to R4
LDR R1,[R4] ;Retrieve saved R0 from top of stack
LDR R2,[R4,#4] ;Retrieve saved R1 from stack
….
STR R1,[R4] ;Replace saved R0 value in stack
BX LR ;Return and restore registers from stack

34
 SVC in C programs
 May associate “standard” function name with the
__svc (imm) function call
 May pass up to four integer arguments
 May return up to four results in a “value_in_regs” structure
 Syntax:
__svc(int svc_num) return-type function-name(argument-list)
 svc_num (8-bit constant) = immediate value in SVC instruction
 “return-type function-name(argument-list)” = C function prototype
 Call the function via: function-name(argument-list);
(examples on next slide)

35 ARM Compiler toolchain Compiler Reference: __svc

 Example: SVC call from C code
/*---------------------------------------------------------------------
Set up SVC “calls” to “SVC_Handler”
SVC_Handler function must be defined elsewhere
*---------------------------------------------------------------------*/
#define SVC_00 0x00
#define SVC_01 0x01

/* define function “svc_zero” as SVC #0, passing pointer in R0 */

/* define function “svc_one” as SVC #1, passing pointer in R0 */
void __svc(SVC_00) svc_zero(const char *string);
void __svc(SVC_01) svc_one(const char *string);

int call_system_func(void) {
svc_zero("String to pass to SVC handler zero"); //Execute SVC #0
svc_one("String to pass to a different OS function"); //Execute SVC #1
}

Reference: ARM Compiler toolchain Developing Software for

36 ARM Processors”: Supervisor Calls, Example 56
 SVC_Handler with SVC #imm operand
(example in MDK-ARM Help)
// Stack contains eight 32-bit values:
// r0, r1, r2, r3, r12, r14, return address, xPSR
// 1st argument = r0 = svc_args[0]
// 2nd argument = r1 = svc_args[1]
// 7th argument = return address = svc_args[6]

void SVC_Handler(unsigned int * svc_args) { Ignore SVC#

unsigned int svc_number;
if only one
//Read SVC# byte from SVC instruction code “service” in
svc_number = ((char *)svc_args[6])[-2];
the handler
//Execute code for each SVC #
switch(svc_number) {
case SVC_00: /* Handle SVC 00 */
break;
case SVC_01: /* Handle SVC 01 */
break;
default: /* Unknown SVC */
break;
37
}
}
 Access SVC immediate operand in assembly language

; Parameters in R0-R3 were pushed onto the stack

EXPORT SVC_Handler
SVC_Handler
TST LR,#0x04 ;Test bit 2 of EXC_RETURN
ITE EQ ;Which stack pointer was used?
MRSEQ R0,MSP ;Copy Main SP to R0
MRSNE R0,PSP ;Copy Process SP to R0
LDR R1,[R0,#24] ;Retrieve stacked PC from stack
LDRB R0,[R1,#-2] ;Get #N from SVC instruction in program
ADR R1,SVC_Table ;SVC Vector Table address
LDR PC,[R1,R0,SLL #2] ;Branch to Nth routine
….
SVC_TABLE ;Table of function addresses
DCD SVC0_Function
DCD SVC1_Function
DCD SVC2_Function
38
 System tick timer interrupts
 SysTick Timer is a simple 24-bit down counter
 Interrupt on count down from 1 -> 0
 Counter rolls over from 0 to 24-bit “reload” value (determines interrupt period)
 User provides interrupt handler: SysTick_Handler(void)
 Control register bits:
 0: enable
 1: interrupt enable
 2: clock source
 FCLK = free-running internal core clock (default)
 STCLK = external clock signal
 16: rollover flag (set on count down from 1->0)
 CMSIS function starts timer, enables interrupt, selects clock source and sets
reload value:
#include “core_cm4.h”
SysTick_Config (numberOfTicks); //Ex. #ticks = SystemCoreClock/1000
39