Digital System Design
Verilog-Part III
Amir Masoud Gharehbaghi
[email protected] Procedural Blocks
initial block
always block
Place in module body
Run concurrently with other module constructs
Continuous Assignment
Instantiation (module, primitive)
Sharif University of Technology 2
Initial Block
initial
procedural_statement
initial
begin
procedural_statements
end
Sharif University of Technology 3
Initial Statement
Runs first statement at time 0
Runs once
Until reaching last statement
Suitable for Testbench
Not Synthesizable
Sharif University of Technology 4
Procedural Statements
Procedural Assignment
Blocking Assignment
Non-Blocking Assignment
Conditional Statements
Loop Statements
…
Sharif University of Technology 5
Blocking Assignment
Assign a value to Register type variables
<delay or event> lhs = <delay or event> rhs;
LHS can be:
A Register variable
An element or a range of elements of arrays and
vectors
A concatenation of above items
Sharif University of Technology 6
Blocking Assignment (cont.)
Delay or Event control is optional
Delay: #delay_value
RHS is an expression:
Constant values
Nets and Registers
Operators
Sharif University of Technology 7
Example: Blocking Assignment
reg [10:0] a, b; reg c; wire w1, w2;
integer i1, i2;
a = -23;
#10 b = a + d;
i1 = #9 a & b + {w1, w2};
#50 i2 = #10 i1 - (b + a);
Sharif University of Technology 8
Blocking Assignment Simulation
#delay1 lhs = #delay2 rhs;
Wait for delay1
Evaluate rhs
Schedule the rhs to be assigned to lhs
after delay2
Wait for delay2
Sharif University of Technology 9
Example: 2 to 1 Multiplexer
module Mux2x1 (o, i1, i2, ctrl);
input i1, i2, ctrl;
output o;
bufif0 #(2, 2, 3) (o, i1, ctrl);
bufif1 #(2, 3, 3) (o, i2, ctrl);
endmodule
Sharif University of Technology 10
Example: Test of Mux2x1
module TestMux2x1 ;
wire o; reg i1, i2, ctrl;
Mux2x1 m1(o, i1, i2, ctrl);
initial ctrl = 1;
initial begin
i1 = 0; i2 = 0;
#10 i1 = 1; i2 = 0;
#10 ctrl = 0;
#10 i2 = 1;
end
endmodule
Sharif University of Technology 11
Example: 8 to 1 Multiplexer
module Mux8x1 (o, inp, ctrl);
output o; input [7:0] inp, input [2:0] ctrl;
wire o1, o2;
Mux4x1 (o1, inp[3:0], ctrl[1:0]);
Mux4x1 (o2, inp[7:4], ctrl[1:0]);
Mux2x1 (o, o1, o2, ctrl[2]);
endmodule
Sharif University of Technology 12
Example: Test1 of Mux8x1
module Test1_Mux8x1 ;
reg [0:7] inp; reg [3:1] ctrl; wire o;
initial begin
inp = 3; ctrl = 0;
#20 ctrl = 3'b101
#50 inp = 8;
#10 inp = 1;
#20 ctrl = 4;
end
Mux8x1 (o, inp, ctrl);
endmodule
Sharif University of Technology 13
Example: Test2 of Mux8x1
module Test2_Mux8x1 ;
reg [0:7] inp; reg [3:1] ctrl; wire o;
initial inp = 0; initial ctrl = 0;
initial begin
ctrl = #10 1;
inp = #10 8'b1000_1110;
#10 ctrl = #10 4;
#10 ctrl = 6;
end
Mux8x1 (o, inp, ctrl);
endmodule
Sharif University of Technology 14
Non-Blocking Assignment
<delay or event> lhs <= <delay or
event> rhs ;
Same as Blocking Assignment except:
Does not block until execution is complete
i.e. After Scheduling goes to next statement
Sharif University of Technology 15
Example:
initial initial
begin begin
a <= b; a = b;
b <= a; b = a;
end end
Sharif University of Technology 16
Always Block
always <event_control>
procedural_statement
always <event_control>
begin
procedural_statements
end
Sharif University of Technology 17
Always Statement
Starts at time 0
Runs forever in a loop
When reaching last statement, begins with
the first statement
If event_control specified:
Waits until the event occurs, then starts
execution of first statement
Sharif University of Technology 18
Example
always
#10 clk = ~clk;
always
begin
{c_out, s} <= a + b + c_in;
m <= n * p;
end
Sharif University of Technology 19
Event Control
@ ( list_of_events )
list_of_events: or separated events
events:
nets, registers
posedge … -> transition to 1
negedge … -> transition to 0
Sharif University of Technology 20
Example
@ ( w)
@ ( posedge clk )
@ ( negedge a or b )
@ ( a or b[3] or c[3:1] )
@ ( posedge a or b[1] or negedge c[1] )
Sharif University of Technology 21
Example: 4 bit adder
module Adder4 (s, c_out, a, b, c_in)
input [3:0] a, b; input c_in;
output [3:0] s; output c_out;
reg [3:0] s; reg c_out;
always @ (a or b or c_in)
{c_out, s} <= a + b + c_in;
endmodule
Sharif University of Technology 22
Example: Alu
module alu (s, a, b, sel);
input [3:0] a,b; output [3:0] s; input sel;
reg [3:0] add, sub;
always @ (a or b) add <= a + b;
always @ (a or b) sub <= a - b;
assign s = sel ? sub : add;
endmodule
Sharif University of Technology 23
Example: Alu
module alu (s, a, b, sel);
input [3:0] a,b; output [3:0] s; input sel;
reg [3:0] s;
always @ (a or b or sel)
s <= a + (sel ? –b : b) ;
endmodule
Sharif University of Technology 24
Example: Alu
module alu (s, a, b, sel);
input [3:0] a,b; output [3:0] s; input sel;
reg [3:0] s, m;
always @ (b or sel) m <= sel ? –b : b;
always @ (a or m) s <= a + m;
endmodule
Sharif University of Technology 25
Example: Comparator
module comp8 (a, b, gt, lt, eq);
input [1:8] a,b;
output gt, lt, eq; reg gt, lt;
assign eq = a == b;
always @ (a or b) begin
gt <= a > b;
lt <= a < b;
end
endmodule
Sharif University of Technology 26
Example: Comparator
module comp8 (a, b, gt, lt, eq);
input [1:8] a,b;
output gt, lt, eq; reg mid_gt;
assign eq = a == b;
assign gt = mid_gt;
assign lt = ~mid_gt & ~eq;
always @ (a or b) mid = a > b;
endmodule
Sharif University of Technology 27
Example: D-FF
module Dff (q, q_bar, d, clk);
input d, clk;
output q, q_bar; reg q, q_bar;
always @(posedge clk) begin
q <= d;
q_bar <= ~d;
end
endmodule
Sharif University of Technology 28
Example: D-FF
module Dff (q, q_bar, d, clk);
input d, clk;
output q, q_bar; reg q;
always @(posedge clk)
q <= d;
assign q_bar = ~q;
endmodule
Sharif University of Technology 29
