Overview of Architecture

and Microcontroller
Resources

Chapter Objectives

~ Study the architecture and resources of microcontrollers

~ Learn 8051 and 68 HC11 resources
~ Introduce resources of memory, ports, DAC, PWM, ADC,
timers, and watchdog timer
~ Learn about the 8-bit and 16-bit internal buses
~ Understand the electrically programmable memories
(EEPROM and Flash)
~ Analyse the power-down mode and RTC

In the previous chapter we learnt about the different types of the

microcontrollers (MCUs), their selection, and their various applica-
tions.
In this chapter we will learn about the architectures and on-chip
resources of MCU s. The chapter describes the resources of memory,
ports, DAC, PWM, ADC, timers, and watchdog timer, and power-
down mode. Details pertaining to individual MCUs resources will be
dealt with in later chapters.
 22 Microcontrollers

2.1 ARCHITECTURE OF A MICROCONTROLLER

2.1.1 Functional Overview of 8048 and 8049 Microcontroller

Architecture
Figure 2.1 shows a functional overview with the help of a block diagram of an exemplary 8048 micro-
computer (microcontroller). Understanding of 8048 microcomputer architecture helps in understanding
the 8051 family architecture.
P2.0-P2.7 PO.0-PO.7
Vcc VDD
A8-A15 ADO-AD7
11111111 11111111 11 11
I II .--- -,& I II :Optfonal-----------
Port 2 ~ Port 0 : second register
Bus rJl : b~~~:~,- _
buffer higher ~ lower :: ",:
address On-chip 1kB
PROGRAM address " ,
MEMORY
ROM r-----U-----,
: ::
1 ~: :l
Resister
EPROM : ->,
: MUX
0-: f-
bank
RO-R7
8././ L-",,_~~, : ".., J
, : J :: 8 level
:
I
2 8 v ::
L
Stack
J.....J

~ :7 43 0 11 8 7 0 8
~~ P2l I P2H I PCH PCl
8 Decoder

~ 14* 4*
,,
4

--,,
8
I INTERNAL BUS
,,
,
,.-----,
-t18 8 8
1

I IR
7 07 0
r 10 I TEMP 1 IIFrom ACC ~

Condition
based I-4--_U..,.8 1=8"7=:t::j~
branch
logic

:/, /
Tr-++~'----q I adjustor
I Decimal

, -'

:-1 CONTROL AND SEQUENCING lOGIC ~-'-:------+-'>-+-X-TA-l 2

:
,

:---------- - --- --- ------------------- ---

i'

L- __
'
I

: -I ~~~~~ r~et INT

RD WRAlE EA

Figure 2.1 Functional overview (block diagram) of an exemplary 8048 microcomputer (microcontrolier).
 Overview of Architecture and Microcontroller Resources 23
It shows the CPU, clock circuit (oscillator circuit), and reset circuit as in a microprocessor. There is
ntrol and sequencing logic with signals like in a microprocessor. There are flags for the processor
ill as in the microprocessor. Abbreviations used in Figure 2.1 are as follows: PCL-program counter
-er byte; PCH-program counter higher byte register and its 2-bit out bus to program memory in
, 3-bit in 8049 and 4-bit in the 8050 and unextended 805118052 families; P2H-Port 2 higher
ble (4-bit); P2L-Port 2 lower nibble (4-bit); MUX- Data/address multiplexer; IR-instruction
regi ter; ID-instruction decoder; ACC- accumulator latch; A-Accumulator; EA - external address
le signal (to disable use of on-chip ROM when = 1 kB); RESET-signal to reset the CPU when 0;
• ~ AL2 and XTALl-crystal oscillator inputs for the processor clock; PSEN - program store enable
en 0 (means read the byte from external program memory); RD - read the byte from external data
mory; WR - write the byte to external data memory.
ections other than CPU are as follows:
1. Since an MCU can be used as a single-chip microcomputer with embedded program in ROM
there is an extra feature-on-chip ROM. The ROM is 1 kB in 8048 and 2 kB in 8049. An internal
RAM saves the temporary variables and stack. The RAM is 64 Bin 8048 and 128 B in 8049.
/ '\ CHIP/PROGRAM
Vcc
supply

Voo
Standby
- power supply
INT

MICROCOMPUTER
(Microcontroller )

8048 lJ pO.o-PO.7
ADo-AD7
PIN

SIGNALS SS Single step

XTAL 1 I-' WR Data write
RD Data read
XTAL2
PSEN Program
"<, memory
EA store (read)
" enable
Vss " External
I ./ ALE address enable
Supply
Address
ground
latch enable

Figure 2.2 Pins/signals in an 8048 series microcomputer.

2. For connecting to additionally needed external memory, there is a program counter lower byte
MAR (memory address register), which can also be used as port (connects through bus buffer)
when the MCU operates in a single-chip mode. There is program counter higher byte MAR which
can also be used as Port 2 (connects through bus buffer) when the MCU operates in single-chip
mode. In this case the Port 2 has the latch and buffer for the port operations.
 24 Microcontrollers

3: Since an MCV is expected to interact with the I/O devices (ports) like the key board and LCD
display, it has I/O ports unlike the microprocessor. For example, there is Port 1. It has the latch
and buffer for the port operations in that case.
4. Since I/O devices may be interrupt driven, there is an interrupt service mechanism and interrupt
circuit, priority assignment, and interrupt mask. The mask is to disable an interrupt source during
a specific time critical action(s).
5. Since an MCV may be required to do real time control of events and tasks, there is a program-
mable timer/event counter(s).
The 8048 microcontroller has the following sections.
1. CPU of 8048 to process instruction within the instruction set.
2. Address cum data time multiplexed bus signals ADO to AD7, RD, WR, ALE, and PSEN. In
expended chip mode bus is connected to the external pins for address bus signals ADO to AD7.
When active, the address latch enables signal at pin ALE and the bus separates address signals.
- - --
Whenever ADO to AD7 bus has the data signals, the signals at RD, WR, and PSEN select
data- either reads from data memory or writes to data memory or reads from program memory.
In a single-chip mode, instead of the signals ADO to AD7, the same pins are for bidirectional Port
- -
o
pins-PO.O to PO.7. In a single-chip mode, the RD and WR pins become P3.7, P3.6 pins to
provide bidirectional signals for Port 3.
3. Address bus A8 to A 15 output bits. In single-chip mode, these are the input cum output Port 2
pins-P2.0 to P2.7. In expended mode, it provides output as the external address bus signals A8
to A15.
4. Oscillator. It connects the XT AL 1 and XT AL2 pins.
5. Reset circuit, which connects to RESET pin.
6. ROM 1 kB (EPROM 1 kB in 8748).
7. RAM 64 B (128 in 8049).
8. Interrupt external through !NT pin.
9. An 8-bit timer/even counter

2.1.1 Microcomputer Pins and Signals in 8048 Series

Figure 2.2 shows the pin signals in an 8048 series microcomputer. Table 2.1 lists the pin signals.

TABLE 2.1 Pins in 8048.

Name of 10rO Name of lor 0 Name of 10rO Name of 10rO

the signal I/O the signal I/O the signal I/O the signal I/O

PO.O/ADO I/O P2.3/A 11 I/O INT/P3.2 1/0 RESET I/O

PO.1/AD1 I/O P2.21A10 I/O P3.3 I/O XTAL2 I
PO.2/AD2 1/0 P2.1/A9 I/O TO/P3.4 I/O XTAL1 I
PO.3/AD3 I/O P2.0/AD2 I/O P3.5 I/O Vss GND

PO.4/AD4 I/O P1.0 I/O WR/P3.6 I/O Voo

(Contd.)
 Overview of Architecture and Microcontroller Resources 25

Name of 10rO Name of 10rO Name of 10rO Name of 10rO

the signal I/O the signal I/O the signal I/O the signal I/O

PO.5/AD5 I/O P1.1 I/O RD/P3.7 I/O VCC

PO.6/AD6 I/O P1.2 I/O PSEN I

PO.7/AD7 I/O P1.3 I/O ALE 0
P2.7/A15 I/O P1.4 I/O EA
P2.6/A14 I/O P1.5 I/O SS
P2.5/A13 I/O P1.6 I/O
P2.4/A12 I/O P1.7 I/O

2.2 FAMIL Y MEMBERS

microcontroller family member has the same basic architecture, but can differ in the number of pins
d the mode of packaging. Further, there are different variants as shown in Tables 1.1 and 1.2 for the
-I and 68HCIlJ12 families. Figures 2.3 and 2.4 show the families of 8051 series and 68HCIlJ12/16
ries and resources in these.

2.3 MICROCONTROLLER RESOURCES

2.3.1 Bus Width

ternal Figure 2.1 shows the internal bus width of 8048 as equal to 8. Similarly, 8051 and 8096
ilies have the 8-bit bus width. A control and sequencing unit activates different sections and subsec-
at different instances, therefore, the same 8-bit bus is used for internally carrying all the data,
e es, and instruction codes. Registers and internal RAMs need only 8-bit addresses.
Bu width equal to 8 is sufficient because two operands of 8 bits each only can be added or subtracted
_ .he ALU of 8048 as well as 8051. A 16-bit operation has to be performed in two separate instruction
__ .e and the 32-bit operation in four cycles .
. IC68HC 11 internal 16-bit address bus accesses in single cycle and that facilitates access to
- = 64 kB. The 8048/8051/8096 facilitates access only in two cycles.
ernal External address bus width (AOto A15) is 16 in 8048/8051 as well as 68HC 11. Therefore,
.ernal address space is 216 = 64 kB. (lkB memory = 1024 B.)
External data bus DOto D7 multiplexes with AOto A7 by time division multiplexing in 8048/8051 as
U as 68HC II. A byte of code or data can be transferred at an instance. The time during which address
h enable (ALE) is active (=1) there is the address at bus. The time during which the ALE is inactive
= 0). there can be the data on the bus (ALE is called ADV (address valid) in 68 HCll).
26 Microcontroiiers

1 8051 Series
T
I I

18051 Families 1 1 8052 Family 1

1
T I I
18051 Classic 1 18051 Extended 1 1Philips 8051 Mxl

I I
Unified 64 MB
8-bit data bus program/data
16-bit address bus 8051 with 128 kB internal/external
64 kB ROM external data, extended 16 8MB ROM +8
64 kB external data MBROM MB constants
Timers TO,T1 extented 16 MB
UART, synchronous serial data 256 B 16 bit
internal ROM 4 KB, RAM 128 B internal RAM configurable stack
Two external interrupts pointer
768 B RAM

80251 Intel/Atmel
8051 with 256 B
8/16/32 bit
internal RAM
address space plus timer T2
like 8051 MX

Figure 2.3 ] Families of 8051 series.

68HC11 /12/16
Familes

r 1 1
8 bit family 16 bit family Family 68HC16
68HC11 with 68HC12 16 bit HC11
variants extended 68HC11 HLL support
0-12 kB ROM 4 MB space programmable
EEPROM 8 channel timers sample hold, 16
ADC or No ADC 16 bit pulse channel queued
64 kB counter ADC,
unified data/ accumlator system integator
program address 12 Ports for
---
space programmable chips.
4 ports 1MB + I MB

• Figure 2.4 I Families of 68HC11 /12/16 series.

 Overview of Architecture and Microcontroller Resources 27
ternal data bus width (DO to D7) is 8. Therefore, since AO to A7 multiplexes with DO to D7,
emal address space is 216 = 64 1eB.(l1eB memory conventionally means 1024 B.) External data bus
o 07 multiplexes with AO to A7 by time division multiplexing. Using a latch like 74LS373, the
,u1re~)sbus can be latched from ADO-AD7 to the memory/port devices.
Eternal data bus width can be optionally 8 or 16 in 8096 series family. The AO to A7 or AO to 15
iplexes with DO to D7 or DO to D15, respectively. In 8096 series, the 16-bit operands are aligned
that the lower and higher bytes are at the even and next available odd addresses.
- gure 2.5 shows the bus widths in three series-80S 1, 68HC II, and 8096. ALU performs in a cycle
. , and 16-bit operand operations, respectively. Instructions can perform operations on l-bit, 8-bit,
6-bit operands in 8051 and 68HC 11 and up to 32-bit operands in 8096. Each MCU has an internal
f fixed width, which controls all the operations in an instruction cycle of the MCU.

68HC11
8051 series ALU 8096 series
ALU 8-bit 8-bit ALU 16-bit 18-bit
operands operands operands

'I'D TJ "I'D
15-

...
...
1\

' '
o 0 ... o ... 8 0 ...
--

'~I 1: 1:1 :1
Instructions: 1,8,
16-bit operands
Instructions: 1,8,
16-bit operands
O~
II \
Instructions: 1,
8,16 or 32-bit
operands

Internal bus 8 bit

~

D..
... ADo-AD? external 8 bit multiplexed lower bits

B As-A1S external address 8 bit higher bits

m Internal bus 16 bit

Option of ADo-AD15 external 16-bit multiplexed bus

~
Figure 2.5 Bus width in various families.
 28 Microcontrollers

2.3.2 Program and Data Memories

Program memory Program functions and routine in an MeV are mostly in a non-volatile r
only memory (ROM). Table 2.2 gives the exemplary contents at the program memories in the Cl-
based system .

TABLE 2.2 Exemplary contents in the program memory in a system.

Memory Exemplary contents Preferred type

of memory

Program Program functions, routines, boot-up program, and interrupt On-chip or extema
memory" service routines for the system after the development phase EPROM or Flash a
is over. Standard macros and functions for program building laboratory test stage
blocks functions, for example for preset delay, for UART masked ROM at ma
communication at the pre-select baud rates; needed library production stage.
functions, for example for finding maximum, minimum,
average, and standard deviation values among the set of
values, for sorting the set of values in descending or
ascending order.
Permanent constants for the bytes for displaying the On-chip EPROM or
pictogram for the companies emblem on LCD display; Flash at laboratory
constants for maximum and minimum limits, for example, test stages, Masked
channels 0 to 99 in a TV remote control, number of ROM at mass
maximum acceptable digits in the phone number when production staqe."
dialing.
Strings for the product version, welcome messages at the On-chip EPROM or
start of the system, messages for system-status display, Flash at laboratory
operational menus for selection (like in press 1 for measuring test stages, masked
voltage, 2 for current, 3 for resistance, and 4 for frequency in ROM at mass
a MCU-based multimeter test equipment), name and contact production staqe."
addresses of the manufacturer.
Modifiable constants and intermediate non-volatile data for On-chip EEPROM
the current values or results for validity date for an account, or Flash."
password, and user ID and present balance in the account,
data and time of last transaction, calibration constants of a
sensor element or telephone numbers in a digital diary.

BAtcommonaddressspace whenarchitectureis Princetonand at separateaddressspace(s)when it is the Harvard

architecture.
bOff-chipvaluescan be at the data memoryspaceat externalEEPROMor Flashor EPROM.
 Overview of Architecture and Microcontroller Resources 29
OYi can be in the form of EPROM during the laboratory testing phase. For example, 8751 erie
ber has the on-chip EPROM and 8951 series member has the flash. The EPROM can be erased b
ight. All the bytes can be erased in each erasing cycle. Flash can be erased by electrical signals and
ffers an advantage of sector-wise erase (a sector may be 1 kB or 2 kB or 4 kB). A laboratory device
.-..-rr..mming tool in case of the MCV having the on-chip EPROM or flash, EPROM chip, flash,
OM, or CPLD is used (Section 12.7). It consists of hardware (with socket for placing the erased
OYi or MCV on-chip PROM) and software. The software takes a file for the codes as the input.
n it runs, it burns the codes and constants into the MCV. Burning is the process to write and install
_"tesat the predefined addresses as per the program(s) and its constants (Table 2.2).
OYi can be in the form of masked ROM after the finally tested and approved phase. The 8351 series
bers have the ROM area in 8051 MCV. A ROM is a factory programmed by first setting a mask,
ets Is and as at the predefined addresses as per the program(s) and its constants. ROM chip or
A area in MCV has an un-etched metal layer, which is etched as per the mask to get Is and as as per
OM image needed to be burned in the ROM in place of all Is before the treatment at the manufac-
ite. For mass production of the systems, ROM is the best alternative and cost decreases with
_ e e in the requirements.
Certain constants, for example, calibration constants of a sensor element or telephone numbers in a
= tal diary can be in the form of EEPROM (electrically erasable and electrically programmable
• I ) ( Table 2.2). These can be modified later. EEPROM bytes can be set online, when running a
gram or by using the device programmer. The advantage of EEPROM is that it can be erased byte by
before writing and can be used for non-volatile constants or intermediate status or result or the final
t of a program.

ta memory Data variables and stacks in an MCV are mostly in a volatile read and write memory
Yi) or registers. Table 2.3 gives the exemplary contents at the data memories in an MCV-based
~ em. (Note that Table 2.2 referred to constants and strings not in internal on-chip program memory
e that can also be at the data memory space.)

ABLE 2.3 Exemplary contents in the data memory in a system.

emory Exemplary contents Preferred type

of memory

Data memory Direct or indirect or both addressable bytes for On-chip RAM
the variables, pointers, look-up table, limited size
array and individually addressable bits.
Stack of all program function program counters
and saved variables.
Device (includes port) control parameters and On-Chip registers
status parameters, the device/port individually (special function
addressable bits. registers in 8051
families) if available,
else on-chip RAM

(Contd.)
 30 Microcontrollers

Memory Exemplary contents Preferred type

of memory

Extended direct or indirectly addressable (or External RAM.

both, it depends on the MCU family) data for
examples, for the online large buffer, queues,
pipes (for examples for printing and for fax),
online file-data or network stream.

Note: (1) Data memory can have distinct separate address spaces like program for the individual bits and bytes,
for the stack, for the registers and RAM in 8051 families.
(2) In separate address space than the program memory in Harvard memory architecture and in common
address space in Princeton memory architecture.

MCUs mostly have on-chip program memory as the ROM or EPROM or flash and internal RAM and
registers.

2.3.3 Parallel Ports

Table 2.4 gives the various types of the ports in the MCU-based systems. Figure 2.6 shows the different
port types. An MCU parallel port is of 8 bits, unless the port bits become less during the alternate use of
certain bits. A microcontroller in a single-chip mode provides few ports at the chip itself. Number of
port pins at the chip reduce when using the expanded mode (external chips) (Table 2.1). The 8048-MCU
has four 8-bit parallel ports in a single-chip microcomputer mode of operation. Port PO is used as
ADO-AD7 lower byte addre s a well as 8-bit data bus when the off-chip access mode MCU accesses
the external memory chips or device (or ports). Port P2 is used as A8-A15 higher byte address bus
when the MCU is in off-chip access mode. The alternate use of Port P3 pins' is for the control and
interrupt signals. The 8051 families have similar architecture for the parallel ports.
MCUs have memory mapped 110 devices. 110 devices share the same address space as the internal
memory and external 110 devices share the same address space as that with external data memory.
Hence, an MCU can interface with large number of ports (theoretically as many as the address space
permits). Exemplary need of large number of ports is a telephone switching exchange. Multiplexing and
de-multiplexing circuits also provide the expansion to more number of ports.
Usually, a port is either an 110 port or input port or output port for all the bits together. However, if an
8-bit port has a data direction register (DDR) of 8 bits, then each bit of the port can be set for the input
or output as per the bit t at the DDR (Fig. 2.6.(c)). The 68HCll families provide these features in a
few ports in them (Section 14.3.1).
 Overview of Architecture and Microcontroller Resources 31
Port Port

Port latch
Port latch 8

Bus buffer

(a) (b)

={i
Port
Port

B{! (c) (e)

If--STAA
~STAB

AMUX Port

~----

Port
l
latch

(d)

Figure 2.6 (a) An 8-bit 10 port. (b) An 8-bit port with the bus buffer. (c) An 8-bit port with a data
direction register bit for each port bit, which sets to either 1 or 0 (in 68HC11/12).
(d) An 8-bit port analog as well digital inputs for either multi-channel ADC or for port
input operations. (e) An 8-bit port with two handshaking signals-STAA for strobe or
acknowledgement signal from the external device and STAS for port to the device
(Section 14.3.1).

TABLE 2.4 Port types in the MCU-based systems.

Port type Example

Eight-bit port with latch for Port P1 in 8048 and in 8051 classic family members
input or output or 10
operations (Fig. 2.6(a»
Eight-bit port with latch as Port POand P2 in 8048 and in 8051 family members, which are also
well as bus buffer for usable as the for ADo-AD7 and A8-A 15 bus as well as the 1/0 ports
address, data, and control with a latch.
buses (Fig. 2.6(b)) Port PB output port as well as A8-A 15 bus and Port PC for the 1/0
with handshaking mode also usable as ADO-AD7 in expanded
mode in 68HC11.

(Contd.)
 32 Microcontrollers

Port type Example

Ports P3 and P4 in 8096 families are usable as ADO-AD? and

A8-A 15 bus (option 1) and as ADO-AD? and AD8-AD 15 bus (option 2).
Port P3 in 8051 families and port P2 in 8096 families provide UART
and control bus signals in expanded mode.
Eight-bit port with data Ports C and D in 68HC11
direction register
(Fig.2.6(c))
Eight-bit input port with Port E (4-bit in certain versions) in 68HC11 with analog inputs for
analog inputs capability multi-channel ADC inputs; Port PO in 8096 families.
(Fig 2.6(d»
Eight-bit port with Port C in 68HC11 is also usable in conjunction with the handshaking
handshaking signals signals.
(Fig.2.6(e»
Open-drain port An open drain (OD) port needs external active (MOSFET or BJT
transistor) or passive (resistive) pull up to output logic 1.
Quasi bidirectional port An open drain (OD) port needs external pull up to output a logic 1,
however, a quasi bidirectional port provides for 1 LSTTL gate driving
capability for few clock cycles so that in case of the use of the LSTTL
latches, for examples for interfacing the external memory chips, the
external pull circuit(s) is not needed.

General notes and instructions for using the parallel ports are as follows:
1. One handshaking signal for strobe request from an input device or acknowledgement from an
external output device. The other handshaking signal is port acknowledgement for port ready
signal to the inputting device or port buffer output full signal to an output device.
2. If an OD port is to be used for the input, the l(s) must be first written. This is to bring output stage
transistor to a non-conducting state from the last state, which may be a conducting state when 0
was sent to the output.
It should be noted that an MCU has a few parallel ports usually, 8 bits each. Port bits can also be put
to the alternate uses and the external buses to the interfacing chips.

2.3.4 EEPROM and Flash

Figure 2.7 shows the types of EEPROMs (electrically erasable and electrically programmable ROMs).
EEPROM is of two types-EEPROM and flash EEPROM (also referred simply as flash). An erase
cycle and write cycle is 10 ms in 68HCIl. Read cycle time of EEPROM or flash byte is same as that in
a RAM.
Table 2.2 shows the values that store an EEPROM and flash store. Usually, an EEPROM erases one
byte at an instant. Flash EEPROM is when a sector consisting of many bytes (say, 1024 Bar 2048 or
4096 B) can be erased. All bits are made Is by placing all floating gates of a sector together in place of
each independent in EEPROM. However, sometimes flash is used for EEPROM that has the
capacity to erase one or a few in a row byte in an instant. The 68HCli has some interesting features.
 Overview of Architecture and Microcontroller Resources 33
n-chip EEPROM can be used in three modes (each in one single cycle with 10 ms erase time) as per
e bit in the configuration register.

EEPROM

Option 1 Option 2 Option 3 r-----------,

I I
-----------1 I
I
I
I
I
1 Sector I
I

Byte by A row of Complete

I
I
1 Sector I
I erase I
I
I I I
byte bytes erase per I erase per I except one I
I I

erasable erasable cycle I cycle I OTP sector:

I I I

per cycle per cycle I

I
I
I
no erase I
I

'-- - - - -- - -- --' ----------- I

Flash Boot mat

flash

Figure 2.7 Types of EEPROMs and flashes.

1. Erase one byte when modifying a variable online.

Erase all addresses EEPROM.
3. Erase 16-byte EEPROM row of addresses.
A variant of flash is boot mat flash. A sector (block) in boot mat flash is OTP (one time
grammable). Boot-up program is one that runs on start up. Hence, OTP sector of flash can be used in
ace of the ROM or EEPROM for the boot up.
EEPROM is of two types, EEPROM and flash EEPROM (also referred simply as flash). An erase
ycle and write cycle is 10 ms in 68HCll. Read cycle time of EEPROM or flash byte is same as that in
RAM. There is great technological advancement in flash designs, like zero wait state 50MHz (Table
- 01). Nowadays, 512 MB flash in a chip is available. It is used in digital cameras and for video
re ording. It can record five hours of music. A flash variant is a boot mat flash.

2.3.5 Pulse Width Modulated Output (PWM)

An MCV pulse width modulated output (PWM) is used to obtain the digital to analog conversion (DAC)
peration. The DAC operation is needed in many control related operations. For example, DC motor
ontrol and heater current control. PWM output is one in which the width percentage is proportional to
the modulation parameter p, which relates linearly to the analog voltage.
Figure 2.8(a) shows the PWM output. The pulse width percentage is (l00)(256-p)/256, where pis
the modulation parameter in an 8-bit pulse-control register. Analog output is obtained when the PWM
output is integrated by an integrator. The output has a linear relationship with bits for p, which is
programmed using an instruction.
Figure 2.8(b) shows analog outputs in two cases as a function of pulse width percentage and pulse
control register parameter.
 34 Microcontrollers

Case 1: It is assumed that the integrator-l design is such that the output V is maximum when p = 255
and is 0 when p = O.
Case 2: It is assumed that the integrator-2 design is such that the output v is maximum when p = 255
and is - v when p = O.
Figure 2.8 (c) shows the application of the MCV pulse count and control registers for the pulse width
modulation. This is assuming that there is an 8-bit internal PWM output control register,
PWM_CONTROL. Software can write p at its address in the MCV. Let a counter run in a free running
mode and the count value be c at an instant. A PWM output will be obtained by an operation in which
at the port bit or PWM output pin the output is 1 when c > = p, and 0 when c < p.

(256-p)T
/ r-. 256-p
// ! "",~ulse width percentage =~ 100
," I •••

PWM input
----lIINTEGARATOR -1 1
(a)

analog output
0
z~------>
V

o
5001

128 255
pulse width

• P

v
+v
PWM input analog output
-~-~----l---~P
---IINTEGARATOR -21 0
-v
o
-----r------r--------~
50% 100% pulse width
-v
(b)
clock
pulses

count register Port '1' for duration

value = c (256 - p).T

PWM
'0' for
I I
I I pulse control duration p.T
~ •• )I I
register

Period Loads value =p

(c)

Figure 2.81 (a) PWM output. (b~AnaIOg outputs in two cases as a function of pulse width percentage
and pulse control register parameter p. (c) Application of the MCU pulse count and control
registers for pulse width modulation.
 Overview of Architecture and Microcontroller Resources 35
PWM_control register can be an out-compare register (OCR) in an MCV. The OCR can be loaded
value p, which it compares with the count value c in the free running counter. The MeV generate
interrupts-one on c = p and other when c = 0 after c = 255. A program loads the value of p as per
needed width percentage.
The count register can be a PACT (Pulse count accumulator) in an MCV. The PACT is periodically
ed with the modulation parameter such that the interrupts at that instances generate Is and Osat each
_ CT overflow interrupt.
An MCV with on-chip PWM operation is needed in many instrumentation and control related opera-
n for obtaining a DAC facility. It generates the pulse of width percentage as per the bits loaded into
ulse accumulator register or PWM-control. Analog output voltage v generates from an integrator. It
z: 'e the output such that it maps to the decimal value loaded in the register. Many MCV variants have
-chip PWM device and the device is used to generate analog outputs through an external integrator.
'M operations can also be implemented indirectly by using a non-stop, no reset timer.

2.3.6 On-Chip D/A (DAC) Using PWM or Timer

DAC stands for digital to analog conversion such that the analog current or voltage output relates lin-
early to the digital values (inputs). The PWM device with PWM control register, an MCV, can be used
- the DAC by installing an appropriate integrator that interfaces with the MCV.
An MCV not having a PWM device but having a timer or a counter/timer with an out-compare
gister or PACT can be programmed to obtain a PWM output, which in turn gives the analog output
through the integrator.

2.3.7 On-Chip AID Converters (ADC)

Many times, a microcontroller has an on-chip AID (called ADC also) conversion feature. This is an
important feature in the control applications. Figure 2.9 shows an MCV with an on-chip ADC. The
ADC operation is needed in many control related operations. Some examples, are the sensor or
transducer input in the instruments measuring the ECG wave form, temperature, pressure, position by an
LVDT, relative humidity and weight by a load cell, DC motor control, heater current control.
Consider a case in which a microcontroller has an ADC device. The ADC is fed a certain signal
(input analog voltage), v through an amplifier, which first samples the signal for a certain period
(- 1 us) and then holds it for the required time. Sampling the signal is averaging for a certain period.
Sample hold circuit amplifier, called sample and hold amplifier (S/H) gives the value close to the true
value. This is because the random noises in this period cancel during averaging.
After conversion to the digital bits that map to the signal ratio [v / (V ;ef - V~ef)]' the converted bits
can be latched at a port in the MCV or used for control applications. Here, V :ef and V;ef are the
reference analog inputs to the ADC, set such that when v = V ~ef with all output bits equal to 1 and
v = V;ef with all output bits equal to O.Mapping means the output bits bo, bl, ••• , bn_1 are such that the
decimal values of these is proportional to signal ratio. These ADC device bits bo, b i, ... , bn_1 are stored
in a register. A program can make it available at the port for use by the external circuit. At constant
programmed intervals, these bits may be updated.
 36 Microcontrollers

V at a port pin
Analog GND
-
End of
r---- V·ref= GND
conversion
option 1

ADC S/H and ADC f--- External V ~ef

register device in
n j-
latch - MCU
.~ Q;

~
+~ f--- V~ef programmable ] option 2
->
ctI~
resister
E-
n-bit 'u>
Ql •
ADC -0;:- option 3
register lii ,
-c:
.!!1N r---- Vief programmable
Ol~
~ II resister

! oQl
02
«~
Conversion over'---
interrupt
1
Start of
conversion( s)

Figure 2.9 An n-bit ADC device in an MCU.

In certain MCVs, V;ef is programmable or not programmable but fixed by an external circuit. The
V~ef is fixed and is equal to analog ground potential. In certain MCUs the programmability of the V~ef
become extremely valuable for instrumentation and control related applications, when both the V;ef and
V ~ef are programmable.
An MCV with on-chip ADC operation is needed in many instrumentation and control related opera-
tions. It converts analog input voltage v and gives the digital bits in the output such that the decimal
value for these maps to the signal ratio is [v / (V ;ef - V~ef)]' The converted bits can be latched to a port
or used for control applications. Here, V;ef and V~ef are the analog inputs to the ADC, set such that when
v = V;ef the all output bits = 1 and v = V~ef' all output bits = O.Many MCV variants have on-chip ADC
device and the device accepts multiple analog inputs one by one.
 Overview of Architecture and Mir.rocontroller Resources 37
2.3.8 Reset Circuit
Certain processors start like 8051 MCU processing from OxOOOO (OxFFFFOin 80x86). Certain proce -
ors tart from an address as per the bytes programmed earl ier at a fixed memory location. For example,
68HClll12 starts processing from the address defined by the bytes programmed at OxFFFE (caJled
vector address for the reset). The MCUs 68HCll and HCl2 have two start-up addres es. One is as per
power-up reset vector address OxFFFE bytes and the other is as per reset vector at OxFFFC bytes. The
latter is for start after the Reset instruction executes or after a time-out from a watchdog timer occurs.
Reset circuit forces a processor to start the processing of in tructions from a starting address
moothly. Processor inputs should not misread any pin logic state by not letting in the intermediate state
voltage levels. Smooth starts mean without glitches-sharp variations between low voltage and needed
oltage. The intermediate levels must not exist in the MCU, for example, between 0.33 Voo and 0.66Voo,
where Voo is the MCU supply voltage and Vss is the supply negative end, which is tied to the ground
potential.
A push-button switch may also be interfaced with MCU through the reset circuit to start the processor
from the beginning start-up address. When there is a power glitch, the processor reset circuit should let
the processor start smoothly from the beginning and prevent the intermediate voltage levels. In addition,
when a clock monitor detects the MCU slowdown below certain frequencies due to a fault, the reset
must activate.
The reset circuit activates for a few clock cycles and then deactivate to let the MCU processor start
executing the instructions. There is a reset pin (Table 2.1) in the MCU. It becomes input on power-up
and becomes output pin for a few clock cycles to enforce reset state in other interfaced external devices
with the system. The pin finally deactivates after the program execution begins.
Reset circuit (Fig. 2.10(a)) can be an external IC circuit like MAX 6314 and Motorola MC 34064.
ote that on reset, not only the program counter reloads but also the default processor values reload.
A reset circuit or device resets the microcontrollers so that a processor starts smoothly. This means
that the processing of instructions from a starting address prevents the intermediate voltages between
o and 1, and all the processor registers and devices and interfaced devices get the default values. The
tart address on reset is programmable in certain MCUs. Reset activates for a few clock cycles.

2.3.9 Watchdog Timer (WDT) Device

The watchdog timer is a timing device that resets the system after a pre-defined timeout. It resets and
then the further processing is from the same address as at the beginning on the power-up or as per the
bytes at a vector address in certain MCU timeouts of the WDT. Most microcontroller variants of an
MCU family have on-chip watchdog timers.
MCU timeout period can be programmed among the choices available in certain MCUs. The WDT
and its timeout period are usually activated and programmed within the first few clock cycles of
instructions after power up.
WDT has many applications. It rescues the system if a fault develops in between. An example is
when a program hangs due to an interfaced circuit fault or loop not exiting due to an exception condition.
On restart, the system is expected to function normally.
 38 Microcontrollers

INPUT
" Active low for a few clocks cycles
I

r--------,
LTr-------, Reset
Trigger on power up or by a
pushdown button

circuit

MCU
RESET

OUTPUT
Active high for a few clock cycles

(a)

WOTI disable by
Progra mmable WOT writing a code
presca led timerl
interna I counter --+-
clock in put
WOTI
Compare

r-
WOT enable by
writing a code
WOT register

WOTI: WOT interru pt

(b)

Figure 2.10 (a) Reset circuit. (b) Watchdog timer device in the MCU.

Consider a system controlling the pressure in a tank in an industrial process. A sume that when the
program starts executing, the pressure transducer inputs work. However, before the de ired pressure is
achieved, the input circuit develops some fault. The controller will continue to boost the pressure in the
tank. The boosting will continue jf the system is not reset. Absence of watchdog time facility can thus be
catastrophic due to tank burst.
Figure 2.1O(b) shows the working of a non-stop timer/counter used as a watchdog timer. V Value at
a reset pin becomes identical to the one expected after a +5V power up or on an external reset signal at
the microcontroller, The watchdog timer is usually programmable. It is like a free running counter with
an output compare register, which on equality situation causes the program counter to be loaded with the
initial value.
A watchdog timer device is a timer provided within the microcontroller, which resets it such that it
starts execution of the instructions from the beginning. The timer initial value, which loads, can be
programmable in certain MCUs. The start address on watchdog timer reset can be programmable in
certain MCUs.
 Overview of Architecture and Microcontroller Resources 39
2.3.10 Bit-Wise Manipulation Capability
Figure 2.11 shows the various bit transfer or manipulation instructions. The 8051 family MCU has
powerful bit manipulation capability and has a bit manipulation capability with the carry bit playing th
role of an accumulator. The role is similar to the accumulator A during the ALU operations. A flag ca
be set or reset. A port bit can be set, reset, complemented, transferred or logically operated. The bit ca
perform these operations in a bit-address space.

Bit of special function

resister address ,,
,,
,,
,,
,,
,,
,,
Bit at a port address ,
.......... -,
...•...... "
..•..•.......•.....•.
Logic operations,
set, reset,
complemented or
Bit at a bit address transfer

--- OPERATION--

Carry bit as 1-bit

accumulator

--- OPERANDS -

Figure 2.11 Bit manipulation operations by a Boolean processing unit in 8051 family.

2.3.11 Power-Down Mode

An MCU-based system may be designed such that it need not be switched off at any time. In this case the
processor runs in the power-down mode. The MCU initiates certain actions on execution of the WAIT
and STOP instructions. The stop state can also occur when clock inputs to a processor stops ticking or
the program has been designed such that it shuts down automatically. During the stop state the MCU
disconnects external devices and the internal clock circuit is deactivated. The battery-backed RAM
activates and protects the protected area. When there is an external interrupt or reset, the MCU
reactivates and forgoes the stop state.
A STOP instruction execution can be enabled or disabled by a bit in a configuration set register in
certain MCUs. The 80S1-MCU provides a power-down mode bit for serial communication. The bit-
transfer rate can be slowed by half, so that power is saved during communication from the MCU.

2.3.12 Timers
Timers are a must for the real time operations in any system (Chapter 6). Figure 2.12 shows the impor-
tant modes of timer functioning in the MCUs.
 o Microcontrollers

Clock
Prescaler 8 or 16-bit timer f---- Timeout loverflow
interrupts
Fixed or Real Time Clock
(a)
programmable Interrupts (RTCI)
Timer feature L- __ Output transition or
toggle

I
Free running Pre loadable Resettable Stopable Auto reload
counter (FRC)
(b)
FRC FRC

ClKI Timer ClKI

OV
Interrupt
16
+ve or - ve edge Out compare
or Toggle r--ln-puLt------, (OC)
input capture one or multiple
change one or multiple
IC
(c) Interrupt (d)
FRC Output
change
ClY ~TCI

(e)

The important modes of timer functioning in the MCUs.

A timer counts the equal interval clock pulses from an oscillator circuit. The pulses are used after a
suitable fixed or programmable pre-scaling (division) factor.
1. A timer can be used in different modes.
2. A timer/counter mode runs in a non-stop, reset, and load disabled state. It, therefore, is also used
as a recorder of an actual time (real time) since the start.
3. For example, we capture the time at the start of the swimming and recapture the time at the end of
swimming. The difference gives the time clocked by the swimmer. Similarly, a timer in non-stop,
reset, and load disabled state can be used for capturing the times at the different input instances.
The timer saves the current timer value into an input capture register for use as a time recorder for
an instance of occurrence and for the interval between the two events.
4. We preset a time instance in an alarm and the clock on reaching that time alarms a ring. Similarly,
a timer in non-stop, reset, and load-disabled state can be used for comparing the different
predefined instances for the programmed outputs (Is or Os) or toggled outputs and generates
interrupts on each successful comparison.
5. Use of the timer in another mode as a real time clock is described in the next section. It gives the
repeated interrupts in order to initiate the events at regular intervals.
8051 family MCU has two programmable timers, TOand Tl. The 8052 variants in the family have an
additional timer T2. 8096 family MCU has the two programmable timers, TI and T2. Tl facilitates the
high-speed inputs unit. It captures the time instances into a FIFO and records up to eight events in quick
 Overview of Architecture and Microcontroller Resources 41
S::;:::'Ce'~sion.It facilitates the high-speed outputs (HSO) unit. It compares the time instances with t
time instances and initiates the HSO actions. It compares up to 16 channel instances in quit
R::'Ce'~sion.
HClll12 family has a main timer, which is a free running counter (FRC). It is used as inp
e . as real time clock and as out compare modes described above. Motorola family MCUs have
erful unit for real time processing. It is called a timer processing unit (TPU). The 68HC16 has
• ·ith a microprogrammed control unit, control memory, and a library of more than 20 differer
:::functions. This facilitates the fast real time controls because of the separate instruction processin
- d in processing the capture operations and compare operations with the timers .

.13 Real Time Clock

CU is said to have a real time clock device if it can make or have one of the timers non-stop and ne
and load-disabled state. The interrupts from this timer, once enabled, cannot be disabled. The timer
row interrupts now acts like a clock that ticks at regular intervals. Timer overflow means transition
its all Is to all Os output state. If the timer does not stop, it repeatedly interrupts at constant
als and it gets inputs from an internal clock continuously after appropriate scaling by a certain
r. Scaling here means division by a factor, say, 2, 4,16, or 64. The word, real time is used because
- er stops and cannot be reset. Figure 2.13 shows the actions of a real time clock device.

To timer
--~ Set prescaling factor - +-
i- - - (FRC)
ClK L..- -' Cl K1

RTCI
II RTCI service routine
I
If---~ Update time
number of ticks

Figure 2.13 The actions of a real time clock device.

Real time clock is an important resource in a microcontroller because using this, an as sets the
_ tern clock and schedules the tasks and time-delay functions. It is an on-chip device made from the
er working in non-reset, non-loadable and non-stop mode. The interrupts from this timer are the real
e clock ticks, which also update time information at certain memory addresses.

2.3.14 Serial Asynchronous and Synchronous

Communication Interface
In erial communication, a stream of Is and Osis sent or received at successive time intervals on a single
line, called serial line. Table 2.5 gives the explanation and the example of the serial asynchronous and
synchronous communication interface device in the MCUs. The serial line device is present in most
. tCUs, because the serial port is needed to communicate with many external and remote devices.
Figures 2.14 (a) and (b) show the exemplary formats during the serial communications.
 42 Microcontrollers

TABLE 2.5 I Exemplary contents in the program memory in a system.

Asynchronous serial communication Synchronous serial

communication

In this communication, a byte or frame of bits on the serial Serial synchronous communication
line need not maintain same phase differences between means each byte (or frame of bits)
them. The transmitter does not communicate explicitly or on the serial line needs to maintain
implicitly clock bit to the receiver for synchronisation of same phase differences between
receiver clock in the same phase. An example-mostly in them. The transmitter does
MCUs-the asynchronous communication is in the UART communicate explicitly or implicitly
UART format (Fig. 2.14(a)). Each bit is for a period T, clock bit to the receiver for sync-
which is the reciprocal of a rate called baud rate. (Saud hronisation of the receiver clock
is a German word meaning a drop. The bytes pour on in the same phase. An example-
the line like raindrops). In this format, there is a start mostly in MCUs-the serial bits
bit = 0 after a 1 to 0 transition on the line. After start bit, and the clock bits are sent on two
the eight data bits for the transmitting byte follow, each separate lines. This mode is called
for the interval T. Now, there is 10T UART format. In this synchronous serial communication
format, the next bit is stop bit, which is 1 for a period T. with a separate clock signal.
In addition, there is 11T UART format. In this format, the (Figure 2.14(b)). This mode is also
next bit after data bits and before the stop bit, is a bit for used for interprocessor comm-
error checking or a bit to indicate the meaning of the prece- unication between the systems.
ding 8 bits as an address or data (or instruction or data). Each bit is for the period T, which
It can also be used as parity bit to reflect odd or even is the reciprocal of a rate called
parity in the 8 bits for checking the error due to any of bit rate. The rate is usually express-
the bits being corrupted due to line noise. ed in kbps unit.

Most MCUs have an UART device in two formats, 10T and 11T with programmable baud rate for the
asynchronous serial communication. These also possess a synchronous serial line with accompanying
sycnchronising clock. This facilitates interprocessor transfers.

2.4 RESOURCES IN ADVANCED AND NEXT GENERATION

MICROCONTROLLERS

Advanced MCUs have ALUs with arithmetic logical subunit, auxiliary logic subunit, multiplier subunit,
floating point processing subunit, assembly optimiser, and C compiler. An MCU can have the CAN
module. (CAN means a network with a bus called control area network bus). MCU can have 7-12
PWM Channels for multi-channel analog outputs. There can be communication IIF, 8 or 16 HPI (host
port interface), 6 or more external DMA channels support, two or more standard serial ports, time-
division multiplexed serial ports, multi-channel and bidirectional serial ports. There can be a special
port that has analog input and output with the CODECs. CODEC is used in telecommunication. It is a
unit for digital PCM coding by ADC and other operations and decoding of analog signals by DAC and
other operations at the output and input, respectively.
 Overview of Architecture and Microcontroller Resources

10010001
00-07
Start
,...•••
---------------------,. i 10 T format

~:
i i

:
lJl~1 2 3 4 5
I---+--+--
6 7 8
-----+-----.

9 10
11T Format

2 3 4 5 6 7 8 9 10 11
Parity bit (even)
or
parity bit (odd)
or
data or instruction
or
address
(a) indicating bit

Synchronous
10010001

Data

2 3 4 5 6 7 8

2 3 4 5 6 7 8

Shift clock
-ve transition :
of edge :
2 3 4 5 6 7 8

Receiver checks at the middle or at the edge

(b)

Figure 2.14 (a) UART communication formats for 8 bits = 10010001. (b) Synchronous serial
communication for 10010001.

ext generation MCUs (Chapter 15) have the 32-bit RISC processor core with CISC instruction et
d on-chip compilation unit. These have super scaling multi-stage integer pipeline (s). They have multi-
entry write buffers. This avoids blocking (waiting) of the processor during the external memory writes.
The 0.13 urn foundry processes deliver 350 to 500+ MHz and over 1 GHz on next generation 0.1 urn
 44 Microcontrollers

processes. For example, ARM 11-based families have the instructions sets, which give reduced code
densities. It has the ARM DSP extensions, and SIMD media processing extensions.

SUMMARY

1. The architecture of 8051 families is based on 8048.

2. The port pins are multi-functional in the MCUs and are used as the buses.
3. Microcontrollers have a number of internal devices and many resources.
4. The 8-bit and l6-bit internal buses in various families of MCUs carry data and the instructions
for central processing.
5. The flash and EEPROM memories are electrically programmable and erasable memories that
provide a rich resource in systems like a digital camera.
6. Pulse width modulation is a device to obtain analog outputs from the MCU.
7. MCUs have multichannel ADCs. The digital bits saved in the ADC register maps to the analog
input(s).
8. Reset circuit of the MCU performs the important functions of starting the MCU and interfaced
devices without any glitch.
9. In an MCU the watchdog timer helps in rescuing the system when a program hangs in between
functions.
10. The power-down mode saves power when the system runs continuously.
11. A system has timers for the real-time control.
12. An MCU of8051 family has a powerful bit-manipulation unit using a Boolean processing unit.
13. Serial UART and synchronous communication devices are present in the MCV.
]4. New generation MCUs have a large number of features with fast processing capabilities.

KEY TERMS

8048 family: A microcontroller on which 8051 families of microcontrollers were introduced

later.
ADC: An analog input converted to digital bits, whose decimal value maps the input with
respect to a reference voltage input.
Address bus: A bus to carry the address for the memory and devices externally interfaced to an
MCUor CPU.
Baud rate: Rate by which the bits are sent in an UART.
Bit transfer: A bit paced at one address from another address.
Bus width: Number of lines in the bus. An 8-bit bus carries one byte data in a single cycle.
CAN: Control area network -a bus for the networked embedded systems, it is mostly used in
the automobile and control systems.
Clock circuit: A circuit to generate the clock pulse to synchronise all the operations in the
system.
CODEe: A unit for the coding for the analog input for the line output and decoding of the line
input to retrive the analog input for a voice or music or analog communciation.
Counter: A digital circuit to count the input pulses.
 Overview of Architecture and Microcontroller Resources

DAC: A unit for obtaining analog output using the digital bit at an input or at a register.
Data bus: A bus to carry the data bits or code bits.
Data direction register: A register in which each bit can be programmed to set each bit at a
parallel port as input or output after the programming.
Data memory: A separate memory with adress space separate from the program memory.
EEPROM: Electrically erasable electrically programmable read only memory.
Erase: A process that makes all bits as the 1s.
Free running counter: A counter in non-reset, non-stop and non-loadable state, which
timeouts at regular intervals and interrupts on overflow .
Flash: An EEPROM in which a sector(s) of byte can be era ed simulatenously using the float-
ing gates technology.
Handshaking: A mechanism by which firstly two signals communicate and then a port sends
the latched byte or strobes the byte into it.
Input capture: A mechanism by which a time register captures the instances of the events at an
input pin or at another device and there is interrupt on each capture.
Instruction decoder: A decoding unit attached to the instruction register, which stores the code
just before execution. The unit intiates the 'controller and sequencer' actions to execute the
code.
Integrator: A circuit based on OPAMP and resistor and capacitors to integrate the input up to
a certain time. If its input is PWM output of an MCU, it implements the DAC operation.
Inter-processor communication: A communication (serial sysnchronous) between two
systems.
Internal bus: A bus to carry data byte(s) or code(s) at an instance from one structural unit of
MCU to another.
Internal RAM: A RAM internally available in the MCU for the registers and/or data variables
and stack.
Interrupt mask: A register where a bit can be set or reset to enable or disable a maskable
source of interrupt from the devices or external sources.
Interrupt source: A hardware or software related event, which interrupts the foreground pro-
gram to enable execution of a service routine called interrupt service routine.
Interrupt mechanism: A mechanism by the interrupting sources are serviced in an MCU or
CPU.
10 devices: The devices or ports to latch the bits for further processing by the MCU or to
accept the latched bits.
kbps: Kilo bits per second-a unit to express the rates of bits transfer on a serial line.
Keyboard: A unit which provides interaction to a user when using a computing system.
Laboratory device programmer: A unit to program the on-chip and off-chip CPLDs,
EPROMs, EEPROMS. and flashes.
Masked ROM: A ROM ready to finally install in the system after undergoing a process to
fabricate a mask as per the program and then etch the unetched metal layers in the ROM
memory unit.
LCD display: A liquid crystal based one line or multiline display.
Open drain port: A port with each bit needing external passive or active pull up when interfac-
ing it. It must also be written Is before using the same as an input port.
46 Microcontrollers

Out compare: A mechanism by which a register called out-compare register compare th

contents with a running timer and can generate interrupt(s) or output(s) at each succe ful
comparison.
Parallel port: An addresable multibit unit, which can latch the bits after processing for the
output and which can strobe the bits and latch before processing.
Power-down mode: A mode in which the processor deactivates the clocking unit and sleeps b.
a stop instruction or by auto shutdown program and from which the processor can wake up
again on interrupt. It save power and only standby RAM is delivered power.
Prescaling: A process, for example, in a unit to divide and set the input pulse rates to a timer.
Prescaling factor can be prefixed in the MCU or may be programmable in the MCU.
Priority assignment: A mechanism to program the priority of servicing among the multiple
interrupt sources.
Program counter: A CPU register to hold the address of a current instruction byte(s).
Programmable timer: A timer whose functions can be programmed in an MCU.
Pulse width moduLation (PWM): A unit to give pulse output with width percentage mapped to
the available digital or analog input or to get a desired analog output from the bits in a register
Real time clock: A clock continously ticking and interrupting the system and used for the real
time control in the system.
Reset circuit: A ciruit which brings the CPU and associated units to the start-up state.
ROM image: A finalised program and constants and strings data, which is placed in the ROM
of the system.
Sample-hold ampLifier: An amplifier to sample the input for a fixed period so that the output i
stable for the hold period. Usually, used with the ADC to let the analog input be noise free and
stable during ADC operation of converting into the bits.
SeriaL asynchronous communication: A serial stream of bits in which the bytes or frames do
not maintain the constant phase difference. The UART mode communication is also a ynchro-
nous serial.
Serial synchronous communication: A serial stream of bits in which the bytes or frames do
maintain constant phase difference.
STOP instruction: An instruction which executes when it should enable execution in an MCU
and which on execution brings the processor to a sleep state by deactivating application of the
clock to the CPU units and which permits only standby power dissipation.
Timer: A device to increment (or decrement) when the input clock pulses are applied to it after
suitable scaling. It interrupts on timeout(s), which occur on its overflow(s).
Timer processor unit: A unit to process the timing operation related instructions.
UART: An asynchronous serial communication mode in which the start bit has I to 0 transition
to begin with and which then sends the data bits and then the stop bit. Before the stop bit there
may be an additional bit for special use like parity checking.
Watchdog timer: A timer, which once set, prevents the processor from hanging in a loop or
waiting state and brings the processor to the restart state.
 Overview of Architecture and Microcontroller Resources 47

(~ R_E_V_IE_W_Q_U__ES_T_IO_N_S ~J
What are the resources available at the 8048 and hence explain the difference in functional over-
view of the 8048 and a microprocessor?
_ Define (a) input port. (b) output port.
- What is a bus cycle? If the internal bus width is 8, then explain why the 16-bit operations take two
bus cycles.
- What is the advantage of having the program memory and data memory at a unified address space
in Princeton architecture?
- \ hat is the advantage of having the program memory and data memory at distinct address spaces
in Harvard architecture?
_ List the benefits of EEPROM and flash.
Vhen should an EEPROM be used and when should a flash be used?
_ Parallel port can be used for short distances, while the serial port can be used for long distances
and remote locations. Why?
_ Internal buses are not serial buses. Explain.
_ Vhat is the advantage of the data and address buses multiplexing at an MCU?
'hat is the advantage of the bus-buffer and port latch multiplexing at an MCU?
'hen should on-chip ports and off-chip ports be used?
_fCUs have the memory mapped I/O operations unlike 80x86. What is the advantage?
'hen do we use a parallel port with and without handshaking signals? List the merits.
- De cribe the different uses of the asynchronous and synchronous serial ports.
_fCUs have a PWM unit in place of the on-chip DACs. Why?
- De cribe the PWM width percentage that is mapped with the bits in an MCU register. If the clock
rate is halved, what happens to the width percentage?
De cribe on-chip multi-channel ADC applications and how the analog input maps with the con-
erted bits.
De cribe reset operation in an MCU. Reset circuitry in the MCU needs special design. Why?
Explain the use of a watchdog timer.
Vhen we use a STOP instruction in a program and the MCU provides for its enabling and dis-
bling, we should disable the STOP instruction execution when using a watchdog timer. Why?
- A watchdog timer timeout period in an MCU is fixed as 2048/ls for 12 MHz CPU clock and we
need timeout 2048 timer, 1024/ls. (Hint: Restart the watchdog timer 1024 times before the expiry
of 2048/ls).
MIen should the watchdog timer be disabled? At what instance and in which application should
'e enable the watchdog timer?
'hat are the uses of a power-down mode in an MCU? When does an MCU run in this mode?
'hat are the applications of the timer in an MCU? Why do the MCUs need at least one timer?
Give an example of the resources in the new generation MCUs.
Li t the applications of an MCU resource.
Explain uses of the open-drain output and quasi open-drain output.
E plain how to obtain a real-time clock in a system.
E plain how you will use a data direction register with a parallel port.
De cribe the synchronous serial port and asynchronous serial port.
Explain an UAR~ port and its operations in lOT and lIT modes.
 48 Microcontrollers

(~ P_RA__ C_T_IC_E_E_X_E_R_C_IS_E_S__ ~)
1. Explain the 8048 pins/signals.
2. Advanced MCUs have RISC core, on-chip CISC compiler and caches. What are their applica-
tions? List 10 examples.
3. How many bus cycles for fetch and execution are needed to fetch a 16-bit instruction of 3 byte
long?
4. An MCU has registers, ports, and internal RAM at the unified address space and with the same
set of addressing methods. What is the advantage?
5. An MCU has registers, ports and internal RAM at the non-unified address space (for example.
special function registers and internal RAM between Ox80 and OxFF) and with a different set of
addressing methods (for example, direct and indirect addressing modes for Ox80 - OxFF SFR
and RAM ). What is the advantage?
6. An MCU has a set of 8-bit addresses for each byte and set of 8-bit addresses for the bits in certain
bytes in the RAM and registers, (for example, OxOO-OxFFfor the internal RAM and OxOO-OxFF
for the bits in certain RAM and SFRs). What is the advantage?
7. An MCU has 8-bit addresses for each byte and does not provide for the 8-bit addresses for the bits
in certain bytes in the RAM and registers. What is the advantage?
8. Why can the constants and strings be placed in EEPROM and OTP data-memory space as well as
in masked ROM and program memory space?
9. How do you quantify the parallel port driving capability and portloading capability?
10. A watchdog timer timeout period in an MCU is fixed as 20481ls for 12 MHz CPU clock. If the
CPU clock is operated at 8 MHz, when will be the enabled case watchdog timer timeout?
11. A timer interrupts after 1024 us. Let the pre-scaling factor now set to 16 in place of 1 earlier out
of four possible values (1, 4, 16, and 64). What will be the timeout-overflow intervals now? What
are the four possible intervals for the timeout interrupts?
12. An MCU has a 16-bit PWM pulse accumulator register. How can we get a duty cycle (PWM
width %) be equal to 75%?
13. Give an integrator design when the analog output is 0 at 50% duty cycle, +ve at < 50% and -ve
at> 50%.
14. How does a single timer create the multiple applications and multiple timings in a system?
15. Show the timing diagrams for handshaking signals and input bits at (i) an input port (ii) an output
port (iii) an I/O port.
16. How do we program software codes for a timing operation? (Hint: Use a loop and on enter and
exit from loop, toggle a port bit and set the number of looping cycles such that the desired time
is set.)
17. An MCU has a memory mapped I/O. How will you create eight external ports between OxEFF8
and OEFF.
18. Using multiplexers and demultiplexers, how can there be more ports from two parallel ports given
in an MCU?
19. Let a microcontroller interface four modems. How will we use the TxD and RxD signals of an
asynchronous serial interface in an MCU using two or four parallel port bits?
 Overview of Architecture and Microcontroller Resources 49

( MULTIPLE CHOICE QUESTIONS J

1. An 8048 port P2 signals have
(a) address by lower 8 bit
(b) 8 data by bits
(c) latched port bits
(d) anyone of these address by lower 8 bit or data by 8 bits or latched port bits
2. 8048 accumulator (A-register)
(a) is an input during an ALU operation and accumulates the results from the ALU
(b) is an input during an ALU operation and accumulates along with the flags the results from
theALU
(c) accumulates the results from the ALU
(d) accumulates temporarily the A-register before an ALU operation
3. EA, PSEN RD, WR and SS are the signals in 8048 (also in 8051). In this
(a) EA, PSEN are not at the Port P3 (b) PSEN, RD, and WR are at P3
(c) all four are at P3 (d) SS, RD, and WR are at P3
4. Classic 8051, extended 8051 and 8051MX have which of the following memories?
(a) 64 kB external program ROM. 64 kB external data and 128 B internal RAMs
(b) 64 kB program memory, 16 MB program plus constants memory and 64 MB program plus
constants
(c) 64 kB program memory, 16 MB program plus constants memory and 8 MB program plus
8 MB constants
(d) 64 kB, 1 MB and 8 MB
5. 68HCl1/12/16 has
(a) 4 kB and 64 kB internal/external common memory in unified address space, no separate
program and data memory and 4 port plus ADC port
(b) 64 kB, I MB and 4 MB common memory in unified address space, no separate program and
data memory and 4 ports each
(c) 64 kB, 1 MB and 4 MB memory with separate separate program and data memory and 4,12
and 12 ports
(d) 64 kB/ 4 MB/ 4 MB common memory in unified address space, no separate program and
data memory and 4, 12, and 12 ports
6. 8096 ALU can perform
(a) 1,83 or 6-bit operations (b) 16-bit operations
(c) 8 or 16 or 32 bit operations (d) 8 or 16 - bit operations only
7. An MCU has a port P2 and 64 kB external data memory. Port PO,PI, and P3 ports are not usable
in an expanded mode. The total external memory space now available is
(a) 65536 B (b) 64 000 B
(c) 65472 B (d) 63036 byte
8. A port must have
(a) one handshaking signal to request data input and one for acknowledgement after data input
(b) one handshaking signal to request data input and one for acknowledgement after data input
and one handshaking signal to convey buffer full and one for acknowledgement after data
output successful on two common or four separate pins
(c) one handshaking signal to convey buffer full and one for acknowledgement after data output
successful on two common or four separate pins
(d) data direction register
 50 Microcontrollers

9. An MCU does not have bit-manipulation instructions and only the byte operations are feasible.
To reset the bit 0 and bit 7, the following operations are needed.
(a) AND with 10000001
(b) XOR with 10000001
(c) XOR with 1111 1111
(d) OR with 10000001 when all the bits were Is earlier
10. EEPROM
(a) is flash also
(b) is for erase at a time of one byte and flash for a sector of bytes
(c) is different from flash
'(d) works identically for erase as well as write
11. A pulse width modulator gives an output pulse width of nl % and after integrator circuit gives 2V
when the pulse accumulator loads Ox40 (= 40H).1t gives the width n2% and -2V when the pulse
accumulator loads Ox80 (= 80H). The nl and n2 are
(a) 0 and 50 (b) -2/25 and +2/25
(c) 50 and 100 (d) 25 and 75
12. A single reference input ADC operated on 5V power supply input to its circuit and gives an output
of 0000 1000. When input is 50 mV and 0000 1001 when input is 56.25 mY. It can measure
maximum
(a) 1.6V
(b) 3.2V
(c) 5V
(d) maximum cannot be determined with this much information alone
13. An 8-bit auto reload timer is loaded to an initial value of 40. It is given an input at the start of a
race from a clock of 8 MHz after pre-scaling by a factor of 64. Now, the timer will overflow
(timeout) in
(a) (256 - 40) us (b) every (40/64) us
(c) every (256 - 40)/8 us (d) (40/8) us
14. A byte 10011110 is sent on an asynchronous UART in lOT periods where T determines the baud
rate of 9600. For how much minimum interval from the first start transition will there be 1s when
this byte is sent twice successively with a gap of 100 us,
(a) (12 x 104 +100) us (b) (11 x 104 +100) us
(c) (10 x 104 +100) us (d) (16 x 104 +100) us
15. A watchdog timer is loaded 2048 in 8051. It is reloaded when the program was running after 1000
us. Watchdog timer will reset the MCU in
(a) 4096 us (b) cannot reset when reloaded
(c) 1000 us (d) 3048 us
16. A free running counter is driven by 16 us period inputs. On the start of a race, its content was
captured and 16384 (= 0100 0000 0000 0000). At the stop ofthe race its contents were captured
again and showed 65530 ( = 1111 1111 1111 1010). The race period is given by the formula
(a) 16 x (65530 - 16384)
(b) 16 x [(65530 - 16384) + 65536 x n]
(c) 16 x [(65536 - 16384 + 65530) + 65536 x n]
(d) 16 x n x (65530 - 16384), where n is the number of times it overflows