AD6620

ABSOLUTE MAXIMUM RATINGS* EXPLANATION OF TEST LEVELS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.5 V I. 100% Production Tested.
Input Voltage . . . –0.3 V to VDD + 0.3 V (Not 5 V Tolerant) II. 100% Production Tested at 25°C, and Sampled Tested at
Output Voltage Swing . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Specified Temperatures.
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Junction Temperature Under Bias . . . . . . . . . . . . . . . . 130°C III. Sample Tested Only.
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C IV. Parameter Guaranteed by Design and Analysis.
Lead Temperature (5 sec) . . . . . . . . . . . . . . . . . . . . . . 280°C
V. Parameter is Typical Value Only.
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only; functional operation of the device at these or VI. 100% Production Tested at 25°C, and Sampled Tested at
any other conditions greater than those indicated in the operational sections of this Temperature Extremes.
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Thermal Characteristics
80-Lead Plastic Quad Flatpack:
θJA = 44°C/W
θJC = 11°C/W
ORDERING GUIDE

Package
Model Temperature Range Package Description Option
AD6620AS –40°C to +85°C (Ambient) 80-Lead PQFP (Plastic Quad Flatpack) S-80A
AD6620S/PCB Evaluation Board with AD6620AS and Software

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the AD6620 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

REV. A –11–
AD6620
PIN FUNCTION DESCRIPTIONS

Name Type Description

VDD P 3.3 V Supply
VSS G Ground
CLK I Input Clock
RESET I Active Low Reset Pin
IN[15:0] I Input Data (Mantissa)
EXP[2:0] I Input Data (Exponent)
A/B I Channel (A/B) Select
SYNC_NCO I/O Sync Signal for NCO
SYNC_CIC I/O Sync Signal for CIC Stages
SYNC_RCF I/O Sync Signal for RCF
MODE I Sets Microport Mode: Mode 1, (MODE = 1), Mode 0, (MODE = 0)
A[2:0] I Microprocessor Interface Address
D[7.0] I/O/T Microprocessor Interface Data
DS or RD I Mode 1: Data Strobe Line, Mode 0: Read Signal
R/W or WR I Read/Write Line (Write Signal)
CS I Chip Select, Enables the Chip for µP Access
DTACK or RDY O Acknowledgment of a Completed Transaction (Signals when µP Port Is Ready for an Access)
PAR/SER I Parallel/Serial Control Select (PAR = 1, SER = 0)
DVOUT O Data Valid Pin for the Parallel Output Data
A/BOUT O Signals to Which Channel the Output Belongs to (A = 1, B = 0)
I/QOUT O Signals Whether I or Q Data Is Present (I = 1, Q = 0)
TRST I Test Reset Pin
TCK I Test Clock Input
TMS I Test Mode Select Input
TDI I Test Data Input
TDO I Test Data Output
Pin Types: I = Input, O = Output, P = Power Supply, G = Ground, T = Three-state.

SHARED PINS
Parallel Outputs (PAR/SER = 1 at RESET) Serial Port (PAR/SER = 0 at RESET)
Name Type Description Name Type Description
OUT15 O Parallel Output Data SCLK I/O Serial Clock Input (SBM =0)
Serial Clock Output (SBM = 1)
OUT14 O Parallel Output Data SDI I Serial Data Input
OUT13 O Parallel Output Data SDO O/T Serial Data Output
OUT12 O Parallel Output Data SDFS I/O Serial Data Frame Sync Input (SBM = 0)
Serial Data Frame Sync Output (SBM = 1)
OUT11 O Parallel Output Data SDFE O Serial Data Frame End
OUT10 O Parallel Output Data SBM I Serial Bus Master (Master = 1, Cascade = 0)
OUT9 O Parallel Output Data WL1 I Serial Port Word Length, Bit 1
OUT8 O Parallel Output Data WL0 I Serial Port Word Length, Bit 0
OUT7 O Parallel Output Data AD I Append Data
OUT[6:4] O Parallel Output Data NC NC Unused, Do Not Connect
OUT3 O Parallel Output Data SDIV3 I SCLK Divide Value, Bit 3
OUT2 O Parallel Output Data SDIV2 I SCLK Divide Value, Bit 2
OUT1 O Parallel Output Data SDIV1 I SCLK Divide Value, Bit 1
OUT0 O Parallel Output Data (LSB) SDIV0 I SCLK Divide Value, Bit 0
Pin Types: I = Input, O = Output, P = Power Supply, G = Ground, T = Three-state.

–12– REV. A
 AD6620
PIN CONFIGURATIONS
Parallel Output Data

(MSB) OUT15
OUT14

OUT10
OUT11
OUT12
OUT13

OUT5
OUT6
OUT7
OUT8
OUT9

OUT4

OUT3
OUT2
OUT1
VDD
VDD

VSS

VSS
D7
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

D6 1 60 OUT0 (LSB)
PIN 1
D5 2 IDENTIFIER 59 A/BOUT
D4 3 58 I/QOUT
VSS 4 57 VDD
D3 5 56 DVOUT
D2 6 55 PAR/SER
D1 7 54 RESET
VDD 8 53 TRST
D0 9 AD6620 52 TCK
DS 10 51 TMS
TOP VIEW
DTACK 11 (Not to Scale) 50 TDO
R/W 12 49 TDI
VSS 13 48 VDD
MODE 14 47 SYNC NCO
A2 15 46 SYNC CIC
A1 16 45 SYNC RCF
A0 17 44 VSS
CS 18 43 CLK
EXP0 19 42 A/B
EXP1 20 41 IN0 (LSB)
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
VSS

VDD
IN12
IN13
VSS
IN14
IN15 (MSB)
EXP2

IN4

IN1
IN5

IN2
IN6

IN3
IN7
IN8
IN9
IN10
VDD
IN11

Serial Port
SDIV3
SDIV2
SDIV1
SCLK

SDFE
SDFS

SBM
SDO

VDD
WL0
WL1
VDD

VSS

VSS
SDI

AD

NC
NC

NC
D7

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

D6 1 60 SDIV0
PIN 1
D5 2 IDENTIFIER 59 A/BOUT
D4 3 58 I/QOUT
VSS 4 57 VDD
D3 5 56 DVOUT
D2 6 55 PAR/SER
D1 7 54 RESET
VDD 8 53 TRST
D0 9 AD6620 52 TCK
DS 10 51 TMS
TOP VIEW
DTACK 11 (Not to Scale) 50 TDO
R/W 12 49 TDI
VSS 13 48 VDD
MODE 14 47 SYNC NCO
A2 15 46 SYNC CIC
A1 16 45 SYNC RCF
A0 17 44 VSS
CS 18 43 CLK
EXP0 19 42 A/B
EXP1 20 41 IN0
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
IN13
VSS
IN14
IN15
EXP2

IN4

IN1
IN5

IN2
IN6

IN3
VSS

VDD
IN7
IN8
IN9
IN10
VDD
IN11
IN12

NC = NO CONNECT THE HIGHEST NUMBERED BIT IS THE MSB FOR ALL PORTS

REV. A –13–
AD6620 –Typical Performance Characteristics
400 0

375 –20

350 RCF DECIMATION –40

REJECTION – dB
POWER – mW

325 –60

300 –80
CIC5 DECIMATION

275 –100

CIC2 DECIMATION
250 –120

225 –140
1 2 3 4 5 0 1 2 3
LOG 2 (M) COMPOSITE FREQUENCY RESPONSE – MHz

TPC 1. Typical Power vs. Decimation Rates TPC 4. High Decimation GSM Filter
Input sample rate 65 MSPS, decimation is 240, FIR taps is 240.
0
Unshown spectrum is below that shown. Decimation distribu-
SPUR = –104dB tion is 3, 10, 8, respectively.
–12 PHASE DITHER OFF
–24

–36
0
–48

–60 –20

–72
–40
–84
REJECTION – dB

–96 –60

–108
–80
–120

–132 –100
0 fSAMP

TPC 2. Typical NCO Spur Without Dither –120

–140
0 2 4 6 8
0 COMPOSITE FREQUENCY RESPONSE – MHz
SPUR = –118dB
–12 PHASE DITHER ON
TPC 5. High Decimation AMPS Filter
–24

–36 Input sample rate 58.32 MSPS, decimation is 300, FIR taps is
128. Unshown spectrum is below that shown. Decimation distri-
–48
bution among CIC2, CIC5, and RCF is 10, 30 and 1, respectively.
–60

–72

–84

–96

–108

–120

–132
0 fSAMP

TPC 3. Typical NCO Spur with Dither

–14– REV. A
 AD6620
INPUT DATA PORT Thus for fixed-point ADCs, the exponents are typically static
The input data port accepts a clock (CLK), a 16-bit mantissa and no input scaling is used in the AD6620.
IN[15:0], a 3-bit exponent EXP[2:0], and channel select Pin A/B.
These pins allow direct interfacing to both standard fixed-point
D11 (MSB) IN15
ADCs such as the AD9225 and AD6640, as well as to gain-
ranging ADCs such as the AD6600. These inputs are not 5 V
tolerant and the ADC I/O should be set to 3.3 V.
The input data port accepts data in one of three input modes: AD6640
AD6620
Single Channel Real, Diversity Channel Real, or Single Channel
Complex. The input mode is selected by programming the Input
Mode Control Register located at internal address space 300h.
D0 (LSB) IN4
Single Channel Real mode is used when a single channel ADC IN3
drives the input to the AD6620. Diversity Channel Real mode is IN2
IN1
the two channel mode used primarily for diversity receiver appli- IN0
cations. Single Channel Complex mode accepts complex data in EXP2
EXP1
conjunction with the A/B input which identifies in-phase and EXP0 A/B
quadrature samples (primarily for cascaded 6620s).
+3.3V
The input data port is sampled on the rising edge of CLK at a
maximum rate of 67 MSPS. The 16-bit mantissa, IN[15:0] is Figure 21. Typical Interconnection of the AD6640 Fixed
interpreted as a twos complement integer. For most applications Point ADC and the AD6620
with ADCs having fewer than 16 bits, the active bits should be Scaling with Floating-Point ADCs
MSB justified and the unused LSBs should be tied low. An example of the exponent control feature combines the AD6600
The 3-bit exponent, EXP[2:0] is interpreted as an unsigned and the AD6620. The AD6600 is an 11-bit ADC with three bits
integer. The exponent can be modified by the 3-bit exponent of gain ranging. In effect, the 11-bit ADC provides the mantissa,
offset ExpOff (Control Register 0x305, Bits (7–5)) and an expo- and the three bits of relative signal strength indicator (RSSI) are
nent invert ExpInv (Control Register 0x305, Bit 4). the exponent. Only five of the eight available steps are used by
the AD6600. See the AD6600 data sheet for additional details.
ExpOff sets the offset of the input exponent, EXP[2:0]. ExpInv
determines the direction of this offset. Equations below show For gain-ranging ADCs such as the AD6600,
how the exponent is handled.
scaled _ input = IN × 2– mod(7– Exp+ ExpOff , 8), ExpInv = 1
– mod(Exp+ ExpOff , 8)
scaled _ input = IN × 2 , ExpInv = 0 where: IN is the value of IN[15:0], Exp is the value of EXP[2:0],
– mod(7– Exp+ ExpOff , 8)
and ExpOff is the value of ExpOff.
scaled _ input = IN × 2 , ExpInv = 1
The RSSI output of the AD6600 numerically grows with increas-
where: IN is the value of IN[15:0], Exp is the value of EXP[2:0], ing signal strength of the analog input (RSSI = 5 for a large
and ExpOff is the value of ExpOff. signal, RSSI = 0 for a small signal). With the Exponent Offset
Input Scaling equal to zero and the Exponent Invert Bit equal to zero, the
In general there are two reasons for scaling digital data. The AD6620 would consider the smallest signal at the parallel input
first is to avoid “clipping” or, in the case of the AD6620 regis- (EXP = 0) the largest and, as the signal and EXP word increase,
ter, “wrap-around” in subsequent stages. Wrap-around is not a it shifts the data down internally (EXP = 5, will shift the 11-bit
concern for the input data since the NCO is designed to accept data right by 5 bits internally before going into the CIC2). The
the largest possible input at the AD6620 data port. AD6620 regards the largest signal possible on the AD6600 as
the smallest signal. Thus the Exponent Invert Bit is used to make
The second use of scaling is to preserve maximum dynamic
the AD6620 exponent agree with the AD6600 RSSI. When it
range through the chip. As data flows from one stage to the next
is set high, it forces the AD6620 to shift the data up for growing
it is important to keep the math functions performed in the
EXP instead of down. The exponent invert bit should always be
MSBs. This will keep the desired signal as far above the noise
set high for use with the AD6600.
floor as possible, thus maximizing signal-to-noise ratio.
Scaling with Fixed-Point ADCs Table I. AD6600 Transfer Function with AD6620 ExpInv = 1,
For fixed-point ADCs, the AD6620 exponent inputs EXP[2:0] and No ExpOff
are typically not used and should be tied low. The ADC outputs
ADC Input AD6600 AD6620 Signal
are tied directly to the AD6620 Inputs, MSB-justified. The
Level RSSI[2.0] Data Reduction
exponent offset (ExpOff) and exponent invert (ExpInv) should
both be programmed to 0. Thus the input equation, Largest 101 (5) ⫼ 4 (>> 2) –12 dB
100 (4) ⫼ 8 (>> 3) –18 dB
scaled _ input = IN × 2– mod(Exp+ ExpOff , 8), ExpInv = 0
011 (3) ⫼ 16 (>> 4) –24 dB
where: IN is the value of IN[15:0], Exp is the value of EXP[0:2], 010 (2) ⫼ 32 (>> 5) –30 dB
and ExpOff is the value of ExpOff, simplifies to, 001 (1) ⫼ 64 (>> 6) –36 dB
Smallest 000 (0) ⫼ 128 (>> 7) –42 dB
scaled _ input = IN × 2– mod(0, 8)
(ExpInv = 1, ExpOff = 0)

REV. A –15–