MSP432
Serial Communication
(UART),
https://www.youtube.com/watch?v=WKcn__hxUz4
Serial I/O
Serial communication
Transmit Data (TxD), Receive Data (RxD), and Signal Ground
(SG) implement duplex communication link
Both communicating devices must operate at the same bit
rate
Least significant bit sent first
Simplex
Half duplex
Full duplex
2
MSP432 enhanced Universal Serial Communication
Interface (eUSCI).
The MSP432 microcontroller is equipped with the enhanced Universal Serial
Communication Interface (eUSCI). The system is equipped with a host of different
serial communication subsystems as shown
eUSCI A modules provide support for
• Universal Asynchronous Serial
Receiver and Transmitter (UART)
• Infrared Data Association (IrDA)
• The Serial Peripheral Interface
(SPI). .
Voir doc SLAU356A
3
1
eUSCI : Enhanced Universal Serial Communication Interface
UART OVERVIEW
Block diagram of the
eUCSI_Ax module
configured for UART
mode (UCSYNC bit D0)
[slau208g]. Illustration
used with permission of
Texas Instruments
www.ti.com.
MSP432 UART – Registers
15 14 13 12 11 10 9 8
0x40001000 PEN PAR MSB 7BIT SPB MODEx SYNC UCAxCTLW0
7 6 5 4 3 2 1 0
SSELx RXEIE BRKIE DORM TXADDR TXBRK SWRST UCAxCTLW0
15 – 0
0x40001006 UCBRx UCAxBRW
15 – 8 7–4 3–1 0
0x40001008 BRSx BRFx UCOS16 UCAxMCTLW
7 6 5 4 3 2 1 0
0x4000100A LISTEN FE OE PE BRK RXERR IDLE BUSY UCAxSTATW
15 – 8 7–0
0x4000100C RXBUFx UCAxRXBUF
15 – 8 7–0
0x4000100E TXBUFx UCAxTXBUF
15 – 4 3 2 1 0
0x4000101A TXCPTIE STTIE TXIE RXIE UCAxIE
15 – 4 3 2 1 0
0x4000101C TXCPTIFG STTIFG TXIFG RXIFG UCAxIFG
SEL1 and SEL0 bits on the MSP432
specify alternate functions. P1.2 and
P1.3 are hardwired to the serial
port.
6
2
UART ports.
In the MSP432 launchpad schematic, we can see pin6, pin7, pin98,
and pin99 as the two UART ports. 7
Configuration of Transmitter and Receiver
Configuration of Transmitter and Receiver must match;
otherwise, they can not communicate.
Examples of configuration parameters:
•transmission rate (baud rate, i.e., bits/s)
•LSB or MSB first
•number of bits per packet
•parity bit
•number of stop bits
•interrupt-based communication
•clock source
Example : print a character to a UART terminal
on the host PC:
...
static consteUSCI_UART_ConfiguartConfig=
{
EUSCI_A_UART_CLOCKSOURCE_SMCLK, // SMCLK Clock Source
39, // BRDIV = 39 , integral part
1, // UCxBRF= 1 , fractional part * 16
0, // UCxBRS= 0
EUSCI_A_UART_NO_PARITY, // No Parity
EUSCI_A_UART_LSB_FIRST, // LSB First
EUSCI_A_UART_ONE_STOP_BIT, // One stop bit
EUSCI_A_UART_MODE, // UART mode
EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION}; // Oversampling Mode
GPIO_setAsPeripheralModuleFunctionInputPin(GPIO_PORT_P1,
GPIO_PIN2 | GPIO_PIN3, GPIO_PRIMARY_MODULE_FUNCTION ); //Configure CPU signals
UART_initModule(EUSCI_A0_BASE, &uartConfig); // Configuring UART Module A0
UART_enableModule(EUSCI_A0_BASE); // Enable UART module A0
UART_transmitData(EUSCI_A0_BASE,'a’); // Write character ‘a’ to UART
3
Replacing UART_transmitData(EUSCI_A0_BASE,'a') by a direct access to
registers:
declare pointers to
... UART configuration
volatile uint16_t* uca0ifg = (uint16_t*) 0x4000101C; registers
volatile uint16_t* uca0txbuf = (uint16_t*) 0x4000100E;
...
// Initialization of UART as before
... wait until transmit
buffer is empty
while ( !((*uca0ifg >> 1) & 0x0001) );
*uca0txbuf = (char) 'g write character ‘g’
to the transmit
buffer
shift 1 bit to the right
!((*uca0ifg >> 1) & 0x0001)
expression is ‘1’ if bit UCTXIFG = 0 (buffer not empty).
10
Baud rate for UART
• For a given BRCLK clock source, the baud rate used determines the
required division factor N: N = fBRCLK / baud rate
• The division factor N is often a non integer value, thus, at least one divider
and one modulator stage is used to meet the factor as closely as possible.
If N is equal or greater than 16, it is recommended to use the oversampling
baud-rate generation mode by setting UCOS16
• MSP432 Technical Reference Manual (pdf) page. 915
11
Baud rate for UART
12
4
RS-232 Serial Port
DB25 RS232 DB9 EIA-574 Signal Description True DTE DCE
Pin Name Pin Name
2 BA 3 103 TxD Transmit Data -5.5V out in
3 BB 2 104 RxD Receive Data -5.5V in out
7 AB 5 102 SG Signal Ground
13
Universal Asynchronous Receiver /Transmitter
(UART)
UART (Serial Port) Interface
Send/receive a frame of (5-8) data bits with a single (start) bit prefix and a 1 or
2 (stop) bit suffix
Baud rate is total number of bits per unit time
Baudrate = 1 / bit-time
Bandwidth is data per unit time
Bandwidth = (data-bits / frame-bits) * baudrate
14
ASCII: the American Standard Code for Information Interchange or ASCII is a
standardized, seven bit method of encoding alphanumeric data
15
5
UART - Transmitter
Tx Operation
Data written to UCA0TXBUF
Shift clock is generated from 16x clock
permits differences in Tx and Rx clocks to be reconciled
16
UART - Transmitter
Stop 7 6 5 4 3 2 1 0 Start
Shift 1 Data 0 P1.3/UCA0TXD
clock
Transmit shift register
Write data UCA0TXBUF
UCTXIFG 1 means
Transmit data register TXBUF empty
17
UART - Receiver
Rx Operation
UCRXIFG is 1 when data are available
entries have four control bits
BRK set when Tx signal held low for more than one frame
(break)
OE set when FIFO is full and new frame has arrived
PE set if frame parity error
FE set if stop bit timing error
18
6
UART - Receiver
Stop 7 6 5 4 3 2 1 0 Start
Shift 1 Data 0 P1.2/UCA0RXD
clock Receive shift register
FE OE PE BRK RXERR
UCRXIFG 1 means data
Read data UCA0RXBUF
in RXBUF
Receive data register
InChar UCRXIFG
Empty 1 Not empty
UCRXIFG UCRXIFG
0
1 Not empty Empty
0 Read UCA0RXBUF
Read UCA0RXBUF
RxFifo_Put
return
19
UART Synchronization
Busy-wait operation
InChar OutChar
Empty Busy
0
UCRXIFG 0
UCTXIFG
1 Not empty 1 Idle
Read UCA0RXBUF Write UCA0TXBUF
return return
20
UART Busy-Wait Send/Recv
// Wait for new input,
// then return ASCII code
char UART_InChar(void)
{
while((UCA0IFG&0x01) == 0);
return((char)(UCA0RXBUF));
}
// Wait for buffer to be not full,
// then output
void UART_OutChar(char data){
while((UCA0IFG&0x02) == 0);
UCA0TXBUF = data;
}
21
7
UART Interrupts
22
Input/Output Sync. (cont.)
INPUT
OUTPUT
23
I/O Sync Options (2)
What to do while the peripheral is BUSY?
BUSY-WAIT (e.g., ready-busy, test-transfer)
Poll peripheral status – wait for READY/NOT BUSY
Perform other tasks between polls
Unless timed correctly, under/over run possible
One solution: POLL CONTINUOUSLY
24
8
I/O Sync Options (3)
What to do while the peripheral is BUSY?
INTERRUPT/TRANSFER
Hardware INTERRUPTS processor on condition of READY/NOT BUSY
Facilitates performing other – background - processing between I/O
transfers
Processor changes context when current transfer complete
Requires program structure to process context change
25
UART Setup
// Assumes a 3MHz bus clock, creates 115200 baud rate
void UART_Init(void){
RxFifo_Init(); // initialize FIFOs
TxFifo_Init();
UCA0CTLW0 = 0x0001; // hold in reset mode
UCA0CTLW0 = 0x00C1; // UART,SMCLK, 8bit, no parity,
UCA0BRW = 26; // = 3000000/115200 = 26.0417
UCA0MCTLW = 0x0000; // first and second, UCOS16=0
UCA0IE = 0x0001; // enable interrupts on receive
// disable interrupts on transmit, start, complete
P1SEL0 |= 0x0C;
P1SEL1 &= ~0x0C; // P1.3 and P1.2 as primary module
NVIC_IPR4 = (NVIC_IPR4&0xFFFFFF00)|0x00000040; // 2
NVIC_ISER0 = 0x00010000; // enable int 16 in NVIC
UCA0CTLW0 &= ~0x0001; // enable the USCI module
}
26
AnalogReadSerial
27
9
SERIAL PERIPHERAL INTERFACE-SPI
8-bits transferred in each direction every time
Master generates clock
MOSI: “Master Out Slave In”; MISO: “Master In Slave Out”
Connect MOSI to MOSI and MISO to MISO
Slave Select (SS) used to select one of many slaves
Terminology varies:
Instead of SS, “Chip Select” (CS)
Instead of MOSI and MISO, SIMOD and SOMI
28
How Does SPI Work?
SPI timing diagram when the data is read on a rising clock edge.
29
SERIAL PERIPHERAL INTERFACE-SPI
The master determines Master Slave Setup
which chip it is talking to by Multiple slave cascaded
the CS lines
30
10
SERIAL PERIPHERAL INTERFACE-SPI
1. MOSI: Master Output, Slave Input
2. MISO: Master Input, Slave Output
3. SCK: Clock line to time the transfer of data
4. Slave Select: Chooses which device to communicate to
31
Inter-Integrated Circuit Bus (I2C)
Supports data transfers
10 kbit / s slow mode
100 kbit / s standard mode
400 kbit / s fast mode
1 Mbit /s fast mode plus
3.4Mbit / s high speed mode
provide many devices
microcontrollers with built-in interface
A/D and D/A converters
parallel I/O ports
memory modules
LCD drivers
real-time clock/calendars
32
Inter-Integrated Circuit Bus (I2C)
1 Master (generates clock, initiates communication)
Up to 112 slaves (7 bit IDs, 16 reserved)
33
11
Serial data format
SDA going low while SCL high signals start of data
SDA going high while SCL high signals end of data
SDA can change when SCL low
SCL high (after start and before end) signals that a data bit can be
read
34
Byte transfer
Byte followed by a 1 bit acknowledge from receiver
Open-collector (open drain) wires
sender allows SDA to rise
receiver pulls low to acknowledge after 8 bits
Multi-byte transfers
• first byte contains address of receiver
• all devices check address to determine if following data is for them
• second byte usually contains address of sender
35
MSP432 SPI FEATURES
As previously mentioned, the MSP432 SPI system has many features that allow the
system to be interfaced to a wide variety of SPI configured devices. ese features
include [SLAU356A]:
7-bit or 8-bit data length;
LSB-first or MSB-first data transmit and receive capability
master or slave modes;
independent transmit and receive shift registers which provide continuous transmit
and receive operation;
selectable clock polarity and phase control;
programmable clock frequency in master mode
independent interrupt capability for receive and transmit.
36
12
MSP432 SPI
the MSP432 provides support for SPI communication in both of the eUSCI_A and eUSCI_B
modules.
A block diagram of an UCSI
module configured for SPI
operation is shown
SPI operation is selected by
setting the UCSYNC
(Synchronous mode enable)
bit to logic one in the
module’s eUSCI_Ax or
USCI_Bx Control Register 0
(UCAxCTL0 or UCBx-CTL0).
SPI hardware overview [SLAU356A, 2015].
Illustration used with permission of Texas
Instruments www.ti.com.
37
13
