5821

Data Sheet
26185.12F
BiMOS II 8-BIT SERIAL-INPUT,
LATCHED DRIVERS
A merged combination of bipolar and MOS technology gives
these devices an interface flexibility beyond the reach of standard
CLOCK 1 CLK 16 OUT 1 logic buffers and power driver arrays. The UCN5821A and
UCN5821LW each have an eight-bit CMOS shift register and
SERIAL 15 OUT 2
DATA IN
2 CMOS control circuitry, eight CMOS data latches, and eight
LOGIC 14 OUT 3 bipolar current-sinking Darlington output drivers.
SHIFT REGISTER

3
GROUND
LATCHES

LOGIC
SUPPLY
4 VDD 13 OUT 4 BiMOS II devices have much higher data-input rates than the
SERIAL
original BiMOS circuits. With a 5 V logic supply, they will
5 12 OUT 5
DATA OUT typically operate at better than 5 MHz. With a 12 V supply,
STROBE 6 ST 11 OUT 6 significantly higher speeds are obtained. The CMOS inputs are
OUTPUT 10 OUT 7
compatible with standard CMOS and NMOS logic levels. TTL
7 OE
ENABLE circuits may require the use of appropriate pull-up resistors. By
POWER
GROUND
8
SUB
9 OUT 8 using the serial data output, the drivers can be cascaded for
interface applications requiring additional drive lines.
Dwg. PP-026A

Note the DIP package and the SOIC package are The UCN5821A are furnished in a standard 16-pin plastic
electrically identical and share common terminal DIP; the UCN5821LW are in a 16-lead wide-body SOIC for sur-
number assignments.
face-mount applications. The UCN5821A is also available for
operation from -40°C to +85°C. To order, change the prefix from
‘UCN’ to ‘UCQ’.
ABSOLUTE MAXIMUM RATINGS
at 25°C Free-Air Temperature
FEATURES
Output Voltage, VOUT ..................... 50 V
Logic Supply Voltage, VDD ............. 15 V ■ To 3.3 MHz Data Input Rate
Input Voltage Range, ■ CMOS, NMOS, TTL Compatible
VIN .................. -0.3 V to VDD + 0.3 V ■ Internal Pull-Down Resistors
Continuous Output Current, ■ Low-Power CMOS Logic & Latches
IOUT ..................................... 500 mA
Package Power Dissipation, PD
■ High-Voltage Current-Sink Outputs
Package Code ‘A’ .................. 2.1 W ■ Automotive Capable
Package Code ‘LW’ ............... 1.5 W
Operating Temperature Range,
TA ............................ -20°C to +85°C
Storage Temperature Range,
TS .......................... -55°C to +150°C
Caution: CMOS devices have input static protection
but are susceptible to damage when exposed to
extremely high static electrical charges.
Always order by complete part number, e.g., UCN5821A .

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5821
8-BIT SERIAL-INPUT,
LATCHED DRIVERS

TYPICAL INPUT CIRCUITS FUNCTIONAL BLOCK DIAGRAM

V
DD
VDD 4 LOGIC
CLOCK 1 SUPPLY

SERIAL SERIAL
2 SERIAL-PARALLEL SHIFT REGISTER 5
DATA IN DATA OUT

LOGIC LATCHES 6 STROBE

3
GROUND

IN 7
OUTPUT ENABLE
(ACTIVE LOW)
MOS
STROBE &
BIPOLAR
OUTPUT
ENABLE POWER
8
GROUND
16 15 14 13 12 11 10 9 SUB
OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 Dwg. FP-013A

NOTE — There is an indeterminate resistance between logic ground and power

ground. For proper operation, these terminals must be externally connected
together.
Dwg. EP-010-3

VDD

CLOCK &
SERIAL
Number of Outputs ON UCN5821A Max. Allowable Duty Cycle
DATA IN
(IOUT = 200 mA at Ambient Temperature of
IN
VDD = 12 V) 25°C 40°C 50°C 60°C 70°C

8 90% 79% 72% 65% 57%

7 100% 90% 82% 74% 65%
6 100% 100% 96% 86% 76%
5 100% 100% 100% 100% 91%
4 100% 100% 100% 100% 100%
3 100% 100% 100% 100% 100%
2 100% 100% 100% 100% 100%
Dwg. EP-010-4A
1 100% 100% 100% 100% 100%

TYPICAL OUTPUT DRIVER Number of Outputs ON UCN5821LW Max. Allowable Duty Cycle
(IOUT = 200 mA at Ambient Temperature of
OUT VDD = 12 V) 25°C 40°C 50°C 60°C 70°C

8 67% 59% 54% 49% 43%

7 77% 68% 62% 56% 49%
7.2K 3K
6 90% 79% 72% 65% 57%
5 100% 95% 86% 78% 68%
SUB 4 100% 100% 100% 98% 86%
3 100% 100% 100% 100% 100%
Dwg. No. A-14,314 2 100% 100% 100% 100% 100%
1 100% 100% 100% 100% 100%

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1985, 2004 Allegro MicroSystems, Inc.
 5821
8-BIT SERIAL-INPUT,
LATCHED DRIVERS

ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V (unless otherwise specified).

Limits
Characteristic Symbol Test Conditions Min. Max. Units
Output Leakage ICEX VOUT = 50 V — 50 µA
Current VOUT = 50 V, TA = +70°C — 100 µA

Collector-Emitter VCE(SAT) IOUT = 100 mA — 1.1 V

Saturation Voltage IOUT = 200 mA — 1.3 V

IOUT = 350 mA, VDD = 7.0 V — 1.6 V

Input Voltage VIN(0) — 0.8 V

VIN(1) VDD = 12 V 10.5 — V

VDD = 5.0 V 3.5 — V

Input Resistance rIN VDD = 12 V 50 — kΩ

VDD = 5.0 V 50 — kΩ

Supply Current IDD(ON) One Driver ON, VDD = 12 V — 4.5 mA

One Driver ON, VDD = 10 V — 3.9 mA

One Driver ON, VDD = 5.0 V — 2.4 mA

IDD(OFF) VDD = 5.0 V, All Drivers OFF, All Inputs = 0 V — 1.6 mA

VDD = 12 V, All Drivers OFF, All Inputs = 0 V — 2.9 mA

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 5821
8-BIT SERIAL-INPUT,
LATCHED DRIVERS

Serial Data present at the input is

CLOCK
A D transferred to the shift register on the
B logic “0” to logic “1” transition of the
DATA IN CLOCK input pulse. On succeeding
E F
CLOCK pulses, the registers shift data
C
STROBE
information towards the SERIAL DATA
OUTPUT. The SERIAL DATA must
appear at the input prior to the rising edge
OUTPUT
ENABLE
of the CLOCK input waveform.
G
OUT N Information present at any register is
transferred to its respective latch when the
STROBE is high (serial-to-parallel con-
Dwg. No. A-12,627
version). The latches will continue to
accept new data as long as the STROBE
TIMING CONDITIONS
(VDD = 5.0 V, TA = +25°C, Logic Levels are VDD and Ground) is held high. Applications where the
latches are bypassed (STROBE tied high)
will require that the ENABLE input be
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) ....................................................................... 75 ns high during serial data entry.
B. Minimum Data Active Time After Clock Pulse
When the ENABLE input is high, all
(Data Hold Time) ........................................................................... 75 ns
of the output buffers are disabled (OFF)
C. Minimum Data Pulse Width .............................................................. 150 ns
D. Minimum Clock Pulse Width ............................................................ 150 ns
without affecting the information stored
E. Minimum Time Between Clock Activation and Strobe ....................... 30 ns
in the latches or shift register. With the
F. Minimum Strobe Pulse Width ........................................................... 100 ns
ENABLE input low, the outputs are
G. Typical Time Between Strobe Activation and
controlled by the state of the latches.
Output Transition .......................................................................... 1.0 µs

TRUTH TABLE
Serial Shift Register Contents Serial Latch Contents Output Contents
Data Clock Data Strobe Output
Input Input I1 I2 I3 .............. I8 Output Input I1 I2 I3 .............. I8 Enable I1 I2 I3 .............. I8

H H R1 R2 .............. R7 R7
L L R1 R2 .............. R7 R7
X R1 R2 R3 .............. R8 R8
X X X .............. X X L R1 R2 R3 .............. R8
P1 P2 P3 .............. P8 P8 H P1 P2 P3 .............. P8 L P1 P2 P3 .............. P8
X X X .............. X H H H H .............. H

L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000
 5821
8-BIT SERIAL-INPUT,
LATCHED DRIVERS

UCN5821A
Dimensions in Inches
(controlling dimensions)
0.014
0.008
16 9

0.430
MAX
0.280
0.300
0.240 BSC

1 8
0.070 0.100 0.005
0.045 0.775 BSC MIN
0.735

0.210
MAX

0.015 0.150
MIN 0.115

0.022
Dwg. MA-001-16A in
0.014

Dimensions in Millimeters
(for reference only)
0.355
0.204
16 9

10.92
MAX
7.11
7.62
6.10 BSC

1 8
1.77 2.54 0.13
1.15 19.68 BSC MIN
18.67

5.33
MAX

0.39 3.81
MIN 2.93

0.558
Dwg. MA-001-16A mm
0.356

NOTES: 1. Lead thickness is measured at seating plane or below.

2. Lead spacing tolerance is non-cumulative.
3. Exact body and lead configuration at vendor’s option within limits shown.

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 5821
8-BIT SERIAL-INPUT,
LATCHED DRIVERS

UCN5821LW
Dimensions in Inches
(for reference only)
16 9
0.0125
0.0091

0.2992 0.419
0.2914 0.394

0.050
0.016

0.020 1 2 3 0.050
0.013 0.4133 BSC 0° TO 8°
0.3977

0.0926
0.1043

Dwg. MA-008-16A in
0.0040 MIN.
Dimensions in Millimeters
(controlling dimensions)
16 9
0.32
0.23

7.60 10.65
7.40 10.00

1.27
0.40

0.51 1 2 3 1.27
0.33 10.50 BSC 0° TO 8°
10.10

2.65
2.35

Dwg. MA-008-16A mm
0.10 MIN.
NOTES: 1. Lead spacing tolerance is non-cumulative.
2. Exact body and lead configuration at vendor’s option within limits shown.

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000
 5821
8-BIT SERIAL-INPUT,
LATCHED DRIVERS

The products described here are manufactured under one or more

U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi-
bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.

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