Intro

to Sequential Logic

CS 64: Computer Organization and Design Logic

Lecture #14
Winter 2019

Ziad Matni, Ph.D.
Dept. of Computer Science, UCSB
 Administrative
•  Lab #7
–  On Thursday
–  It’s a little on the tough side, so partner up if you
want to
–  Due next week on Wednesday
–  Paper copy

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 Lecture Outline

•  General ALU Design

•  Sequential Logic

•  S-R Latch

•  D-Latch

•  Reviewing what’s needed for Lab 7

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 Arithmetic-Logic Unit (ALU)
•  Recall: the ALU does all the computations
necessary in a CPU

•  The previous circuit was a simplified ALU:

–  When S = 00, R = A + B
–  When S = 01, R = A – B
–  When S = 10, R = A AND B
–  When S = 11, R = A OR B

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 Co
Simplified ALU
A
1bit R
B
ALU
•  We can string 1-bit ALUs together to S

make bigger-bit ALUs (e.g. 32b ALU)

Ci

A0 B0 S A1 B1 S A2 B2 S A3 B3 S A31 B31 S



…
ALU

ALU

ALU

ALU

ALU
1bit

1bit

1bit

1bit

1bit
Co Ci

R0 R1 R2 R3 R31

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 Abstract Schematic of the MIPS CPU
Relevant to a future lab…

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 Combinatorial vs. Sequential Logic
•  The CPU schematic shows
both combinatorial and sequential logic blocks

•  Combinatorial Logic
–  Combining multiple logic blocks
–  The output is a function only of the present inputs
–  There is no memory of past “states”

•  Sequential Logic
–  Combining multiple logic blocks
–  The output is a function of both the present inputs and past inputs
–  There exists a memory of past “states”
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 The S-R Latch
•  Only involves 2 NORs

•  The outputs are fed-back to

the inputs

•  The result is that the output

state (either a 1 or a 0) is
maintained even if the input
changes!

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 How a S-R Latch Works
•  Note that if one NOR input is 0, the output
becomes the inverse of the other input

•  So, if output Q already exists and if

S = 0, R = 0, then Q will remain at whatever
it was before! (hold output state)

S R Q0 Comment •  If S = 0, R = 1, then Q becomes 0

0 0 Q* Hold output (reset output)
0 1 0 Reset output
1 0 1 Set output •  If S = 1, R = 0, then Q becomes 1
1 1 X Undetermined
(set output)

•  Making S = 1, R = 1 is not allowed

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 Consequences?
•  As long as S = 0 and R = 0, S R Q0 Comment
0 0 Q* Hold output
the circuit output holds memory
0 1 0 Reset output
of its prior value (state)
1 0 1 Set output
1 1 X Undetermined
•  To change the output, just make
S = 1 (but also R = 0) to make the output 1 (set) OR
S = 0 (but also R = 1) to make the output 0 (reset)

•  Just avoid S = 1, R = 1…

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 S R Q0 Comment
0 0 Q* Hold output

About that S = 1, R = 1 Case… 0 1

1 0
0
1
Reset output
Set output
1 1 X Undetermined

•  What if we avoided it on purpose by making

R = NOT (S)?
–  Where’s the problem?
S/R’

•  This, by itself, precludes a case when R = S = 0

–  You’d need that if you want to
preserve the previous output state!

•  Solution: the clocked latch and the flip-flop

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 Adding an “Enable” Input:
The Gated S-R Latch
•  Create a way to “gate” the inputs
–  R/S inputs go through only if an
“enable input” (E) is 1
–  If E is 0, then the S-R latch gets SR = 00
and it hold the state of previous outputs

•  So, the truth table would change from a “normal” S-R Latch:
S R Q0 Comment
S R E Q0 Comment
0 0 Q* Hold output
X X 0 Q* Hold output
0 1 0 Reset output
0 1 1 0 Reset output
1 0 1 Set output
1 0 1 1 Set output
1 1 X Undetermined
We got rid of the “undetermined” state!!! JJJ
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 Combining R and S inputs into One:
The Gated D Latch
•  Force S and R inputs D S
to always be opposite Q

of each other
E
–  Make them the same as

an input D, R Q
where D = S and !D = R.

•  Create a way to “gate” the D input

–  D input goes through D E Q0 Comment
only if an enable input (E) is 1 X 0 Q* Hold output
–  If E is 0, then hold the state of the 0 1 0 Reset output
previous outputs
1 1 1 Set output
We got rid of an extra input!!! JJJ
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 The Gated D Latch
•  The gated D-Latch is very commonly used in electronic circuits
in computer hardware, especially as a register because it’s a
circuit that holds memory!

D Q


E Q

Whatever data you present to the input D,

the D-Latch will hold that value (as long as input E is 0)
You can present this value to output Q as soon as input E is 1.
There is no synchronicity to this circuit (meaning what???)
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 Lab 7

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 What’s Lab 7 About?
•  Task 1: Design a “simple” ALU
•  Task 2: Design a “simple” Register Block using D-Latches
•  Task 3: You are given a specification for a “simple” CPU that uses:
–  1 “Simple” Register Block
–  1 “Simple” ALU
–  1 Abstract Computer Memory Interface
–  As many ANDs, ORs, NOTs, XORs, Muxes that you need
•  Design this CPU! (Task 3)

•  You will draw all of these (BE NEAT!)

–  Turn it in (physical copy) at the CS64 BOX in HFH on 2nd floor

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 Abstract Schematic
of the MIPS CPU

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 I/O Name I/O Description

Register Object for R0

The first register to read, as a single bit.
If 0, then reg0 should be read. If 1,
then reg1 should be read.

Lab 7 (Task 2) R1
The second register to read, as a single bit.
If 0, then reg0 should be read. If 1,
then reg1 should be read.
“Write Register”. Specifies which register
to write to. If 0, then reg0 should be
WR
written to. If 1, then reg1 should be
written to.
The data that should be written to the
W register specified by WR. This is a single
bit.
“Write Enable”. If 1, then we will write to
a register. If 0, then we will not write to a
WE register. Note that if WE = 0, then the
inputs to WR and W are effectively
ignored.
Value of the first register read. As
described previously, this depends on
O1
which register was selected to be read,
This will be made from D-FFs or D-Latches via R0.
and Combinatorial Logic
Value of the second register read. As
described previously, this depends on
O2
which register was selected to be read,
via R1.
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 Memory Interface I/O Name I/O Description

Object for Lab 7 A0 Bit 0 of the address (LSB)

A1 Bit 1 of the address (MSB)

“Output Enable”. If 1, then the value at

the address specified by A0 and A1 will be
read, and sent to the output line O. If 0,
OE then the memory will not be accessed,
and the value sent to the output line is
unspecified (could be either 0 or 1, in an
unpredictable fashion).

W The value to write to memory.

“Write Enable”. If 1, then the value sent

into W will be written to memory at the
WE address specified by A0 and A1. If 0, then
no memory write occurs (the value sent to
W will be ignored).
The value read from memory (or
O
unspecified if OE = 0).

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 Task 3: Build a Mock-CPU!
Actually, just a small instruction decoder and executor…

OP1 OP0 B0 B1 B2 Human-readable Encoding Description

Compute the XOR of the contents of reg0 with the
0 0 0 0 0 xor reg0, reg0, reg0 contents of reg0, storing the result in reg0.
Compute the NOR of the contents of reg0 with the
0 1 1 0 1 nor reg1, reg0, reg1 contents of reg1, storing the result in reg1.
Copy the bit stored at address 01 (decimal 1) into
1 0 1 0 1 load reg1, 01 register reg1.
1 1 0 1 0 store reg0, 10 Store the contents of reg0 at address 10 (decimal 2)
1 1 1 1 1 store reg1, 11 Store the contents of reg1 at address 11 (decimal 3)

These say something about which registers are used

These say something about which operation is being done

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 Hints for Task 3
•  Design the final circuit in pieces:
–  One piece for each of the 3 types of instruction: load, store, XOR/NOR

•  For example, the store task:

–  If an output isn’t used, tie it to a permanent “0” (i.e. ground)
–  If an input isn’t used, then you can use “X” (don’t care) on it
What registers How do I best
am I using? connect the
Which instruction registers to the Is the output even
bits go where? memory interface? used in this “store”
Again, ask yourself task?
What controls if some of the
should I use? inputs here should
What values be op-code bits.
should they be?

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 Tying In All The Pieces (Task 3)
•  Now see how they can all fit together
–  You will have 1 register block + 1 memory interface
–  You won’t need to use any additional latches here
–  You will need to use muxes and regular logic
(and the simple ALU you designed earlier – see lab
instructions for more details)

•  REQUIREMENT:
Use ONLY 1 register block, 1 ALU,
and 1 memory interface
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 YOUR TO-DOs
•  Lab 7
– Start on Thursday
– Due back on Wednesday
– Paper copy – not electronic
– Drop off in the CS64 BOX in HFH 2nd Floor

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