Addis Ababa University

Addis Ababa Institute of Technology

School of Electrical and Computer Engineering

Computer Organization and Architecture

ASSIGNMENT
SECTION B

NAME ID

NATNAEL GETACHEW ATR/0382/10

SUBMISSION DATE 15/04/2020

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Assignment IV
12.1 Show in hex notation:

a. The packed decimal format for 23

Solution:-

A packed decimal representation stores two digits in one byte where each digit
is stored in four bits, therefore in byte there are two 4bits where packed
decimal can store two hexadecimal digits

23dec = (00100011)bin

Converting the binary (00100011)bin into hexadecimal is 23

b. The ASCII characters 23

Solution:-

ASCII character 23 is represented by

ASCII 2 in decimal is 48+2=50 and ASCII 3 in decimal is 48+3=51 , so 23 ASCII 23

is 50 51 in decimal. For converting the decimal to hexadecimal we divide 50
and 51 by 16

50/16=3 remainder 2 so 50dec=32hex and 51/16=3 remainder 3 so 51dec=33hex

Finally ASCII character 23 in hexadecimal is 32 33

12.2 For each of the following packed decimal numbers, show the decimal
value:

C. 0100 1010 0110

Solution:-There is an error because 1010 is not a valid packed decimal

number.

12.3 A given microprocessor has words of 1 byte. What is the smallest and
largest integer that can be represented in the following representations:

a. Unsigned

Solution:- 0—255

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b. Sign-magnitude

Solution:- (-127)—(127)

c. Ones complement

Solution:- (-127)—(127)

d. Twos complement

Solution:- (-128)—(127)

e. Unsigned packed decimal

Solution:- 0—99

f. Signed packed decimal

Solution:- (-9)—(+9)

12.5 The tens complement of the decimal number X is defined to be 10N-X,

where Nis the number of decimal digits in the number. Describe the use of
ten’s complement representation to perform decimal subtraction. Illustrate
the procedure by subtracting (0326)10 from (0736)10.

Solution:- The tens complement of a number is formed by subtracting

each digit from 9, and adding 1 to the result,

First the tens complement 104-0326=9674 and add the result to 0736

And finally add 1 =>0410

12.6 Compare zero-, one-, two-, and three-address machines by writing

programs to compute

X=(A+B*C)>(D-E*F)

for each of the four machines. The instructions available for use are as follows:

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0 Address 1 Address 2 Address 3 Address
PUSH M LOAD M MOVE(XY) MOVE(XY)
POP M STORE M ADD(XX+Y) ADD(XY+Z)
ADD ADD M SUB(XX-Y) SUB(XY-Z)
SUB SUB M MUL(XX*Y) MUL(XY*Z)
MUL MUL M DIV(XX/Y) DIV(XY/Z)
DIV DIV M

Solution:-

0 Address 1 Address 2 Address 3 Address

PUSH A LOAD E MOVE R1, E MUL R1, E, F

PUSH B MUL F MUL R1, F SUB R1, D, R1
PUSH C STORE T MOVE R2, D MUL R2, B, C
MUL LOAD D SUB R2, R1 ADD R2, A, R2
ADD SUB T MOVE R1, B DIV X, R1, R2
PUSH D STORE T MUL R1, C
PUSH E LOAD C ADD R1, A
PUSH F MUL B DIV R1, R2
MUL ADD A MOVE X, R1
SUB DIV T
DIV STORE X
POP X

12.7 Consider a hypothetical computer with an instruction set of only two n-bit
instructions. The first bit specifies the opcode, and the remaining bits specify
n-1
one of the 2 n-bit words of main memory. The two instructions are as
follows:

SUBS X Subtract the contents of location X from the accumulator, and store the
result in location X and the accumulator.

JUMP X Place address X in the program counter.

A word in main memory may contain either an instruction or a binary number

in twos complement notation. Demonstrate that this instruction repertoire is
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reasonably complete by specifying how the following operations can be
programmed:

a. Data transfer: Location X to accumulator, accumulator to location X

b. Addition: Add contents of location X to accumulator

c. Conditional branch

d. Logical OR

e. I/O Operations

Solution:-

a. A memory location whose initial contents are zero is needed for both
X → AC and AC → X. The program for X → AC, and its effects are
shown below. Assume AC initially contains the value a.

Instruction AC Effect on M(0) M(X)

SUBS 0 a a x
SUBS 0 0 0 x
SUBS X –x 0 –x
SUBS 0 –x –x –x
SUBS 0 0 0 –x
SUBS X x 0 x

b. For addition, we again need a location, M(0), whose initial value is 0.

We also need destination location, M(1). Assume the initial value in M(1)
is y.

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Instruction AC M(0) M(1) M(X)

SUBS 0 a a y x
SUBS 1 a– y a a–y x
SUBS 1 0 a 0 x
SUBS X –x a 0 –x
SUBS 0 –x – a –x – a 0 –x
SUBS 1 –x – a –x – a –x – a –x
SUBS 0 0 0 –x – a –x
SUBS X x 0 –x – a x
SUBS 0 x x –x – a x
SUBS 0 0 0 –x – a x
SUBS 1 a+x 0 a+x x

12.8 Many instruction sets contain the instruction NOOP, meaning no

operation, which has no effect on the processor state other than incrementing
the program counter. Suggest some uses of this instruction.

Solution:-

No operation(NOOP) instruction does not have any effect on the code that is
no instruction execution is performed rather than incrementing the program
counter and is commonly used for :-

Memory alignment ,to prevent hazards , to occupy branch delay slots and is
frequently used for debugging and updating the program

A NOOP can be useful for debugging. When it is desired to interrupt a program

at a particular point, the NOOP is replaced with a jump to a debug routine.
When temporarily patching or altering a program, instructions may be
replaced with NOOPs.
For timing purpose, equal to the instruction cycle time for the NOOP. This can
be used for measuring time or introducing time delays. 3. NOOPs can be used
to pad out portions of a program to align instructions on word boundaries or

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subroutines on page boundaries.
NOOPs are useful in RISC pipelining

12.9 In Section 12.4, it was stated that both an arithmetic left shift and a
logical left shift correspond to a multiplication by 2 when there is no overflow,
and if overflow occurs, arithmetic and logical left shift operations produce
different results, but the arithmetic left shift retains the sign of the number.
Demonstrate that these statements are true for 5-bit twos complement
integers.

Solution:-

Bit Value Arithmetic Value Logical left Value

left Shift shift
00000 0 00000 0 00000 0
00001 1 00010 2 00010 2
00010 2 00100 4 00100 4
00011 3 00110 6 00110 6
00100 4 01000 8 01000 8
00101 5 00101 10 01010 10
00110 6 01100 12 01100 12
00111 7 01110 14 01110 14
01000 8 00000 Overflow 10000 Overflow
01001 9 00010 Overflow 10010 Overflow
01010 10 00100 Overflow 10100 Overflow
01011 11 00110 Overflow 10110 Overflow
01100 12 01000 Overflow 11000 Overflow
01101 13 01010 Overflow 11010 Overflow
01110 14 01100 Overflow 11100 Overflow
01111 15 01110 Overflow 11110 Overflow
10000 -16 10000 Overflow 00000 Overflow
10001 -15 00010 Overflow 00010 Overflow
10010 -14 10100 Overflow 00100 Overflow
10011 -13 10011 Overflow 00110 Overflow
10100 -12 11000 Overflow 10100 Overflow
10101 -11 11010 Overflow 01010 Overflow
10110 -10 11100 Overflow 01100 Overflow
10111 -9 11110 Overflow 01110 Overflow
11000 -8 10000 -16 10000 -16

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11001 -7 10010 -14 10010 -14
11010 -6 10100 -12 10100 -12
11011 -5 10110 -10 10110 -10
11100 -4 11000 -8 10100 -8
11101 -3 11010 -6 11010 -6
11110 -2 11100 -4 11100 -4
11111 -1 11110 -2 11111 -2

12.16 Suppose that two registers contain the following hexadecimal values:
AB0890C2, 4598EE50. What is the result of adding them using MMX
instructions:

a. for packed byte

Solution:- one byte at a time

AB 08 90 C2
+45 98 EE 50
=FO A0 7E 12

b. for packed word

Solution:- 16 bits at a time

AB08 90 C2
+4598 EE 50
=FOA0 7E 12

Assume saturation arithmetic is not used.

12.18 Convert the following formulas from reverse Polish to infix:

a. AB+C+D×

Solution:- (A + B + C) * D

b. AB/CD/+

Solution:- (A/B) + (C/D)

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c. ABCDE+××/

Solution:- A/(B * C * (D + E))

d. ABCDE+F/+G-H/×+

Solution:- A + (B * ((C + (D – E)/F) – G)/H)

12.26 Write a small program to determine the endianness of machine and

report the results. Run the program on a computer available to you and turn in
the output.

Solution:-

#include <iostream>

using namespace std;

#include <stdio.h>

main()

{ int integer; char *p;

integer = 0x30313233; /* ASCII for chars '0', '1', '2', '3' */

p = (char *)&integer;

if (*p=='0' && *(p+1)=='1' && *(p+2)=='2' && *(p+3)=='3')

printf("This is a big endian machine.\n");

else if (*p=='3' && *(p+1)=='2' && *(p+2)=='1' && *(p+3)=='0')

printf("This is a little endian machine.\n");

else printf("Error in logic to determine machine endian-ness.\n");}

13.1 Given the following memory values and a one-address machine with an
accumulator, what values do the following instructions load into the
accumulator?

• Word 20 contains 40.

• Word 30 contains 50.
• Word 40 contains 60.

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• Word 50 contains 70.
a. LOAD IMMEDIATE 20
Solution:- An immediate addressing model specifies an operand in the
instruction itself and it contains an immediate value 20 therefore the
instruction loads an immediate value 20 to the accumulator. Thus this results
an accumulator with the data 20
b. LOAD DIRECT 20
Solution:- The direct addressing mode specifies the address of an operand and
it represents that the operand is stored in address 20 the data given by that
address word is 40
c. LOAD INDIRECT 20
Solution:- This instruction specifies that address in the memory word 20
contains 40 which acts as an address for the data 60
d. LOAD IMMEDIATE 30
Solution:- This instruction loads an immediate value 30 in the accumulator and
the instruction itself contains an immediate value 30
e. LOAD DIRECT 30
Solution:- This instruction loads the value present in the address 30 which is 50
f. LOAD INDIRECT 30
Solution:- This instruction specifies that address in the memory word 30
contains 50 which acts as an address for the data 70

13.2 Let the address stored in the program counter be designated by the symbol
X1. The instruction stored in X1 has an address part (operand reference) X2.
The operand needed to execute the instruction is stored in the memory word
with address X3. An index register contains the value X4. What is the
relationship between these various quantities if the addressing mode of the
instruction is (a) direct; (b) indirect; (c) PC relative; (d) indexed?
Solution:- a.X3 = X2
b.X3 = (X2)
c.X3 = X1 + X2 + 1
d.X3 = X2 + X4

13.3 An address field in an instruction contains decimal value 14. Where is the
corresponding operand located for
a. immediate addressing?
Solution:- the address filed
b. direct addressing?
Solution:- memory location 14
c. indirect addressing?
Solution:- the memory location whose address in memory location 14

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d. register addressing?
Solution:- register 14
e. register indirect addressing?
Solution:- the memory location whose address is in register 14

13.4 Consider a 16-bit processor in which the following appears in main

memory, starting at location 200:

200 Load to AC Mode

201 500

202 Next instruction

The first part of the first word indicates that this instruction loads a value into an
accumulator. The Mode field specifies an addressing mode and, if appropriate,
indicates a source register; assume that when used, the source register is R1,
which has a value of 400. There is also a base register that contains the value
100. The value of 500 in location 201 may be part of the address calculation.
Assume that location 399 contains the value 999, location 400 contains the
value 1000, and so on. Determine the effective address and the operand to be
loaded for the following address modes:
a. Direct d. PC relative g. Register indirect
b. Immediate e. Displacement h. Autoindexing with increment, using R1
c. Indirect f. Register

Solution:-
a. EA 500,operand 1100 d. EA 702,operand 1302 g. EA 400,operand 1000
b. EA 201,operand 500 e. EA 600,operand 1200 h. EA 400,operand 1000
c. EA 1100,operand 1700 f. EA R1,operand 400

The autoindexing with increment is the same as the register indirect mode
except that R1 is incremented to 401 after the execution of the instruction

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13.5 A PC-relative mode branch instruction is 3 bytes long. The address of the
instruction, in decimal, is 256028. Determine the branch target address if the
signed displacement in the instruction is -31.
Solution:-
Relative addressing uses the contents of the program counter, which points to the next
instruction after the current instruction. In this case, the current instruction is at decimal
address 256028 and is 3 bytes long, so the PC contains 256031. With the displacement of –
31, the effective address is 256000

13.6 A PC-relative mode branch instruction is stored in memory at address

62010. The branch is made to location 53010. The address field in the
instruction is 10 bits long. What is the binary value in the instruction?
Solution:-
Effective address= (PC + 1) + Relative Address
Relative Address = –621 + 530 = –91
Converting to twos-complement representation, we have: 1110100101

13.7 How many times does the processor need to refer to memory when it
fetches and executes an indirect-address-mode instruction if the instruction is
(a) a computation requiring a single operand; (b) a branch?

Solution:-
a. it makes reference 3times :-one to fetch instruction, one to fetch operand reference, one
to fetch operand.
b. it makes reference 2 times:- one to fetch instruction, fetch operand reference and load
into PC

13.11 Consider a processor that includes a base with indexing addressing

mode. Suppose an instruction is encountered that employs this addressing
mode and specifies a displacement of 1970, in decimal. Currently the base and
index register contain the decimal numbers 48,022 and 8, respectively. What is
the address of the operand?

Solution:- adding the three values: 1970 + 48022 + 8 = 5000

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13.12 Define: EA=(X)+ is the effective address equal to the contents of location
X, with X incremented by one word length after the effective address is
calculated; EA=-(X) is the effective address equal to the contents of location X,
with X decremented by one word length before the effective address is
calculated; EA=(X)- is the effective address equal to the contents of location X,
with X decremented by one word length after the effective address is
calculated. Consider the following instructions, each in the format (Operation
Source Operand, Destination Operand), with the result of the operation placed
in the destination operand.

a. OP X, (X)

Solution:- No, because the source operand is the contents of X, rather than the top
of the stack, which is in the location pointed to by X.

b. OP (X), (X)+

Solution:- No, because address of the top of the stack is not changed until after the
fetching of the destination operand.

c. OP (X)+, (X)

Solution:- Yes. The stack grows away from memory location 0.

d. OP-(X), (X)

Solution:- No, because the second element of the stack is fetched twice.

e. OP-(X), (X)+

Solution:- No, because the second element of the stack is fetched twice.

f. OP (X)+, (X)+

Solution:- No, because the stack pointer is incremented twice, so that the result is
thrown away.

g. OP (X)-, (X)

Solution:- Yes. The stack grows toward memory location 0.

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Using X as the stack pointer, which of these instructions can pop the top two
elements from the stack, perform the designated operation (e.g., ADD source
to destination and store in destination), and push the result back on the stack?
For each such instruction, does the stack grow toward memory location 0 or in
the opposite direction?

13.13 Assume a stack-oriented processor that includes the stack operations

PUSH and POP. Arithmetic operations automatically involve the top one or two
stack elements. Begin with an empty stack. What stack elements remain after
the following instructions are executed?

PUSH 4 , PUSH 7, PUSH 8 , ADD ,PUSH 10 , SUB , MUL

Solution:-
Instruction Stack(top on left)
PUSH 4 4
PUSH 7 7, 4
PUSH 8 8, 7, 4
ADD 15, 4
PUSH 10 10, 15, 4
SUB 5, 4
MUL 20

13.17 Design a variable-length opcode to allow all of the following to be

encoded in a 36-bit instruction:

• Instructions with two 15-bit addresses and one 3-bit register number

• Instructions with one 15-bit address and one 3-bit register number

• Instructions with no addresses or registers

Solution:-
First Divide the 36-bit instruction into variable sized 4 fields and represent as A, B,
C, D. Field A is the first 3 bits; field B is the next 15 bits; field C is the next 15 bits,
and field D is the last 3 bits.
The 7 instructions with three operands use B, C, and D for operands and A for
opcode. Let 000 through 110 be opcodes and 111 be a code indicating that there are
less than three operands. The 500 instructions with two operands are specified with
111 in field A and an opcode in field B, with operands in D and C. The opcodes for
the 50 instructions with no operands can also be accommodated in B.

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