Depletion mode MOSFET,
MOSFET Scaling and Small Geometry
Effects
Depletion Mode NMOS
Depletion Mode NMOS
• “Depletion mode MOSFET'', acts as a ``normally closed''
switch.
• A thin layer (Channel) of semiconductor material just below
the gate oxide is permanently doped with the same type
material as the source and drain regions.
• Channel allows conduction even when no charge is applied
to the gate.
Depletion Mode NMOS
• A negative charge applied to gate, repelled the the negative
charge carriers in the channel, leaves no free charge
carriers, and conduction will cease.
• The least negative value of gate voltage, responsible for
depleted channel is called threshold voltage of depletion
transistor.
• Vgs=0 and Vds=+value allow the drain current to flow. As
Vgs moves towards more and more negative values
(towards Vt) drain current decreases.
• Fixed Vgs and with increasing Vds, drain currents
increases and reaches at saturation. Same Ids expression
can be used but with –ve Vt.
• What will happen if we apply positive voltage on gate?
Depletion Mode NMOS
Depletion Mode NMOS
Importance of Scaling
• To integrate more number of transistors on the same area
(to improve the performance) one has to decrease the size
of transistors.
• Reduction of transistor size is known as scalimg.
• With reduce size the operational characteristics of
transistor also change.
• There are also some limitations which do not allow futher
scaling of transistor.
MOSFET Scaling
SCALING -> refers to ordered reduction in
dimensions of the MOSFET and other VLSI
features. It allows the same decision to be made
using less power and area and thus drives the
electronic revolution.
Reduce Size of VLSI chips.
TWO TYPES OF SCALING
• Constant field or full scaling.
Tries to maintain the same electric filed distribution in the scaled
device.
Not always possible (The transistors still have to be able to interface
with the outside world.)
• Constant voltage scaling.
VDD, VT are unchanged.
Power dissipation and density go up.
To describe scaling, a scaling factor S>1 is
introduced.
•Constant field or full scaling.
The electric field E is kept constant, to achieve this all
potentials must be scaled down proportionally. This will
affect the VT. Thus to keep field constant one has to increase
charge density by a factor S.
•Constant field or full scaling.
The significant reduction in power dissipation is very
important feature of full scaling
Constant Voltage Scaling :
•Power supply and terminal voltages are kept constant, while all the
process dimensions are scaled by (1/S).
•Doping densities are increased by a factor of S2 to keep charge-field
relationship preserve.
Short Channel Effects
When MOSFET is called Short Channel Device?
• If channel length is of the order of magnitude as Depletion layer
thickness of D and S.
• If Leff is of the order of junction depth.
Short –channel effects are related to two phenomenon :
• The limitation imposed on electron drift characteristics in the
channel. Modification in Vt due to short channel length.
• Lateral electric filed increases as length decreases. The electron drift
velocity vd saturates at high channel electric fields.
Short-channel Effects
1. Mobility degradation due to lateral field
Electron velocity saturation due to high electric field and small channel
length
Short-channel Effects
2. Mobility degradation due to Vertical field
Carrier velocity is also function of Ex. Vertical electric field influences the
scattering of carriers at surface. Due to collision surface mobility
reduces.
• Symbol η is also used in place of θ.
• Next step is to calculate the threshold voltage change due to short
channel effect.
Effect on Threshold Voltage due to Short-channel
• Long channel case:
• Depletion regions of the source and drain are small compared to the
channel length.
• The regions are rectangular and shape of gate induced bulk
depletion region exists from source to drain.
• Short-channel case :
• Depletion regions of the source and drain are large compared to the
channel length.
• The regions are trapezoidal in shape and channel length would be
effectively reduced.
• Drain and source diffusions induce a significant amount of charge in
bulk. As a result long channel Vt overestimates the depletion charge
supported by gate.
• thus threshold voltage is smaller in short-channel case as compared
to long one.
Effect on Threshold Voltage due to Short-channel
Narrow-channel Effects
• When MOS transistor has width W of the order of maximum depletion
region thickness Xdm than it is called narrow device.
• The regions around the channel are covered by FOX. Gate terminal
overlaps with FOX.
• Shallow depletion region under the FOX overlap area.
• Gate voltage supports this additional depletion charge.
• Thus threshold voltage > large channel device.
• k is an empirical parameter and depends upon shape of depletion
region. For quarter circular arcs it value is equal to k=Л / 2.
Subthreshold Effects
• In small geometry device the drain current is controlled by 2-D electric
field vector. One typical condition which is due to 2D current flow is
called subthreshold conduction.
• if Vgs < Vto, the electrons in channel face a potential barrier that
blocks the flow.
• Increasing gate voltage reduces the barrier and current flow under
the effect of electric field.
• This problem is more complicated when geometry is small because
potential barrier is controlled by both Vgs and Vds.
• Vgs < Vto and Vds is increased then potential barrier in the channel
decreases. This is known as drain induced potential barrier lowering
(DIBL).
• The reduction in barrier causes a current to flow between S and D.
• This current is called subthreshold current and GCA can not model
this .
Other small geometry effects are :
• Punch through.
• Oxide Breakdown.
• Hot Carrier effects.
Punch through :
• In small geometry when drain bias is large the depletion
regions of source and drain can merge.
• Gate voltage loses its control upon drain current.
• Current rises sharply.
• Can result in permanent damage by localizing melting of
material.
Oxide Breakdown :
• Gate oxide thickness is also reduced by a factor of
S in scaling.
• Difficult to grow uniform very thin layer of oxide.
• Non-uniform thin gate oxide results in pinholes.
• They may cause shorts between gate and bulk.
• Other possibility is oxide breakdown. If field is
large it may break the layer during operation and
lead to device failure.
Hot Carrier effects:
• Hot electron effects are due to High electric field within the device.
• In scaling, device dimensions and supply voltages are not scaled down
in proportional way.
• This results in increased both electric fields.
• After gaining high KE in high field carriers becomes hot and they may be
injected into the gate oxide. This results in permanent change in oxide-
interface charge distribution.
• This effect is more prominent when Vds is large. The electrons arriving at
Si-SiO2 interface with high KE are able to surmount the surface potential
barrier and injected into the oxide.
• The damage caused by hot carriers affects the transistor characteristics
and reduces the performance.
