International Journal of Science and Research (IJSR)

ISSN (Online): 2319-7064

Index Copernicus Value (2013): 6.14 | Impact Factor (2013): 4.438

Complementary Metal-Oxide Semiconductor: A

Review
Komal Rohilla1, Ritu Pahwa2, Shaifali Ruhil3
1, 3
Vaish College of Engineering and Technology, M.D.U, Rohtak, Haryana, India
2
AP, Vaish College of Engineering and Technology, M.D.U, Rohtak, Haryana, India

Abstract: In this paper we have focused on the complementary metal-oxide semiconductor technology. This paper covers overview of
power consumption sources and discusses the techniques for reduction of power dissipation in high performance designs. Power dissi-
pation is very serious matter in CMOS technology. The first section contains introduction, second section contains review of CMOS,
third section contains overview of power consumption sources and leakage current mechanisms, fourth section contains techniques to
reduce power dissipation, and the last section presents the conclusion and references.

Keywords: CMOS structure, Power consumption, Leakage currents, VTCMOS, MTCMOS

1. Introduction dustry today. Simultaneously, we also need to speed up the

critical paths of the circuit, while reducing its power con-
The persistent development of electronics, information tech- sumption [1].
nology (IT), and communications has been mainly enabled
by nonstop development in silicon-based complementary 2. CMOS Technology Review
metal-oxide-semiconductor (CMOS) technology. This non-
stop development has been maintained frequently by its di- The concept of cmos was introduced in 1963 by FRANK
mensional scaling, that results in exponential development in WANLASS AND CHIN-TANG SHAN OF FAIRCHILD.
both gadget compactness and production. The decrease in In CMOS (complementary metal oxide semiconductor)
cost-per-function has gradually been increasing the financial technology both kinds of transistors are used.
efficiency with all new technology generation. Today CMOS
ICs are random and indispensable in our life, ranging from
moveable electronics to telecommunications and transporta-
tion. [3] Now a days VLSI, a key challenge and critical mat-
ter in electronics industry is control and management of pow-
er consumption. Power consumption is the main problem in
VLSI design.[2]. Too much power dissipation in IC’s discou-
raging their use in convenient systems. Much power causes
overheating, and decreases the performance and reduces chip
natural life.[1] CMOS technology, the supply voltage and
threshold voltage had been scaled down to attain quicker
performance devices [4]. But leakage current have Increased Figure 1: CMOS structure
significantly and have become a major component of the total
power consumption [5].In CMOS design the sources of pow- CMOS is made up of two transistor NMOS and PMOS tran-
er consumption mainly due to dynamic power dissipation and sistor. P-channel MOSFET and N-channel MOSFET in a
leakage power dissipation. complementary way on the same substrate. The CMOS tran-
sistors (devices) are formed by the intersection of the polysi-
Leakage power dissipation is the power dissipated by the licon and diffusion; N+ diffusion for the N device & P+ dif-
circuit when the circuit is in sleep mode. Leakage power is fusion for the P device (illustrated in fig1). The output
given by this equation.[6] ("out") is connected together in metal (illustrated in fig1).
Pleak= Ileak * Vdd Connections between metal and polysilicon or diffusion are
made through contacts and these contacts called source, drain
So, Ileak is the leakage current that is flows in a transistor and gate point. complete CMOS structure are shown below.
when the transistor is in off state, Vdd is the supply voltage.

Dynamic power dissipation is the power dissipated by the

circuit, when the circuit is switching and it is done due to the
charging and discharging of capacitor.
Pdynmic=αfCVdd2
So, α is the switching activity. f is the operating frequency, C
is the load capacitance, Vdd is the Supply voltage.Low power
design critical technology needed in the Semiconductor in-
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 International Journal of Science and Research (IJSR)
ISSN (Online): 2319-7064
Index Copernicus Value (2013): 6.14 | Impact Factor (2013): 4.438

Figure 2: CMOS N-well structure

Besides, CMOS technology is used in the fabrication of con-

ventional microchip. .since it is less expensive than BiCMOS Figure 4: Transient Characteristics of CMOS Inverter [11]
and SOI technologies and offers high performance, high den-
sity and low-power dissipation .CMOS reduce complexity of Transient response of CMOS inverter is showing in Fig-4 i.e.
circuit. because in this CMOS two transistor are fabricated input and output waveform w.r.t time in ns.[11]
on a single chip. CMOS used in logic circuit design. Switch-
ing speed is faster as compare to other logic families. CMOS 3. Overview of Power Consumption Sources
structure is ratio less .because output of CMOS is not de-
pends upon the transistor size.[7] The average power consumption in conventional CMOS digi-
tal circuits can be expressed as the sum of three main compo-
2.1. CMOS - based logic circuit nents (i) dynamic (switching) power consumption (ii) short-
circuit power consumption(iii) Leakage power consumption.
As the time passed, the advancements in CMOS were also
done. Later on it was used for logic gates like inverter, AND Dynamic power consumption: This represents the power
gate, NAND gate, NOR gate etc. It is also used in the design- dissipated during a switching. This power depends upon the
ing of SRAM cells. A new logic called ternary logic is also charging and discharging of capacitor.
developed. Ternary logic design functions are used in
CMOS. The main advantage of it is that it reduces the num-
ber of computational steps required.[8] To evaluate the per-
formance of a CMOS, various simulation models have been
proposed. The CMOS tanner tool model is widely used in
circuit design and simulation.

Using this Eda tanner tool 14.1 version 32 bit , we can draw
the circuit design in s-edit of tanner tool of CMOS as a inver-
ter using 32nm,45nm,90nm CMOS technology and Model
parameters are extracted from BSIM4.6.1 user manual [10].
These windows are given below.

Figure 5: CMOS logic gate for dynamic power calculation

This transition can be represented by PMOS and NMOS

networks. The average power dissipation of the CMOS logic
gate, driven by a periodic input voltage waveform with ideal-
ly zero rise-time and fall-times, can be calculated from the
energy required to charge up the output node 0 to Vdd and
charge down the total output load capacitance to ground lev-
el.
Pavg=1/TCloadV2dd
Figure 3: Schematic diagram of CMOS Inverter [11]
Pavg=Cload V2dd Fclk
This fig.3 shows the snapshot of CMOS inverter which is
taken from EDA Tanner simulation tool. So, F is the operating frequency, C is the load capacitance,
Vdd is the supply voltage. Note that the average switching
power dissipation of a CMOS gate is essentially independent
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Paper ID: SUB153132 1044
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 International Journal of Science and Research (IJSR)
ISSN (Online): 2319-7064
Index Copernicus Value (2013): 6.14 | Impact Factor (2013): 4.438
of all transistor characteristics and transistor sizes as long as
a full voltage swing is achieved. [12] Reverse junction leakage current (IREV): IREV is the re-
verse-bias PN junction leakage. A reverse bias PN junction
Short circuit power consumption: CMOS inverter (or a leakage IREV has two main components: one is minority carri-
logic gate) is driven with input voltage waveforms with finite er diffusion/drift near the edge of the depletion region; the
rise and fall times, both the NMOS and the PMOS transistors other is due to electron-hole pair generation in the depletion
in the circuit may conduct simultaneously for a short amount region of the reverse-biased junction.[1]
of time during switching, forming a ground, as shown in fig.5 IREV LEAKAG=IS *(e(Vdd/Vth)-1)

Here IS is the reverse saturation current, Vdd is the voltage

Bias, and Vth=kt/q is the thermal voltage. For engineering

purposes, we can assume that the reverse leakage current is
equal to the leakage current is equal to the reverse saturation
current. The reverse saturation current is given by:
IS=q ni2A (Dp/NdWn+Dn/NaWp)
Where q is electron charge the intrinsic concentration, A is
area of PN junction diode (actually drain area), Dp and Dn are
Figure 6: NMOS and PMOS transistor conduct (simulta- the electron and hole diffusion coefficient, Nd and Na are the
neously) a short circuit current during switching [12] donor and acceptor concentration, Wp and Wn are the width
of P and N side of PN junction diode.[1]
The current component which passes through both the
NMOS and the PMOS devices during switching does not Gate leakage tunneling current (IG) : IG is the oxide tunne-
contribute to the charging of the capacitances in the circuit, ling current; Reduction of gate oxide thickness due to this an
and hence, it is called the short-circuit current component. increase in the field across the oxide. The high electric field
For a simple analysis consider a symmetric CMOS inverter coupled with low oxide thickness in tunneling of electrons
with Kn=Kp=K and VT,n=|VT,p|=VT, and with a very small from substrate to gate and also from gate to substrate through
capacitive load. If the inverter voltage waveform with equal the gate oxide, that is the gate oxide tunneling current.
rise and fall times (Trise=Tfall=T), time-averaged short circuit
current drawn from the power supply is Gate induced drain leakage (IGIDL): The gate induced drain
Iavg (short-circuit) =1/12 K*T* Fclk/Vdd(Vdd -2VT)3 leakage is caused by high field effect in the drain junction of
Hence, the short-circuit power dissipation becomes, MOS transistors. For an NMOS transistor with grounded gate
and drain potential at Vdd, significant band bending in the
Pavg (short-circuit) =1/12 K*T* Fclk (Vdd -2VT)3 drain allows electron-hole pair generation through avalanche
The short-circuit power dissipation is linearly proportional to multiplication and band-to-band tunneling. A deep depletion
the input signal rise and fall times, and also to the Tran con- condition is created since the holes are rapidly swept out to
ductance of the transistors. Hence, reducing the input transi- the substrate. At the same time, electrons are M collected by
tion times will decrease short-circuit current component. the drain, resulting in GIDL current. Transistor scaling has
led to increasingly steep halo implants, where the substrate
Leakage power consumption: power leakage consumption doping at the junction interfaces is increased, while the chan-
is due to the leakage current. This power is done at that time nel doping is low. This is done mainly to control punch-
when the transistor is in sleep mode. through and drain-induced barrier lowering while having a
Pleak= Ileak * Vdd low impact on the carrier mobility in the channel. The result-
So, Ileak is the leakage current that is flows in a transistor ing steep doping profile at the drain edge increases band to
when the transistor is in off state, Vdd is the supply voltage. band tunneling currents there, particularly as Vdb is increased.
Thinner oxide and higher supply voltage increase GIDL cur-
3.1. Mechanism of Leakage Currents rent.[9]

There are four main sources of leakage current in MOS tran- Sub threshold leakage current (ISUB): The sub threshold
sistor as shown in Fig.6 which may leads leakage power dis- current, this is due to carrier diffusion between the source
sipati and the drain regions of the transistor in weak inversion. The
on. behavior of an MOS transistor in the sub threshold operating
region is similar to a bipolar device, and the sub threshold
current exhibits an exponential dependence on the gate vol-
tage. The amount of the sub threshold current may become
significant when the gate-to-source voltage is smaller than,
but very close to, the threshold voltage of the device. In this
case, the power dissipation due to sub threshold leakage can
become comparable in magnitude to the switching power
dissipation of the circuit. In current CMOS technologies, the
Figure 7: Leakage current in CMOS transistor [2] sub threshold leakage current, ISUB, is much larger than the
other leakage current components. This is mainly because of
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Paper ID: SUB153132 1045
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 International Journal of Science and Research (IJSR)
ISSN (Online): 2319-7064
Index Copernicus Value (2013): 6.14 | Impact Factor (2013): 4.438
the relatively low VT in modern CMOS devices. The source
then injects carriers into the channel surface, causing an in-
crease in IOFF.

Let IOFF denote the leakage of an OFF transistor (VGS=0V for

an NMOS device.), we know that from equation 2. The IOFF
can be expressed:
IOFF=IREV+IGIDL+ISUB
C IREV and IGIDL are maximized when VDB = VDD. Similar-
ly, for short-channel devices, ISUB increases with VDB be-
cause of the DIBL effect. Note the IG is not a component of
the OFF current, since the transistor gate must be at a high
potential with respect to the source and substrate for this cur-
rent to flow. Figure 9: A Variable-threshold CMOS Inverter [12]
This circuit is done in two modes
1. Active mode
4. Leakage reduction techniques of CMOS 2. Standby mode
IN active mode the substrate bias voltage of the NMOS tran-
Here we discuss two leakage reduction techniques. These are
sistor is VON= 0 and the substrate bias voltage of the PMOS
given below.
transistor is VBP=VDD. Thus, the inverter transistors do not
1. VTCMOS (Variable-threshold CMOS)
experience any back gate-bias effect. The circuit operates
2. MTCMOS (Multiple-threshold CMOS)We have seen that
with low VDD and low Vt benefiting from both low power
using a low supply voltage(Vdd) and a low threshold voltage
dissipation (due to low VDD ) and high switching speed (due
(Vt) in CMOS logic circuits is an efficient method for reduc-
to low Vt )
ing the overall power dissipation, While maintaining high
speed performance. Yet designing a CMOS logic gate entire-
In the standby mode, the substrate bias control circuit gene-
ly with low Vt transistors will inevitably lead to increased sub
rates a lower substrate bias voltage for the NMOS transistor
threshold leakage, and consequently, to higher stand-by pow-
and a higher substrate bias voltage for the PMOS transistor.
er dissipation when the output is not switching. One possible
As a result, the magnitudes of the threshold voltages VTn and
way to overcome this problem is to adjust the threshold vol-
VTp both increase in the stand-by mode, due to the back gate
tages of the transistors in order to avoid leakage in the stand-
bias effect. Since the sub threshold leakage current drops
by mode, by changing the substrate bias.
exponentially with increasing threshold voltage, the leakage
power dissipation in the stand-by mode can be significantly
reduced with this technique.

The VTCMOS technique can also be used to automatically

control the threshold voltages of the transistors in order to
reduce leakage currents, and to compensate for process-
related fluctuations of the threshold voltages. This approach
is also called the Self-Adjusting Threshold-Voltage Scheme
(SATS).[12]

2) Multi-threshold CMOS circuit (MTCMOS)

This is the another technique which can be applied for reduc-

ing leakage currents in low voltage circuits in the stand-by
Figure 8: Power dependant on threshold voltage[1] mode is based on using two different types of transistors
(both NMOS and PMOS) with two different threshold vol-
1)Voltage threshold CMOS circuits (VTCMOS): In tages in the circuit. Here, low-VT transistors are typically
VTCMOS circuit technique, the transistors are designed in- used to design the logic gates where switching speed is essen-
herently with a low threshold voltage, and the substrate bias tial, whereas high- VT transistors are used to effectively iso-
voltages of NMOS and PMOS transistors are generated by a late the logic gates in stand-by and to prevent leakage dissi-
variable substrate bias control circuit, as shown in Fig.8 pation. The circuit structure of the MTCMOS logic gate
shown below.

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Paper ID: SUB153132 1046
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 International Journal of Science and Research (IJSR)
ISSN (Online): 2319-7064
Index Copernicus Value (2013): 6.14 | Impact Factor (2013): 4.438
hai, China 2008 May 15-16, IEEE Press) p. 1. [DOI:
10.1109/IWJT.2008.4540004].
[4] Ratul kr. Baruah “ Design of a low power low voltage
CMOS op amp”, International Journal of VLSI design
and Communication system, Vol. 1, No. 1 March 2010.
[5] K. Roy, S. Mukhopadhyay and H. Mahmoodi-Meimand
“Leakage Current Mechanisms and Leakage Reduction
techniques in Deep-Sub micrometer CMOS Circuits”
Proceedings of the IEEE, Vol. 91,No.2, February, 2003.
[6] Borivoje Nikolic, (2008) “Design in the Power–Limited
Scaling Regime”, IEEE transactions on Electron Devic-
Figure 90: A Multiple-threshold CMOS (MTCMOS) logic es, Vol. 55, No. 1, pp.71-83.
gate [7] Fabian KHATEB,”A Survey of Non-conventional Tech-
This circuit is also have two modes niques for Low-voltage Low-power Analog Circuit De-
1. Active mode sign,” RADIO ENGINEERING, VOL. 22, NO. 2, JUNE
2. Stand by mode 2013.
[8] M. Yoeli, G. Rosenfeld, “Logical Design of ternary
In active mode the high-Vt Transistors are turned on and the switching circuits ”, IEEE Trans. Comput., vol. C-14,
logic gates consisting of low-Vt transistors can operate with pp. 19-29, Feb. 1965.
low switching power dissipation and small propagation delay. [9] Farzan Fallah ,Massoud Pedram , “Standby and active
In standby mode the high-Vt Transistors are turned off and leakage currentcontrol and minimization CMOS VLSI
the conduction paths for any sub threshold leakage currents circuits,” IEICE Trans.Electron., vol.E88-C, no. 4, pp.
that may originate from the internal low-Vt circuitry are ef- 509–519, 2005.
fectively cut off. [10] ASU, Berkeley Predictive Technology Model (BPTM)
Dept. of EE, Arizona State Univ., Tempe, AZ, 2006
5. Conclusion [Online].
[11] Jagannath Samanta,”Comparative study for delay &
This paper gives just a review of CMOS Technology. Overall power dissipation of CMOS Inverter in UDSM range,”
conclusion after analyzing the previous research paper is that International Journal of Soft Computing and Engineering
CMOS having the low power consumption. Due this low (IJSCE) ISSN: 2231-2307, Volume-1, Issue-6, January
power consumption CMOS technology is used in high per- 2012.
formance analysis of digital circuits. The leakage power is of [12] S-M. Kang and Y. Lelebici, CMOS Digital Integrated
great anxiety for designs in nanometer technologies and is Circuits, Mc Graw Hill, third edition, 2003.
becoming a major supplier to the total power consumption;
leakage power has become more dominant as compared to
Dynamic power. The gate leakage has become dominant
sources of leakage and is expected to increase with the tech-
nology scaling. The solutions for leakage power dissipation
or reduction of leakage power dissipation have to be required
both at the process technology and circuit levels. Here we
thoroughly reviewed the techniques for controlling the Lea-
kage current of CMOS circuits in both standby and active
modes of circuit operation and increase the speed of CMOS
circuits.

References
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[2] Raju Hebbale1, Pallavi Hiremath,”Leakage power re-
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[3] H. Iwai, Extended Abstracts 2008 8th International
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