Control Design

Chapter 5. JPH.
Processor with DP and CU
Data Control
Signals Instructions
Datapath
Unit

Multiplexers MUX1

Register File
RF

CONTROL
UNIT
Multiplexers MUX2

F1 F2
 A := A + B
Control
Signals Instructions
Datapath
Unit
p q r s MUX1
Select p-t
t
A+B
RF
Write A
A Read A
B Read B

CU
u v MUX2
Select u-w
w x y z Select v-x
A B

F1 F2
A+B Add
Overflow
Finite State Machine

Wikipedia
GCD Procedure
 GCD Procedure

Conditions Actions
XR := 20; YR := 12; 20 12
XR > 0: XR > YR: XR := XR – YR = 8; 8 12
XR > 0: XR ≤ YR: YR := 8; XR := 12; XR := XR – YR = 4; 12 8
4 8
XR > 0: XR ≤ YR: YR := 4; XR := 8; XR := XR – YR = 4; 8 4
4 4
XR > 0: XR ≤ YR: YR := 4; XR := 4; XR := XR – YR = 0; 0 4
XR ≤ 0: Z := 4;
 GCD Hardware
Reset
Z X Y

Control
Unit

Subtract
Multiplexers MUX Swap
Select XY

Load XR

Register XR Register YR Load YR

Subtractor Comparators
(XR ≥ YR)
Datapath Unit (XR > 0)
 GCD Hardware
Reset Begin
Z X Y

Control
Unit

Subtract
Multiplexers MUX Swap
Select XY

Load XR

Register XR Register YR Load YR

Subtractor Comparators
(XR ≥ YR)
Datapath Unit (XR > 0)
 GCD Hardware
Reset Begin
Z X Y

Control
Unit Select XY

Subtract
Multiplexers MUX Swap
Select XY

Load XR

Register XR Register YR Load YR

Subtractor Comparators
(XR ≥ YR)
Datapath Unit (XR > 0)
 GCD Hardware
Reset Begin
Z X Y

Control
Unit Select XY

Subtract
Multiplexers MUX Swap
Select XY

Load XR

Register XR Register YR Load YR

Subtractor Comparators
(XR ≥ YR)
Datapath Unit (XR > 0)
 GCD Hardware
Reset Begin
Z X Y

Control
Unit Select XY

Load XR
Subtract
Load YR
Multiplexers MUX Swap
Select XY

Load XR

Register XR Register YR Load YR

Subtractor Comparators
(XR ≥ YR)
Datapath Unit (XR > 0)
 GCD Control Unit
Inputs
Outputs

State Subtract Swap Select XY Load XR Load YR

S0 (Begin) 0 0 1 1 1
 GCD Hardware
Reset Begin
Z X Y

Control Next States?

Unit

Subtract
Multiplexers MUX Swap
Select XY

Load XR

Register XR Register YR Load YR

Subtractor Comparators
(XR ≥ YR)
Datapath Unit (XR > 0)
 GCD Hardware
Reset Begin
Z X Y

Control
Unit

Subtract
Multiplexers MUX Swap
Select XY

Load XR

Register XR Register YR Load YR

Subtractor Comparators
(XR ≥ YR)
Datapath Unit (XR > 0)
 GCD Hardware
Reset Begin
Z X Y

Control CU Inputs
Unit
XR > 0

Subtract XR >= YR
Multiplexers MUX Swap
Select XY

Load XR

Register XR Register YR Load YR

Subtractor Comparators
(XR ≥ YR)
Datapath Unit (XR > 0)
 GCD Hardware
Reset Begin
Z X Y

Control CU Inputs
Unit
XR > 0

Subtract XR >= YR
Multiplexers MUX Swap
Select XY CU New State
Subtract
Load XR

Register XR Register YR Load YR

Subtractor Comparators
(XR ≥ YR)
Datapath Unit (XR > 0)
 GCD Hardware
Reset Begin
Z X Y

Control CU Inputs
Unit
XR > 0

Subtract XR >= YR
Multiplexers MUX Swap
Select XY CU New State
Swap
Load XR

Register XR Register YR Load YR

Subtractor Comparators
(XR ≥ YR)
Datapath Unit (XR > 0)
 GCD Hardware
Reset Begin
Z X Y

Control CU Inputs
Unit
XR > 0

Subtract XR >= YR
Multiplexers MUX Swap
Select XY CU New State
Exit
Load XR

Register XR Register YR Load YR

Subtractor Comparators
(XR ≥ YR)
Datapath Unit (XR > 0)
 GCD Control Unit
Inputs
Outputs
(XR > 0) (XR >= YR)
State 0- 10 11 Subtract Swap Select XY Load XR Load YR

S0 (Begin) S3 S1 S2 0 0 1 1 1

S1
10

S0
0X
S3
11

S2
S1 Swap
S2 Subtract
 GCD Hardware
Reset Swap
Z X Y

Control CU Outputs
Unit

Subtract
Multiplexers MUX Swap
Select XY

Load XR

Register XR Register YR Load YR

Subtractor Comparators
(XR ≥ YR)
Datapath Unit (XR > 0)
 GCD Hardware
Reset Swap
Z X Y

CU Outputs
Control
Unit Swap

Load XR
Subtract
Multiplexers MUX Load YR
Swap
Select XY

Load XR

Register XR Register YR Load YR

Subtractor Comparators
(XR ≥ YR)
Datapath Unit (XR > 0)
 GCD Control Unit
Inputs
Outputs
(XR > 0) (XR >= YR)
State 0- 10 11 Subtract Swap Select XY Load XR Load YR

S0 (Begin) S3 S1 S2 0 0 1 1 1
S1 (Swap) 0 1 0 1 1

S1
10

S0 0X
S3
11
S1 Swap S2
S2 Subtract
 GCD Hardware
Reset Swap
Z X Y

Control CU Next States

Unit CU Inputs
XR > 0
Subtract
XR >= YR
Multiplexers MUX Swap
Select XY
Subtract
Load XR

Register XR Register YR Load YR CU Inputs

XR > 0

XR >= YR
Subtractor Comparators
(XR ≥ YR)
Datapath Unit (XR > 0) Subtract
 GCD Hardware
Reset Swap
Z X Y

Control CU Next States

Unit CU Inputs
XR > 0
Subtract
XR >= YR
Multiplexers MUX Swap
Select XY
Subtract
Load XR

Register XR Register YR Load YR CU Inputs

XR > 0

XR >= YR
Subtractor Comparators
(XR ≥ YR)
Datapath Unit (XR > 0) Subtract
 GCD Control Unit
Inputs
Outputs
(XR > 0) (XR >= YR)
State 0- 10 11 Subtract Swap Select XY Load XR Load YR

S0 (Begin) S3 S1 S2 0 0 1 1 1
S1 (Swap) S2 S2 S2 0 1 0 1 1

S1
10
XX
S0
0X
S3
11

S2
 GCD Hardware
Reset Subtract
Z X Y

Control CU Outputs
Unit

Subtract
Multiplexers MUX Swap
Select XY

Load XR

Register XR Register YR Load YR

Subtractor Comparators
(XR ≥ YR)
Datapath Unit (XR > 0)
 GCD Hardware
Reset Subtract
Z X Y

Control CU Outputs
Unit
Subtract

Subtract Load XR
Multiplexers MUX Swap
Select XY

Load XR

Register XR Register YR Load YR

Subtractor Comparators
(XR ≥ YR)
Datapath Unit (XR > 0)
 GCD Control Unit
Inputs
Outputs
(XR > 0) (XR >= YR)
State 0- 10 11 Subtract Swap Select XY Load XR Load YR

S0 (Begin) S3 S1 S2 0 0 1 1 1
S1 (Swap) S2 S2 S2 0 1 0 1 1
S2 (Subtract) 1 0 0 1 0

S1
10
XX
S0
0X
S3
11

S2
 GCD Hardware
Reset Subtract
Z X Y

CU Next State?
Control
Unit CU Inputs
XR > 0
Subtract
XR >= YR
Multiplexers MUX Swap
Select XY
Swap
Load XR

Register XR Register YR Load YR CU Inputs

XR > 0

XR >= YR
Subtractor Comparators
(XR ≥ YR)
Datapath Unit (XR > 0) Subtract
 GCD Hardware
Reset Subtract
Z X Y

CU Next State?
Control
Unit CU Inputs
XR > 0
Subtract
XR >= YR
Multiplexers MUX Swap
Select XY
Swap
Load XR

Register XR Register YR Load YR CU Inputs

XR > 0

XR >= YR
Subtractor Comparators
(XR ≥ YR)
Datapath Unit (XR > 0) Exit
 GCD Control Unit
Inputs
Outputs
(XR > 0) (XR >= YR)
State 0- 10 11 Subtract Swap Select XY Load XR Load YR

S0 (Begin) S3 S1 S2 0 0 1 1 1
S1 (Swap) S2 S2 S2 0 1 0 1 1
S2 (Subtract) S3 S1 S2 1 0 0 1 0

S1
10
XX
S0
0X
S3
11 10

Exit State? S2
0X
 GCD Control Unit – Truth Table
Inputs
Outputs
(XR > 0) (XR >= YR)
State 0- 10 11 Subtract Swap Select XY Load XR Load YR

S0 (Begin) S3 S1 S2 0 0 1 1 1
S1 (Swap) S2 S2 S2 0 1 0 1 1
S2 (Subtract) S3 S1 S2 1 0 0 1 0
S3 (End) S3 S3 S3 0 0 0 0 0

S1
10
XX
S0
0X
S3
11 10

S2
FSM 0X
 Control Unit Design
● Hardwired Control
– Specific to the function of the processor (eg. GCD)
– CU design starts from the FSM
– Fast
– Classical Method
– One hot method
● Microprogrammed Control
– Uses control memory – can be reprogrammed to suit
the function
– Software controlled
Hardwired Control Design

Sequential
Status Logic Control
Signals Signals
Circuit

Instruction
Register
 GCD Control Unit – Truth Table
Inputs
Outputs
(XR > 0) (XR >= YR)
State 0- 10 11 Subtract Swap Select XY Load XR Load YR

S0 (Begin) S3 S1 S2 0 0 1 1 1
S1 (Swap) S2 S2 S2 0 1 0 1 1
S2 (Subtract) S3 S1 S2 1 0 0 1 0
S3 (End) S3 S3 S3 0 0 0 0 0

S1
10
XX
S0
0X
S3
11 10

S2
FSM 0X
 GCD – Excitation Table
XR > 0 XR ≥ YR Old State New State Subtract Swap Select XY Load XR Load YR

0 d S0 S3 0 0 1 1 1
0 d S1 S2 0 1 0 1 1
0 d S2 S3 1 0 0 1 0
0 d S3 S3 0 0 0 0 0

1 0 S0 S1 0 0 1 1 1
1 0 S1 S2 0 1 0 1 1
1 0 S2 S1 1 0 0 1 0
1 0 S3 S3 0 0 0 0 0
1 1 S0 S2 0 0 1 1 1
1 1 S1 S2 0 1 0 1 1
1 1 S2 S2 1 0 0 1 0
1 1 S3 S3 0 0 0 0 0
 CU Design – Classical Method
● How many Flip flops are needed to realize an
n state FSM?
● D0 and D1 are FF present state outputs.
● D0+ and D1+ are FF next state outputs.
D1 D0

S0 = 0 0

Assign a number
S1 = 0 1
for each State
S2 = 1 0
S3 = 1 1
 GCD – Excitation Table
XR > 0 XR ≥ YR D1 D0 New State Subtract Swap Select XY Load XR Load YR

0 d 0 0 S3 0 0 1 1 1
0 d 0 1 S2 0 1 0 1 1
0 d 1 0 S3 1 0 0 1 0
0 d 1 1 S3 0 0 0 0 0

1 0 0 0 S1 0 0 1 1 1
1 0 0 1 S2 0 1 0 1 1
1 0 1 0 S1 1 0 0 1 0
1 0 1 1 S3 0 0 0 0 0
1 1 0 0 S2 0 0 1 1 1
1 1 0 1 S2 0 1 0 1 1
1 1 1 0 S2 1 0 0 1 0
1 1 1 1 S3 0 0 0 0 0
 GCD – Excitation Table
+ +
XR > 0 XR ≥ YR D1 D0 D1 D0 Subtract Swap Select XY Load XR Load YR

0 d 0 0 1 1 0 0 1 1 1
0 d 0 1 1 0 0 1 0 1 1
0 d 1 0 1 1 1 0 0 1 0
0 d 1 1 1 1 0 0 0 0 0

1 0 0 0 0 1 0 0 1 1 1
1 0 0 1 1 0 0 1 0 1 1
1 0 1 0 0 1 1 0 0 1 0
1 0 1 1 1 1 0 0 0 0 0
1 1 0 0 1 0 0 0 1 1 1
1 1 0 1 1 0 0 1 0 1 1
1 1 1 0 1 0 1 0 0 1 0
1 1 1 1 1 1 0 0 0 0 0
 GCD – Classical Method
What
Whatare
arethe
theequations
equationsfor
foreach
eachof
ofthe
theoutputs
outputsin
inthe
theexcitation
excitationtable?
table?

Subtract= D 1⋅D̄0 Subtract= D1⋅D̄0

Swap= D
̄ 1⋅D 0 Swap= D ̄ 1⋅D 0
Select XY = D̄ 1⋅D̄ 0 ̄ 1⋅D̄ 0
Select XY = D
Load XR= D̄0 + D̄1 Load XR=D0⋅D1
Load YR= D̄ 1
 GCD – All NAND Classical Design

Subtract= D 1⋅D̄0
̄ 1⋅D 0
Swap= D Load XR=D0⋅D1 ̄ 1⋅D̄ 0
Select XY = D Load YR= D̄ 1
 CU Design – One Hot Method

D3 D2 D1 D0

S0 = 0 0 0 1
Assign a one hot combination
S1 = 0 0 1 0
for each State
S2 = 0 1 0 0
S3 = 1 0 0 0

● n Flip flops are needed to realize an n state

FSM
 CU Design – One Hot Method
Inputs
Outputs
(XR > 0) (XR >= YR)
State 0- 10 11 Subtract Swap Select XY Load XR Load YR

S0 (Begin) S3 S1 S2 0 0 1 1 1
S1 (Swap) S2 S2 S2 0 1 0 1 1
S2 (Subtract) S3 S1 S2 1 0 0 1 0
S3 (End) S3 S3 S3 0 0 0 0 0

D 0+

D 1+

D 2+

D 3+
 CU Design – One Hot Method
Inputs
Outputs
(XR > 0) (XR >= YR)
State 0- 10 11 Subtract Swap Select XY Load XR Load YR

S0 (Begin) S3 S1 S2 0 0 1 1 1
S1 (Swap) S2 S2 S2 0 1 0 1 1
S2 (Subtract) S3 S1 S2 1 0 0 1 0
S3 (End) S3 S3 S3 0 0 0 0 0
 CU Design – One Hot Method
Inputs
Outputs
(XR > 0) (XR >= YR)
State 0- 10 11 Subtract Swap Select XY Load XR Load YR

S0 (Begin) S3 S1 S2 0 0 1 1 1
S1 (Swap) S2 S2 S2 0 1 0 1 1
S2 (Subtract) S3 S1 S2 1 0 0 1 0
S3 (End) S3 S3 S3 0 0 0 0 0

Subtract= D 2 Load XR=D 0 + D1 + D 2

Swap= D1
Select XY =D 0 Load YR=D 0 + D 1
All NAND One-Hot Design
 Two's Complement Multiplier
Sign
Logic
M[7]
F Q[0]

A Q M

Parallel Adder cin

OUTBUS

INBUS

COUNT7 Control
Unit
BEGIN
External Comparator c0
Control END ... Internal
c1 Control
Signals 7
CLOCK Signals
Count c10
 Multiplier Flowchart
Begin
S0
S1 Yes COUNT7 = 1?
Q(0) = 0? No
A := 0
COUNT := 0 Yes
F := 0 No
M := INBUS
S3 Yes
Q(0) = 0? S7
A := A + M
F := M(7) and Q(0) or F OUTBUS := A
S2 No
S5
Q := INBUS A := A – M
S4 Q(0) := 0

A(7) := F S0
A(6:0).Q := A.Q(7:1) S6 End
COUNT := COUNT + 1
OUTBUS := Q

Cycle 0 Cycle 1 to 7 Cycle 8 Cycle 9

 Multiplier Control Points S1

A := 0
Sign COUNT := 0
c10 Logic F := 0
M[7] M := INBUS
F Q[0]

c10 A Q M

Parallel Adder cin

c9

OUTBUS

INBUS

COUNT7 Control
Unit
BEGIN
External Comparator c0
Control END ... Internal
c1 Control
Signals 7
CLOCK c10 Signals
Count c10
 S2
Multiplier Control Points
Q := INBUS
Sign
c10 Logic
M[7]
F Q[0]

c10 A Q M

Parallel Adder cin

c9
c8

OUTBUS

INBUS

COUNT7 Control
Unit
BEGIN
External Comparator c0
Control END ... Internal
c1 Control
Signals 7
CLOCK c10 Signals
Count c10
 S3
Multiplier Control Points
A := A + M
Sign F := M(7) and Q(0) or F
c10 Logic
M[7]
F Q[0]

c10 A Q M

c3 c4
c2

Parallel Adder cin

c9
c8

OUTBUS

INBUS

COUNT7 Control
Unit
BEGIN
External Comparator c0
Control END ... Internal
c1 Control
Signals 7
CLOCK c10 Signals
Count c10
 S4
Multiplier Control Points
A(7) := F
Sign A(6:0).Q := A.Q(7:1)
c0 Logic
c10 COUNT := COUNT + 1
c1 M[7]
F Q[0]

c10 A Q M

c3 c4
c2

Parallel Adder cin

c9
c8

OUTBUS

INBUS

COUNT7 Control
Unit
BEGIN
External Comparator c0
Control END ... Internal
c1 Control
Signals 7
CLOCK c10 Signals
Count c11 c10
 S5
Multiplier Control Points
A := A – M
Sign Q(0) := 0
c0 Logic
c10 M[7]
c1 Q[0]
F

c10 A Q M

c3 c4
c2

Parallel Adder cin

c9
c8

OUTBUS

INBUS

COUNT7 Control
Unit
BEGIN
External Comparator c0
Control END ... Internal
c1 Control
Signals 7
CLOCK c10 Signals
Count c11 c10
 S5
Multiplier Control Points
A := A – M
Sign Q(0) := 0
c0 Logic
c10 c5 M[7]
c1 Q[0]
F

c10 A Q M

c3 c4
c2

Parallel Adder cin

c9
c8

OUTBUS

INBUS

COUNT7 Control c5
Unit
BEGIN
External Comparator c0
Control END ... Internal
c1 Control
Signals 7
CLOCK c10 Signals
Count c11 c10
 S6
Multiplier Control Points
OUTBUS := Q
Sign
c0 Logic
c10 c5 M[7]
c1 Q[0]
F

c10 A Q M

c3 c4
c2

Parallel Adder cin

c9
c8 c7

OUTBUS

INBUS

COUNT7 Control c5
Unit
BEGIN
External Comparator c0
Control END ... Internal
c1 Control
Signals 7
CLOCK c10 Signals
Count c11 c10
 S7
Multiplier Control Points
OUTBUS := A
Sign
c0 Logic
c10 c5 M[7]
c1 Q[0]
F

c10 A Q M

c3 c4
c2

Parallel Adder cin

c6 c9
c8 c7

OUTBUS

INBUS

COUNT7 Control c5
Unit
BEGIN
External Comparator c0
Control END ... Internal
c1 Control
Signals 7
CLOCK c10 Signals
Count c11 c10
Multiplier Control Signals
c0 Set sign bit of A to F

c1 Right-shift register-pair A.Q

c2 Transfer adder output to A
c3 Transfer A to left input of adder
c4 Transfer M to right input of adder
c5 Perform subtraction. Clear Q[0].
c6 Transfer A to output bus.
c7 Transfer Q to output bus.
c8 Transfer word on input bus to Q
c9 Transfer word on input bus to M
c10 Clear A, COUNT, and F registers
c11 Increment COUNT
END Completion signal (CU idle)
 Multiplier Flowchart
Begin
S0
S1 c9, c10 Yes COUNT7 = 1?
Q(0) = 0? No
A := 0
COUNT := 0 Yes
F := 0 No
M := INBUS
S3 c2, c3, c4
Yes
Q(0) = 0? S7 c7
A := A + M
F := M(7) and Q(0) or F OUTBUS := A
No c2, c3,
S2 c8 S5 c4, c5
Q := INBUS A := A – M
S4 c0, c1, c11 Q(0) := 0

A(7) := F S0
A(6:0).Q := A.Q(7:1) S6 c6
End
COUNT := COUNT + 1
OUTBUS := Q

Cycle 0 Cycle 1 to 7 Cycle 8 Cycle 9

 Multiplier Control Unit – State Table
Inputs: BEGIN Q[0] Count7 Inputs: BEGIN Q[0] Count7
State 000 001 010 011 100 101 110 111 c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 END

S0 S0 S0 S0 S0 S1 S1 S1 S1 0 0 0 0 0 0 0 0 0 0 0 0 1
S1 S2 S2 S2 S2 S2 S2 S2 S2 0 0 0 0 0 0 0 0 0 1 1 0 0
S2 S4 S4 S3 S3 S4 S4 S3 S3 0 0 0 0 0 0 0 0 1 0 0 0 0
S3 S4 S4 S4 S4 S4 S4 S4 S4 0 0 1 1 1 0 0 0 0 0 0 0 0
S4 S4 S6 S3 S5 S4 S6 S3 S5 1 1 0 0 0 0 0 0 0 0 0 1 0
S5 S6 S6 S6 S6 S6 S6 S6 S6 0 0 1 1 1 1 0 0 0 0 0 0 0

S6 S7 S7 S7 S7 S7 S7 S7 S7 0 0 0 0 0 0 1 0 0 0 0 0 0
S7 S0 S0 S0 S0 S0 S0 S0 S0 0 0 0 0 0 0 0 1 0 0 0 0 0

D+0 =D 0⋅BEGIN + D 7 D+3 =D 2⋅Q [0]+ D4⋅Q[0 ]⋅COUNT7

D+1 =D0⋅BEGIN D+4= D2⋅D0 + D 3 + D 4⋅Q [0]⋅COUNT7
+
D 2=D 1 D+5 =D 4⋅Q [0]⋅COUNT7
 Multiplier Control Unit – State Table
Inputs: BEGIN Q[0] Count7 Inputs: BEGIN Q[0] Count7
State 000 001 010 011 100 101 110 111 c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 END

S0 S0 S0 S0 S0 S1 S1 S1 S1 0 0 0 0 0 0 0 0 0 0 0 0 1
S1 S2 S2 S2 S2 S2 S2 S2 S2 0 0 0 0 0 0 0 0 0 1 1 0 0
S2 S4 S4 S3 S3 S4 S4 S3 S3 0 0 0 0 0 0 0 0 1 0 0 0 0
S3 S4 S4 S4 S4 S4 S4 S4 S4 0 0 1 1 1 0 0 0 0 0 0 0 0
S4 S4 S6 S3 S5 S4 S6 S3 S5 1 1 0 0 0 0 0 0 0 0 0 1 0
S5 S6 S6 S6 S6 S6 S6 S6 S6 0 0 1 1 1 1 0 0 0 0 0 0 0

S6 S7 S7 S7 S7 S7 S7 S7 S7 0 0 0 0 0 0 1 0 0 0 0 0 0
S7 S0 S0 S0 S0 S0 S0 S0 S0 0 0 0 0 0 0 0 1 0 0 0 0 0

D+6 =D 5+ D4⋅Q [0]⋅COUNT7

D+7 =D 6
 Multiplier Control Unit – State Table
Inputs: BEGIN Q[0] Count7 Inputs: BEGIN Q[0] Count7
State 000 001 010 011 100 101 110 111 c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 END

S0 S0 S0 S0 S0 S1 S1 S1 S1 0 0 0 0 0 0 0 0 0 0 0 0 1
S1 S2 S2 S2 S2 S2 S2 S2 S2 0 0 0 0 0 0 0 0 0 1 1 0 0
S2 S4 S4 S3 S3 S4 S4 S3 S3 0 0 0 0 0 0 0 0 1 0 0 0 0
S3 S4 S4 S4 S4 S4 S4 S4 S4 0 0 1 1 1 0 0 0 0 0 0 0 0
S4 S4 S6 S3 S5 S4 S6 S3 S5 1 1 0 0 0 0 0 0 0 0 0 1 0
S5 S6 S6 S6 S6 S6 S6 S6 S6 0 0 1 1 1 1 0 0 0 0 0 0 0

S6 S7 S7 S7 S7 S7 S7 S7 S7 0 0 0 0 0 0 1 0 0 0 0 0 0
S7 S0 S0 S0 S0 S0 S0 S0 S0 0 0 0 0 0 0 0 1 0 0 0 0 0

c 0 =c 1=c11 =D 4 c 6 =D6 c 9 =c 10= D 1

c 2 =c 3=c 4 =D 3 + D 5 c 7 =D7 END= D0
c 5= D 5 c 8= D 2
Multiplier
CU –
One Hot
Design
 Microprogrammed Control
● Hardwired control unit design – inflexible,
difficult to verify.
● Microprogramming
– Control Memory
– Microinstructions, Microprogram
– Microassembler
Microprogrammed Control Design

Address
Control
Logic Memory

μInstruction
Register

Decoder
Instruction
Register
 Microprogrammed Controller
External
address

External
conditions MUX Microprogram
μPC Counter
Increment
Condition
Select
CONTROL
MEMORY
(CM)
Microinstruction Format

Branch Control Microinstruction

Address fields Register μIR
Condition
Select
Decoders

Control signals to DPU

 Two's Complement Multiplication
BEGIN: A := 0, COUNT := 0, F := 0, M := INBUS; c9, c10
INPUT: Q := INBUS; c8
TEST1: If Q[0] = 0 then go to RSHIFT:

ADD: A[7:0] := A[7:0] + M[7:0], F := (M[7] and Q[0]) or F; c2, c3, c4

RSHIFT: A[7] = F, A[6:0].Q = A.Q[7:1], COUNT = COUNT + 1, c0, c1, c11
if COUNT7 = 0 then go to TEST1;
TEST2: if Q[0] = 0 then go to OUTPUT1;

SUBTRACT: A[7:0] := A[7:0] – M[7:0], Q[0] := 0; c2, c3, c4, c5

OUTPUT1: OUTBUS := A; c6
OUTPUT2: OUTBUS := Q; c7

END: Halt; END

 Binary Microprogram for 2's
Complement Multiplication
Control fields
Address Condition Branch
in CM select Address c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 END

0000 00 0000 0 0 0 0 0 0 0 0 0 1 1 0 0

0001 00 0000 0 0 0 0 0 0 0 0 1 0 0 0 0

0010 01 0100 0 0 0 0 0 0 0 0 0 0 0 0 0

0011 00 0000 0 0 1 1 1 0 0 0 0 0 0 0 0

0100 10 0010 1 1 0 0 0 0 0 0 0 0 0 1 0
0101 01 0111 0 0 0 0 0 0 0 0 0 0 0 0 0
0110 00 0000 0 0 1 1 1 1 0 0 0 0 0 0 0

0111 00 0000 0 0 0 0 0 0 1 0 0 0 0 0 0

1000 00 0000 0 0 0 0 0 0 0 1 0 0 0 0 0

1001 11 1001 0 0 0 0 0 0 0 0 0 0 0 0 1
 Two's Complement Multiplier
Microprogrammed Control Unit
BEGIN Timing
Logic
0 00 Branch
Address
Q[0] 01
COUNT7 10 μPC Reset
11 Increment
1

Condition
Select CONTROL
MEMORY
2 (10 x 19 bits)

19

μIR
4 13

{ci}, END