NAME: FARHAN ASLAM

CLASS: MCS Previous (Morning)

SEAT NO: P19101036

PARITY GENERATORS AND CHECKERS

1-) OBJECTIVE :
To explain the concept of parity and study the operation principles of basic parity
generators and checker.

2-) THEORY :
Errors can occur as digital codes are being transferred from one point to another (i.e
from one digital device (computer) to another (printer) within a digital system or while
codes are being transmitted from one system to another. The errors take the form of
undesired changes in the bits that make up the coded information; that is, a 1 can change to
a 0, or a 0 to a 1, because of component malfunctions, electrical noise or other
disturbances. In most digital systems, the probability that even a single bit error will occur
is very small, and the likelihood that more than one will occur is even smaller.
Nevertheless, when an error occurs undetected, it can cause serious problems in a digital
system.
Exclusive-OR and equivalence functions are very useful in systems requiring error-
detection and error-correction codes. A parity bit is a scheme for detecting errors during
transmission of binary information. A parity bit is an extra bit included with a binary
message to make the number of 1’s either odd or even. The message, including the parity
bit, is transmitted and then checked at the receiving end for errors. An error is detected if
the checked parity does not correspond to the one transmitted. The circuit that generates
the parity bit in the transmitter is called a parity generator; the circuit that checks the parity
in the receiver is called a parity checker.
Parity systems are defined as either odd parity or even parity. The parity system
adds an extra bit to the digital information being transmitted. A 2-bit system will require a
third bit, an 3-bit system will require a forth bit, and so on. In an odd-parity system, the
parity bit that is added must make the sum of all n-bits odd. In an even-parity system, the
parity bit makes the sum of all bits even.
The parity generator is the circuit that creates the parity bit. On the receiving end, a
parity checker determines if the n-bits result is of the right parity. The type of system (odd

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or even) must be agreed on before hand so that the parity checker knows what to look for
(this is called protocol). Also, the parity bit can be placed next to the MSB or LSB as long
as the device on the receiving end knows which bit is parity and which bits are data.
For example, during the transmission of BCD number 9 (1001) in an odd-parity
system, the parity generator puts a 1 on the parity-bit line to make the sum of all bits odd
(1+0+0+1+1=3). The parity checker at the receiving end checks to see that the transferred
all-bits are odd, it assumes that no error then BCD information is valid. Otherwise, an error
indicator indicates an error. The error indicator is actually a signal that initiates a
retransmission of the original signal or produces an error message on a computer display.
A block diagram of a parity generator and checker system is shown in Figure 7.1.

B B
C C
D D

Parity Bit Error

Transmitting Device Receiving Device

Figure 7.1 : A parity generator/checker system.

3-) EXPERIMENTAL PROCEDURE :

5 Volt
- +
+5
0 P
X Y Z

Figure 7.2 : 3-bit parity generator

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 Three-bit message Parity bit
generated
X Y Z P
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
3.2-) Parity Checker : Set up the following circuit.

5 Volt
- + F
+5
0

X Y Z P

Figure 7.3 : A 3-bits parity checker.

Parity error
Four-bits received
generated
X Y Z P F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1

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4-) DISCUSSIONS :
4.1-) Determine the type of the system in part 3.1 and .2.
4.2-) Write the Boolean expression of P and F in the simplest form.
4.3-) Add a parity bit next to the LSB of the following hexadecimal codes to form even parity:
0011, 1000, 1101, 0111, 1010, 0001, 0000, 0100.
4.4-) Suppose that a computer and printer system uses 4-bit odd parity generator and
checker, a-) Tabulate the truth table of parity generator.
b-) Write and simplify the output function of parity generator using any simplification
technique which you learned.
c-) Implement the logic circuits of parity generator and checker in the simplest form.
d-) Discuss in which conditions parity checker gives error.
4.5-) Design a logic circuit that detects the errors occur when a binary information
transferring from a computer to a printer. Restrict that the long of binary information
are four bits.
4.6-) One popular 9-bit parity generator/checker is the 74280 TTL IC or 74HC280 CMOS

IC (see Figure 7.4). Using 74280s, design a complete parity generator/checking

Function Table I0 I1 I2 I3 I4 I5 I6 I7 I8
Number of HIGH data Sum Output
inputs (I - I ) E O 74280 TTL IC
Even HIGH LOW
Odd LOW HIGH E o

5 6
VCC= Pin-14
GND=Pin-7

4.7-) Which output of the 74280 parity generator is used as the parity bit in an odd system?

A0
A0
A1 A1
Parity Generator P
A2 A2
A3
A3

Figure 7.4 : Input waveforms and block diagram of parity generator.

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 ANSWER (4.1):

The generator shown in 3.1 is an even parity generator because that system have 2 XOR Gates.

The generator shown in 3.2 is an odd parity generator because that system have 3 XNOR Gates.

ANSWER (4.2):
BOOLEAN EXPRESSION OF (3.1)

P = (X ⊕ Y) ⊕ Z

BOOLEAN EXPRESSION OF (3.2)

F = X ⊕ Y Ex-NOR Z

ANSWER (4.3):

(1) 0011 : 0
00011
(2) 1000 : 1
11000
(3) 1101 : 1

11101

(4) 0111 : 1

10111
(5) 1010 : 0

01010
(6) 0000 : 0

00000
(7) 0100 : 1

10100

ANSWER (4.4):
ANSWER (4.5):
ANSWER (4.6):