5-1 Chapter 5 - Datapath and Control

Computer Architecture and

Organization
Miles Murdocca and Vincent Heuring

Chapter 5 – Datapath
and Control

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
 5-2 Chapter 5 - Datapath and Control

Chapter Contents
5.1 Basics of the Microarchitecture
5.2 The Datapath
5.3 The Control Section – Microprogrammed
5.4 The Control Section – Hardwired
5.5 Case Study: The VHDL Hardware Description Language
5.6 Case Study: What Happens when a Computer Boots Up?

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
 5-3 Chapter 5 - Datapath and Control

The Fetch-Execute Cycle

• The steps that the control unit carries out in executing a
program are:
(1) Fetch the next instruction to be executed from memory.
(2) Decode the opcode.
(3) Read operand(s) from main memory, if any.
(4) Execute the instruction and store results, if any.
(5) Go to step 1.

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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High Level View of Microarchitecture

• The microarchitecture consists of the control unit and the
programmer-visible registers, functional units such as the
ALU, and any additional registers that may be required by
the control unit.

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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A More Detailed View

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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ARC Instruction Subset

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ARC Instruction Formats

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ARC
Datapath

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
 5-9 Chapter 5 - Datapath and Control

ARC ALU Operations

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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Block Diagram of ALU

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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Gate-Level Layout of Barrel Shifter

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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Truth Table for (Most of the) ALU LUTs

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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Design of Register %r1

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Outputs to Control Unit from

Register %ir

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
 5-15 Chapter 5 - Datapath and Control

Microarch-
itecture of
the ARC

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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Microword Format

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Settings for the COND Field of the

Microword

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
 5-18 Chapter 5 - Datapath and Control

DECODE Format for Microinstruction

Address

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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Timing Relationships for the Registers

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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Partial
ARC
Micro-
program

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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Partial ARC
Microprogram
(cont’)

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
 5-22 Chapter 5 - Datapath and Control

Translating the Microprogram

0: R[ir] ← AND(R[pc],R[pc]); READ;

1: DECODE; /256-way jump according to opcode

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
 5-23 Chapter 5 - Datapath and Control

Branch Decoding
• Decoding tree for
branch instructions
shows corresponding
microprogram lines:

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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Assembled
ARC
Microprogram

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Assembled
ARC
Microprogram
(cont’)

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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Example: Add the subcc Instruction

• Consider adding instruction subcc (subtract) to the ARC instruction set.
subcc uses the Arithmetic format and op3 = 001100.

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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Branch Table
• A branch table for trap handlers and interrupt service routines:

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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Microprogramming vs.
Nanoprogramming

(a) Micropro-
gramming,

(b) nano-
programming.

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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Hardware Description Language

• HDL sequence
for a resettable
modulo 4
counter.

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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Circuit Derived from HDL

• Logic design for a modulo 4 counter described in HDL.

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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HDL for
ARC

• HDL description of
the ARC control
unit.

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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HDL for ARC (cont’)

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
 5-33 Chapter 5 - Datapath and Control

HDL ARC
Circuit

• The hardwired
control section of
the ARC:
generation of the
control signals.

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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HDL ARC Circuit (cont’)

• Hardwired
control
section of
the ARC:
signals from
the data
section of
the control
unit to the
datapath.

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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Case Study: The VHDL Hardware

Description Language
• The majority function. a) truth table, b) AND-OR implementation, c)
black box representation.

Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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VHDL Specification
Interface specification for the majority component
-- Interface
entity MAJORITY is
port
(A_IN, B_IN, C_IN: in BIT
F_OUT: out BIT);
end MAJORITY;
Behavioral model for the majority component
-- Body
architecture LOGIC_SPEC of MAJORITY is
begin
-- compute the output using a Boolean expression
F_OUT <= (not A_IN and B_IN and C_IN) or
(A_IN and not B_IN and C_IN) or
(A_IN and B_IN and not C_IN) or
(A_IN and B_IN and C_IN) after 4 ns;
end LOGIC_SPEC;
Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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VHDL Specification (cont’)

-- Package declaration, in library WORK
package LOGIC_GATES is
component AND3
port (A, B, C : in BIT; X : out BIT);
end component;
component OR4
port (A, B, C, D : in BIT; X : out BIT);
end component;
component NOT1
port (A : in BIT; X : out BIT);
end component;
-- Interface
entity MAJORITY is
port
(A_IN, B_IN, C_IN: in BIT
F_OUT: out BIT);
end MAJORITY;
Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring
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VHDL Specification (cont’)

-- Body
-- Uses components declared in package LOGIC_GATES
-- in the WORK library
-- import all the components in WORK.LOGIC_GATES
use WORK.LOGIC_GATES.all
architecture LOGIC_SPEC of MAJORITY is
-- declare signals used internally in MAJORITY
signal A_BAR, B_BAR, C_BAR, I1, I2, I3, I4: BIT;
begin
-- connect the logic gates
NOT_1 : NOT1 port map (A_IN, A_BAR);
NOT_2 : NOT1 port map (B_IN, B_BAR);
NOT_3 : NOT1 port map (C_IN, C_BAR);
AND_1 : AND3 port map (A_BAR, B_IN, C_IN, I1);
AND_2 : AND3 port map (A_IN, B_BAR, C_IN, I2);
AND_3 : AND3 port map (A_IN, B_IN, C_BAR, I3);
AND_4 : AND3 port map (A_IN, B_IN, C_IN, I4);
OR_1 : OR3 port map (I1, I2, I3, I4, F_OUT);
end LOGIC_SPEC;
Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring