Static Timing Analysis
Course Instructor: Dr. Ramesh S R
[email protected] Outline
What is Static Timing Analysis?
Impact of noise and crosstalk
How these analyses are used?
Which phase of over all design process are these analyses
applicable?
Nanometer Designs
In semiconductor devices, metal interconnect traces
are used to make connection
This is to realize a design
As process technology shrinks, interconnect traces
affects the performance of design
Deep submicron or nanometer technologies
Coupling in the interconnect produces noise and cross
talk
Limits the operating speed of the design
Physical design should consider the effect of crosstalk
and noise
What is Static Timing Analysis(STA)?
To verify the timing of a digital design
Alternate approach to verify timing is timing simulation
- verifies the functionality as well as timing
• Timing analysis refers to either STA or timing simulation
• Analysis of the design for timing issues
• STA is static because analysis of design is carried out
statistically and does not depend on data value at input pins
• Simulation based timing analysis – a stimulus is applied
• Resulting behavior is observed and verified
Static Timing Analysis
STA
Purpose is to validate if the design can operate at the rated
speed
Given a design with a set of input CLK definitions and
definition of external environment
Check whether design can operate safely at the specified
frequency of the clocks without any timing violations
DUA –Design Under Analysis
Examples of timing checks – setup and hold check
Entire design is analyzed once and the required timing
checks are performed for all possible paths and scenarios
STA
DUA is specified by VHDL or Verilog HDL
External environment including clock definitions are
specified using SDC or an equivalent format
SDC is timing constraint specification language
Timing reports are in ASCII form with multiple
columns
Each column highlights one attribute of path delay
Why STA??
STA is a complete and exhaustive verification of all
timing checks of a design
Other timing analysis methods can verify the portions
of the design that get exercised by stimulus
Simulation and verification of a design with 10-100
million gates is very slow and timing cannot be
verified completely
STA is a faster and simpler way of checking and
analyzing all timing paths for any timing violations
Given the complexity of present day ASICs , STA is a
better choice
Crosstalk and Noise
Design functionality and performance affected by
noise
Noise occurs due to crosstalk with other signals or due
to noise on primary inputs or the power supply
Noise impact – causes functional failures
Design implementation must be verified to be robust
which means it can withstand noise
Without affecting performance of design
Verification based on logic simulation cannot handle
effects of noise, crosstalk etc
Design Flow – CMOS Digital Design
CMOS Digital designs
STA is rarely done at RTL level as it this point it is very
important to verify the functionality of the design
Also not all timing information will be available since the
description of the blocks are at behavioral level
STA can also be run prior to performing logic optimization
Goal is to identify the worst or critical timing paths
STA can be rerun after logic optimization to see whether
there are failing paths still remaining that need to be
optimized
At the start of physical design ,CLK trees are considered as
ideal – i.e they have zero delay
CMOS Digital designs
Once PD starts and after CLK trees are built, STA can
be performed to check timing again.
It is done to identify worst paths
In physical implementation, logic cells are connected
by interconnect metal traces
Parasitic RC of metal traces impact the signal path
delay
It affects the delay and power dissipation
Coupling between signal traces contributes to noise
.So design verification should include impact of noise.
CMOS Digital designs
At the logical design phase, ideal interconnect may be used
since there is no physical information related to placement
Another technique is estimation of length of interconnect
using wireload models
Before finalization of routing traces, the implementation
tools use an estimate of the routing distance to obtain RC
parasitics
It is called as global route phase
In this phase simplified routes are used to estimate the
routing lengths and the routing estimates are used to find
R,C
CMOS Digital designs
It Is done to compute the wire delays
Extraction tool is used to extract the detailed RC
parasitics from a routed design
During iterative optimization ,extractor have an option
to obtain parasitics with small runtime and less
accurate RC values
For final verification very accurate RC values are
extracted
Summary
STA can be performed on a GLN depending on
- How interconnect is modeled =ideal, WLM,global
routes or real routes
- How CLKs are modeled? - Ideal or propagated
- Whether coupling between signals is included
- whether any crosstalk noise is analyzed
